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authorStephen Warren <swarren@nvidia.com>2013-11-25 19:53:16 -0500
committerStephen Warren <swarren@nvidia.com>2013-12-16 16:09:16 -0500
commit58ecb23f64ee3a2ef66bb55b2e1e841385b6d08b (patch)
tree91933b662c5ea802874259c9a1b555774834c4f2
parent18f48a4f1d49d522285b5a9f3c5d984f4fdaae01 (diff)
ARM: tegra: add missing unit addresses to DT
DT node names should include a unit address iff the node has a reg property. For Tegra DTs at least, we were previously applying a different rule, namely that node names only needed to include a unit address if it was required to make the node name unique. Consequently, many unit addresses are missing. Add them. Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts18
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi24
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi12
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts14
-rw-r--r--arch/arm/boot/dts/tegra20-iris-512.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts12
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts12
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi12
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts12
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts10
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts14
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi54
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts18
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi12
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi50
18 files changed, 146 insertions, 146 deletions
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb5ec23b03a7..5d2d6f6387e8 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -11,7 +11,7 @@
11 reg = <0x80000000 0x40000000>; 11 reg = <0x80000000 0x40000000>;
12 }; 12 };
13 13
14 pinmux { 14 pinmux@70000868 {
15 pinctrl-names = "default"; 15 pinctrl-names = "default";
16 pinctrl-0 = <&state_default>; 16 pinctrl-0 = <&state_default>;
17 17
@@ -722,7 +722,7 @@
722 status = "okay"; 722 status = "okay";
723 clock-frequency = <100000>; 723 clock-frequency = <100000>;
724 724
725 battery: smart-battery { 725 battery: smart-battery@b {
726 compatible = "ti,bq20z45", "sbs,sbs-battery"; 726 compatible = "ti,bq20z45", "sbs,sbs-battery";
727 reg = <0xb>; 727 reg = <0xb>;
728 battery-name = "battery"; 728 battery-name = "battery";
@@ -731,7 +731,7 @@
731 power-supplies = <&charger>; 731 power-supplies = <&charger>;
732 }; 732 };
733 733
734 rt5640: rt5640 { 734 rt5640: rt5640@1c {
735 compatible = "realtek,rt5640"; 735 compatible = "realtek,rt5640";
736 reg = <0x1c>; 736 reg = <0x1c>;
737 interrupt-parent = <&gpio>; 737 interrupt-parent = <&gpio>;
@@ -753,7 +753,7 @@
753 status = "okay"; 753 status = "okay";
754 clock-frequency = <400000>; 754 clock-frequency = <400000>;
755 755
756 tps51632 { 756 tps51632@43 {
757 compatible = "ti,tps51632"; 757 compatible = "ti,tps51632";
758 reg = <0x43>; 758 reg = <0x43>;
759 regulator-name = "vdd-cpu"; 759 regulator-name = "vdd-cpu";
@@ -763,7 +763,7 @@
763 regulator-always-on; 763 regulator-always-on;
764 }; 764 };
765 765
766 tps65090 { 766 tps65090@48 {
767 compatible = "ti,tps65090"; 767 compatible = "ti,tps65090";
768 reg = <0x48>; 768 reg = <0x48>;
769 interrupt-parent = <&gpio>; 769 interrupt-parent = <&gpio>;
@@ -846,7 +846,7 @@
846 }; 846 };
847 }; 847 };
848 848
849 palmas: tps65913 { 849 palmas: tps65913@58 {
850 compatible = "ti,palmas"; 850 compatible = "ti,palmas";
851 reg = <0x58>; 851 reg = <0x58>;
852 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>; 852 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
@@ -1046,7 +1046,7 @@
1046 }; 1046 };
1047 }; 1047 };
1048 1048
1049 pmc { 1049 pmc@7000e400 {
1050 nvidia,invert-interrupt; 1050 nvidia,invert-interrupt;
1051 nvidia,suspend-mode = <1>; 1051 nvidia,suspend-mode = <1>;
1052 nvidia,cpu-pwr-good-time = <500>; 1052 nvidia,cpu-pwr-good-time = <500>;
@@ -1057,7 +1057,7 @@
1057 nvidia,sys-clock-req-active-high; 1057 nvidia,sys-clock-req-active-high;
1058 }; 1058 };
1059 1059
1060 ahub { 1060 ahub@70080000 {
1061 i2s@70080400 { 1061 i2s@70080400 {
1062 status = "okay"; 1062 status = "okay";
1063 }; 1063 };
@@ -1089,7 +1089,7 @@
1089 #address-cells = <1>; 1089 #address-cells = <1>;
1090 #size-cells = <0>; 1090 #size-cells = <0>;
1091 1091
1092 clk32k_in: clock { 1092 clk32k_in: clock@0 {
1093 compatible = "fixed-clock"; 1093 compatible = "fixed-clock";
1094 reg=<0>; 1094 reg=<0>;
1095 #clock-cells = <0>; 1095 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 731249fbe206..8fdf8d5cff09 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -15,7 +15,7 @@
15 serial3 = &uartd; 15 serial3 = &uartd;
16 }; 16 };
17 17
18 gic: interrupt-controller { 18 gic: interrupt-controller@50041000 {
19 compatible = "arm,cortex-a15-gic"; 19 compatible = "arm,cortex-a15-gic";
20 #interrupt-cells = <3>; 20 #interrupt-cells = <3>;
21 interrupt-controller; 21 interrupt-controller;
@@ -39,14 +39,14 @@
39 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 39 clocks = <&tegra_car TEGRA114_CLK_TIMER>;
40 }; 40 };
41 41
42 tegra_car: clock { 42 tegra_car: clock@60006000 {
43 compatible = "nvidia,tegra114-car"; 43 compatible = "nvidia,tegra114-car";
44 reg = <0x60006000 0x1000>; 44 reg = <0x60006000 0x1000>;
45 #clock-cells = <1>; 45 #clock-cells = <1>;
46 #reset-cells = <1>; 46 #reset-cells = <1>;
47 }; 47 };
48 48
49 apbdma: dma { 49 apbdma: dma@6000a000 {
50 compatible = "nvidia,tegra114-apbdma"; 50 compatible = "nvidia,tegra114-apbdma";
51 reg = <0x6000a000 0x1400>; 51 reg = <0x6000a000 0x1400>;
52 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 52 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -87,12 +87,12 @@
87 #dma-cells = <1>; 87 #dma-cells = <1>;
88 }; 88 };
89 89
90 ahb: ahb { 90 ahb: ahb@6000c004 {
91 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 91 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb";
92 reg = <0x6000c004 0x14c>; 92 reg = <0x6000c004 0x14c>;
93 }; 93 };
94 94
95 gpio: gpio { 95 gpio: gpio@6000d000 {
96 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 96 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
97 reg = <0x6000d000 0x1000>; 97 reg = <0x6000d000 0x1000>;
98 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 98 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -109,7 +109,7 @@
109 interrupt-controller; 109 interrupt-controller;
110 }; 110 };
111 111
112 pinmux: pinmux { 112 pinmux: pinmux@70000868 {
113 compatible = "nvidia,tegra114-pinmux"; 113 compatible = "nvidia,tegra114-pinmux";
114 reg = <0x70000868 0x148 /* Pad control registers */ 114 reg = <0x70000868 0x148 /* Pad control registers */
115 0x70003000 0x40c>; /* Mux registers */ 115 0x70003000 0x40c>; /* Mux registers */
@@ -175,7 +175,7 @@
175 status = "disabled"; 175 status = "disabled";
176 }; 176 };
177 177
178 pwm: pwm { 178 pwm: pwm@7000a000 {
179 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 179 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm";
180 reg = <0x7000a000 0x100>; 180 reg = <0x7000a000 0x100>;
181 #pwm-cells = <2>; 181 #pwm-cells = <2>;
@@ -350,14 +350,14 @@
350 status = "disabled"; 350 status = "disabled";
351 }; 351 };
352 352
353 rtc { 353 rtc@7000e000 {
354 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 354 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
355 reg = <0x7000e000 0x100>; 355 reg = <0x7000e000 0x100>;
356 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 356 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&tegra_car TEGRA114_CLK_RTC>; 357 clocks = <&tegra_car TEGRA114_CLK_RTC>;
358 }; 358 };
359 359
360 kbc { 360 kbc@7000e200 {
361 compatible = "nvidia,tegra114-kbc"; 361 compatible = "nvidia,tegra114-kbc";
362 reg = <0x7000e200 0x100>; 362 reg = <0x7000e200 0x100>;
363 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 363 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -367,14 +367,14 @@
367 status = "disabled"; 367 status = "disabled";
368 }; 368 };
369 369
370 pmc { 370 pmc@7000e400 {
371 compatible = "nvidia,tegra114-pmc"; 371 compatible = "nvidia,tegra114-pmc";
372 reg = <0x7000e400 0x400>; 372 reg = <0x7000e400 0x400>;
373 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 373 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>;
374 clock-names = "pclk", "clk32k_in"; 374 clock-names = "pclk", "clk32k_in";
375 }; 375 };
376 376
377 iommu { 377 iommu@70019010 {
378 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; 378 compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu";
379 reg = <0x70019010 0x02c 379 reg = <0x70019010 0x02c
380 0x700191f0 0x010 380 0x700191f0 0x010
@@ -385,7 +385,7 @@
385 nvidia,ahb = <&ahb>; 385 nvidia,ahb = <&ahb>;
386 }; 386 };
387 387
388 ahub { 388 ahub@70080000 {
389 compatible = "nvidia,tegra114-ahub"; 389 compatible = "nvidia,tegra114-ahub";
390 reg = <0x70080000 0x200>, 390 reg = <0x70080000 0x200>,
391 <0x70080200 0x100>, 391 <0x70080200 0x100>,
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index d5c9bca01232..f20fc9794e89 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -8,8 +8,8 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x { 11 host1x@50000000 {
12 hdmi { 12 hdmi@54280000 {
13 vdd-supply = <&hdmi_vdd_reg>; 13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>; 14 pll-supply = <&hdmi_pll_reg>;
15 15
@@ -19,7 +19,7 @@
19 }; 19 };
20 }; 20 };
21 21
22 pinmux { 22 pinmux@70000014 {
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>; 24 pinctrl-0 = <&state_default>;
25 25
@@ -362,7 +362,7 @@
362 }; 362 };
363 }; 363 };
364 364
365 pmc { 365 pmc@7000e400 {
366 nvidia,suspend-mode = <1>; 366 nvidia,suspend-mode = <1>;
367 nvidia,cpu-pwr-good-time = <5000>; 367 nvidia,cpu-pwr-good-time = <5000>;
368 nvidia,cpu-pwr-off-time = <5000>; 368 nvidia,cpu-pwr-off-time = <5000>;
@@ -442,7 +442,7 @@
442 }; 442 };
443 }; 443 };
444 444
445 ac97: ac97 { 445 ac97: ac97@70002000 {
446 status = "okay"; 446 status = "okay";
447 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0) 447 nvidia,codec-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
448 GPIO_ACTIVE_HIGH>; 448 GPIO_ACTIVE_HIGH>;
@@ -471,7 +471,7 @@
471 #address-cells = <1>; 471 #address-cells = <1>;
472 #size-cells = <0>; 472 #size-cells = <0>;
473 473
474 clk32k_in: clock { 474 clk32k_in: clock@0 {
475 compatible = "fixed-clock"; 475 compatible = "fixed-clock";
476 reg=<0>; 476 reg=<0>;
477 #clock-cells = <0>; 477 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index e156ab30e763..b9c6f67e87ef 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -10,8 +10,8 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x { 13 host1x@50000000 {
14 hdmi { 14 hdmi@54280000 {
15 status = "okay"; 15 status = "okay";
16 16
17 vdd-supply = <&hdmi_vdd_reg>; 17 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +23,7 @@
23 }; 23 };
24 }; 24 };
25 25
26 pinmux { 26 pinmux@70000014 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 28 pinctrl-0 = <&state_default>;
29 29
@@ -415,7 +415,7 @@
415 }; 415 };
416 }; 416 };
417 417
418 pmc { 418 pmc@7000e400 {
419 nvidia,invert-interrupt; 419 nvidia,invert-interrupt;
420 nvidia,suspend-mode = <1>; 420 nvidia,suspend-mode = <1>;
421 nvidia,cpu-pwr-good-time = <5000>; 421 nvidia,cpu-pwr-good-time = <5000>;
@@ -425,7 +425,7 @@
425 nvidia,sys-clock-req-active-high; 425 nvidia,sys-clock-req-active-high;
426 }; 426 };
427 427
428 pcie-controller { 428 pcie-controller@80003000 {
429 pex-clk-supply = <&pci_clk_reg>; 429 pex-clk-supply = <&pci_clk_reg>;
430 vdd-supply = <&pci_vdd_reg>; 430 vdd-supply = <&pci_vdd_reg>;
431 status = "okay"; 431 status = "okay";
@@ -488,7 +488,7 @@
488 #address-cells = <1>; 488 #address-cells = <1>;
489 #size-cells = <0>; 489 #size-cells = <0>;
490 490
491 clk32k_in: clock { 491 clk32k_in: clock@0 {
492 compatible = "fixed-clock"; 492 compatible = "fixed-clock";
493 reg=<0>; 493 reg=<0>;
494 #clock-cells = <0>; 494 #clock-cells = <0>;
@@ -507,7 +507,7 @@
507 }; 507 };
508 }; 508 };
509 509
510 kbc { 510 kbc@7000e200 {
511 status = "okay"; 511 status = "okay";
512 nvidia,debounce-delay-ms = <2>; 512 nvidia,debounce-delay-ms = <2>;
513 nvidia,repeat-delay-ms = <160>; 513 nvidia,repeat-delay-ms = <160>;
diff --git a/arch/arm/boot/dts/tegra20-iris-512.dts b/arch/arm/boot/dts/tegra20-iris-512.dts
index f2222bd74eab..770fc66e5fce 100644
--- a/arch/arm/boot/dts/tegra20-iris-512.dts
+++ b/arch/arm/boot/dts/tegra20-iris-512.dts
@@ -6,13 +6,13 @@
6 model = "Toradex Colibri T20 512MB on Iris"; 6 model = "Toradex Colibri T20 512MB on Iris";
7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20"; 7 compatible = "toradex,iris", "toradex,colibri_t20-512", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
14 14
15 pinmux { 15 pinmux@70000014 {
16 state_default: pinmux { 16 state_default: pinmux {
17 hdint { 17 hdint {
18 nvidia,tristate = <0>; 18 nvidia,tristate = <0>;
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 7580578903cf..6d3a4cbc36cc 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -6,7 +6,7 @@
6 model = "Avionic Design Medcom-Wide board"; 6 model = "Avionic Design Medcom-Wide board";
7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,medcom-wide", "ad,tamonten", "nvidia,tegra20";
8 8
9 pwm { 9 pwm@7000a000 {
10 status = "okay"; 10 status = "okay";
11 }; 11 };
12 12
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index e57fb3aefc2a..4b961b1b4252 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -10,8 +10,8 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 host1x { 13 host1x@50000000 {
14 hdmi { 14 hdmi@54280000 {
15 status = "okay"; 15 status = "okay";
16 16
17 vdd-supply = <&hdmi_vdd_reg>; 17 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +23,7 @@
23 }; 23 };
24 }; 24 };
25 25
26 pinmux { 26 pinmux@70000014 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 28 pinctrl-0 = <&state_default>;
29 29
@@ -268,7 +268,7 @@
268 clock-frequency = <100000>; 268 clock-frequency = <100000>;
269 }; 269 };
270 270
271 nvec { 271 nvec@7000c500 {
272 compatible = "nvidia,nvec"; 272 compatible = "nvidia,nvec";
273 reg = <0x7000c500 0x100>; 273 reg = <0x7000c500 0x100>;
274 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 274 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -417,7 +417,7 @@
417 }; 417 };
418 }; 418 };
419 419
420 pmc { 420 pmc@7000e400 {
421 nvidia,invert-interrupt; 421 nvidia,invert-interrupt;
422 nvidia,suspend-mode = <1>; 422 nvidia,suspend-mode = <1>;
423 nvidia,cpu-pwr-good-time = <2000>; 423 nvidia,cpu-pwr-good-time = <2000>;
@@ -474,7 +474,7 @@
474 #address-cells = <1>; 474 #address-cells = <1>;
475 #size-cells = <0>; 475 #size-cells = <0>;
476 476
477 clk32k_in: clock { 477 clk32k_in: clock@0 {
478 compatible = "fixed-clock"; 478 compatible = "fixed-clock";
479 reg=<0>; 479 reg=<0>;
480 #clock-cells = <0>; 480 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index d7a358a6a647..29051a2ae0ae 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -6,8 +6,8 @@
6 model = "Avionic Design Plutux board"; 6 model = "Avionic Design Plutux board";
7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,plutux", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 315aae26c3cd..01442fc257de 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -10,8 +10,8 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x { 13 host1x@50000000 {
14 hdmi { 14 hdmi@54280000 {
15 status = "okay"; 15 status = "okay";
16 16
17 vdd-supply = <&hdmi_vdd_reg>; 17 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +23,7 @@
23 }; 23 };
24 }; 24 };
25 25
26 pinmux { 26 pinmux@70000014 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 28 pinctrl-0 = <&state_default>;
29 29
@@ -516,7 +516,7 @@
516 }; 516 };
517 }; 517 };
518 518
519 pmc { 519 pmc@7000e400 {
520 nvidia,invert-interrupt; 520 nvidia,invert-interrupt;
521 nvidia,suspend-mode = <1>; 521 nvidia,suspend-mode = <1>;
522 nvidia,cpu-pwr-good-time = <5000>; 522 nvidia,cpu-pwr-good-time = <5000>;
@@ -621,7 +621,7 @@
621 #address-cells = <1>; 621 #address-cells = <1>;
622 #size-cells = <0>; 622 #size-cells = <0>;
623 623
624 clk32k_in: clock { 624 clk32k_in: clock@0 {
625 compatible = "fixed-clock"; 625 compatible = "fixed-clock";
626 reg=<0>; 626 reg=<0>;
627 #clock-cells = <0>; 627 #clock-cells = <0>;
@@ -649,7 +649,7 @@
649 }; 649 };
650 }; 650 };
651 651
652 kbc { 652 kbc@7000e200 {
653 status = "okay"; 653 status = "okay";
654 nvidia,debounce-delay-ms = <32>; 654 nvidia,debounce-delay-ms = <32>;
655 nvidia,repeat-delay-ms = <160>; 655 nvidia,repeat-delay-ms = <160>;
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 7726dab3d08d..02dbc6965fdc 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -8,8 +8,8 @@
8 reg = <0x00000000 0x20000000>; 8 reg = <0x00000000 0x20000000>;
9 }; 9 };
10 10
11 host1x { 11 host1x@50000000 {
12 hdmi { 12 hdmi@54280000 {
13 vdd-supply = <&hdmi_vdd_reg>; 13 vdd-supply = <&hdmi_vdd_reg>;
14 pll-supply = <&hdmi_pll_reg>; 14 pll-supply = <&hdmi_pll_reg>;
15 15
@@ -19,7 +19,7 @@
19 }; 19 };
20 }; 20 };
21 21
22 pinmux { 22 pinmux@70000014 {
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&state_default>; 24 pinctrl-0 = <&state_default>;
25 25
@@ -457,7 +457,7 @@
457 }; 457 };
458 }; 458 };
459 459
460 pmc { 460 pmc@7000e400 {
461 nvidia,invert-interrupt; 461 nvidia,invert-interrupt;
462 nvidia,suspend-mode = <1>; 462 nvidia,suspend-mode = <1>;
463 nvidia,cpu-pwr-good-time = <5000>; 463 nvidia,cpu-pwr-good-time = <5000>;
@@ -467,7 +467,7 @@
467 nvidia,sys-clock-req-active-high; 467 nvidia,sys-clock-req-active-high;
468 }; 468 };
469 469
470 pcie-controller { 470 pcie-controller@80003000 {
471 pex-clk-supply = <&pci_clk_reg>; 471 pex-clk-supply = <&pci_clk_reg>;
472 vdd-supply = <&pci_vdd_reg>; 472 vdd-supply = <&pci_vdd_reg>;
473 }; 473 };
@@ -492,7 +492,7 @@
492 #address-cells = <1>; 492 #address-cells = <1>;
493 #size-cells = <0>; 493 #size-cells = <0>;
494 494
495 clk32k_in: clock { 495 clk32k_in: clock@0 {
496 compatible = "fixed-clock"; 496 compatible = "fixed-clock";
497 reg=<0>; 497 reg=<0>;
498 #clock-cells = <0>; 498 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 3ada3cb67f07..890562c667fb 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -6,8 +6,8 @@
6 model = "Avionic Design Tamonten Evaluation Carrier"; 6 model = "Avionic Design Tamonten Evaluation Carrier";
7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20"; 7 compatible = "ad,tec", "ad,tamonten", "nvidia,tegra20";
8 8
9 host1x { 9 host1x@50000000 {
10 hdmi { 10 hdmi@54280000 {
11 status = "okay"; 11 status = "okay";
12 }; 12 };
13 }; 13 };
@@ -32,7 +32,7 @@
32 }; 32 };
33 }; 33 };
34 34
35 pcie-controller { 35 pcie-controller@80003000 {
36 status = "okay"; 36 status = "okay";
37 37
38 pci@1,0 { 38 pci@1,0 {
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 78deea5c0d21..eab7cd25dd55 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -10,8 +10,8 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x { 13 host1x@50000000 {
14 hdmi { 14 hdmi@54280000 {
15 status = "okay"; 15 status = "okay";
16 16
17 vdd-supply = <&hdmi_vdd_reg>; 17 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +23,7 @@
23 }; 23 };
24 }; 24 };
25 25
26 pinmux { 26 pinmux@70000014 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 28 pinctrl-0 = <&state_default>;
29 29
@@ -301,7 +301,7 @@
301 }; 301 };
302 }; 302 };
303 303
304 pmc { 304 pmc@7000e400 {
305 nvidia,suspend-mode = <1>; 305 nvidia,suspend-mode = <1>;
306 nvidia,cpu-pwr-good-time = <5000>; 306 nvidia,cpu-pwr-good-time = <5000>;
307 nvidia,cpu-pwr-off-time = <5000>; 307 nvidia,cpu-pwr-off-time = <5000>;
@@ -310,7 +310,7 @@
310 nvidia,sys-clock-req-active-high; 310 nvidia,sys-clock-req-active-high;
311 }; 311 };
312 312
313 pcie-controller { 313 pcie-controller@80003000 {
314 status = "okay"; 314 status = "okay";
315 pex-clk-supply = <&pci_clk_reg>; 315 pex-clk-supply = <&pci_clk_reg>;
316 vdd-supply = <&pci_vdd_reg>; 316 vdd-supply = <&pci_vdd_reg>;
@@ -366,7 +366,7 @@
366 #address-cells = <1>; 366 #address-cells = <1>;
367 #size-cells = <0>; 367 #size-cells = <0>;
368 368
369 clk32k_in: clock { 369 clk32k_in: clock@0 {
370 compatible = "fixed-clock"; 370 compatible = "fixed-clock";
371 reg=<0>; 371 reg=<0>;
372 #clock-cells = <0>; 372 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index aab872cd0530..bce764099853 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -10,8 +10,8 @@
10 reg = <0x00000000 0x40000000>; 10 reg = <0x00000000 0x40000000>;
11 }; 11 };
12 12
13 host1x { 13 host1x@50000000 {
14 hdmi { 14 hdmi@54280000 {
15 status = "okay"; 15 status = "okay";
16 16
17 vdd-supply = <&hdmi_vdd_reg>; 17 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +23,7 @@
23 }; 23 };
24 }; 24 };
25 25
26 pinmux { 26 pinmux@70000014 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 28 pinctrl-0 = <&state_default>;
29 29
@@ -492,7 +492,7 @@
492 }; 492 };
493 }; 493 };
494 494
495 pmc { 495 pmc@7000e400 {
496 nvidia,invert-interrupt; 496 nvidia,invert-interrupt;
497 nvidia,suspend-mode = <1>; 497 nvidia,suspend-mode = <1>;
498 nvidia,cpu-pwr-good-time = <2000>; 498 nvidia,cpu-pwr-good-time = <2000>;
@@ -556,7 +556,7 @@
556 #address-cells = <1>; 556 #address-cells = <1>;
557 #size-cells = <0>; 557 #size-cells = <0>;
558 558
559 clk32k_in: clock { 559 clk32k_in: clock@0 {
560 compatible = "fixed-clock"; 560 compatible = "fixed-clock";
561 reg=<0>; 561 reg=<0>;
562 #clock-cells = <0>; 562 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index d33a73cf167c..b047621b95d2 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -10,8 +10,8 @@
10 reg = <0x00000000 0x20000000>; 10 reg = <0x00000000 0x20000000>;
11 }; 11 };
12 12
13 host1x { 13 host1x@50000000 {
14 hdmi { 14 hdmi@54280000 {
15 status = "okay"; 15 status = "okay";
16 16
17 vdd-supply = <&hdmi_vdd_reg>; 17 vdd-supply = <&hdmi_vdd_reg>;
@@ -23,7 +23,7 @@
23 }; 23 };
24 }; 24 };
25 25
26 pinmux { 26 pinmux@70000014 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&state_default>; 28 pinctrl-0 = <&state_default>;
29 29
@@ -495,7 +495,7 @@
495 }; 495 };
496 }; 496 };
497 497
498 pmc { 498 pmc@7000e400 {
499 nvidia,invert-interrupt; 499 nvidia,invert-interrupt;
500 nvidia,suspend-mode = <1>; 500 nvidia,suspend-mode = <1>;
501 nvidia,cpu-pwr-good-time = <2000>; 501 nvidia,cpu-pwr-good-time = <2000>;
@@ -543,7 +543,7 @@
543 #address-cells = <1>; 543 #address-cells = <1>;
544 #size-cells = <0>; 544 #size-cells = <0>;
545 545
546 clk32k_in: clock { 546 clk32k_in: clock@0 {
547 compatible = "fixed-clock"; 547 compatible = "fixed-clock";
548 reg=<0>; 548 reg=<0>;
549 #clock-cells = <0>; 549 #clock-cells = <0>;
@@ -551,7 +551,7 @@
551 }; 551 };
552 }; 552 };
553 553
554 kbc { 554 kbc@7000e200 {
555 status = "okay"; 555 status = "okay";
556 nvidia,debounce-delay-ms = <20>; 556 nvidia,debounce-delay-ms = <20>;
557 nvidia,repeat-delay-ms = <160>; 557 nvidia,repeat-delay-ms = <160>;
@@ -569,7 +569,7 @@
569 #address-cells = <1>; 569 #address-cells = <1>;
570 #size-cells = <0>; 570 #size-cells = <0>;
571 571
572 usb0_vbus_reg: regulator { 572 usb0_vbus_reg: regulator@0 {
573 compatible = "regulator-fixed"; 573 compatible = "regulator-fixed";
574 reg = <0>; 574 reg = <0>;
575 regulator-name = "usb0_vbus"; 575 regulator-name = "usb0_vbus";
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c90d0aac3afe..648c494e927f 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -16,7 +16,7 @@
16 serial4 = &uarte; 16 serial4 = &uarte;
17 }; 17 };
18 18
19 host1x { 19 host1x@50000000 {
20 compatible = "nvidia,tegra20-host1x", "simple-bus"; 20 compatible = "nvidia,tegra20-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>; 21 reg = <0x50000000 0x00024000>;
22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -30,7 +30,7 @@
30 30
31 ranges = <0x54000000 0x54000000 0x04000000>; 31 ranges = <0x54000000 0x54000000 0x04000000>;
32 32
33 mpe { 33 mpe@54040000 {
34 compatible = "nvidia,tegra20-mpe"; 34 compatible = "nvidia,tegra20-mpe";
35 reg = <0x54040000 0x00040000>; 35 reg = <0x54040000 0x00040000>;
36 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 36 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -39,7 +39,7 @@
39 reset-names = "mpe"; 39 reset-names = "mpe";
40 }; 40 };
41 41
42 vi { 42 vi@54080000 {
43 compatible = "nvidia,tegra20-vi"; 43 compatible = "nvidia,tegra20-vi";
44 reg = <0x54080000 0x00040000>; 44 reg = <0x54080000 0x00040000>;
45 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 45 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -48,7 +48,7 @@
48 reset-names = "vi"; 48 reset-names = "vi";
49 }; 49 };
50 50
51 epp { 51 epp@540c0000 {
52 compatible = "nvidia,tegra20-epp"; 52 compatible = "nvidia,tegra20-epp";
53 reg = <0x540c0000 0x00040000>; 53 reg = <0x540c0000 0x00040000>;
54 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 54 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -57,7 +57,7 @@
57 reset-names = "epp"; 57 reset-names = "epp";
58 }; 58 };
59 59
60 isp { 60 isp@54100000 {
61 compatible = "nvidia,tegra20-isp"; 61 compatible = "nvidia,tegra20-isp";
62 reg = <0x54100000 0x00040000>; 62 reg = <0x54100000 0x00040000>;
63 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 63 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -66,7 +66,7 @@
66 reset-names = "isp"; 66 reset-names = "isp";
67 }; 67 };
68 68
69 gr2d { 69 gr2d@54140000 {
70 compatible = "nvidia,tegra20-gr2d"; 70 compatible = "nvidia,tegra20-gr2d";
71 reg = <0x54140000 0x00040000>; 71 reg = <0x54140000 0x00040000>;
72 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 72 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -75,9 +75,9 @@
75 reset-names = "2d"; 75 reset-names = "2d";
76 }; 76 };
77 77
78 gr3d { 78 gr3d@54140000 {
79 compatible = "nvidia,tegra20-gr3d"; 79 compatible = "nvidia,tegra20-gr3d";
80 reg = <0x54180000 0x00040000>; 80 reg = <0x54140000 0x00040000>;
81 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 81 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
82 resets = <&tegra_car 24>; 82 resets = <&tegra_car 24>;
83 reset-names = "3d"; 83 reset-names = "3d";
@@ -113,7 +113,7 @@
113 }; 113 };
114 }; 114 };
115 115
116 hdmi { 116 hdmi@54280000 {
117 compatible = "nvidia,tegra20-hdmi"; 117 compatible = "nvidia,tegra20-hdmi";
118 reg = <0x54280000 0x00040000>; 118 reg = <0x54280000 0x00040000>;
119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -125,7 +125,7 @@
125 status = "disabled"; 125 status = "disabled";
126 }; 126 };
127 127
128 tvo { 128 tvo@542c0000 {
129 compatible = "nvidia,tegra20-tvo"; 129 compatible = "nvidia,tegra20-tvo";
130 reg = <0x542c0000 0x00040000>; 130 reg = <0x542c0000 0x00040000>;
131 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 131 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -133,9 +133,9 @@
133 status = "disabled"; 133 status = "disabled";
134 }; 134 };
135 135
136 dsi { 136 dsi@542c0000 {
137 compatible = "nvidia,tegra20-dsi"; 137 compatible = "nvidia,tegra20-dsi";
138 reg = <0x54300000 0x00040000>; 138 reg = <0x542c0000 0x00040000>;
139 clocks = <&tegra_car TEGRA20_CLK_DSI>; 139 clocks = <&tegra_car TEGRA20_CLK_DSI>;
140 resets = <&tegra_car 48>; 140 resets = <&tegra_car 48>;
141 reset-names = "dsi"; 141 reset-names = "dsi";
@@ -151,7 +151,7 @@
151 clocks = <&tegra_car TEGRA20_CLK_TWD>; 151 clocks = <&tegra_car TEGRA20_CLK_TWD>;
152 }; 152 };
153 153
154 intc: interrupt-controller { 154 intc: interrupt-controller@50041000 {
155 compatible = "arm,cortex-a9-gic"; 155 compatible = "arm,cortex-a9-gic";
156 reg = <0x50041000 0x1000 156 reg = <0x50041000 0x1000
157 0x50040100 0x0100>; 157 0x50040100 0x0100>;
@@ -159,7 +159,7 @@
159 #interrupt-cells = <3>; 159 #interrupt-cells = <3>;
160 }; 160 };
161 161
162 cache-controller { 162 cache-controller@50043000 {
163 compatible = "arm,pl310-cache"; 163 compatible = "arm,pl310-cache";
164 reg = <0x50043000 0x1000>; 164 reg = <0x50043000 0x1000>;
165 arm,data-latency = <5 5 2>; 165 arm,data-latency = <5 5 2>;
@@ -178,14 +178,14 @@
178 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 178 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
179 }; 179 };
180 180
181 tegra_car: clock { 181 tegra_car: clock@60006000 {
182 compatible = "nvidia,tegra20-car"; 182 compatible = "nvidia,tegra20-car";
183 reg = <0x60006000 0x1000>; 183 reg = <0x60006000 0x1000>;
184 #clock-cells = <1>; 184 #clock-cells = <1>;
185 #reset-cells = <1>; 185 #reset-cells = <1>;
186 }; 186 };
187 187
188 apbdma: dma { 188 apbdma: dma@6000a000 {
189 compatible = "nvidia,tegra20-apbdma"; 189 compatible = "nvidia,tegra20-apbdma";
190 reg = <0x6000a000 0x1200>; 190 reg = <0x6000a000 0x1200>;
191 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 191 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -210,12 +210,12 @@
210 #dma-cells = <1>; 210 #dma-cells = <1>;
211 }; 211 };
212 212
213 ahb { 213 ahb@6000c004 {
214 compatible = "nvidia,tegra20-ahb"; 214 compatible = "nvidia,tegra20-ahb";
215 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ 215 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
216 }; 216 };
217 217
218 gpio: gpio { 218 gpio: gpio@6000d000 {
219 compatible = "nvidia,tegra20-gpio"; 219 compatible = "nvidia,tegra20-gpio";
220 reg = <0x6000d000 0x1000>; 220 reg = <0x6000d000 0x1000>;
221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -231,7 +231,7 @@
231 interrupt-controller; 231 interrupt-controller;
232 }; 232 };
233 233
234 pinmux: pinmux { 234 pinmux: pinmux@70000014 {
235 compatible = "nvidia,tegra20-pinmux"; 235 compatible = "nvidia,tegra20-pinmux";
236 reg = <0x70000014 0x10 /* Tri-state registers */ 236 reg = <0x70000014 0x10 /* Tri-state registers */
237 0x70000080 0x20 /* Mux registers */ 237 0x70000080 0x20 /* Mux registers */
@@ -239,12 +239,12 @@
239 0x70000868 0xa8>; /* Pad control registers */ 239 0x70000868 0xa8>; /* Pad control registers */
240 }; 240 };
241 241
242 das { 242 das@70000c00 {
243 compatible = "nvidia,tegra20-das"; 243 compatible = "nvidia,tegra20-das";
244 reg = <0x70000c00 0x80>; 244 reg = <0x70000c00 0x80>;
245 }; 245 };
246 246
247 tegra_ac97: ac97 { 247 tegra_ac97: ac97@70002000 {
248 compatible = "nvidia,tegra20-ac97"; 248 compatible = "nvidia,tegra20-ac97";
249 reg = <0x70002000 0x200>; 249 reg = <0x70002000 0x200>;
250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -352,7 +352,7 @@
352 status = "disabled"; 352 status = "disabled";
353 }; 353 };
354 354
355 pwm: pwm { 355 pwm: pwm@7000a000 {
356 compatible = "nvidia,tegra20-pwm"; 356 compatible = "nvidia,tegra20-pwm";
357 reg = <0x7000a000 0x100>; 357 reg = <0x7000a000 0x100>;
358 #pwm-cells = <2>; 358 #pwm-cells = <2>;
@@ -362,7 +362,7 @@
362 status = "disabled"; 362 status = "disabled";
363 }; 363 };
364 364
365 rtc { 365 rtc@7000e000 {
366 compatible = "nvidia,tegra20-rtc"; 366 compatible = "nvidia,tegra20-rtc";
367 reg = <0x7000e000 0x100>; 367 reg = <0x7000e000 0x100>;
368 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 368 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +503,7 @@
503 status = "disabled"; 503 status = "disabled";
504 }; 504 };
505 505
506 kbc { 506 kbc@7000e200 {
507 compatible = "nvidia,tegra20-kbc"; 507 compatible = "nvidia,tegra20-kbc";
508 reg = <0x7000e200 0x100>; 508 reg = <0x7000e200 0x100>;
509 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 509 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -513,7 +513,7 @@
513 status = "disabled"; 513 status = "disabled";
514 }; 514 };
515 515
516 pmc { 516 pmc@7000e400 {
517 compatible = "nvidia,tegra20-pmc"; 517 compatible = "nvidia,tegra20-pmc";
518 reg = <0x7000e400 0x400>; 518 reg = <0x7000e400 0x400>;
519 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 519 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
@@ -527,7 +527,7 @@
527 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 527 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
528 }; 528 };
529 529
530 iommu { 530 iommu@7000f024 {
531 compatible = "nvidia,tegra20-gart"; 531 compatible = "nvidia,tegra20-gart";
532 reg = <0x7000f024 0x00000018 /* controller registers */ 532 reg = <0x7000f024 0x00000018 /* controller registers */
533 0x58000000 0x02000000>; /* GART aperture */ 533 0x58000000 0x02000000>; /* GART aperture */
@@ -540,7 +540,7 @@
540 #size-cells = <0>; 540 #size-cells = <0>;
541 }; 541 };
542 542
543 pcie-controller { 543 pcie-controller@80003000 {
544 compatible = "nvidia,tegra20-pcie"; 544 compatible = "nvidia,tegra20-pcie";
545 device_type = "pci"; 545 device_type = "pci";
546 reg = <0x80003000 0x00000800 /* PADS registers */ 546 reg = <0x80003000 0x00000800 /* PADS registers */
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 08cad696e89f..bc28e27e4fe7 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -10,7 +10,7 @@
10 reg = <0x80000000 0x7ff00000>; 10 reg = <0x80000000 0x7ff00000>;
11 }; 11 };
12 12
13 pcie-controller { 13 pcie-controller@00003000 {
14 status = "okay"; 14 status = "okay";
15 pex-clk-supply = <&sys_3v3_pexs_reg>; 15 pex-clk-supply = <&sys_3v3_pexs_reg>;
16 vdd-supply = <&ldo1_reg>; 16 vdd-supply = <&ldo1_reg>;
@@ -31,8 +31,8 @@
31 }; 31 };
32 }; 32 };
33 33
34 host1x { 34 host1x@50000000 {
35 hdmi { 35 hdmi@54280000 {
36 status = "okay"; 36 status = "okay";
37 37
38 vdd-supply = <&sys_3v3_reg>; 38 vdd-supply = <&sys_3v3_reg>;
@@ -44,7 +44,7 @@
44 }; 44 };
45 }; 45 };
46 46
47 pinmux { 47 pinmux@70000868 {
48 pinctrl-names = "default"; 48 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>; 49 pinctrl-0 = <&state_default>;
50 50
@@ -159,7 +159,7 @@
159 status = "okay"; 159 status = "okay";
160 clock-frequency = <100000>; 160 clock-frequency = <100000>;
161 161
162 rt5640: rt5640 { 162 rt5640: rt5640@1c {
163 compatible = "realtek,rt5640"; 163 compatible = "realtek,rt5640";
164 reg = <0x1c>; 164 reg = <0x1c>;
165 interrupt-parent = <&gpio>; 165 interrupt-parent = <&gpio>;
@@ -168,7 +168,7 @@
168 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>; 168 <&gpio TEGRA_GPIO(X, 2) GPIO_ACTIVE_HIGH>;
169 }; 169 };
170 170
171 tps62361 { 171 tps62361@60 {
172 compatible = "ti,tps62361"; 172 compatible = "ti,tps62361";
173 reg = <0x60>; 173 reg = <0x60>;
174 174
@@ -296,13 +296,13 @@
296 }; 296 };
297 }; 297 };
298 298
299 ahub { 299 ahub@70080000 {
300 i2s@70080400 { 300 i2s@70080400 {
301 status = "okay"; 301 status = "okay";
302 }; 302 };
303 }; 303 };
304 304
305 pmc { 305 pmc@7000e400 {
306 status = "okay"; 306 status = "okay";
307 nvidia,invert-interrupt; 307 nvidia,invert-interrupt;
308 nvidia,suspend-mode = <1>; 308 nvidia,suspend-mode = <1>;
@@ -342,7 +342,7 @@
342 #address-cells = <1>; 342 #address-cells = <1>;
343 #size-cells = <0>; 343 #size-cells = <0>;
344 344
345 clk32k_in: clock { 345 clk32k_in: clock@0 {
346 compatible = "fixed-clock"; 346 compatible = "fixed-clock";
347 reg=<0>; 347 reg=<0>;
348 #clock-cells = <0>; 348 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 5ea7dfa4d9fa..b159a41c7338 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -31,7 +31,7 @@
31 reg = <0x80000000 0x40000000>; 31 reg = <0x80000000 0x40000000>;
32 }; 32 };
33 33
34 pcie-controller { 34 pcie-controller@00003000 {
35 status = "okay"; 35 status = "okay";
36 pex-clk-supply = <&pex_hvdd_3v3_reg>; 36 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>; 37 vdd-supply = <&ldo1_reg>;
@@ -51,7 +51,7 @@
51 }; 51 };
52 }; 52 };
53 53
54 pinmux { 54 pinmux@70000868 {
55 pinctrl-names = "default"; 55 pinctrl-names = "default";
56 pinctrl-0 = <&state_default>; 56 pinctrl-0 = <&state_default>;
57 57
@@ -302,7 +302,7 @@
302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>; 302 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
303 }; 303 };
304 304
305 tps62361 { 305 tps62361@60 {
306 compatible = "ti,tps62361"; 306 compatible = "ti,tps62361";
307 reg = <0x60>; 307 reg = <0x60>;
308 308
@@ -326,13 +326,13 @@
326 }; 326 };
327 }; 327 };
328 328
329 ahub { 329 ahub@70080000 {
330 i2s@70080400 { 330 i2s@70080400 {
331 status = "okay"; 331 status = "okay";
332 }; 332 };
333 }; 333 };
334 334
335 pmc { 335 pmc@7000e400 {
336 status = "okay"; 336 status = "okay";
337 nvidia,invert-interrupt; 337 nvidia,invert-interrupt;
338 nvidia,suspend-mode = <1>; 338 nvidia,suspend-mode = <1>;
@@ -372,7 +372,7 @@
372 #address-cells = <1>; 372 #address-cells = <1>;
373 #size-cells = <0>; 373 #size-cells = <0>;
374 374
375 clk32k_in: clock { 375 clk32k_in: clock@0 {
376 compatible = "fixed-clock"; 376 compatible = "fixed-clock";
377 reg=<0>; 377 reg=<0>;
378 #clock-cells = <0>; 378 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 31259b09e7cc..829eb4b5091d 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -16,7 +16,7 @@
16 serial4 = &uarte; 16 serial4 = &uarte;
17 }; 17 };
18 18
19 pcie-controller { 19 pcie-controller@00003000 {
20 compatible = "nvidia,tegra30-pcie"; 20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci"; 21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */ 22 reg = <0x00003000 0x00000800 /* PADS registers */
@@ -89,7 +89,7 @@
89 }; 89 };
90 }; 90 };
91 91
92 host1x { 92 host1x@50000000 {
93 compatible = "nvidia,tegra30-host1x", "simple-bus"; 93 compatible = "nvidia,tegra30-host1x", "simple-bus";
94 reg = <0x50000000 0x00024000>; 94 reg = <0x50000000 0x00024000>;
95 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 95 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -103,7 +103,7 @@
103 103
104 ranges = <0x54000000 0x54000000 0x04000000>; 104 ranges = <0x54000000 0x54000000 0x04000000>;
105 105
106 mpe { 106 mpe@54040000 {
107 compatible = "nvidia,tegra30-mpe"; 107 compatible = "nvidia,tegra30-mpe";
108 reg = <0x54040000 0x00040000>; 108 reg = <0x54040000 0x00040000>;
109 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 109 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
@@ -112,7 +112,7 @@
112 reset-names = "mpe"; 112 reset-names = "mpe";
113 }; 113 };
114 114
115 vi { 115 vi@54080000 {
116 compatible = "nvidia,tegra30-vi"; 116 compatible = "nvidia,tegra30-vi";
117 reg = <0x54080000 0x00040000>; 117 reg = <0x54080000 0x00040000>;
118 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 118 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
@@ -121,7 +121,7 @@
121 reset-names = "vi"; 121 reset-names = "vi";
122 }; 122 };
123 123
124 epp { 124 epp@540c0000 {
125 compatible = "nvidia,tegra30-epp"; 125 compatible = "nvidia,tegra30-epp";
126 reg = <0x540c0000 0x00040000>; 126 reg = <0x540c0000 0x00040000>;
127 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 127 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
@@ -130,7 +130,7 @@
130 reset-names = "epp"; 130 reset-names = "epp";
131 }; 131 };
132 132
133 isp { 133 isp@54100000 {
134 compatible = "nvidia,tegra30-isp"; 134 compatible = "nvidia,tegra30-isp";
135 reg = <0x54100000 0x00040000>; 135 reg = <0x54100000 0x00040000>;
136 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 136 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -139,7 +139,7 @@
139 reset-names = "isp"; 139 reset-names = "isp";
140 }; 140 };
141 141
142 gr2d { 142 gr2d@54140000 {
143 compatible = "nvidia,tegra30-gr2d"; 143 compatible = "nvidia,tegra30-gr2d";
144 reg = <0x54140000 0x00040000>; 144 reg = <0x54140000 0x00040000>;
145 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 145 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
@@ -148,7 +148,7 @@
148 clocks = <&tegra_car TEGRA30_CLK_GR2D>; 148 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
149 }; 149 };
150 150
151 gr3d { 151 gr3d@54180000 {
152 compatible = "nvidia,tegra30-gr3d"; 152 compatible = "nvidia,tegra30-gr3d";
153 reg = <0x54180000 0x00040000>; 153 reg = <0x54180000 0x00040000>;
154 clocks = <&tegra_car TEGRA30_CLK_GR3D 154 clocks = <&tegra_car TEGRA30_CLK_GR3D
@@ -189,7 +189,7 @@
189 }; 189 };
190 }; 190 };
191 191
192 hdmi { 192 hdmi@54280000 {
193 compatible = "nvidia,tegra30-hdmi"; 193 compatible = "nvidia,tegra30-hdmi";
194 reg = <0x54280000 0x00040000>; 194 reg = <0x54280000 0x00040000>;
195 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 195 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -201,7 +201,7 @@
201 status = "disabled"; 201 status = "disabled";
202 }; 202 };
203 203
204 tvo { 204 tvo@542c0000 {
205 compatible = "nvidia,tegra30-tvo"; 205 compatible = "nvidia,tegra30-tvo";
206 reg = <0x542c0000 0x00040000>; 206 reg = <0x542c0000 0x00040000>;
207 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 207 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -209,7 +209,7 @@
209 status = "disabled"; 209 status = "disabled";
210 }; 210 };
211 211
212 dsi { 212 dsi@54300000 {
213 compatible = "nvidia,tegra30-dsi"; 213 compatible = "nvidia,tegra30-dsi";
214 reg = <0x54300000 0x00040000>; 214 reg = <0x54300000 0x00040000>;
215 clocks = <&tegra_car TEGRA30_CLK_DSIA>; 215 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
@@ -227,7 +227,7 @@
227 clocks = <&tegra_car TEGRA30_CLK_TWD>; 227 clocks = <&tegra_car TEGRA30_CLK_TWD>;
228 }; 228 };
229 229
230 intc: interrupt-controller { 230 intc: interrupt-controller@50041000 {
231 compatible = "arm,cortex-a9-gic"; 231 compatible = "arm,cortex-a9-gic";
232 reg = <0x50041000 0x1000 232 reg = <0x50041000 0x1000
233 0x50040100 0x0100>; 233 0x50040100 0x0100>;
@@ -235,7 +235,7 @@
235 #interrupt-cells = <3>; 235 #interrupt-cells = <3>;
236 }; 236 };
237 237
238 cache-controller { 238 cache-controller@50043000 {
239 compatible = "arm,pl310-cache"; 239 compatible = "arm,pl310-cache";
240 reg = <0x50043000 0x1000>; 240 reg = <0x50043000 0x1000>;
241 arm,data-latency = <6 6 2>; 241 arm,data-latency = <6 6 2>;
@@ -256,14 +256,14 @@
256 clocks = <&tegra_car TEGRA30_CLK_TIMER>; 256 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
257 }; 257 };
258 258
259 tegra_car: clock { 259 tegra_car: clock@60006000 {
260 compatible = "nvidia,tegra30-car"; 260 compatible = "nvidia,tegra30-car";
261 reg = <0x60006000 0x1000>; 261 reg = <0x60006000 0x1000>;
262 #clock-cells = <1>; 262 #clock-cells = <1>;
263 #reset-cells = <1>; 263 #reset-cells = <1>;
264 }; 264 };
265 265
266 apbdma: dma { 266 apbdma: dma@6000a000 {
267 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; 267 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
268 reg = <0x6000a000 0x1400>; 268 reg = <0x6000a000 0x1400>;
269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 269 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -304,12 +304,12 @@
304 #dma-cells = <1>; 304 #dma-cells = <1>;
305 }; 305 };
306 306
307 ahb: ahb { 307 ahb: ahb@6000c004 {
308 compatible = "nvidia,tegra30-ahb"; 308 compatible = "nvidia,tegra30-ahb";
309 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ 309 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
310 }; 310 };
311 311
312 gpio: gpio { 312 gpio: gpio@6000d000 {
313 compatible = "nvidia,tegra30-gpio"; 313 compatible = "nvidia,tegra30-gpio";
314 reg = <0x6000d000 0x1000>; 314 reg = <0x6000d000 0x1000>;
315 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 315 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -326,7 +326,7 @@
326 interrupt-controller; 326 interrupt-controller;
327 }; 327 };
328 328
329 pinmux: pinmux { 329 pinmux: pinmux@70000868 {
330 compatible = "nvidia,tegra30-pinmux"; 330 compatible = "nvidia,tegra30-pinmux";
331 reg = <0x70000868 0xd4 /* Pad control registers */ 331 reg = <0x70000868 0xd4 /* Pad control registers */
332 0x70003000 0x3e4>; /* Mux registers */ 332 0x70003000 0x3e4>; /* Mux registers */
@@ -405,7 +405,7 @@
405 status = "disabled"; 405 status = "disabled";
406 }; 406 };
407 407
408 pwm: pwm { 408 pwm: pwm@7000a000 {
409 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; 409 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
410 reg = <0x7000a000 0x100>; 410 reg = <0x7000a000 0x100>;
411 #pwm-cells = <2>; 411 #pwm-cells = <2>;
@@ -415,7 +415,7 @@
415 status = "disabled"; 415 status = "disabled";
416 }; 416 };
417 417
418 rtc { 418 rtc@7000e000 {
419 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; 419 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
420 reg = <0x7000e000 0x100>; 420 reg = <0x7000e000 0x100>;
421 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 421 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
@@ -586,7 +586,7 @@
586 status = "disabled"; 586 status = "disabled";
587 }; 587 };
588 588
589 kbc { 589 kbc@7000e200 {
590 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; 590 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
591 reg = <0x7000e200 0x100>; 591 reg = <0x7000e200 0x100>;
592 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 592 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -596,14 +596,14 @@
596 status = "disabled"; 596 status = "disabled";
597 }; 597 };
598 598
599 pmc { 599 pmc@7000e400 {
600 compatible = "nvidia,tegra30-pmc"; 600 compatible = "nvidia,tegra30-pmc";
601 reg = <0x7000e400 0x400>; 601 reg = <0x7000e400 0x400>;
602 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; 602 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
603 clock-names = "pclk", "clk32k_in"; 603 clock-names = "pclk", "clk32k_in";
604 }; 604 };
605 605
606 memory-controller { 606 memory-controller@7000f000 {
607 compatible = "nvidia,tegra30-mc"; 607 compatible = "nvidia,tegra30-mc";
608 reg = <0x7000f000 0x010 608 reg = <0x7000f000 0x010
609 0x7000f03c 0x1b4 609 0x7000f03c 0x1b4
@@ -612,7 +612,7 @@
612 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 612 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
613 }; 613 };
614 614
615 iommu { 615 iommu@7000f010 {
616 compatible = "nvidia,tegra30-smmu"; 616 compatible = "nvidia,tegra30-smmu";
617 reg = <0x7000f010 0x02c 617 reg = <0x7000f010 0x02c
618 0x7000f1f0 0x010 618 0x7000f1f0 0x010
@@ -622,7 +622,7 @@
622 nvidia,ahb = <&ahb>; 622 nvidia,ahb = <&ahb>;
623 }; 623 };
624 624
625 ahub { 625 ahub@70080000 {
626 compatible = "nvidia,tegra30-ahub"; 626 compatible = "nvidia,tegra30-ahub";
627 reg = <0x70080000 0x200 627 reg = <0x70080000 0x200
628 0x70080200 0x100>; 628 0x70080200 0x100>;
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-15 01:39:16 -0400