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authorRussell King <rmk+kernel@arm.linux.org.uk>2015-07-15 13:11:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-10-01 09:33:28 -0400
commit5740d27fa5594344ed4d2c18d7ae7bea69002004 (patch)
tree0492fb981e3d3ac7c19b2a83e91d911adb362aa3
parent6908cf755af74b38d67195ee6607976a55f53d95 (diff)
drm/armada: move frame wait into armada_frame
Both the CRTC and overlay frames have their own wait queues. It would make more sense if these were part of the plane - the primary plane for the CRTC and overlay plane for the overlay. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-rw-r--r--drivers/gpu/drm/armada/armada_crtc.c22
-rw-r--r--drivers/gpu/drm/armada/armada_crtc.h4
-rw-r--r--drivers/gpu/drm/armada/armada_overlay.c12
3 files changed, 29 insertions, 9 deletions
diff --git a/drivers/gpu/drm/armada/armada_crtc.c b/drivers/gpu/drm/armada/armada_crtc.c
index e3e6f81593c0..46d932bc7678 100644
--- a/drivers/gpu/drm/armada/armada_crtc.c
+++ b/drivers/gpu/drm/armada/armada_crtc.c
@@ -455,7 +455,7 @@ static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat)
455 if (work) 455 if (work)
456 armada_drm_crtc_complete_frame_work(dcrtc, work); 456 armada_drm_crtc_complete_frame_work(dcrtc, work);
457 457
458 wake_up(&dcrtc->frame_wait); 458 wake_up(&drm_to_armada_plane(dcrtc->crtc.primary)->frame_wait);
459 } 459 }
460} 460}
461 461
@@ -571,7 +571,8 @@ static int armada_drm_crtc_mode_set(struct drm_crtc *crtc,
571 adj->crtc_vtotal, tm, bm); 571 adj->crtc_vtotal, tm, bm);
572 572
573 /* Wait for pending flips to complete */ 573 /* Wait for pending flips to complete */
574 wait_event(dcrtc->frame_wait, !dcrtc->frame_work); 574 wait_event(drm_to_armada_plane(dcrtc->crtc.primary)->frame_wait,
575 !dcrtc->frame_work);
575 576
576 drm_crtc_vblank_off(crtc); 577 drm_crtc_vblank_off(crtc);
577 578
@@ -688,7 +689,8 @@ static int armada_drm_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
688 armada_reg_queue_end(regs, i); 689 armada_reg_queue_end(regs, i);
689 690
690 /* Wait for pending flips to complete */ 691 /* Wait for pending flips to complete */
691 wait_event(dcrtc->frame_wait, !dcrtc->frame_work); 692 wait_event(drm_to_armada_plane(dcrtc->crtc.primary)->frame_wait,
693 !dcrtc->frame_work);
692 694
693 /* Take a reference to the new fb as we're using it */ 695 /* Take a reference to the new fb as we're using it */
694 drm_framebuffer_reference(crtc->primary->fb); 696 drm_framebuffer_reference(crtc->primary->fb);
@@ -1096,6 +1098,13 @@ static const struct drm_plane_funcs armada_primary_plane_funcs = {
1096 .destroy = drm_primary_helper_destroy, 1098 .destroy = drm_primary_helper_destroy,
1097}; 1099};
1098 1100
1101int armada_drm_plane_init(struct armada_plane *plane)
1102{
1103 init_waitqueue_head(&plane->frame_wait);
1104
1105 return 0;
1106}
1107
1099static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = { 1108static struct drm_prop_enum_list armada_drm_csc_yuv_enum_list[] = {
1100 { CSC_AUTO, "Auto" }, 1109 { CSC_AUTO, "Auto" },
1101 { CSC_YUV_CCIR601, "CCIR601" }, 1110 { CSC_YUV_CCIR601, "CCIR601" },
@@ -1166,7 +1175,6 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1166 spin_lock_init(&dcrtc->irq_lock); 1175 spin_lock_init(&dcrtc->irq_lock);
1167 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; 1176 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR;
1168 INIT_LIST_HEAD(&dcrtc->vbl_list); 1177 INIT_LIST_HEAD(&dcrtc->vbl_list);
1169 init_waitqueue_head(&dcrtc->frame_wait);
1170 1178
1171 /* Initialize some registers which we don't otherwise set */ 1179 /* Initialize some registers which we don't otherwise set */
1172 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); 1180 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);
@@ -1208,6 +1216,12 @@ static int armada_drm_crtc_create(struct drm_device *drm, struct device *dev,
1208 if (!primary) 1216 if (!primary)
1209 return -ENOMEM; 1217 return -ENOMEM;
1210 1218
1219 ret = armada_drm_plane_init(primary);
1220 if (ret) {
1221 kfree(primary);
1222 return ret;
1223 }
1224
1211 ret = drm_universal_plane_init(drm, &primary->base, 0, 1225 ret = drm_universal_plane_init(drm, &primary->base, 0,
1212 &armada_primary_plane_funcs, 1226 &armada_primary_plane_funcs,
1213 armada_primary_formats, 1227 armada_primary_formats,
diff --git a/drivers/gpu/drm/armada/armada_crtc.h b/drivers/gpu/drm/armada/armada_crtc.h
index 500ce0f43f64..3ec5101e13f7 100644
--- a/drivers/gpu/drm/armada/armada_crtc.h
+++ b/drivers/gpu/drm/armada/armada_crtc.h
@@ -36,9 +36,12 @@ struct armada_variant;
36 36
37struct armada_plane { 37struct armada_plane {
38 struct drm_plane base; 38 struct drm_plane base;
39 wait_queue_head_t frame_wait;
39}; 40};
40#define drm_to_armada_plane(p) container_of(p, struct armada_plane, base) 41#define drm_to_armada_plane(p) container_of(p, struct armada_plane, base)
41 42
43int armada_drm_plane_init(struct armada_plane *plane);
44
42struct armada_crtc { 45struct armada_crtc {
43 struct drm_crtc crtc; 46 struct drm_crtc crtc;
44 const struct armada_variant *variant; 47 const struct armada_variant *variant;
@@ -71,7 +74,6 @@ struct armada_crtc {
71 uint32_t dumb_ctrl; 74 uint32_t dumb_ctrl;
72 uint32_t spu_iopad_ctrl; 75 uint32_t spu_iopad_ctrl;
73 76
74 wait_queue_head_t frame_wait;
75 struct armada_frame_work *frame_work; 77 struct armada_frame_work *frame_work;
76 78
77 spinlock_t irq_lock; 79 spinlock_t irq_lock;
diff --git a/drivers/gpu/drm/armada/armada_overlay.c b/drivers/gpu/drm/armada/armada_overlay.c
index 6ec42eb85981..9a5bab765085 100644
--- a/drivers/gpu/drm/armada/armada_overlay.c
+++ b/drivers/gpu/drm/armada/armada_overlay.c
@@ -39,7 +39,6 @@ struct armada_ovl_plane {
39 struct { 39 struct {
40 struct armada_vbl_event update; 40 struct armada_vbl_event update;
41 struct armada_regs regs[13]; 41 struct armada_regs regs[13];
42 wait_queue_head_t wait;
43 } vbl; 42 } vbl;
44 struct armada_ovl_plane_properties prop; 43 struct armada_ovl_plane_properties prop;
45}; 44};
@@ -90,7 +89,7 @@ static void armada_ovl_plane_vbl(struct armada_crtc *dcrtc, void *data)
90 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs); 89 armada_drm_crtc_update_regs(dcrtc, dplane->vbl.regs);
91 armada_ovl_retire_fb(dplane, NULL); 90 armada_ovl_retire_fb(dplane, NULL);
92 91
93 wake_up(&dplane->vbl.wait); 92 wake_up(&dplane->base.frame_wait);
94} 93}
95 94
96static int 95static int
@@ -163,7 +162,7 @@ armada_ovl_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
163 dcrtc->base + LCD_SPU_SRAM_PARA1); 162 dcrtc->base + LCD_SPU_SRAM_PARA1);
164 } 163 }
165 164
166 wait_event_timeout(dplane->vbl.wait, 165 wait_event_timeout(dplane->base.frame_wait,
167 list_empty(&dplane->vbl.update.node), 166 list_empty(&dplane->vbl.update.node),
168 HZ/25); 167 HZ/25);
169 168
@@ -451,7 +450,12 @@ int armada_overlay_plane_create(struct drm_device *dev, unsigned long crtcs)
451 if (!dplane) 450 if (!dplane)
452 return -ENOMEM; 451 return -ENOMEM;
453 452
454 init_waitqueue_head(&dplane->vbl.wait); 453 ret = armada_drm_plane_init(&dplane->base);
454 if (ret) {
455 kfree(dplane);
456 return ret;
457 }
458
455 armada_drm_vbl_event_init(&dplane->vbl.update, armada_ovl_plane_vbl, 459 armada_drm_vbl_event_init(&dplane->vbl.update, armada_ovl_plane_vbl,
456 dplane); 460 dplane);
457 461