diff options
author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-08-30 13:34:01 -0400 |
---|---|---|
committer | Stephen Boyd <sboyd@codeaurora.org> | 2016-08-30 17:58:15 -0400 |
commit | 54fe0791fa0dbe075f6465860bdd38a4b4e6e59c (patch) | |
tree | 869e1eeef2941d71d24fb74ceaa0f5816b990c78 | |
parent | 3174b0c9a62bb3738b4a2a506b8a075d4430e353 (diff) |
clk: imx7d: Add PLL_AUDIO_TEST_DIV/POST_DIV clocks
Currently we see the following error when using the SAI audio
driver on mx7:
Division by zero in kernel.
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.8.0-rc3-next-20160823
Hardware name: Freescale i.MX7 Dual (Device Tree)
Backtrace:
[<c010b70c>] (dump_backtrace) from [<c010b8a8>] (show_stack+0x18)
r6:60000013 r5:ffffffff r4:00000000 r3:00000000
[<c010b890>] (show_stack) from [<c03e9324>] (dump_stack+0xb0/0xe)
[<c03e9274>] (dump_stack) from [<c010b578>] (__div0+0x18/0x20)
r8:00000000 r7:ffffffff r6:ffffffff r5:00000000 r4:00000000 r3:0
[<c010b560>] (__div0) from [<c03e795c>] (Ldiv0_64+0x8/0x18)
[<c06cd860>] (divider_get_val) from [<c06cda28>] (clk_divider_se)
This error happens due to the lack of definition of the
IMX7D_PLL_AUDIO_TEST_DIV/IMX7D_PLL_AUDIO_POST_DIV clocks.
Add support for them.
Tested on a imx7s-warp board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
-rw-r--r-- | drivers/clk/imx/clk-imx7d.c | 101 |
1 files changed, 61 insertions, 40 deletions
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index 6bafcaa4451f..e7c7353a86fc 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c | |||
@@ -26,43 +26,59 @@ static u32 share_count_sai1; | |||
26 | static u32 share_count_sai2; | 26 | static u32 share_count_sai2; |
27 | static u32 share_count_sai3; | 27 | static u32 share_count_sai3; |
28 | 28 | ||
29 | static struct clk_div_table test_div_table[] = { | ||
30 | { .val = 3, .div = 1, }, | ||
31 | { .val = 2, .div = 1, }, | ||
32 | { .val = 1, .div = 2, }, | ||
33 | { .val = 0, .div = 4, }, | ||
34 | { } | ||
35 | }; | ||
36 | |||
37 | static struct clk_div_table post_div_table[] = { | ||
38 | { .val = 3, .div = 4, }, | ||
39 | { .val = 2, .div = 1, }, | ||
40 | { .val = 1, .div = 2, }, | ||
41 | { .val = 0, .div = 1, }, | ||
42 | { } | ||
43 | }; | ||
44 | |||
29 | static struct clk *clks[IMX7D_CLK_END]; | 45 | static struct clk *clks[IMX7D_CLK_END]; |
30 | static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", | 46 | static const char *arm_a7_sel[] = { "osc", "pll_arm_main_clk", |
31 | "pll_enet_500m_clk", "pll_dram_main_clk", | 47 | "pll_enet_500m_clk", "pll_dram_main_clk", |
32 | "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_main_clk", | 48 | "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_audio_post_div", |
33 | "pll_usb_main_clk", }; | 49 | "pll_usb_main_clk", }; |
34 | 50 | ||
35 | static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", | 51 | static const char *arm_m4_sel[] = { "osc", "pll_sys_main_240m_clk", |
36 | "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", | 52 | "pll_enet_250m_clk", "pll_sys_pfd2_270m_clk", |
37 | "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 53 | "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", |
38 | "pll_usb_main_clk", }; | 54 | "pll_usb_main_clk", }; |
39 | 55 | ||
40 | static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk", | 56 | static const char *arm_m0_sel[] = { "osc", "pll_sys_main_120m_clk", |
41 | "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk", | 57 | "pll_enet_125m_clk", "pll_sys_pfd2_135m_clk", |
42 | "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 58 | "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", |
43 | "pll_usb_main_clk", }; | 59 | "pll_usb_main_clk", }; |
44 | 60 | ||
45 | static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", | 61 | static const char *axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", |
46 | "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", | 62 | "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd5_clk", |
47 | "pll_audio_main_clk", "pll_video_main_clk", "pll_sys_pfd7_clk", }; | 63 | "pll_audio_post_div", "pll_video_main_clk", "pll_sys_pfd7_clk", }; |
48 | 64 | ||
49 | static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", | 65 | static const char *disp_axi_sel[] = { "osc", "pll_sys_pfd1_332m_clk", |
50 | "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", | 66 | "pll_dram_533m_clk", "pll_enet_250m_clk", "pll_sys_pfd6_clk", |
51 | "pll_sys_pfd7_clk", "pll_audio_main_clk", "pll_video_main_clk", }; | 67 | "pll_sys_pfd7_clk", "pll_audio_post_div", "pll_video_main_clk", }; |
52 | 68 | ||
53 | static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", | 69 | static const char *enet_axi_sel[] = { "osc", "pll_sys_pfd2_270m_clk", |
54 | "pll_dram_533m_clk", "pll_enet_250m_clk", | 70 | "pll_dram_533m_clk", "pll_enet_250m_clk", |
55 | "pll_sys_main_240m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 71 | "pll_sys_main_240m_clk", "pll_audio_post_div", "pll_video_main_clk", |
56 | "pll_sys_pfd4_clk", }; | 72 | "pll_sys_pfd4_clk", }; |
57 | 73 | ||
58 | static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", | 74 | static const char *nand_usdhc_bus_sel[] = { "osc", "pll_sys_pfd2_270m_clk", |
59 | "pll_dram_533m_clk", "pll_sys_main_240m_clk", | 75 | "pll_dram_533m_clk", "pll_sys_main_240m_clk", |
60 | "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", | 76 | "pll_sys_pfd2_135m_clk", "pll_sys_pfd6_clk", "pll_enet_250m_clk", |
61 | "pll_audio_main_clk", }; | 77 | "pll_audio_post_div", }; |
62 | 78 | ||
63 | static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", | 79 | static const char *ahb_channel_sel[] = { "osc", "pll_sys_pfd2_270m_clk", |
64 | "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", | 80 | "pll_dram_533m_clk", "pll_sys_pfd0_392m_clk", |
65 | "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_main_clk", | 81 | "pll_enet_125m_clk", "pll_usb_main_clk", "pll_audio_post_div", |
66 | "pll_video_main_clk", }; | 82 | "pll_video_main_clk", }; |
67 | 83 | ||
68 | static const char *dram_phym_sel[] = { "pll_dram_main_clk", | 84 | static const char *dram_phym_sel[] = { "pll_dram_main_clk", |
@@ -73,13 +89,13 @@ static const char *dram_sel[] = { "pll_dram_main_clk", | |||
73 | 89 | ||
74 | static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", | 90 | static const char *dram_phym_alt_sel[] = { "osc", "pll_dram_533m_clk", |
75 | "pll_sys_main_clk", "pll_enet_500m_clk", | 91 | "pll_sys_main_clk", "pll_enet_500m_clk", |
76 | "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_main_clk", | 92 | "pll_usb_main_clk", "pll_sys_pfd7_clk", "pll_audio_post_div", |
77 | "pll_video_main_clk", }; | 93 | "pll_video_main_clk", }; |
78 | 94 | ||
79 | static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", | 95 | static const char *dram_alt_sel[] = { "osc", "pll_dram_533m_clk", |
80 | "pll_sys_main_clk", "pll_enet_500m_clk", | 96 | "pll_sys_main_clk", "pll_enet_500m_clk", |
81 | "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk", | 97 | "pll_enet_250m_clk", "pll_sys_pfd0_392m_clk", |
82 | "pll_audio_main_clk", "pll_sys_pfd2_270m_clk", }; | 98 | "pll_audio_post_div", "pll_sys_pfd2_270m_clk", }; |
83 | 99 | ||
84 | static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk", | 100 | static const char *usb_hsic_sel[] = { "osc", "pll_sys_main_clk", |
85 | "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", | 101 | "pll_usb_main_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", |
@@ -105,53 +121,53 @@ static const char *lcdif_pixel_sel[] = { "osc", "pll_sys_pfd5_clk", | |||
105 | 121 | ||
106 | static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", | 122 | static const char *mipi_dsi_sel[] = { "osc", "pll_sys_pfd5_clk", |
107 | "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", | 123 | "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", |
108 | "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", }; | 124 | "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", }; |
109 | 125 | ||
110 | static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", | 126 | static const char *mipi_csi_sel[] = { "osc", "pll_sys_pfd4_clk", |
111 | "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", | 127 | "pll_sys_pfd3_clk", "pll_sys_main_clk", "pll_sys_pfd0_196m_clk", |
112 | "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_main_clk", }; | 128 | "pll_dram_533m_clk", "pll_video_main_clk", "pll_audio_post_div", }; |
113 | 129 | ||
114 | static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", | 130 | static const char *mipi_dphy_sel[] = { "osc", "pll_sys_main_120m_clk", |
115 | "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", | 131 | "pll_dram_533m_clk", "pll_sys_pfd5_clk", "ref_1m_clk", "ext_clk_2", |
116 | "pll_video_main_clk", "ext_clk_3", }; | 132 | "pll_video_main_clk", "ext_clk_3", }; |
117 | 133 | ||
118 | static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 134 | static const char *sai1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
119 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | 135 | "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", |
120 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; | 136 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; |
121 | 137 | ||
122 | static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 138 | static const char *sai2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
123 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | 139 | "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", |
124 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; | 140 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_2", }; |
125 | 141 | ||
126 | static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 142 | static const char *sai3_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
127 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | 143 | "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", |
128 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; | 144 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_clk_3", }; |
129 | 145 | ||
130 | static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 146 | static const char *spdif_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
131 | "pll_audio_main_clk", "pll_dram_533m_clk", "pll_video_main_clk", | 147 | "pll_audio_post_div", "pll_dram_533m_clk", "pll_video_main_clk", |
132 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; | 148 | "pll_sys_pfd4_clk", "pll_enet_125m_clk", "ext_3_clk", }; |
133 | 149 | ||
134 | static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", | 150 | static const char *enet1_ref_sel[] = { "osc", "pll_enet_125m_clk", |
135 | "pll_enet_50m_clk", "pll_enet_25m_clk", | 151 | "pll_enet_50m_clk", "pll_enet_25m_clk", |
136 | "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 152 | "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk", |
137 | "ext_clk_4", }; | 153 | "ext_clk_4", }; |
138 | 154 | ||
139 | static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", | 155 | static const char *enet1_time_sel[] = { "osc", "pll_enet_100m_clk", |
140 | "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", | 156 | "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", |
141 | "ext_clk_4", "pll_video_main_clk", }; | 157 | "ext_clk_4", "pll_video_main_clk", }; |
142 | 158 | ||
143 | static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", | 159 | static const char *enet2_ref_sel[] = { "osc", "pll_enet_125m_clk", |
144 | "pll_enet_50m_clk", "pll_enet_25m_clk", | 160 | "pll_enet_50m_clk", "pll_enet_25m_clk", |
145 | "pll_sys_main_120m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 161 | "pll_sys_main_120m_clk", "pll_audio_post_div", "pll_video_main_clk", |
146 | "ext_clk_4", }; | 162 | "ext_clk_4", }; |
147 | 163 | ||
148 | static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", | 164 | static const char *enet2_time_sel[] = { "osc", "pll_enet_100m_clk", |
149 | "pll_audio_main_clk", "ext_clk_1", "ext_clk_2", "ext_clk_3", | 165 | "pll_audio_post_div", "ext_clk_1", "ext_clk_2", "ext_clk_3", |
150 | "ext_clk_4", "pll_video_main_clk", }; | 166 | "ext_clk_4", "pll_video_main_clk", }; |
151 | 167 | ||
152 | static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", | 168 | static const char *enet_phy_ref_sel[] = { "osc", "pll_enet_25m_clk", |
153 | "pll_enet_50m_clk", "pll_enet_125m_clk", | 169 | "pll_enet_50m_clk", "pll_enet_125m_clk", |
154 | "pll_dram_533m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 170 | "pll_dram_533m_clk", "pll_audio_post_div", "pll_video_main_clk", |
155 | "pll_sys_pfd3_clk", }; | 171 | "pll_sys_pfd3_clk", }; |
156 | 172 | ||
157 | static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 173 | static const char *eim_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
@@ -192,22 +208,22 @@ static const char *can2_sel[] = { "osc", "pll_sys_main_120m_clk", | |||
192 | 208 | ||
193 | static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", | 209 | static const char *i2c1_sel[] = { "osc", "pll_sys_main_120m_clk", |
194 | "pll_enet_50m_clk", "pll_dram_533m_clk", | 210 | "pll_enet_50m_clk", "pll_dram_533m_clk", |
195 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | 211 | "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", |
196 | "pll_sys_pfd2_135m_clk", }; | 212 | "pll_sys_pfd2_135m_clk", }; |
197 | 213 | ||
198 | static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", | 214 | static const char *i2c2_sel[] = { "osc", "pll_sys_main_120m_clk", |
199 | "pll_enet_50m_clk", "pll_dram_533m_clk", | 215 | "pll_enet_50m_clk", "pll_dram_533m_clk", |
200 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | 216 | "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", |
201 | "pll_sys_pfd2_135m_clk", }; | 217 | "pll_sys_pfd2_135m_clk", }; |
202 | 218 | ||
203 | static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", | 219 | static const char *i2c3_sel[] = { "osc", "pll_sys_main_120m_clk", |
204 | "pll_enet_50m_clk", "pll_dram_533m_clk", | 220 | "pll_enet_50m_clk", "pll_dram_533m_clk", |
205 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | 221 | "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", |
206 | "pll_sys_pfd2_135m_clk", }; | 222 | "pll_sys_pfd2_135m_clk", }; |
207 | 223 | ||
208 | static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", | 224 | static const char *i2c4_sel[] = { "osc", "pll_sys_main_120m_clk", |
209 | "pll_enet_50m_clk", "pll_dram_533m_clk", | 225 | "pll_enet_50m_clk", "pll_dram_533m_clk", |
210 | "pll_audio_main_clk", "pll_video_main_clk", "pll_usb_main_clk", | 226 | "pll_audio_post_div", "pll_video_main_clk", "pll_usb_main_clk", |
211 | "pll_sys_pfd2_135m_clk", }; | 227 | "pll_sys_pfd2_135m_clk", }; |
212 | 228 | ||
213 | static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", | 229 | static const char *uart1_sel[] = { "osc", "pll_sys_main_240m_clk", |
@@ -266,32 +282,32 @@ static const char *ecspi4_sel[] = { "osc", "pll_sys_main_240m_clk", | |||
266 | "pll_usb_main_clk", }; | 282 | "pll_usb_main_clk", }; |
267 | 283 | ||
268 | static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", | 284 | static const char *pwm1_sel[] = { "osc", "pll_enet_100m_clk", |
269 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | 285 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", |
270 | "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; | 286 | "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; |
271 | 287 | ||
272 | static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", | 288 | static const char *pwm2_sel[] = { "osc", "pll_enet_100m_clk", |
273 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | 289 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", |
274 | "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; | 290 | "ext_clk_1", "ref_1m_clk", "pll_video_main_clk", }; |
275 | 291 | ||
276 | static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", | 292 | static const char *pwm3_sel[] = { "osc", "pll_enet_100m_clk", |
277 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | 293 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", |
278 | "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; | 294 | "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; |
279 | 295 | ||
280 | static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", | 296 | static const char *pwm4_sel[] = { "osc", "pll_enet_100m_clk", |
281 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | 297 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", |
282 | "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; | 298 | "ext_clk_2", "ref_1m_clk", "pll_video_main_clk", }; |
283 | 299 | ||
284 | static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", | 300 | static const char *flextimer1_sel[] = { "osc", "pll_enet_100m_clk", |
285 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | 301 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", |
286 | "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; | 302 | "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; |
287 | 303 | ||
288 | static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", | 304 | static const char *flextimer2_sel[] = { "osc", "pll_enet_100m_clk", |
289 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_main_clk", | 305 | "pll_sys_main_120m_clk", "pll_enet_40m_clk", "pll_audio_post_div", |
290 | "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; | 306 | "ext_clk_3", "ref_1m_clk", "pll_video_main_clk", }; |
291 | 307 | ||
292 | static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 308 | static const char *sim1_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
293 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | 309 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", |
294 | "pll_usb_main_clk", "pll_audio_main_clk", "pll_enet_125m_clk", | 310 | "pll_usb_main_clk", "pll_audio_post_div", "pll_enet_125m_clk", |
295 | "pll_sys_pfd7_clk", }; | 311 | "pll_sys_pfd7_clk", }; |
296 | 312 | ||
297 | static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 313 | static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
@@ -301,19 +317,19 @@ static const char *sim2_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |||
301 | 317 | ||
302 | static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", | 318 | static const char *gpt1_sel[] = { "osc", "pll_enet_100m_clk", |
303 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | 319 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", |
304 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_1", }; | 320 | "ref_1m_clk", "pll_audio_post_div", "ext_clk_1", }; |
305 | 321 | ||
306 | static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", | 322 | static const char *gpt2_sel[] = { "osc", "pll_enet_100m_clk", |
307 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | 323 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", |
308 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_2", }; | 324 | "ref_1m_clk", "pll_audio_post_div", "ext_clk_2", }; |
309 | 325 | ||
310 | static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", | 326 | static const char *gpt3_sel[] = { "osc", "pll_enet_100m_clk", |
311 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | 327 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", |
312 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_3", }; | 328 | "ref_1m_clk", "pll_audio_post_div", "ext_clk_3", }; |
313 | 329 | ||
314 | static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", | 330 | static const char *gpt4_sel[] = { "osc", "pll_enet_100m_clk", |
315 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", | 331 | "pll_sys_pfd0_392m_clk", "pll_enet_40m_clk", "pll_video_main_clk", |
316 | "ref_1m_clk", "pll_audio_main_clk", "ext_clk_4", }; | 332 | "ref_1m_clk", "pll_audio_post_div", "ext_clk_4", }; |
317 | 333 | ||
318 | static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 334 | static const char *trace_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
319 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | 335 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", |
@@ -327,12 +343,12 @@ static const char *wdog_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | |||
327 | 343 | ||
328 | static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 344 | static const char *csi_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
329 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | 345 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", |
330 | "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 346 | "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk", |
331 | "pll_usb_main_clk", }; | 347 | "pll_usb_main_clk", }; |
332 | 348 | ||
333 | static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", | 349 | static const char *audio_mclk_sel[] = { "osc", "pll_sys_pfd2_135m_clk", |
334 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", | 350 | "pll_sys_main_120m_clk", "pll_dram_533m_clk", |
335 | "pll_enet_125m_clk", "pll_audio_main_clk", "pll_video_main_clk", | 351 | "pll_enet_125m_clk", "pll_audio_post_div", "pll_video_main_clk", |
336 | "pll_usb_main_clk", }; | 352 | "pll_usb_main_clk", }; |
337 | 353 | ||
338 | static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", | 354 | static const char *wrclk_sel[] = { "osc", "pll_enet_40m_clk", |
@@ -346,13 +362,13 @@ static const char *clko1_sel[] = { "osc", "pll_sys_main_clk", | |||
346 | 362 | ||
347 | static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", | 363 | static const char *clko2_sel[] = { "osc", "pll_sys_main_240m_clk", |
348 | "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", | 364 | "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_166m_clk", "pll_sys_pfd4_clk", |
349 | "pll_audio_main_clk", "pll_video_main_clk", "ckil", }; | 365 | "pll_audio_post_div", "pll_video_main_clk", "ckil", }; |
350 | 366 | ||
351 | static const char *lvds1_sel[] = { "pll_arm_main_clk", | 367 | static const char *lvds1_sel[] = { "pll_arm_main_clk", |
352 | "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", | 368 | "pll_sys_main_clk", "pll_sys_pfd0_392m_clk", "pll_sys_pfd1_332m_clk", |
353 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", | 369 | "pll_sys_pfd2_270m_clk", "pll_sys_pfd3_clk", "pll_sys_pfd4_clk", |
354 | "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", | 370 | "pll_sys_pfd5_clk", "pll_sys_pfd6_clk", "pll_sys_pfd7_clk", |
355 | "pll_audio_main_clk", "pll_video_main_clk", "pll_enet_500m_clk", | 371 | "pll_audio_post_div", "pll_video_main_clk", "pll_enet_500m_clk", |
356 | "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", | 372 | "pll_enet_250m_clk", "pll_enet_125m_clk", "pll_enet_100m_clk", |
357 | "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", | 373 | "pll_enet_50m_clk", "pll_enet_40m_clk", "pll_enet_25m_clk", |
358 | "pll_dram_main_clk", }; | 374 | "pll_dram_main_clk", }; |
@@ -434,6 +450,11 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) | |||
434 | clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); | 450 | clks[IMX7D_PLL_AUDIO_MAIN_CLK] = imx_clk_gate("pll_audio_main_clk", "pll_audio_main_bypass", base + 0xf0, 13); |
435 | clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); | 451 | clks[IMX7D_PLL_VIDEO_MAIN_CLK] = imx_clk_gate("pll_video_main_clk", "pll_video_main_bypass", base + 0x130, 13); |
436 | 452 | ||
453 | clks[IMX7D_PLL_AUDIO_TEST_DIV] = clk_register_divider_table(NULL, "pll_audio_test_div", "pll_audio_main_clk", | ||
454 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 19, 2, 0, test_div_table, &imx_ccm_lock); | ||
455 | clks[IMX7D_PLL_AUDIO_POST_DIV] = clk_register_divider_table(NULL, "pll_audio_post_div", "pll_audio_test_div", | ||
456 | CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); | ||
457 | |||
437 | clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); | 458 | clks[IMX7D_PLL_SYS_PFD0_392M_CLK] = imx_clk_pfd("pll_sys_pfd0_392m_clk", "pll_sys_main_clk", base + 0xc0, 0); |
438 | clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); | 459 | clks[IMX7D_PLL_SYS_PFD1_332M_CLK] = imx_clk_pfd("pll_sys_pfd1_332m_clk", "pll_sys_main_clk", base + 0xc0, 1); |
439 | clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); | 460 | clks[IMX7D_PLL_SYS_PFD2_270M_CLK] = imx_clk_pfd("pll_sys_pfd2_270m_clk", "pll_sys_main_clk", base + 0xc0, 2); |