dmaengine: ioatdma: disable relaxed ordering for ioatdma

ioatdma by default is in snoop mode. Relaxed ordering according to spec
does not do anything in snoop mode. However, it causes hang or significant
performance degrade when tested with NTB. Disabling in the driver due to
some BIOS do not configure it correctly.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

2 files changed, 19 insertions, 0 deletions

diff --git a/drivers/dma/ioat/init.c b/drivers/dma/ioat/init.c
index d4c63d48b970..d406056e8892 100644
--- a/drivers/dma/ioat/init.c
+++ b/drivers/dma/ioat/init.c
@@ -1073,6 +1073,7 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
         struct ioatdma_chan *ioat_chan;
         bool is_raid_device = false;
         int err;
+        u16 val16;
 
         dma = &ioat_dma->dma_dev;
         dma->device_prep_dma_memcpy = ioat_dma_prep_memcpy_lock;
@@ -1172,6 +1173,17 @@ static int ioat3_dma_probe(struct ioatdma_device *ioat_dma, int dca)
         if (dca)
                 ioat_dma->dca = ioat_dca_init(pdev, ioat_dma->reg_base);
 
+        /* disable relaxed ordering */
+        err = pcie_capability_read_word(pdev, IOAT_DEVCTRL_OFFSET, &val16);
+        if (err)
+                return err;
+
+        /* clear relaxed ordering enable */
+        val16 &= ~IOAT_DEVCTRL_ROE;
+        err = pcie_capability_write_word(pdev, IOAT_DEVCTRL_OFFSET, val16);
+        if (err)
+                return err;
+
         return 0;
 }
 
diff --git a/drivers/dma/ioat/registers.h b/drivers/dma/ioat/registers.h
index 4994a3623aee..70534981a49b 100644
--- a/drivers/dma/ioat/registers.h
+++ b/drivers/dma/ioat/registers.h
@@ -26,6 +26,13 @@
 #define IOAT_PCI_CHANERR_INT_OFFSET             0x180
 #define IOAT_PCI_CHANERRMASK_INT_OFFSET         0x184
 
+/* PCIe config registers */
+
+/* EXPCAPID + N */
+#define IOAT_DEVCTRL_OFFSET                     0x8
+/* relaxed ordering enable */
+#define IOAT_DEVCTRL_ROE                        0x10
+
 /* MMIO Device Registers */
 #define IOAT_CHANCNT_OFFSET                     0x00    /*  8-bit */