diff options
| author | Mike Turquette <mturquette@linaro.org> | 2014-05-28 03:15:10 -0400 |
|---|---|---|
| committer | Mike Turquette <mturquette@linaro.org> | 2014-05-28 03:15:10 -0400 |
| commit | 4c8f8062515a3e809cc48c2d378f51bf0346d587 (patch) | |
| tree | eec9a7b08432e048fd5f74a9f53c81f07ed2cb73 | |
| parent | b59e869674f5b6779c65ddb13cf799cd01c07072 (diff) | |
| parent | 5178438041cc94680e606e5a9c6d1ad9c911199b (diff) | |
Merge branch 'clk-fixes' into clk-next
| -rw-r--r-- | drivers/clk/st/clkgen-pll.c | 4 | ||||
| -rw-r--r-- | drivers/clk/tegra/clk-pll.c | 64 |
2 files changed, 46 insertions, 22 deletions
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c index bca0a0badbfa..a886702f7c8b 100644 --- a/drivers/clk/st/clkgen-pll.c +++ b/drivers/clk/st/clkgen-pll.c | |||
| @@ -521,8 +521,10 @@ static struct clk * __init clkgen_odf_register(const char *parent_name, | |||
| 521 | gate->lock = odf_lock; | 521 | gate->lock = odf_lock; |
| 522 | 522 | ||
| 523 | div = kzalloc(sizeof(*div), GFP_KERNEL); | 523 | div = kzalloc(sizeof(*div), GFP_KERNEL); |
| 524 | if (!div) | 524 | if (!div) { |
| 525 | kfree(gate); | ||
| 525 | return ERR_PTR(-ENOMEM); | 526 | return ERR_PTR(-ENOMEM); |
| 527 | } | ||
| 526 | 528 | ||
| 527 | div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; | 529 | div->flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO; |
| 528 | div->reg = reg + pll_data->odf[odf].offset; | 530 | div->reg = reg + pll_data->odf[odf].offset; |
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index 39e0959b61bd..637b62ccc91e 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c | |||
| @@ -58,9 +58,9 @@ | |||
| 58 | #define PLLDU_LFCON_SET_DIVN 600 | 58 | #define PLLDU_LFCON_SET_DIVN 600 |
| 59 | 59 | ||
| 60 | #define PLLE_BASE_DIVCML_SHIFT 24 | 60 | #define PLLE_BASE_DIVCML_SHIFT 24 |
| 61 | #define PLLE_BASE_DIVCML_WIDTH 4 | 61 | #define PLLE_BASE_DIVCML_MASK 0xf |
| 62 | #define PLLE_BASE_DIVP_SHIFT 16 | 62 | #define PLLE_BASE_DIVP_SHIFT 16 |
| 63 | #define PLLE_BASE_DIVP_WIDTH 7 | 63 | #define PLLE_BASE_DIVP_WIDTH 6 |
| 64 | #define PLLE_BASE_DIVN_SHIFT 8 | 64 | #define PLLE_BASE_DIVN_SHIFT 8 |
| 65 | #define PLLE_BASE_DIVN_WIDTH 8 | 65 | #define PLLE_BASE_DIVN_WIDTH 8 |
| 66 | #define PLLE_BASE_DIVM_SHIFT 0 | 66 | #define PLLE_BASE_DIVM_SHIFT 0 |
| @@ -193,6 +193,14 @@ | |||
| 193 | #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ | 193 | #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\ |
| 194 | mask(p->params->div_nmp->divp_width)) | 194 | mask(p->params->div_nmp->divp_width)) |
| 195 | 195 | ||
| 196 | #define divm_shift(p) (p)->params->div_nmp->divm_shift | ||
| 197 | #define divn_shift(p) (p)->params->div_nmp->divn_shift | ||
| 198 | #define divp_shift(p) (p)->params->div_nmp->divp_shift | ||
| 199 | |||
| 200 | #define divm_mask_shifted(p) (divm_mask(p) << divm_shift(p)) | ||
| 201 | #define divn_mask_shifted(p) (divn_mask(p) << divn_shift(p)) | ||
| 202 | #define divp_mask_shifted(p) (divp_mask(p) << divp_shift(p)) | ||
| 203 | |||
| 196 | #define divm_max(p) (divm_mask(p)) | 204 | #define divm_max(p) (divm_mask(p)) |
| 197 | #define divn_max(p) (divn_mask(p)) | 205 | #define divn_max(p) (divn_mask(p)) |
| 198 | #define divp_max(p) (1 << (divp_mask(p))) | 206 | #define divp_max(p) (1 << (divp_mask(p))) |
| @@ -486,13 +494,12 @@ static void _update_pll_mnp(struct tegra_clk_pll *pll, | |||
| 486 | } else { | 494 | } else { |
| 487 | val = pll_readl_base(pll); | 495 | val = pll_readl_base(pll); |
| 488 | 496 | ||
| 489 | val &= ~((divm_mask(pll) << div_nmp->divm_shift) | | 497 | val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) | |
| 490 | (divn_mask(pll) << div_nmp->divn_shift) | | 498 | divp_mask_shifted(pll)); |
| 491 | (divp_mask(pll) << div_nmp->divp_shift)); | ||
| 492 | 499 | ||
| 493 | val |= ((cfg->m << div_nmp->divm_shift) | | 500 | val |= (cfg->m << divm_shift(pll)) | |
| 494 | (cfg->n << div_nmp->divn_shift) | | 501 | (cfg->n << divn_shift(pll)) | |
| 495 | (cfg->p << div_nmp->divp_shift)); | 502 | (cfg->p << divp_shift(pll)); |
| 496 | 503 | ||
| 497 | pll_writel_base(val, pll); | 504 | pll_writel_base(val, pll); |
| 498 | } | 505 | } |
| @@ -740,11 +747,12 @@ static int clk_plle_enable(struct clk_hw *hw) | |||
| 740 | if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { | 747 | if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { |
| 741 | /* configure dividers */ | 748 | /* configure dividers */ |
| 742 | val = pll_readl_base(pll); | 749 | val = pll_readl_base(pll); |
| 743 | val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); | 750 | val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | |
| 744 | val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT); | 751 | divm_mask_shifted(pll)); |
| 745 | val |= sel.m << pll->params->div_nmp->divm_shift; | 752 | val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); |
| 746 | val |= sel.n << pll->params->div_nmp->divn_shift; | 753 | val |= sel.m << divm_shift(pll); |
| 747 | val |= sel.p << pll->params->div_nmp->divp_shift; | 754 | val |= sel.n << divn_shift(pll); |
| 755 | val |= sel.p << divp_shift(pll); | ||
| 748 | val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; | 756 | val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; |
| 749 | pll_writel_base(val, pll); | 757 | pll_writel_base(val, pll); |
| 750 | } | 758 | } |
| @@ -755,10 +763,11 @@ static int clk_plle_enable(struct clk_hw *hw) | |||
| 755 | pll_writel_misc(val, pll); | 763 | pll_writel_misc(val, pll); |
| 756 | 764 | ||
| 757 | val = readl(pll->clk_base + PLLE_SS_CTRL); | 765 | val = readl(pll->clk_base + PLLE_SS_CTRL); |
| 766 | val &= ~PLLE_SS_COEFFICIENTS_MASK; | ||
| 758 | val |= PLLE_SS_DISABLE; | 767 | val |= PLLE_SS_DISABLE; |
| 759 | writel(val, pll->clk_base + PLLE_SS_CTRL); | 768 | writel(val, pll->clk_base + PLLE_SS_CTRL); |
| 760 | 769 | ||
| 761 | val |= pll_readl_base(pll); | 770 | val = pll_readl_base(pll); |
| 762 | val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); | 771 | val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE); |
| 763 | pll_writel_base(val, pll); | 772 | pll_writel_base(val, pll); |
| 764 | 773 | ||
| @@ -1302,10 +1311,11 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) | |||
| 1302 | pll_writel(val, PLLE_SS_CTRL, pll); | 1311 | pll_writel(val, PLLE_SS_CTRL, pll); |
| 1303 | 1312 | ||
| 1304 | val = pll_readl_base(pll); | 1313 | val = pll_readl_base(pll); |
| 1305 | val &= ~(divm_mask(pll) | divn_mask(pll) | divp_mask(pll)); | 1314 | val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) | |
| 1306 | val &= ~(PLLE_BASE_DIVCML_WIDTH << PLLE_BASE_DIVCML_SHIFT); | 1315 | divm_mask_shifted(pll)); |
| 1307 | val |= sel.m << pll->params->div_nmp->divm_shift; | 1316 | val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT); |
| 1308 | val |= sel.n << pll->params->div_nmp->divn_shift; | 1317 | val |= sel.m << divm_shift(pll); |
| 1318 | val |= sel.n << divn_shift(pll); | ||
| 1309 | val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; | 1319 | val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; |
| 1310 | pll_writel_base(val, pll); | 1320 | pll_writel_base(val, pll); |
| 1311 | udelay(1); | 1321 | udelay(1); |
| @@ -1441,6 +1451,15 @@ struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, | |||
| 1441 | return clk; | 1451 | return clk; |
| 1442 | } | 1452 | } |
| 1443 | 1453 | ||
| 1454 | static struct div_nmp pll_e_nmp = { | ||
| 1455 | .divn_shift = PLLE_BASE_DIVN_SHIFT, | ||
| 1456 | .divn_width = PLLE_BASE_DIVN_WIDTH, | ||
| 1457 | .divm_shift = PLLE_BASE_DIVM_SHIFT, | ||
| 1458 | .divm_width = PLLE_BASE_DIVM_WIDTH, | ||
| 1459 | .divp_shift = PLLE_BASE_DIVP_SHIFT, | ||
| 1460 | .divp_width = PLLE_BASE_DIVP_WIDTH, | ||
| 1461 | }; | ||
| 1462 | |||
| 1444 | struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, | 1463 | struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, |
| 1445 | void __iomem *clk_base, void __iomem *pmc, | 1464 | void __iomem *clk_base, void __iomem *pmc, |
| 1446 | unsigned long flags, struct tegra_clk_pll_params *pll_params, | 1465 | unsigned long flags, struct tegra_clk_pll_params *pll_params, |
| @@ -1451,6 +1470,10 @@ struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, | |||
| 1451 | 1470 | ||
| 1452 | pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; | 1471 | pll_params->flags |= TEGRA_PLL_LOCK_MISC | TEGRA_PLL_BYPASS; |
| 1453 | pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; | 1472 | pll_params->flags |= TEGRA_PLL_HAS_LOCK_ENABLE; |
| 1473 | |||
| 1474 | if (!pll_params->div_nmp) | ||
| 1475 | pll_params->div_nmp = &pll_e_nmp; | ||
| 1476 | |||
| 1454 | pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); | 1477 | pll = _tegra_init_pll(clk_base, pmc, pll_params, lock); |
| 1455 | if (IS_ERR(pll)) | 1478 | if (IS_ERR(pll)) |
| 1456 | return ERR_CAST(pll); | 1479 | return ERR_CAST(pll); |
| @@ -1588,9 +1611,8 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, | |||
| 1588 | int m; | 1611 | int m; |
| 1589 | 1612 | ||
| 1590 | m = _pll_fixed_mdiv(pll_params, parent_rate); | 1613 | m = _pll_fixed_mdiv(pll_params, parent_rate); |
| 1591 | val = m << PLL_BASE_DIVM_SHIFT; | 1614 | val = m << divm_shift(pll); |
| 1592 | val |= (pll_params->vco_min / parent_rate) | 1615 | val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); |
| 1593 | << PLL_BASE_DIVN_SHIFT; | ||
| 1594 | pll_writel_base(val, pll); | 1616 | pll_writel_base(val, pll); |
| 1595 | } | 1617 | } |
| 1596 | 1618 | ||