diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2016-04-27 04:23:44 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2016-04-27 04:23:44 -0400 |
commit | 451938d52fe838c766687484fd9a69e35d8a68bc (patch) | |
tree | 361aee5bc66501fcc0d322f55503f85de7a4c065 | |
parent | 0c0451e7634564052a045d4398a91ea4ef1f755b (diff) |
gpio: clarify open drain/source docs
Make the text clearer, remove reference to confusing "positive"
and "negative" and elaborate a bit.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | Documentation/gpio/driver.txt | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/Documentation/gpio/driver.txt b/Documentation/gpio/driver.txt index ae6e0299b16c..6cb35a78eff4 100644 --- a/Documentation/gpio/driver.txt +++ b/Documentation/gpio/driver.txt | |||
@@ -100,6 +100,10 @@ Both usecases require that the line be equipped with a pull-up resistor. This | |||
100 | resistor will make the line tend to high level unless one of the transistors on | 100 | resistor will make the line tend to high level unless one of the transistors on |
101 | the rail actively pulls it down. | 101 | the rail actively pulls it down. |
102 | 102 | ||
103 | The level on the line will go as high as the VDD on the pull-up resistor, which | ||
104 | may be higher than the level supported by the transistor, achieveing a | ||
105 | level-shift to the higher VDD. | ||
106 | |||
103 | Integrated electronics often have an output driver stage in the form of a CMOS | 107 | Integrated electronics often have an output driver stage in the form of a CMOS |
104 | "totem-pole" with one N-MOS and one P-MOS transistor where one of them drives | 108 | "totem-pole" with one N-MOS and one P-MOS transistor where one of them drives |
105 | the line high and one of them drives the line low. This is called a push-pull | 109 | the line high and one of them drives the line low. This is called a push-pull |
@@ -110,14 +114,18 @@ output. The "totem-pole" looks like so: | |||
110 | OD ||--+ | 114 | OD ||--+ |
111 | +--/ ---o|| P-MOS-FET | 115 | +--/ ---o|| P-MOS-FET |
112 | | ||--+ | 116 | | ||--+ |
113 | in --+ +----- out | 117 | IN --+ +----- out |
114 | | ||--+ | 118 | | ||--+ |
115 | +--/ ----|| N-MOS-FET | 119 | +--/ ----|| N-MOS-FET |
116 | OS ||--+ | 120 | OS ||--+ |
117 | | | 121 | | |
118 | GND | 122 | GND |
119 | 123 | ||
120 | You see the little "switches" named "OD" and "OS" that enable/disable the | 124 | The desired output signal (e.g. coming directly from some GPIO output register) |
125 | arrives at IN. The switches named "OD" and "OS" are normally closed, creating | ||
126 | a push-pull circuit. | ||
127 | |||
128 | Consider the little "switches" named "OD" and "OS" that enable/disable the | ||
121 | P-MOS or N-MOS transistor right after the split of the input. As you can see, | 129 | P-MOS or N-MOS transistor right after the split of the input. As you can see, |
122 | either transistor will go totally numb if this switch is open. The totem-pole | 130 | either transistor will go totally numb if this switch is open. The totem-pole |
123 | is then halved and give high impedance instead of actively driving the line | 131 | is then halved and give high impedance instead of actively driving the line |
@@ -128,8 +136,8 @@ Some GPIO hardware come in open drain / open source configuration. Some are | |||
128 | hard-wired lines that will only support open drain or open source no matter | 136 | hard-wired lines that will only support open drain or open source no matter |
129 | what: there is only one transistor there. Some are software-configurable: | 137 | what: there is only one transistor there. Some are software-configurable: |
130 | by flipping a bit in a register the output can be configured as open drain | 138 | by flipping a bit in a register the output can be configured as open drain |
131 | or open source, by flicking open the switches labeled "OD" and "OS" in the | 139 | or open source, in practice by flicking open the switches labeled "OD" and "OS" |
132 | drawing above. | 140 | in the drawing above. |
133 | 141 | ||
134 | By disabling the P-MOS transistor, the output can be driven between GND and | 142 | By disabling the P-MOS transistor, the output can be driven between GND and |
135 | high impedance (open drain), and by disabling the N-MOS transistor, the output | 143 | high impedance (open drain), and by disabling the N-MOS transistor, the output |
@@ -146,8 +154,8 @@ set in the machine file, or coming from other hardware descriptions. | |||
146 | If this state can not be configured in hardware, i.e. if the GPIO hardware does | 154 | If this state can not be configured in hardware, i.e. if the GPIO hardware does |
147 | not support open drain/open source in hardware, the GPIO library will instead | 155 | not support open drain/open source in hardware, the GPIO library will instead |
148 | use a trick: when a line is set as output, if the line is flagged as open | 156 | use a trick: when a line is set as output, if the line is flagged as open |
149 | drain, and the output value is negative, it will be driven low as usual. But | 157 | drain, and the IN output value is low, it will be driven low as usual. But |
150 | if the output value is set to positive, it will instead *NOT* be driven high, | 158 | if the IN output value is set to high, it will instead *NOT* be driven high, |
151 | instead it will be switched to input, as input mode is high impedance, thus | 159 | instead it will be switched to input, as input mode is high impedance, thus |
152 | achieveing an "open drain emulation" of sorts: electrically the behaviour will | 160 | achieveing an "open drain emulation" of sorts: electrically the behaviour will |
153 | be identical, with the exception of possible hardware glitches when switching | 161 | be identical, with the exception of possible hardware glitches when switching |