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authorArnd Bergmann <arnd@arndb.de>2015-05-13 11:59:35 -0400
committerArnd Bergmann <arnd@arndb.de>2015-05-13 11:59:35 -0400
commit44fb3026ad28d2a2b935dc9c47ec2dffadca3f35 (patch)
tree9235a53f17b59c883bee7be16ab35cf816ce6ece
parent92d19e26d67704397b70cf5728fd77bd13b74c43 (diff)
parent9c77a81f215bfeee8f96c50c8ab27dbebffec80d (diff)
Merge tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
Merge "ARM: tegra: Add EMC driver for v4.2-rc1" from Thierry Reding: This introduces the EMC driver that's required to scale the external memory frequency. * tag 'tegra-for-4.2-emc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Add EMC frequency debugfs entry memory: tegra: Add EMC (external memory controller) driver memory: tegra: Add API needed by the EMC driver of: Add Tegra124 EMC bindings of: Document timings subnode of nvidia,tegra-mc
Diffstat
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt84
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt374
-rw-r--r--drivers/memory/tegra/Kconfig10
-rw-r--r--drivers/memory/tegra/Makefile2
-rw-r--r--drivers/memory/tegra/mc.c136
-rw-r--r--drivers/memory/tegra/tegra124-emc.c1140
-rw-r--r--drivers/memory/tegra/tegra124.c44
-rw-r--r--include/soc/tegra/emc.h19
-rw-r--r--include/soc/tegra/mc.h14
9 files changed, 1820 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
index f3db93c85eea..3338a2834ad7 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
@@ -1,6 +1,9 @@
1NVIDIA Tegra Memory Controller device tree bindings 1NVIDIA Tegra Memory Controller device tree bindings
2=================================================== 2===================================================
3 3
4memory-controller node
5----------------------
6
4Required properties: 7Required properties:
5- compatible: Should be "nvidia,tegra<chip>-mc" 8- compatible: Should be "nvidia,tegra<chip>-mc"
6- reg: Physical base address and length of the controller's registers. 9- reg: Physical base address and length of the controller's registers.
@@ -15,9 +18,49 @@ Required properties:
15This device implements an IOMMU that complies with the generic IOMMU binding. 18This device implements an IOMMU that complies with the generic IOMMU binding.
16See ../iommu/iommu.txt for details. 19See ../iommu/iommu.txt for details.
17 20
18Example: 21emc-timings subnode
19-------- 22-------------------
23
24The node should contain a "emc-timings" subnode for each supported RAM type (see field RAM_CODE in
25register PMC_STRAPPING_OPT_A).
26
27Required properties for "emc-timings" nodes :
28- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is used for.
29
30timing subnode
31--------------
32
33Each "emc-timings" node should contain a subnode for every supported EMC clock rate.
34
35Required properties for timing nodes :
36- clock-frequency : Should contain the memory clock rate in Hz.
37- nvidia,emem-configuration : Values to be written to the EMEM register block. For the Tegra124 SoC
38(see section "15.6.1 MC Registers" in the TRM), these are the registers whose values need to be
39specified, according to the board documentation:
40
41 MC_EMEM_ARB_CFG
42 MC_EMEM_ARB_OUTSTANDING_REQ
43 MC_EMEM_ARB_TIMING_RCD
44 MC_EMEM_ARB_TIMING_RP
45 MC_EMEM_ARB_TIMING_RC
46 MC_EMEM_ARB_TIMING_RAS
47 MC_EMEM_ARB_TIMING_FAW
48 MC_EMEM_ARB_TIMING_RRD
49 MC_EMEM_ARB_TIMING_RAP2PRE
50 MC_EMEM_ARB_TIMING_WAP2PRE
51 MC_EMEM_ARB_TIMING_R2R
52 MC_EMEM_ARB_TIMING_W2W
53 MC_EMEM_ARB_TIMING_R2W
54 MC_EMEM_ARB_TIMING_W2R
55 MC_EMEM_ARB_DA_TURNS
56 MC_EMEM_ARB_DA_COVERS
57 MC_EMEM_ARB_MISC0
58 MC_EMEM_ARB_MISC1
59 MC_EMEM_ARB_RING1_THROTTLE
20 60
61Example SoC include file:
62
63/ {
21 mc: memory-controller@0,70019000 { 64 mc: memory-controller@0,70019000 {
22 compatible = "nvidia,tegra124-mc"; 65 compatible = "nvidia,tegra124-mc";
23 reg = <0x0 0x70019000 0x0 0x1000>; 66 reg = <0x0 0x70019000 0x0 0x1000>;
@@ -34,3 +77,40 @@ Example:
34 ... 77 ...
35 iommus = <&mc TEGRA_SWGROUP_SDMMC1A>; 78 iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
36 }; 79 };
80};
81
82Example board file:
83
84/ {
85 memory-controller@0,70019000 {
86 emc-timings-3 {
87 nvidia,ram-code = <3>;
88
89 timing-12750000 {
90 clock-frequency = <12750000>;
91
92 nvidia,emem-configuration = <
93 0x40040001 /* MC_EMEM_ARB_CFG */
94 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */
95 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */
96 0x00000001 /* MC_EMEM_ARB_TIMING_RP */
97 0x00000002 /* MC_EMEM_ARB_TIMING_RC */
98 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */
99 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */
100 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
101 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */
102 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */
103 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */
104 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
105 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */
106 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */
107 0x06030203 /* MC_EMEM_ARB_DA_TURNS */
108 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */
109 0x77e30303 /* MC_EMEM_ARB_MISC0 */
110 0x70000f03 /* MC_EMEM_ARB_MISC1 */
111 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */
112 >;
113 };
114 };
115 };
116};
diff --git a/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
new file mode 100644
index 000000000000..b59c625d6336
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
@@ -0,0 +1,374 @@
1NVIDIA Tegra124 SoC EMC (external memory controller)
2====================================================
3
4Required properties :
5- compatible : Should be "nvidia,tegra124-emc".
6- reg : physical base address and length of the controller's registers.
7- nvidia,memory-controller : phandle of the MC driver.
8
9The node should contain a "emc-timings" subnode for each supported RAM type
10(see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
11being its RAM_CODE.
12
13Required properties for "emc-timings" nodes :
14- nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
15used for.
16
17Each "emc-timings" node should contain a "timing" subnode for every supported
18EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
19their unit address.
20
21Required properties for "timing" nodes :
22- clock-frequency : Should contain the memory clock rate in Hz.
23- The following properties contain EMC timing characterization values
24(specified in the board documentation) :
25 - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
26 - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
27 - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
28 - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
29 - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
30 - nvidia,emc-cfg : EMC_CFG
31 - nvidia,emc-cfg-2 : EMC_CFG_2
32 - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
33 - nvidia,emc-mode-1 : Mode Register 1
34 - nvidia,emc-mode-2 : Mode Register 2
35 - nvidia,emc-mode-4 : Mode Register 4
36 - nvidia,emc-mode-reset : Mode Register 0
37 - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
38 - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
39 - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
40 - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
41 - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
42- nvidia,emc-configuration : EMC timing characterization data. These are the
43registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
44be specified, according to the board documentation:
45
46 EMC_RC
47 EMC_RFC
48 EMC_RFC_SLR
49 EMC_RAS
50 EMC_RP
51 EMC_R2W
52 EMC_W2R
53 EMC_R2P
54 EMC_W2P
55 EMC_RD_RCD
56 EMC_WR_RCD
57 EMC_RRD
58 EMC_REXT
59 EMC_WEXT
60 EMC_WDV
61 EMC_WDV_MASK
62 EMC_QUSE
63 EMC_QUSE_WIDTH
64 EMC_IBDLY
65 EMC_EINPUT
66 EMC_EINPUT_DURATION
67 EMC_PUTERM_EXTRA
68 EMC_PUTERM_WIDTH
69 EMC_PUTERM_ADJ
70 EMC_CDB_CNTL_1
71 EMC_CDB_CNTL_2
72 EMC_CDB_CNTL_3
73 EMC_QRST
74 EMC_QSAFE
75 EMC_RDV
76 EMC_RDV_MASK
77 EMC_REFRESH
78 EMC_BURST_REFRESH_NUM
79 EMC_PRE_REFRESH_REQ_CNT
80 EMC_PDEX2WR
81 EMC_PDEX2RD
82 EMC_PCHG2PDEN
83 EMC_ACT2PDEN
84 EMC_AR2PDEN
85 EMC_RW2PDEN
86 EMC_TXSR
87 EMC_TXSRDLL
88 EMC_TCKE
89 EMC_TCKESR
90 EMC_TPD
91 EMC_TFAW
92 EMC_TRPAB
93 EMC_TCLKSTABLE
94 EMC_TCLKSTOP
95 EMC_TREFBW
96 EMC_FBIO_CFG6
97 EMC_ODT_WRITE
98 EMC_ODT_READ
99 EMC_FBIO_CFG5
100 EMC_CFG_DIG_DLL
101 EMC_CFG_DIG_DLL_PERIOD
102 EMC_DLL_XFORM_DQS0
103 EMC_DLL_XFORM_DQS1
104 EMC_DLL_XFORM_DQS2
105 EMC_DLL_XFORM_DQS3
106 EMC_DLL_XFORM_DQS4
107 EMC_DLL_XFORM_DQS5
108 EMC_DLL_XFORM_DQS6
109 EMC_DLL_XFORM_DQS7
110 EMC_DLL_XFORM_DQS8
111 EMC_DLL_XFORM_DQS9
112 EMC_DLL_XFORM_DQS10
113 EMC_DLL_XFORM_DQS11
114 EMC_DLL_XFORM_DQS12
115 EMC_DLL_XFORM_DQS13
116 EMC_DLL_XFORM_DQS14
117 EMC_DLL_XFORM_DQS15
118 EMC_DLL_XFORM_QUSE0
119 EMC_DLL_XFORM_QUSE1
120 EMC_DLL_XFORM_QUSE2
121 EMC_DLL_XFORM_QUSE3
122 EMC_DLL_XFORM_QUSE4
123 EMC_DLL_XFORM_QUSE5
124 EMC_DLL_XFORM_QUSE6
125 EMC_DLL_XFORM_QUSE7
126 EMC_DLL_XFORM_ADDR0
127 EMC_DLL_XFORM_ADDR1
128 EMC_DLL_XFORM_ADDR2
129 EMC_DLL_XFORM_ADDR3
130 EMC_DLL_XFORM_ADDR4
131 EMC_DLL_XFORM_ADDR5
132 EMC_DLL_XFORM_QUSE8
133 EMC_DLL_XFORM_QUSE9
134 EMC_DLL_XFORM_QUSE10
135 EMC_DLL_XFORM_QUSE11
136 EMC_DLL_XFORM_QUSE12
137 EMC_DLL_XFORM_QUSE13
138 EMC_DLL_XFORM_QUSE14
139 EMC_DLL_XFORM_QUSE15
140 EMC_DLI_TRIM_TXDQS0
141 EMC_DLI_TRIM_TXDQS1
142 EMC_DLI_TRIM_TXDQS2
143 EMC_DLI_TRIM_TXDQS3
144 EMC_DLI_TRIM_TXDQS4
145 EMC_DLI_TRIM_TXDQS5
146 EMC_DLI_TRIM_TXDQS6
147 EMC_DLI_TRIM_TXDQS7
148 EMC_DLI_TRIM_TXDQS8
149 EMC_DLI_TRIM_TXDQS9
150 EMC_DLI_TRIM_TXDQS10
151 EMC_DLI_TRIM_TXDQS11
152 EMC_DLI_TRIM_TXDQS12
153 EMC_DLI_TRIM_TXDQS13
154 EMC_DLI_TRIM_TXDQS14
155 EMC_DLI_TRIM_TXDQS15
156 EMC_DLL_XFORM_DQ0
157 EMC_DLL_XFORM_DQ1
158 EMC_DLL_XFORM_DQ2
159 EMC_DLL_XFORM_DQ3
160 EMC_DLL_XFORM_DQ4
161 EMC_DLL_XFORM_DQ5
162 EMC_DLL_XFORM_DQ6
163 EMC_DLL_XFORM_DQ7
164 EMC_XM2CMDPADCTRL
165 EMC_XM2CMDPADCTRL4
166 EMC_XM2CMDPADCTRL5
167 EMC_XM2DQPADCTRL2
168 EMC_XM2DQPADCTRL3
169 EMC_XM2CLKPADCTRL
170 EMC_XM2CLKPADCTRL2
171 EMC_XM2COMPPADCTRL
172 EMC_XM2VTTGENPADCTRL
173 EMC_XM2VTTGENPADCTRL2
174 EMC_XM2VTTGENPADCTRL3
175 EMC_XM2DQSPADCTRL3
176 EMC_XM2DQSPADCTRL4
177 EMC_XM2DQSPADCTRL5
178 EMC_XM2DQSPADCTRL6
179 EMC_DSR_VTTGEN_DRV
180 EMC_TXDSRVTTGEN
181 EMC_FBIO_SPARE
182 EMC_ZCAL_WAIT_CNT
183 EMC_MRS_WAIT_CNT2
184 EMC_CTT
185 EMC_CTT_DURATION
186 EMC_CFG_PIPE
187 EMC_DYN_SELF_REF_CONTROL
188 EMC_QPOP
189
190Example SoC include file:
191
192/ {
193 emc@0,7001b000 {
194 compatible = "nvidia,tegra124-emc";
195 reg = <0x0 0x7001b000 0x0 0x1000>;
196
197 nvidia,memory-controller = <&mc>;
198 };
199};
200
201Example board file:
202
203/ {
204 emc@0,7001b000 {
205 emc-timings-3 {
206 nvidia,ram-code = <3>;
207
208 timing-12750000 {
209 clock-frequency = <12750000>;
210
211 nvidia,emc-zcal-cnt-long = <0x00000042>;
212 nvidia,emc-auto-cal-interval = <0x001fffff>;
213 nvidia,emc-ctt-term-ctrl = <0x00000802>;
214 nvidia,emc-cfg = <0x73240000>;
215 nvidia,emc-cfg-2 = <0x000008c5>;
216 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
217 nvidia,emc-bgbias-ctl0 = <0x00000008>;
218 nvidia,emc-auto-cal-config = <0xa1430000>;
219 nvidia,emc-auto-cal-config2 = <0x00000000>;
220 nvidia,emc-auto-cal-config3 = <0x00000000>;
221 nvidia,emc-mode-reset = <0x80001221>;
222 nvidia,emc-mode-1 = <0x80100003>;
223 nvidia,emc-mode-2 = <0x80200008>;
224 nvidia,emc-mode-4 = <0x00000000>;
225
226 nvidia,emc-configuration = <
227 0x00000000 /* EMC_RC */
228 0x00000003 /* EMC_RFC */
229 0x00000000 /* EMC_RFC_SLR */
230 0x00000000 /* EMC_RAS */
231 0x00000000 /* EMC_RP */
232 0x00000004 /* EMC_R2W */
233 0x0000000a /* EMC_W2R */
234 0x00000003 /* EMC_R2P */
235 0x0000000b /* EMC_W2P */
236 0x00000000 /* EMC_RD_RCD */
237 0x00000000 /* EMC_WR_RCD */
238 0x00000003 /* EMC_RRD */
239 0x00000003 /* EMC_REXT */
240 0x00000000 /* EMC_WEXT */
241 0x00000006 /* EMC_WDV */
242 0x00000006 /* EMC_WDV_MASK */
243 0x00000006 /* EMC_QUSE */
244 0x00000002 /* EMC_QUSE_WIDTH */
245 0x00000000 /* EMC_IBDLY */
246 0x00000005 /* EMC_EINPUT */
247 0x00000005 /* EMC_EINPUT_DURATION */
248 0x00010000 /* EMC_PUTERM_EXTRA */
249 0x00000003 /* EMC_PUTERM_WIDTH */
250 0x00000000 /* EMC_PUTERM_ADJ */
251 0x00000000 /* EMC_CDB_CNTL_1 */
252 0x00000000 /* EMC_CDB_CNTL_2 */
253 0x00000000 /* EMC_CDB_CNTL_3 */
254 0x00000004 /* EMC_QRST */
255 0x0000000c /* EMC_QSAFE */
256 0x0000000d /* EMC_RDV */
257 0x0000000f /* EMC_RDV_MASK */
258 0x00000060 /* EMC_REFRESH */
259 0x00000000 /* EMC_BURST_REFRESH_NUM */
260 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
261 0x00000002 /* EMC_PDEX2WR */
262 0x00000002 /* EMC_PDEX2RD */
263 0x00000001 /* EMC_PCHG2PDEN */
264 0x00000000 /* EMC_ACT2PDEN */
265 0x00000007 /* EMC_AR2PDEN */
266 0x0000000f /* EMC_RW2PDEN */
267 0x00000005 /* EMC_TXSR */
268 0x00000005 /* EMC_TXSRDLL */
269 0x00000004 /* EMC_TCKE */
270 0x00000005 /* EMC_TCKESR */
271 0x00000004 /* EMC_TPD */
272 0x00000000 /* EMC_TFAW */
273 0x00000000 /* EMC_TRPAB */
274 0x00000005 /* EMC_TCLKSTABLE */
275 0x00000005 /* EMC_TCLKSTOP */
276 0x00000064 /* EMC_TREFBW */
277 0x00000000 /* EMC_FBIO_CFG6 */
278 0x00000000 /* EMC_ODT_WRITE */
279 0x00000000 /* EMC_ODT_READ */
280 0x106aa298 /* EMC_FBIO_CFG5 */
281 0x002c00a0 /* EMC_CFG_DIG_DLL */
282 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
283 0x00064000 /* EMC_DLL_XFORM_DQS0 */
284 0x00064000 /* EMC_DLL_XFORM_DQS1 */
285 0x00064000 /* EMC_DLL_XFORM_DQS2 */
286 0x00064000 /* EMC_DLL_XFORM_DQS3 */
287 0x00064000 /* EMC_DLL_XFORM_DQS4 */
288 0x00064000 /* EMC_DLL_XFORM_DQS5 */
289 0x00064000 /* EMC_DLL_XFORM_DQS6 */
290 0x00064000 /* EMC_DLL_XFORM_DQS7 */
291 0x00064000 /* EMC_DLL_XFORM_DQS8 */
292 0x00064000 /* EMC_DLL_XFORM_DQS9 */
293 0x00064000 /* EMC_DLL_XFORM_DQS10 */
294 0x00064000 /* EMC_DLL_XFORM_DQS11 */
295 0x00064000 /* EMC_DLL_XFORM_DQS12 */
296 0x00064000 /* EMC_DLL_XFORM_DQS13 */
297 0x00064000 /* EMC_DLL_XFORM_DQS14 */
298 0x00064000 /* EMC_DLL_XFORM_DQS15 */
299 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
300 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
301 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
302 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
303 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
304 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
305 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
306 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
307 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
308 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
309 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
310 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
311 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
312 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
313 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
314 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
315 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
316 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
317 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
318 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
319 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
320 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
321 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
322 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
323 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
324 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
325 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
326 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
327 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
328 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
329 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
330 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
331 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
332 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
333 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
334 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
335 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
336 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
337 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
338 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
339 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
340 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
341 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
342 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
343 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
344 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
345 0x10000280 /* EMC_XM2CMDPADCTRL */
346 0x00000000 /* EMC_XM2CMDPADCTRL4 */
347 0x00111111 /* EMC_XM2CMDPADCTRL5 */
348 0x00000000 /* EMC_XM2DQPADCTRL2 */
349 0x00000000 /* EMC_XM2DQPADCTRL3 */
350 0x77ffc081 /* EMC_XM2CLKPADCTRL */
351 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
352 0x81f1f108 /* EMC_XM2COMPPADCTRL */
353 0x07070004 /* EMC_XM2VTTGENPADCTRL */
354 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
355 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
356 0x51451400 /* EMC_XM2DQSPADCTRL3 */
357 0x00514514 /* EMC_XM2DQSPADCTRL4 */
358 0x00514514 /* EMC_XM2DQSPADCTRL5 */
359 0x51451400 /* EMC_XM2DQSPADCTRL6 */
360 0x0000003f /* EMC_DSR_VTTGEN_DRV */
361 0x00000007 /* EMC_TXDSRVTTGEN */
362 0x00000000 /* EMC_FBIO_SPARE */
363 0x00000042 /* EMC_ZCAL_WAIT_CNT */
364 0x000e000e /* EMC_MRS_WAIT_CNT2 */
365 0x00000000 /* EMC_CTT */
366 0x00000003 /* EMC_CTT_DURATION */
367 0x0000f2f3 /* EMC_CFG_PIPE */
368 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
369 0x0000000a /* EMC_QPOP */
370 >;
371 };
372 };
373 };
374};
diff --git a/drivers/memory/tegra/Kconfig b/drivers/memory/tegra/Kconfig
index 571087621827..6d74e499e18d 100644
--- a/drivers/memory/tegra/Kconfig
+++ b/drivers/memory/tegra/Kconfig
@@ -5,3 +5,13 @@ config TEGRA_MC
5 help 5 help
6 This driver supports the Memory Controller (MC) hardware found on 6 This driver supports the Memory Controller (MC) hardware found on
7 NVIDIA Tegra SoCs. 7 NVIDIA Tegra SoCs.
8
9config TEGRA124_EMC
10 bool "NVIDIA Tegra124 External Memory Controller driver"
11 default y
12 depends on TEGRA_MC && ARCH_TEGRA_124_SOC
13 help
14 This driver is for the External Memory Controller (EMC) found on
15 Tegra124 chips. The EMC controls the external DRAM on the board.
16 This driver is required to change memory timings / clock rate for
17 external memory.
diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile
index 9d4f4319b527..6a0b9ac54f05 100644
--- a/drivers/memory/tegra/Makefile
+++ b/drivers/memory/tegra/Makefile
@@ -6,3 +6,5 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_124_SOC) += tegra124.o
6tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o 6tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
7 7
8obj-$(CONFIG_TEGRA_MC) += tegra-mc.o 8obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
9
10obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 918236457c16..c71ede67e6c8 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -13,6 +13,9 @@
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/platform_device.h> 14#include <linux/platform_device.h>
15#include <linux/slab.h> 15#include <linux/slab.h>
16#include <linux/sort.h>
17
18#include <soc/tegra/fuse.h>
16 19
17#include "mc.h" 20#include "mc.h"
18 21
@@ -48,6 +51,9 @@
48#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff 51#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff
49#define MC_EMEM_ARB_MISC0 0xd8 52#define MC_EMEM_ARB_MISC0 0xd8
50 53
54#define MC_EMEM_ADR_CFG 0x54
55#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0)
56
51static const struct of_device_id tegra_mc_of_match[] = { 57static const struct of_device_id tegra_mc_of_match[] = {
52#ifdef CONFIG_ARCH_TEGRA_3x_SOC 58#ifdef CONFIG_ARCH_TEGRA_3x_SOC
53 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc }, 59 { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
@@ -94,6 +100,130 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
94 return 0; 100 return 0;
95} 101}
96 102
103void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
104{
105 unsigned int i;
106 struct tegra_mc_timing *timing = NULL;
107
108 for (i = 0; i < mc->num_timings; i++) {
109 if (mc->timings[i].rate == rate) {
110 timing = &mc->timings[i];
111 break;
112 }
113 }
114
115 if (!timing) {
116 dev_err(mc->dev, "no memory timing registered for rate %lu\n",
117 rate);
118 return;
119 }
120
121 for (i = 0; i < mc->soc->num_emem_regs; ++i)
122 mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
123}
124
125unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
126{
127 u8 dram_count;
128
129 dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
130 dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
131 dram_count++;
132
133 return dram_count;
134}
135
136static int load_one_timing(struct tegra_mc *mc,
137 struct tegra_mc_timing *timing,
138 struct device_node *node)
139{
140 int err;
141 u32 tmp;
142
143 err = of_property_read_u32(node, "clock-frequency", &tmp);
144 if (err) {
145 dev_err(mc->dev,
146 "timing %s: failed to read rate\n", node->name);
147 return err;
148 }
149
150 timing->rate = tmp;
151 timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
152 sizeof(u32), GFP_KERNEL);
153 if (!timing->emem_data)
154 return -ENOMEM;
155
156 err = of_property_read_u32_array(node, "nvidia,emem-configuration",
157 timing->emem_data,
158 mc->soc->num_emem_regs);
159 if (err) {
160 dev_err(mc->dev,
161 "timing %s: failed to read EMEM configuration\n",
162 node->name);
163 return err;
164 }
165
166 return 0;
167}
168
169static int load_timings(struct tegra_mc *mc, struct device_node *node)
170{
171 struct device_node *child;
172 struct tegra_mc_timing *timing;
173 int child_count = of_get_child_count(node);
174 int i = 0, err;
175
176 mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
177 GFP_KERNEL);
178 if (!mc->timings)
179 return -ENOMEM;
180
181 mc->num_timings = child_count;
182
183 for_each_child_of_node(node, child) {
184 timing = &mc->timings[i++];
185
186 err = load_one_timing(mc, timing, child);
187 if (err)
188 return err;
189 }
190
191 return 0;
192}
193
194static int tegra_mc_setup_timings(struct tegra_mc *mc)
195{
196 struct device_node *node;
197 u32 ram_code, node_ram_code;
198 int err;
199
200 ram_code = tegra_read_ram_code();
201
202 mc->num_timings = 0;
203
204 for_each_child_of_node(mc->dev->of_node, node) {
205 err = of_property_read_u32(node, "nvidia,ram-code",
206 &node_ram_code);
207 if (err || (node_ram_code != ram_code)) {
208 of_node_put(node);
209 continue;
210 }
211
212 err = load_timings(mc, node);
213 if (err)
214 return err;
215 of_node_put(node);
216 break;
217 }
218
219 if (mc->num_timings == 0)
220 dev_warn(mc->dev,
221 "no memory timings for RAM code %u registered\n",
222 ram_code);
223
224 return 0;
225}
226
97static const char *const status_names[32] = { 227static const char *const status_names[32] = {
98 [ 1] = "External interrupt", 228 [ 1] = "External interrupt",
99 [ 6] = "EMEM address decode error", 229 [ 6] = "EMEM address decode error",
@@ -251,6 +381,12 @@ static int tegra_mc_probe(struct platform_device *pdev)
251 return err; 381 return err;
252 } 382 }
253 383
384 err = tegra_mc_setup_timings(mc);
385 if (err < 0) {
386 dev_err(&pdev->dev, "failed to setup timings: %d\n", err);
387 return err;
388 }
389
254 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) { 390 if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU)) {
255 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc); 391 mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
256 if (IS_ERR(mc->smmu)) { 392 if (IS_ERR(mc->smmu)) {
diff --git a/drivers/memory/tegra/tegra124-emc.c b/drivers/memory/tegra/tegra124-emc.c
new file mode 100644
index 000000000000..8620355776fe
--- /dev/null
+++ b/drivers/memory/tegra/tegra124-emc.c
@@ -0,0 +1,1140 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Author:
5 * Mikko Perttunen <mperttunen@nvidia.com>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/clk.h>
20#include <linux/clkdev.h>
21#include <linux/debugfs.h>
22#include <linux/delay.h>
23#include <linux/of_address.h>
24#include <linux/of_platform.h>
25#include <linux/platform_device.h>
26#include <linux/sort.h>
27#include <linux/string.h>
28
29#include <soc/tegra/emc.h>
30#include <soc/tegra/fuse.h>
31#include <soc/tegra/mc.h>
32
33#define EMC_FBIO_CFG5 0x104
34#define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
35#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT 0
36
37#define EMC_INTSTATUS 0x0
38#define EMC_INTSTATUS_CLKCHANGE_COMPLETE BIT(4)
39
40#define EMC_CFG 0xc
41#define EMC_CFG_DRAM_CLKSTOP_PD BIT(31)
42#define EMC_CFG_DRAM_CLKSTOP_SR BIT(30)
43#define EMC_CFG_DRAM_ACPD BIT(29)
44#define EMC_CFG_DYN_SREF BIT(28)
45#define EMC_CFG_PWR_MASK ((0xF << 28) | BIT(18))
46#define EMC_CFG_DSR_VTTGEN_DRV_EN BIT(18)
47
48#define EMC_REFCTRL 0x20
49#define EMC_REFCTRL_DEV_SEL_SHIFT 0
50#define EMC_REFCTRL_ENABLE BIT(31)
51
52#define EMC_TIMING_CONTROL 0x28
53#define EMC_RC 0x2c
54#define EMC_RFC 0x30
55#define EMC_RAS 0x34
56#define EMC_RP 0x38
57#define EMC_R2W 0x3c
58#define EMC_W2R 0x40
59#define EMC_R2P 0x44
60#define EMC_W2P 0x48
61#define EMC_RD_RCD 0x4c
62#define EMC_WR_RCD 0x50
63#define EMC_RRD 0x54
64#define EMC_REXT 0x58
65#define EMC_WDV 0x5c
66#define EMC_QUSE 0x60
67#define EMC_QRST 0x64
68#define EMC_QSAFE 0x68
69#define EMC_RDV 0x6c
70#define EMC_REFRESH 0x70
71#define EMC_BURST_REFRESH_NUM 0x74
72#define EMC_PDEX2WR 0x78
73#define EMC_PDEX2RD 0x7c
74#define EMC_PCHG2PDEN 0x80
75#define EMC_ACT2PDEN 0x84
76#define EMC_AR2PDEN 0x88
77#define EMC_RW2PDEN 0x8c
78#define EMC_TXSR 0x90
79#define EMC_TCKE 0x94
80#define EMC_TFAW 0x98
81#define EMC_TRPAB 0x9c
82#define EMC_TCLKSTABLE 0xa0
83#define EMC_TCLKSTOP 0xa4
84#define EMC_TREFBW 0xa8
85#define EMC_ODT_WRITE 0xb0
86#define EMC_ODT_READ 0xb4
87#define EMC_WEXT 0xb8
88#define EMC_CTT 0xbc
89#define EMC_RFC_SLR 0xc0
90#define EMC_MRS_WAIT_CNT2 0xc4
91
92#define EMC_MRS_WAIT_CNT 0xc8
93#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT 0
94#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK \
95 (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
96#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT 16
97#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK \
98 (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
99
100#define EMC_MRS 0xcc
101#define EMC_MODE_SET_DLL_RESET BIT(8)
102#define EMC_MODE_SET_LONG_CNT BIT(26)
103#define EMC_EMRS 0xd0
104#define EMC_REF 0xd4
105#define EMC_PRE 0xd8
106
107#define EMC_SELF_REF 0xe0
108#define EMC_SELF_REF_CMD_ENABLED BIT(0)
109#define EMC_SELF_REF_DEV_SEL_SHIFT 30
110
111#define EMC_MRW 0xe8
112
113#define EMC_MRR 0xec
114#define EMC_MRR_MA_SHIFT 16
115#define LPDDR2_MR4_TEMP_SHIFT 0
116
117#define EMC_XM2DQSPADCTRL3 0xf8
118#define EMC_FBIO_SPARE 0x100
119
120#define EMC_FBIO_CFG6 0x114
121#define EMC_EMRS2 0x12c
122#define EMC_MRW2 0x134
123#define EMC_MRW4 0x13c
124#define EMC_EINPUT 0x14c
125#define EMC_EINPUT_DURATION 0x150
126#define EMC_PUTERM_EXTRA 0x154
127#define EMC_TCKESR 0x158
128#define EMC_TPD 0x15c
129
130#define EMC_AUTO_CAL_CONFIG 0x2a4
131#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START BIT(31)
132#define EMC_AUTO_CAL_INTERVAL 0x2a8
133#define EMC_AUTO_CAL_STATUS 0x2ac
134#define EMC_AUTO_CAL_STATUS_ACTIVE BIT(31)
135#define EMC_STATUS 0x2b4
136#define EMC_STATUS_TIMING_UPDATE_STALLED BIT(23)
137
138#define EMC_CFG_2 0x2b8
139#define EMC_CFG_2_MODE_SHIFT 0
140#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR BIT(6)
141
142#define EMC_CFG_DIG_DLL 0x2bc
143#define EMC_CFG_DIG_DLL_PERIOD 0x2c0
144#define EMC_RDV_MASK 0x2cc
145#define EMC_WDV_MASK 0x2d0
146#define EMC_CTT_DURATION 0x2d8
147#define EMC_CTT_TERM_CTRL 0x2dc
148#define EMC_ZCAL_INTERVAL 0x2e0
149#define EMC_ZCAL_WAIT_CNT 0x2e4
150
151#define EMC_ZQ_CAL 0x2ec
152#define EMC_ZQ_CAL_CMD BIT(0)
153#define EMC_ZQ_CAL_LONG BIT(4)
154#define EMC_ZQ_CAL_LONG_CMD_DEV0 \
155 (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
156#define EMC_ZQ_CAL_LONG_CMD_DEV1 \
157 (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
158
159#define EMC_XM2CMDPADCTRL 0x2f0
160#define EMC_XM2DQSPADCTRL 0x2f8
161#define EMC_XM2DQSPADCTRL2 0x2fc
162#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE BIT(0)
163#define EMC_XM2DQSPADCTRL2_VREF_ENABLE BIT(5)
164#define EMC_XM2DQPADCTRL 0x300
165#define EMC_XM2DQPADCTRL2 0x304
166#define EMC_XM2CLKPADCTRL 0x308
167#define EMC_XM2COMPPADCTRL 0x30c
168#define EMC_XM2VTTGENPADCTRL 0x310
169#define EMC_XM2VTTGENPADCTRL2 0x314
170#define EMC_XM2VTTGENPADCTRL3 0x318
171#define EMC_XM2DQSPADCTRL4 0x320
172#define EMC_DLL_XFORM_DQS0 0x328
173#define EMC_DLL_XFORM_DQS1 0x32c
174#define EMC_DLL_XFORM_DQS2 0x330
175#define EMC_DLL_XFORM_DQS3 0x334
176#define EMC_DLL_XFORM_DQS4 0x338
177#define EMC_DLL_XFORM_DQS5 0x33c
178#define EMC_DLL_XFORM_DQS6 0x340
179#define EMC_DLL_XFORM_DQS7 0x344
180#define EMC_DLL_XFORM_QUSE0 0x348
181#define EMC_DLL_XFORM_QUSE1 0x34c
182#define EMC_DLL_XFORM_QUSE2 0x350
183#define EMC_DLL_XFORM_QUSE3 0x354
184#define EMC_DLL_XFORM_QUSE4 0x358
185#define EMC_DLL_XFORM_QUSE5 0x35c
186#define EMC_DLL_XFORM_QUSE6 0x360
187#define EMC_DLL_XFORM_QUSE7 0x364
188#define EMC_DLL_XFORM_DQ0 0x368
189#define EMC_DLL_XFORM_DQ1 0x36c
190#define EMC_DLL_XFORM_DQ2 0x370
191#define EMC_DLL_XFORM_DQ3 0x374
192#define EMC_DLI_TRIM_TXDQS0 0x3a8
193#define EMC_DLI_TRIM_TXDQS1 0x3ac
194#define EMC_DLI_TRIM_TXDQS2 0x3b0
195#define EMC_DLI_TRIM_TXDQS3 0x3b4
196#define EMC_DLI_TRIM_TXDQS4 0x3b8
197#define EMC_DLI_TRIM_TXDQS5 0x3bc
198#define EMC_DLI_TRIM_TXDQS6 0x3c0
199#define EMC_DLI_TRIM_TXDQS7 0x3c4
200#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
201#define EMC_SEL_DPD_CTRL 0x3d8
202#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD BIT(8)
203#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD BIT(5)
204#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD BIT(4)
205#define EMC_SEL_DPD_CTRL_CA_SEL_DPD BIT(3)
206#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD BIT(2)
207#define EMC_SEL_DPD_CTRL_DDR3_MASK \
208 ((0xf << 2) | BIT(8))
209#define EMC_SEL_DPD_CTRL_MASK \
210 ((0x3 << 2) | BIT(5) | BIT(8))
211#define EMC_PRE_REFRESH_REQ_CNT 0x3dc
212#define EMC_DYN_SELF_REF_CONTROL 0x3e0
213#define EMC_TXSRDLL 0x3e4
214#define EMC_CCFIFO_ADDR 0x3e8
215#define EMC_CCFIFO_DATA 0x3ec
216#define EMC_CCFIFO_STATUS 0x3f0
217#define EMC_CDB_CNTL_1 0x3f4
218#define EMC_CDB_CNTL_2 0x3f8
219#define EMC_XM2CLKPADCTRL2 0x3fc
220#define EMC_AUTO_CAL_CONFIG2 0x458
221#define EMC_AUTO_CAL_CONFIG3 0x45c
222#define EMC_IBDLY 0x468
223#define EMC_DLL_XFORM_ADDR0 0x46c
224#define EMC_DLL_XFORM_ADDR1 0x470
225#define EMC_DLL_XFORM_ADDR2 0x474
226#define EMC_DSR_VTTGEN_DRV 0x47c
227#define EMC_TXDSRVTTGEN 0x480
228#define EMC_XM2CMDPADCTRL4 0x484
229#define EMC_XM2CMDPADCTRL5 0x488
230#define EMC_DLL_XFORM_DQS8 0x4a0
231#define EMC_DLL_XFORM_DQS9 0x4a4
232#define EMC_DLL_XFORM_DQS10 0x4a8
233#define EMC_DLL_XFORM_DQS11 0x4ac
234#define EMC_DLL_XFORM_DQS12 0x4b0
235#define EMC_DLL_XFORM_DQS13 0x4b4
236#define EMC_DLL_XFORM_DQS14 0x4b8
237#define EMC_DLL_XFORM_DQS15 0x4bc
238#define EMC_DLL_XFORM_QUSE8 0x4c0
239#define EMC_DLL_XFORM_QUSE9 0x4c4
240#define EMC_DLL_XFORM_QUSE10 0x4c8
241#define EMC_DLL_XFORM_QUSE11 0x4cc
242#define EMC_DLL_XFORM_QUSE12 0x4d0
243#define EMC_DLL_XFORM_QUSE13 0x4d4
244#define EMC_DLL_XFORM_QUSE14 0x4d8
245#define EMC_DLL_XFORM_QUSE15 0x4dc
246#define EMC_DLL_XFORM_DQ4 0x4e0
247#define EMC_DLL_XFORM_DQ5 0x4e4
248#define EMC_DLL_XFORM_DQ6 0x4e8
249#define EMC_DLL_XFORM_DQ7 0x4ec
250#define EMC_DLI_TRIM_TXDQS8 0x520
251#define EMC_DLI_TRIM_TXDQS9 0x524
252#define EMC_DLI_TRIM_TXDQS10 0x528
253#define EMC_DLI_TRIM_TXDQS11 0x52c
254#define EMC_DLI_TRIM_TXDQS12 0x530
255#define EMC_DLI_TRIM_TXDQS13 0x534
256#define EMC_DLI_TRIM_TXDQS14 0x538
257#define EMC_DLI_TRIM_TXDQS15 0x53c
258#define EMC_CDB_CNTL_3 0x540
259#define EMC_XM2DQSPADCTRL5 0x544
260#define EMC_XM2DQSPADCTRL6 0x548
261#define EMC_XM2DQPADCTRL3 0x54c
262#define EMC_DLL_XFORM_ADDR3 0x550
263#define EMC_DLL_XFORM_ADDR4 0x554
264#define EMC_DLL_XFORM_ADDR5 0x558
265#define EMC_CFG_PIPE 0x560
266#define EMC_QPOP 0x564
267#define EMC_QUSE_WIDTH 0x568
268#define EMC_PUTERM_WIDTH 0x56c
269#define EMC_BGBIAS_CTL0 0x570
270#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX BIT(3)
271#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN BIT(2)
272#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD BIT(1)
273#define EMC_PUTERM_ADJ 0x574
274
275#define DRAM_DEV_SEL_ALL 0
276#define DRAM_DEV_SEL_0 (2 << 30)
277#define DRAM_DEV_SEL_1 (1 << 30)
278
279#define EMC_CFG_POWER_FEATURES_MASK \
280 (EMC_CFG_DYN_SREF | EMC_CFG_DRAM_ACPD | EMC_CFG_DRAM_CLKSTOP_SR | \
281 EMC_CFG_DRAM_CLKSTOP_PD | EMC_CFG_DSR_VTTGEN_DRV_EN)
282#define EMC_REFCTRL_DEV_SEL(n) (((n > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
283#define EMC_DRAM_DEV_SEL(n) ((n > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
284
285/* Maximum amount of time in us. to wait for changes to become effective */
286#define EMC_STATUS_UPDATE_TIMEOUT 1000
287
288enum emc_dram_type {
289 DRAM_TYPE_DDR3 = 0,
290 DRAM_TYPE_DDR1 = 1,
291 DRAM_TYPE_LPDDR3 = 2,
292 DRAM_TYPE_DDR2 = 3
293};
294
295enum emc_dll_change {
296 DLL_CHANGE_NONE,
297 DLL_CHANGE_ON,
298 DLL_CHANGE_OFF
299};
300
301static const unsigned long emc_burst_regs[] = {
302 EMC_RC,
303 EMC_RFC,
304 EMC_RFC_SLR,
305 EMC_RAS,
306 EMC_RP,
307 EMC_R2W,
308 EMC_W2R,
309 EMC_R2P,
310 EMC_W2P,
311 EMC_RD_RCD,
312 EMC_WR_RCD,
313 EMC_RRD,
314 EMC_REXT,
315 EMC_WEXT,
316 EMC_WDV,
317 EMC_WDV_MASK,
318 EMC_QUSE,
319 EMC_QUSE_WIDTH,
320 EMC_IBDLY,
321 EMC_EINPUT,
322 EMC_EINPUT_DURATION,
323 EMC_PUTERM_EXTRA,
324 EMC_PUTERM_WIDTH,
325 EMC_PUTERM_ADJ,
326 EMC_CDB_CNTL_1,
327 EMC_CDB_CNTL_2,
328 EMC_CDB_CNTL_3,
329 EMC_QRST,
330 EMC_QSAFE,
331 EMC_RDV,
332 EMC_RDV_MASK,
333 EMC_REFRESH,
334 EMC_BURST_REFRESH_NUM,
335 EMC_PRE_REFRESH_REQ_CNT,
336 EMC_PDEX2WR,
337 EMC_PDEX2RD,
338 EMC_PCHG2PDEN,
339 EMC_ACT2PDEN,
340 EMC_AR2PDEN,
341 EMC_RW2PDEN,
342 EMC_TXSR,
343 EMC_TXSRDLL,
344 EMC_TCKE,
345 EMC_TCKESR,
346 EMC_TPD,
347 EMC_TFAW,
348 EMC_TRPAB,
349 EMC_TCLKSTABLE,
350 EMC_TCLKSTOP,
351 EMC_TREFBW,
352 EMC_FBIO_CFG6,
353 EMC_ODT_WRITE,
354 EMC_ODT_READ,
355 EMC_FBIO_CFG5,
356 EMC_CFG_DIG_DLL,
357 EMC_CFG_DIG_DLL_PERIOD,
358 EMC_DLL_XFORM_DQS0,
359 EMC_DLL_XFORM_DQS1,
360 EMC_DLL_XFORM_DQS2,
361 EMC_DLL_XFORM_DQS3,
362 EMC_DLL_XFORM_DQS4,
363 EMC_DLL_XFORM_DQS5,
364 EMC_DLL_XFORM_DQS6,
365 EMC_DLL_XFORM_DQS7,
366 EMC_DLL_XFORM_DQS8,
367 EMC_DLL_XFORM_DQS9,
368 EMC_DLL_XFORM_DQS10,
369 EMC_DLL_XFORM_DQS11,
370 EMC_DLL_XFORM_DQS12,
371 EMC_DLL_XFORM_DQS13,
372 EMC_DLL_XFORM_DQS14,
373 EMC_DLL_XFORM_DQS15,
374 EMC_DLL_XFORM_QUSE0,
375 EMC_DLL_XFORM_QUSE1,
376 EMC_DLL_XFORM_QUSE2,
377 EMC_DLL_XFORM_QUSE3,
378 EMC_DLL_XFORM_QUSE4,
379 EMC_DLL_XFORM_QUSE5,
380 EMC_DLL_XFORM_QUSE6,
381 EMC_DLL_XFORM_QUSE7,
382 EMC_DLL_XFORM_ADDR0,
383 EMC_DLL_XFORM_ADDR1,
384 EMC_DLL_XFORM_ADDR2,
385 EMC_DLL_XFORM_ADDR3,
386 EMC_DLL_XFORM_ADDR4,
387 EMC_DLL_XFORM_ADDR5,
388 EMC_DLL_XFORM_QUSE8,
389 EMC_DLL_XFORM_QUSE9,
390 EMC_DLL_XFORM_QUSE10,
391 EMC_DLL_XFORM_QUSE11,
392 EMC_DLL_XFORM_QUSE12,
393 EMC_DLL_XFORM_QUSE13,
394 EMC_DLL_XFORM_QUSE14,
395 EMC_DLL_XFORM_QUSE15,
396 EMC_DLI_TRIM_TXDQS0,
397 EMC_DLI_TRIM_TXDQS1,
398 EMC_DLI_TRIM_TXDQS2,
399 EMC_DLI_TRIM_TXDQS3,
400 EMC_DLI_TRIM_TXDQS4,
401 EMC_DLI_TRIM_TXDQS5,
402 EMC_DLI_TRIM_TXDQS6,
403 EMC_DLI_TRIM_TXDQS7,
404 EMC_DLI_TRIM_TXDQS8,
405 EMC_DLI_TRIM_TXDQS9,
406 EMC_DLI_TRIM_TXDQS10,
407 EMC_DLI_TRIM_TXDQS11,
408 EMC_DLI_TRIM_TXDQS12,
409 EMC_DLI_TRIM_TXDQS13,
410 EMC_DLI_TRIM_TXDQS14,
411 EMC_DLI_TRIM_TXDQS15,
412 EMC_DLL_XFORM_DQ0,
413 EMC_DLL_XFORM_DQ1,
414 EMC_DLL_XFORM_DQ2,
415 EMC_DLL_XFORM_DQ3,
416 EMC_DLL_XFORM_DQ4,
417 EMC_DLL_XFORM_DQ5,
418 EMC_DLL_XFORM_DQ6,
419 EMC_DLL_XFORM_DQ7,
420 EMC_XM2CMDPADCTRL,
421 EMC_XM2CMDPADCTRL4,
422 EMC_XM2CMDPADCTRL5,
423 EMC_XM2DQPADCTRL2,
424 EMC_XM2DQPADCTRL3,
425 EMC_XM2CLKPADCTRL,
426 EMC_XM2CLKPADCTRL2,
427 EMC_XM2COMPPADCTRL,
428 EMC_XM2VTTGENPADCTRL,
429 EMC_XM2VTTGENPADCTRL2,
430 EMC_XM2VTTGENPADCTRL3,
431 EMC_XM2DQSPADCTRL3,
432 EMC_XM2DQSPADCTRL4,
433 EMC_XM2DQSPADCTRL5,
434 EMC_XM2DQSPADCTRL6,
435 EMC_DSR_VTTGEN_DRV,
436 EMC_TXDSRVTTGEN,
437 EMC_FBIO_SPARE,
438 EMC_ZCAL_WAIT_CNT,
439 EMC_MRS_WAIT_CNT2,
440 EMC_CTT,
441 EMC_CTT_DURATION,
442 EMC_CFG_PIPE,
443 EMC_DYN_SELF_REF_CONTROL,
444 EMC_QPOP
445};
446
447struct emc_timing {
448 unsigned long rate;
449
450 u32 emc_burst_data[ARRAY_SIZE(emc_burst_regs)];
451
452 u32 emc_auto_cal_config;
453 u32 emc_auto_cal_config2;
454 u32 emc_auto_cal_config3;
455 u32 emc_auto_cal_interval;
456 u32 emc_bgbias_ctl0;
457 u32 emc_cfg;
458 u32 emc_cfg_2;
459 u32 emc_ctt_term_ctrl;
460 u32 emc_mode_1;
461 u32 emc_mode_2;
462 u32 emc_mode_4;
463 u32 emc_mode_reset;
464 u32 emc_mrs_wait_cnt;
465 u32 emc_sel_dpd_ctrl;
466 u32 emc_xm2dqspadctrl2;
467 u32 emc_zcal_cnt_long;
468 u32 emc_zcal_interval;
469};
470
471struct tegra_emc {
472 struct device *dev;
473
474 struct tegra_mc *mc;
475
476 void __iomem *regs;
477
478 enum emc_dram_type dram_type;
479 unsigned int dram_num;
480
481 struct emc_timing last_timing;
482 struct emc_timing *timings;
483 unsigned int num_timings;
484};
485
486/* Timing change sequence functions */
487
488static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value,
489 unsigned long offset)
490{
491 writel(value, emc->regs + EMC_CCFIFO_DATA);
492 writel(offset, emc->regs + EMC_CCFIFO_ADDR);
493}
494
495static void emc_seq_update_timing(struct tegra_emc *emc)
496{
497 unsigned int i;
498 u32 value;
499
500 writel(1, emc->regs + EMC_TIMING_CONTROL);
501
502 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
503 value = readl(emc->regs + EMC_STATUS);
504 if ((value & EMC_STATUS_TIMING_UPDATE_STALLED) == 0)
505 return;
506 udelay(1);
507 }
508
509 dev_err(emc->dev, "timing update timed out\n");
510}
511
512static void emc_seq_disable_auto_cal(struct tegra_emc *emc)
513{
514 unsigned int i;
515 u32 value;
516
517 writel(0, emc->regs + EMC_AUTO_CAL_INTERVAL);
518
519 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
520 value = readl(emc->regs + EMC_AUTO_CAL_STATUS);
521 if ((value & EMC_AUTO_CAL_STATUS_ACTIVE) == 0)
522 return;
523 udelay(1);
524 }
525
526 dev_err(emc->dev, "auto cal disable timed out\n");
527}
528
529static void emc_seq_wait_clkchange(struct tegra_emc *emc)
530{
531 unsigned int i;
532 u32 value;
533
534 for (i = 0; i < EMC_STATUS_UPDATE_TIMEOUT; ++i) {
535 value = readl(emc->regs + EMC_INTSTATUS);
536 if (value & EMC_INTSTATUS_CLKCHANGE_COMPLETE)
537 return;
538 udelay(1);
539 }
540
541 dev_err(emc->dev, "clock change timed out\n");
542}
543
544static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
545 unsigned long rate)
546{
547 struct emc_timing *timing = NULL;
548 unsigned int i;
549
550 for (i = 0; i < emc->num_timings; i++) {
551 if (emc->timings[i].rate == rate) {
552 timing = &emc->timings[i];
553 break;
554 }
555 }
556
557 if (!timing) {
558 dev_err(emc->dev, "no timing for rate %lu\n", rate);
559 return NULL;
560 }
561
562 return timing;
563}
564
565int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
566 unsigned long rate)
567{
568 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
569 struct emc_timing *last = &emc->last_timing;
570 enum emc_dll_change dll_change;
571 unsigned int pre_wait = 0;
572 u32 val, val2, mask;
573 bool update = false;
574 unsigned int i;
575
576 if (!timing)
577 return -ENOENT;
578
579 if ((last->emc_mode_1 & 0x1) == (timing->emc_mode_1 & 0x1))
580 dll_change = DLL_CHANGE_NONE;
581 else if (timing->emc_mode_1 & 0x1)
582 dll_change = DLL_CHANGE_ON;
583 else
584 dll_change = DLL_CHANGE_OFF;
585
586 /* Clear CLKCHANGE_COMPLETE interrupts */
587 writel(EMC_INTSTATUS_CLKCHANGE_COMPLETE, emc->regs + EMC_INTSTATUS);
588
589 /* Disable dynamic self-refresh */
590 val = readl(emc->regs + EMC_CFG);
591 if (val & EMC_CFG_PWR_MASK) {
592 val &= ~EMC_CFG_POWER_FEATURES_MASK;
593 writel(val, emc->regs + EMC_CFG);
594
595 pre_wait = 5;
596 }
597
598 /* Disable SEL_DPD_CTRL for clock change */
599 if (emc->dram_type == DRAM_TYPE_DDR3)
600 mask = EMC_SEL_DPD_CTRL_DDR3_MASK;
601 else
602 mask = EMC_SEL_DPD_CTRL_MASK;
603
604 val = readl(emc->regs + EMC_SEL_DPD_CTRL);
605 if (val & mask) {
606 val &= ~mask;
607 writel(val, emc->regs + EMC_SEL_DPD_CTRL);
608 }
609
610 /* Prepare DQ/DQS for clock change */
611 val = readl(emc->regs + EMC_BGBIAS_CTL0);
612 val2 = last->emc_bgbias_ctl0;
613 if (!(timing->emc_bgbias_ctl0 &
614 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) &&
615 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX)) {
616 val2 &= ~EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX;
617 update = true;
618 }
619
620 if ((val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD) ||
621 (val & EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN)) {
622 update = true;
623 }
624
625 if (update) {
626 writel(val2, emc->regs + EMC_BGBIAS_CTL0);
627 if (pre_wait < 5)
628 pre_wait = 5;
629 }
630
631 update = false;
632 val = readl(emc->regs + EMC_XM2DQSPADCTRL2);
633 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_VREF_ENABLE &&
634 !(val & EMC_XM2DQSPADCTRL2_VREF_ENABLE)) {
635 val |= EMC_XM2DQSPADCTRL2_VREF_ENABLE;
636 update = true;
637 }
638
639 if (timing->emc_xm2dqspadctrl2 & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE &&
640 !(val & EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE)) {
641 val |= EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE;
642 update = true;
643 }
644
645 if (update) {
646 writel(val, emc->regs + EMC_XM2DQSPADCTRL2);
647 if (pre_wait < 30)
648 pre_wait = 30;
649 }
650
651 /* Wait to settle */
652 if (pre_wait) {
653 emc_seq_update_timing(emc);
654 udelay(pre_wait);
655 }
656
657 /* Program CTT_TERM control */
658 if (last->emc_ctt_term_ctrl != timing->emc_ctt_term_ctrl) {
659 emc_seq_disable_auto_cal(emc);
660 writel(timing->emc_ctt_term_ctrl,
661 emc->regs + EMC_CTT_TERM_CTRL);
662 emc_seq_update_timing(emc);
663 }
664
665 /* Program burst shadow registers */
666 for (i = 0; i < ARRAY_SIZE(timing->emc_burst_data); ++i)
667 writel(timing->emc_burst_data[i],
668 emc->regs + emc_burst_regs[i]);
669
670 writel(timing->emc_xm2dqspadctrl2, emc->regs + EMC_XM2DQSPADCTRL2);
671 writel(timing->emc_zcal_interval, emc->regs + EMC_ZCAL_INTERVAL);
672
673 tegra_mc_write_emem_configuration(emc->mc, timing->rate);
674
675 val = timing->emc_cfg & ~EMC_CFG_POWER_FEATURES_MASK;
676 emc_ccfifo_writel(emc, val, EMC_CFG);
677
678 /* Program AUTO_CAL_CONFIG */
679 if (timing->emc_auto_cal_config2 != last->emc_auto_cal_config2)
680 emc_ccfifo_writel(emc, timing->emc_auto_cal_config2,
681 EMC_AUTO_CAL_CONFIG2);
682
683 if (timing->emc_auto_cal_config3 != last->emc_auto_cal_config3)
684 emc_ccfifo_writel(emc, timing->emc_auto_cal_config3,
685 EMC_AUTO_CAL_CONFIG3);
686
687 if (timing->emc_auto_cal_config != last->emc_auto_cal_config) {
688 val = timing->emc_auto_cal_config;
689 val &= EMC_AUTO_CAL_CONFIG_AUTO_CAL_START;
690 emc_ccfifo_writel(emc, val, EMC_AUTO_CAL_CONFIG);
691 }
692
693 /* DDR3: predict MRS long wait count */
694 if (emc->dram_type == DRAM_TYPE_DDR3 &&
695 dll_change == DLL_CHANGE_ON) {
696 u32 cnt = 512;
697
698 if (timing->emc_zcal_interval != 0 &&
699 last->emc_zcal_interval == 0)
700 cnt -= emc->dram_num * 256;
701
702 val = (timing->emc_mrs_wait_cnt
703 & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK)
704 >> EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT;
705 if (cnt < val)
706 cnt = val;
707
708 val = timing->emc_mrs_wait_cnt
709 & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
710 val |= (cnt << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
711 & EMC_MRS_WAIT_CNT_LONG_WAIT_MASK;
712
713 writel(val, emc->regs + EMC_MRS_WAIT_CNT);
714 }
715
716 val = timing->emc_cfg_2;
717 val &= ~EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR;
718 emc_ccfifo_writel(emc, val, EMC_CFG_2);
719
720 /* DDR3: Turn off DLL and enter self-refresh */
721 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF)
722 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
723
724 /* Disable refresh controller */
725 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num),
726 EMC_REFCTRL);
727 if (emc->dram_type == DRAM_TYPE_DDR3)
728 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num) |
729 EMC_SELF_REF_CMD_ENABLED,
730 EMC_SELF_REF);
731
732 /* Flow control marker */
733 emc_ccfifo_writel(emc, 1, EMC_STALL_THEN_EXE_AFTER_CLKCHANGE);
734
735 /* DDR3: Exit self-refresh */
736 if (emc->dram_type == DRAM_TYPE_DDR3)
737 emc_ccfifo_writel(emc, EMC_DRAM_DEV_SEL(emc->dram_num),
738 EMC_SELF_REF);
739 emc_ccfifo_writel(emc, EMC_REFCTRL_DEV_SEL(emc->dram_num) |
740 EMC_REFCTRL_ENABLE,
741 EMC_REFCTRL);
742
743 /* Set DRAM mode registers */
744 if (emc->dram_type == DRAM_TYPE_DDR3) {
745 if (timing->emc_mode_1 != last->emc_mode_1)
746 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_EMRS);
747 if (timing->emc_mode_2 != last->emc_mode_2)
748 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_EMRS2);
749
750 if ((timing->emc_mode_reset != last->emc_mode_reset) ||
751 dll_change == DLL_CHANGE_ON) {
752 val = timing->emc_mode_reset;
753 if (dll_change == DLL_CHANGE_ON) {
754 val |= EMC_MODE_SET_DLL_RESET;
755 val |= EMC_MODE_SET_LONG_CNT;
756 } else {
757 val &= ~EMC_MODE_SET_DLL_RESET;
758 }
759 emc_ccfifo_writel(emc, val, EMC_MRS);
760 }
761 } else {
762 if (timing->emc_mode_2 != last->emc_mode_2)
763 emc_ccfifo_writel(emc, timing->emc_mode_2, EMC_MRW2);
764 if (timing->emc_mode_1 != last->emc_mode_1)
765 emc_ccfifo_writel(emc, timing->emc_mode_1, EMC_MRW);
766 if (timing->emc_mode_4 != last->emc_mode_4)
767 emc_ccfifo_writel(emc, timing->emc_mode_4, EMC_MRW4);
768 }
769
770 /* Issue ZCAL command if turning ZCAL on */
771 if (timing->emc_zcal_interval != 0 && last->emc_zcal_interval == 0) {
772 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV0, EMC_ZQ_CAL);
773 if (emc->dram_num > 1)
774 emc_ccfifo_writel(emc, EMC_ZQ_CAL_LONG_CMD_DEV1,
775 EMC_ZQ_CAL);
776 }
777
778 /* Write to RO register to remove stall after change */
779 emc_ccfifo_writel(emc, 0, EMC_CCFIFO_STATUS);
780
781 if (timing->emc_cfg_2 & EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR)
782 emc_ccfifo_writel(emc, timing->emc_cfg_2, EMC_CFG_2);
783
784 /* Disable AUTO_CAL for clock change */
785 emc_seq_disable_auto_cal(emc);
786
787 /* Read register to wait until programming has settled */
788 readl(emc->regs + EMC_INTSTATUS);
789
790 return 0;
791}
792
793void tegra_emc_complete_timing_change(struct tegra_emc *emc,
794 unsigned long rate)
795{
796 struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
797 struct emc_timing *last = &emc->last_timing;
798 u32 val;
799
800 if (!timing)
801 return;
802
803 /* Wait until the state machine has settled */
804 emc_seq_wait_clkchange(emc);
805
806 /* Restore AUTO_CAL */
807 if (timing->emc_ctt_term_ctrl != last->emc_ctt_term_ctrl)
808 writel(timing->emc_auto_cal_interval,
809 emc->regs + EMC_AUTO_CAL_INTERVAL);
810
811 /* Restore dynamic self-refresh */
812 if (timing->emc_cfg & EMC_CFG_PWR_MASK)
813 writel(timing->emc_cfg, emc->regs + EMC_CFG);
814
815 /* Set ZCAL wait count */
816 writel(timing->emc_zcal_cnt_long, emc->regs + EMC_ZCAL_WAIT_CNT);
817
818 /* LPDDR3: Turn off BGBIAS if low frequency */
819 if (emc->dram_type == DRAM_TYPE_LPDDR3 &&
820 timing->emc_bgbias_ctl0 &
821 EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX) {
822 val = timing->emc_bgbias_ctl0;
823 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN;
824 val |= EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD;
825 writel(val, emc->regs + EMC_BGBIAS_CTL0);
826 } else {
827 if (emc->dram_type == DRAM_TYPE_DDR3 &&
828 readl(emc->regs + EMC_BGBIAS_CTL0) !=
829 timing->emc_bgbias_ctl0) {
830 writel(timing->emc_bgbias_ctl0,
831 emc->regs + EMC_BGBIAS_CTL0);
832 }
833
834 writel(timing->emc_auto_cal_interval,
835 emc->regs + EMC_AUTO_CAL_INTERVAL);
836 }
837
838 /* Wait for timing to settle */
839 udelay(2);
840
841 /* Reprogram SEL_DPD_CTRL */
842 writel(timing->emc_sel_dpd_ctrl, emc->regs + EMC_SEL_DPD_CTRL);
843 emc_seq_update_timing(emc);
844
845 emc->last_timing = *timing;
846}
847
848/* Initialization and deinitialization */
849
850static void emc_read_current_timing(struct tegra_emc *emc,
851 struct emc_timing *timing)
852{
853 unsigned int i;
854
855 for (i = 0; i < ARRAY_SIZE(emc_burst_regs); ++i)
856 timing->emc_burst_data[i] =
857 readl(emc->regs + emc_burst_regs[i]);
858
859 timing->emc_cfg = readl(emc->regs + EMC_CFG);
860
861 timing->emc_auto_cal_interval = 0;
862 timing->emc_zcal_cnt_long = 0;
863 timing->emc_mode_1 = 0;
864 timing->emc_mode_2 = 0;
865 timing->emc_mode_4 = 0;
866 timing->emc_mode_reset = 0;
867}
868
869static int emc_init(struct tegra_emc *emc)
870{
871 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5);
872 emc->dram_type &= EMC_FBIO_CFG5_DRAM_TYPE_MASK;
873 emc->dram_type >>= EMC_FBIO_CFG5_DRAM_TYPE_SHIFT;
874
875 emc->dram_num = tegra_mc_get_emem_device_count(emc->mc);
876
877 emc_read_current_timing(emc, &emc->last_timing);
878
879 return 0;
880}
881
882static int load_one_timing_from_dt(struct tegra_emc *emc,
883 struct emc_timing *timing,
884 struct device_node *node)
885{
886 u32 value;
887 int err;
888
889 err = of_property_read_u32(node, "clock-frequency", &value);
890 if (err) {
891 dev_err(emc->dev, "timing %s: failed to read rate: %d\n",
892 node->name, err);
893 return err;
894 }
895
896 timing->rate = value;
897
898 err = of_property_read_u32_array(node, "nvidia,emc-configuration",
899 timing->emc_burst_data,
900 ARRAY_SIZE(timing->emc_burst_data));
901 if (err) {
902 dev_err(emc->dev,
903 "timing %s: failed to read emc burst data: %d\n",
904 node->name, err);
905 return err;
906 }
907
908#define EMC_READ_PROP(prop, dtprop) { \
909 err = of_property_read_u32(node, dtprop, &timing->prop); \
910 if (err) { \
911 dev_err(emc->dev, "timing %s: failed to read " #prop ": %d\n", \
912 node->name, err); \
913 return err; \
914 } \
915}
916
917 EMC_READ_PROP(emc_auto_cal_config, "nvidia,emc-auto-cal-config")
918 EMC_READ_PROP(emc_auto_cal_config2, "nvidia,emc-auto-cal-config2")
919 EMC_READ_PROP(emc_auto_cal_config3, "nvidia,emc-auto-cal-config3")
920 EMC_READ_PROP(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval")
921 EMC_READ_PROP(emc_bgbias_ctl0, "nvidia,emc-bgbias-ctl0")
922 EMC_READ_PROP(emc_cfg, "nvidia,emc-cfg")
923 EMC_READ_PROP(emc_cfg_2, "nvidia,emc-cfg-2")
924 EMC_READ_PROP(emc_ctt_term_ctrl, "nvidia,emc-ctt-term-ctrl")
925 EMC_READ_PROP(emc_mode_1, "nvidia,emc-mode-1")
926 EMC_READ_PROP(emc_mode_2, "nvidia,emc-mode-2")
927 EMC_READ_PROP(emc_mode_4, "nvidia,emc-mode-4")
928 EMC_READ_PROP(emc_mode_reset, "nvidia,emc-mode-reset")
929 EMC_READ_PROP(emc_mrs_wait_cnt, "nvidia,emc-mrs-wait-cnt")
930 EMC_READ_PROP(emc_sel_dpd_ctrl, "nvidia,emc-sel-dpd-ctrl")
931 EMC_READ_PROP(emc_xm2dqspadctrl2, "nvidia,emc-xm2dqspadctrl2")
932 EMC_READ_PROP(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long")
933 EMC_READ_PROP(emc_zcal_interval, "nvidia,emc-zcal-interval")
934
935#undef EMC_READ_PROP
936
937 return 0;
938}
939
940static int cmp_timings(const void *_a, const void *_b)
941{
942 const struct emc_timing *a = _a;
943 const struct emc_timing *b = _b;
944
945 if (a->rate < b->rate)
946 return -1;
947 else if (a->rate == b->rate)
948 return 0;
949 else
950 return 1;
951}
952
953static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
954 struct device_node *node)
955{
956 int child_count = of_get_child_count(node);
957 struct device_node *child;
958 struct emc_timing *timing;
959 unsigned int i = 0;
960 int err;
961
962 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
963 GFP_KERNEL);
964 if (!emc->timings)
965 return -ENOMEM;
966
967 emc->num_timings = child_count;
968
969 for_each_child_of_node(node, child) {
970 timing = &emc->timings[i++];
971
972 err = load_one_timing_from_dt(emc, timing, child);
973 if (err)
974 return err;
975 }
976
977 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
978 NULL);
979
980 return 0;
981}
982
983static const struct of_device_id tegra_emc_of_match[] = {
984 { .compatible = "nvidia,tegra124-emc" },
985 {}
986};
987
988static struct device_node *
989tegra_emc_find_node_by_ram_code(struct device_node *node, u32 ram_code)
990{
991 struct device_node *np;
992 int err;
993
994 for_each_child_of_node(node, np) {
995 u32 value;
996
997 err = of_property_read_u32(np, "nvidia,ram-code", &value);
998 if (err || (value != ram_code)) {
999 of_node_put(np);
1000 continue;
1001 }
1002
1003 return np;
1004 }
1005
1006 return NULL;
1007}
1008
1009/* Debugfs entry */
1010
1011static int emc_debug_rate_get(void *data, u64 *rate)
1012{
1013 struct clk *c = data;
1014
1015 *rate = clk_get_rate(c);
1016
1017 return 0;
1018}
1019
1020static int emc_debug_rate_set(void *data, u64 rate)
1021{
1022 struct clk *c = data;
1023
1024 return clk_set_rate(c, rate);
1025}
1026
1027DEFINE_SIMPLE_ATTRIBUTE(emc_debug_rate_fops, emc_debug_rate_get,
1028 emc_debug_rate_set, "%lld\n");
1029
1030static void emc_debugfs_init(struct device *dev)
1031{
1032 struct dentry *root, *file;
1033 struct clk *clk;
1034
1035 root = debugfs_create_dir("emc", NULL);
1036 if (!root) {
1037 dev_err(dev, "failed to create debugfs directory\n");
1038 return;
1039 }
1040
1041 clk = clk_get_sys("tegra-clk-debug", "emc");
1042 if (IS_ERR(clk)) {
1043 dev_err(dev, "failed to get debug clock: %ld\n", PTR_ERR(clk));
1044 return;
1045 }
1046
1047 file = debugfs_create_file("rate", S_IRUGO | S_IWUSR, root, clk,
1048 &emc_debug_rate_fops);
1049 if (!file)
1050 dev_err(dev, "failed to create debugfs entry\n");
1051}
1052
1053static int tegra_emc_probe(struct platform_device *pdev)
1054{
1055 struct platform_device *mc;
1056 struct device_node *np;
1057 struct tegra_emc *emc;
1058 struct resource *res;
1059 u32 ram_code;
1060 int err;
1061
1062 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1063 if (!emc)
1064 return -ENOMEM;
1065
1066 emc->dev = &pdev->dev;
1067
1068 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1069 emc->regs = devm_ioremap_resource(&pdev->dev, res);
1070 if (IS_ERR(emc->regs))
1071 return PTR_ERR(emc->regs);
1072
1073 np = of_parse_phandle(pdev->dev.of_node, "nvidia,memory-controller", 0);
1074 if (!np) {
1075 dev_err(&pdev->dev, "could not get memory controller\n");
1076 return -ENOENT;
1077 }
1078
1079 mc = of_find_device_by_node(np);
1080 if (!mc)
1081 return -ENOENT;
1082
1083 of_node_put(np);
1084
1085 emc->mc = platform_get_drvdata(mc);
1086 if (!emc->mc)
1087 return -EPROBE_DEFER;
1088
1089 ram_code = tegra_read_ram_code();
1090
1091 np = tegra_emc_find_node_by_ram_code(pdev->dev.of_node, ram_code);
1092 if (!np) {
1093 dev_err(&pdev->dev,
1094 "no memory timings for RAM code %u found in DT\n",
1095 ram_code);
1096 return -ENOENT;
1097 }
1098
1099 err = tegra_emc_load_timings_from_dt(emc, np);
1100
1101 of_node_put(np);
1102
1103 if (err)
1104 return err;
1105
1106 if (emc->num_timings == 0) {
1107 dev_err(&pdev->dev,
1108 "no memory timings for RAM code %u registered\n",
1109 ram_code);
1110 return -ENOENT;
1111 }
1112
1113 err = emc_init(emc);
1114 if (err) {
1115 dev_err(&pdev->dev, "EMC initialization failed: %d\n", err);
1116 return err;
1117 }
1118
1119 platform_set_drvdata(pdev, emc);
1120
1121 if (IS_ENABLED(CONFIG_DEBUG_FS))
1122 emc_debugfs_init(&pdev->dev);
1123
1124 return 0;
1125};
1126
1127static struct platform_driver tegra_emc_driver = {
1128 .probe = tegra_emc_probe,
1129 .driver = {
1130 .name = "tegra-emc",
1131 .of_match_table = tegra_emc_of_match,
1132 .suppress_bind_attrs = true,
1133 },
1134};
1135
1136static int tegra_emc_init(void)
1137{
1138 return platform_driver_register(&tegra_emc_driver);
1139}
1140subsys_initcall(tegra_emc_init);
diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c
index b996dfb9358b..966e1557e6f4 100644
--- a/drivers/memory/tegra/tegra124.c
+++ b/drivers/memory/tegra/tegra124.c
@@ -15,6 +15,48 @@
15 15
16#include "mc.h" 16#include "mc.h"
17 17
18#define MC_EMEM_ARB_CFG 0x90
19#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94
20#define MC_EMEM_ARB_TIMING_RCD 0x98
21#define MC_EMEM_ARB_TIMING_RP 0x9c
22#define MC_EMEM_ARB_TIMING_RC 0xa0
23#define MC_EMEM_ARB_TIMING_RAS 0xa4
24#define MC_EMEM_ARB_TIMING_FAW 0xa8
25#define MC_EMEM_ARB_TIMING_RRD 0xac
26#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0
27#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4
28#define MC_EMEM_ARB_TIMING_R2R 0xb8
29#define MC_EMEM_ARB_TIMING_W2W 0xbc
30#define MC_EMEM_ARB_TIMING_R2W 0xc0
31#define MC_EMEM_ARB_TIMING_W2R 0xc4
32#define MC_EMEM_ARB_DA_TURNS 0xd0
33#define MC_EMEM_ARB_DA_COVERS 0xd4
34#define MC_EMEM_ARB_MISC0 0xd8
35#define MC_EMEM_ARB_MISC1 0xdc
36#define MC_EMEM_ARB_RING1_THROTTLE 0xe0
37
38static const unsigned long tegra124_mc_emem_regs[] = {
39 MC_EMEM_ARB_CFG,
40 MC_EMEM_ARB_OUTSTANDING_REQ,
41 MC_EMEM_ARB_TIMING_RCD,
42 MC_EMEM_ARB_TIMING_RP,
43 MC_EMEM_ARB_TIMING_RC,
44 MC_EMEM_ARB_TIMING_RAS,
45 MC_EMEM_ARB_TIMING_FAW,
46 MC_EMEM_ARB_TIMING_RRD,
47 MC_EMEM_ARB_TIMING_RAP2PRE,
48 MC_EMEM_ARB_TIMING_WAP2PRE,
49 MC_EMEM_ARB_TIMING_R2R,
50 MC_EMEM_ARB_TIMING_W2W,
51 MC_EMEM_ARB_TIMING_R2W,
52 MC_EMEM_ARB_TIMING_W2R,
53 MC_EMEM_ARB_DA_TURNS,
54 MC_EMEM_ARB_DA_COVERS,
55 MC_EMEM_ARB_MISC0,
56 MC_EMEM_ARB_MISC1,
57 MC_EMEM_ARB_RING1_THROTTLE
58};
59
18static const struct tegra_mc_client tegra124_mc_clients[] = { 60static const struct tegra_mc_client tegra124_mc_clients[] = {
19 { 61 {
20 .id = 0x00, 62 .id = 0x00,
@@ -991,6 +1033,8 @@ const struct tegra_mc_soc tegra124_mc_soc = {
991 .num_address_bits = 34, 1033 .num_address_bits = 34,
992 .atom_size = 32, 1034 .atom_size = 32,
993 .smmu = &tegra124_smmu_soc, 1035 .smmu = &tegra124_smmu_soc,
1036 .emem_regs = tegra124_mc_emem_regs,
1037 .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
994}; 1038};
995#endif /* CONFIG_ARCH_TEGRA_124_SOC */ 1039#endif /* CONFIG_ARCH_TEGRA_124_SOC */
996 1040
diff --git a/include/soc/tegra/emc.h b/include/soc/tegra/emc.h
new file mode 100644
index 000000000000..f6db33b579ec
--- /dev/null
+++ b/include/soc/tegra/emc.h
@@ -0,0 +1,19 @@
1/*
2 * Copyright (c) 2014 NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __SOC_TEGRA_EMC_H__
10#define __SOC_TEGRA_EMC_H__
11
12struct tegra_emc;
13
14int tegra_emc_prepare_timing_change(struct tegra_emc *emc,
15 unsigned long rate);
16void tegra_emc_complete_timing_change(struct tegra_emc *emc,
17 unsigned long rate);
18
19#endif /* __SOC_TEGRA_EMC_H__ */
diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
index e5ba518aaece..1ab2813273cd 100644
--- a/include/soc/tegra/mc.h
+++ b/include/soc/tegra/mc.h
@@ -20,6 +20,12 @@ struct tegra_smmu_enable {
20 unsigned int bit; 20 unsigned int bit;
21}; 21};
22 22
23struct tegra_mc_timing {
24 unsigned long rate;
25
26 u32 *emem_data;
27};
28
23/* latency allowance */ 29/* latency allowance */
24struct tegra_mc_la { 30struct tegra_mc_la {
25 unsigned int reg; 31 unsigned int reg;
@@ -90,7 +96,7 @@ struct tegra_mc_soc {
90 const struct tegra_mc_client *clients; 96 const struct tegra_mc_client *clients;
91 unsigned int num_clients; 97 unsigned int num_clients;
92 98
93 const unsigned int *emem_regs; 99 const unsigned long *emem_regs;
94 unsigned int num_emem_regs; 100 unsigned int num_emem_regs;
95 101
96 unsigned int num_address_bits; 102 unsigned int num_address_bits;
@@ -108,6 +114,12 @@ struct tegra_mc {
108 114
109 const struct tegra_mc_soc *soc; 115 const struct tegra_mc_soc *soc;
110 unsigned long tick; 116 unsigned long tick;
117
118 struct tegra_mc_timing *timings;
119 unsigned int num_timings;
111}; 120};
112 121
122void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
123unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
124
113#endif /* __SOC_TEGRA_MC_H__ */ 125#endif /* __SOC_TEGRA_MC_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 11:17:42 -0400