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authorThomas Petazzoni <thomas.petazzoni@free-electrons.com>2015-03-03 09:41:08 -0500
committerGregory CLEMENT <gregory.clement@free-electrons.com>2015-03-04 09:18:48 -0500
commit42b5f40610fd222a9e7100f5b77582940bfdcbde (patch)
tree1d916b102c5bfb8cf40aa4bf96eb3eb19b31fc5d
parent9baf96886780c3ec137350da3c6418c825b2dd0a (diff)
clk: mvebu: extend common code to allow an optional refclk
The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
-rw-r--r--drivers/clk/mvebu/common.c17
-rw-r--r--drivers/clk/mvebu/common.h1
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 0d4d1216f2dd..15b370ff3748 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
121 121
122 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ 122 /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
123 clk_data.clk_num = 2 + desc->num_ratios; 123 clk_data.clk_num = 2 + desc->num_ratios;
124
125 /* One more clock for the optional refclk */
126 if (desc->get_refclk_freq)
127 clk_data.clk_num += 1;
128
124 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), 129 clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
125 GFP_KERNEL); 130 GFP_KERNEL);
126 if (WARN_ON(!clk_data.clks)) { 131 if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
162 WARN_ON(IS_ERR(clk_data.clks[2+n])); 167 WARN_ON(IS_ERR(clk_data.clks[2+n]));
163 }; 168 };
164 169
170 /* Register optional refclk */
171 if (desc->get_refclk_freq) {
172 const char *name = "refclk";
173 of_property_read_string_index(np, "clock-output-names",
174 2 + desc->num_ratios, &name);
175 rate = desc->get_refclk_freq(base);
176 clk_data.clks[2 + desc->num_ratios] =
177 clk_register_fixed_rate(NULL, name, NULL,
178 CLK_IS_ROOT, rate);
179 WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
180 }
181
165 /* SAR register isn't needed anymore */ 182 /* SAR register isn't needed anymore */
166 iounmap(base); 183 iounmap(base);
167 184
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index 783b5631a453..f0de6c8a494a 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -30,6 +30,7 @@ struct coreclk_soc_desc {
30 u32 (*get_tclk_freq)(void __iomem *sar); 30 u32 (*get_tclk_freq)(void __iomem *sar);
31 u32 (*get_cpu_freq)(void __iomem *sar); 31 u32 (*get_cpu_freq)(void __iomem *sar);
32 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); 32 void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
33 u32 (*get_refclk_freq)(void __iomem *sar);
33 bool (*is_sscg_enabled)(void __iomem *sar); 34 bool (*is_sscg_enabled)(void __iomem *sar);
34 u32 (*fix_sscg_deviation)(u32 system_clk); 35 u32 (*fix_sscg_deviation)(u32 system_clk);
35 const struct coreclk_ratio *ratios; 36 const struct coreclk_ratio *ratios;