diff options
| author | Alexandre Belloni <alexandre.belloni@free-electrons.com> | 2016-10-25 05:37:58 -0400 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-03-12 00:41:41 -0500 |
| commit | 37e70c4de51bf80123292f175dfce6b19af9c5d8 (patch) | |
| tree | e3d6479a43da38018a1e5158799bf7ca6d66845b | |
| parent | 404950add4ce0bfb95346a8233f5daba7fad8a54 (diff) | |
ARM: at91: define LPDDR types
commit e3f0a4017c2143b4b813df6a93e8cf79e3f76936 upstream.
The Atmel MPDDR controller support LPDDR2 and LPDDR3 memories, add their
types.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | include/soc/at91/at91sam9_ddrsdr.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/soc/at91/at91sam9_ddrsdr.h b/include/soc/at91/at91sam9_ddrsdr.h index dc10c52e0e91..393362bdb860 100644 --- a/include/soc/at91/at91sam9_ddrsdr.h +++ b/include/soc/at91/at91sam9_ddrsdr.h | |||
| @@ -81,6 +81,7 @@ | |||
| 81 | #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 | 81 | #define AT91_DDRSDRC_LPCB_POWER_DOWN 2 |
| 82 | #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 | 82 | #define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3 |
| 83 | #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ | 83 | #define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */ |
| 84 | #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */ | ||
| 84 | #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ | 85 | #define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */ |
| 85 | #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ | 86 | #define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */ |
| 86 | #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ | 87 | #define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */ |
| @@ -96,7 +97,9 @@ | |||
| 96 | #define AT91_DDRSDRC_MD_SDR 0 | 97 | #define AT91_DDRSDRC_MD_SDR 0 |
| 97 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 | 98 | #define AT91_DDRSDRC_MD_LOW_POWER_SDR 1 |
| 98 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 | 99 | #define AT91_DDRSDRC_MD_LOW_POWER_DDR 3 |
| 100 | #define AT91_DDRSDRC_MD_LPDDR3 5 | ||
| 99 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ | 101 | #define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */ |
| 102 | #define AT91_DDRSDRC_MD_LPDDR2 7 | ||
| 100 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ | 103 | #define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */ |
| 101 | #define AT91_DDRSDRC_DBW_32BITS (0 << 4) | 104 | #define AT91_DDRSDRC_DBW_32BITS (0 << 4) |
| 102 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) | 105 | #define AT91_DDRSDRC_DBW_16BITS (1 << 4) |