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authorPhilippe Reynes <tremyfr@gmail.com>2015-07-26 17:37:49 -0400
committerShawn Guo <shawnguo@kernel.org>2015-08-05 08:01:21 -0400
commit3713e3f5e9274bbe52e94716bde303071364c1ed (patch)
tree46c2e5ef75c4d152793ed8922088e67989681c0d
parent00a48fe341ed497be64df2c6875af0da45d6ae90 (diff)
clk: imx35: define two clocks for rtc
The imx35 don't define clocks for rtc. This patch add two clocks, as needed by the mxc rtc driver. Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
-rw-r--r--drivers/clk/imx/clk-imx35.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c
index 69138ba3dec7..8623cd4e49fd 100644
--- a/drivers/clk/imx/clk-imx35.c
+++ b/drivers/clk/imx/clk-imx35.c
@@ -66,7 +66,7 @@ static const char *std_sel[] = {"ppll", "arm"};
66static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"}; 66static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
67 67
68enum mx35_clks { 68enum mx35_clks {
69 ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg, 69 ckih, ckil, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
70 arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel, 70 arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
71 esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre, 71 esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
72 spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre, 72 spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
@@ -107,6 +107,7 @@ int __init mx35_clocks_init(void)
107 } 107 }
108 108
109 clk[ckih] = imx_clk_fixed("ckih", 24000000); 109 clk[ckih] = imx_clk_fixed("ckih", 24000000);
110 clk[ckil] = imx_clk_fixed("ckih", 32768);
110 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL); 111 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "mpll", "ckih", base + MX35_CCM_MPCTL);
111 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL); 112 clk[ppll] = imx_clk_pllv1(IMX_PLLV1_IMX35, "ppll", "ckih", base + MX35_CCM_PPCTL);
112 113
@@ -258,6 +259,9 @@ int __init mx35_clocks_init(void)
258 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1"); 259 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.1");
259 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2"); 260 clk_register_clkdev(clk[uart3_gate], "per", "imx21-uart.2");
260 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2"); 261 clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.2");
262 /* i.mx35 has the i.mx21 type rtc */
263 clk_register_clkdev(clk[ckil], "ref", "imx21-rtc");
264 clk_register_clkdev(clk[rtc_gate], "ipg", "imx21-rtc");
261 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0"); 265 clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.0");
262 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0"); 266 clk_register_clkdev(clk[ipg], "ipg", "mxc-ehci.0");
263 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0"); 267 clk_register_clkdev(clk[usbotg_gate], "ahb", "mxc-ehci.0");