aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJammy Zhou <Jammy.Zhou@amd.com>2015-07-21 23:29:01 -0400
committerAlex Deucher <alexander.deucher@amd.com>2015-08-17 16:50:21 -0400
commit2f7d10b393c83acd3eedc3d6ab94dce29ac6a890 (patch)
treedc13e4604dc31f280f0593123e29450460969fa5
parentfa9f1d4e86f67a4df03e153d9b9cd1bd1838767c (diff)
drm/amdgpu: merge amdgpu_family.h into amd_shared.h (v2)
Make the definitions common for all driver components v2: fix kfd Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c128
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_family.h62
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_object.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_encoders.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c4
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c10
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h27
23 files changed, 138 insertions, 174 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index e6c26c1716b6..a9ead9731b35 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -47,7 +47,6 @@
47#include <drm/amdgpu_drm.h> 47#include <drm/amdgpu_drm.h>
48 48
49#include "amd_shared.h" 49#include "amd_shared.h"
50#include "amdgpu_family.h"
51#include "amdgpu_mode.h" 50#include "amdgpu_mode.h"
52#include "amdgpu_ih.h" 51#include "amdgpu_ih.h"
53#include "amdgpu_irq.h" 52#include "amdgpu_irq.h"
@@ -1900,7 +1899,7 @@ struct amdgpu_device {
1900 struct rw_semaphore exclusive_lock; 1899 struct rw_semaphore exclusive_lock;
1901 1900
1902 /* ASIC */ 1901 /* ASIC */
1903 enum amdgpu_asic_type asic_type; 1902 enum amd_asic_type asic_type;
1904 uint32_t family; 1903 uint32_t family;
1905 uint32_t rev_id; 1904 uint32_t rev_id;
1906 uint32_t external_rev_id; 1905 uint32_t external_rev_id;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index bc763e0c8f4c..4c7c09cead45 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -21,7 +21,7 @@
21 */ 21 */
22 22
23#include "amdgpu_amdkfd.h" 23#include "amdgpu_amdkfd.h"
24#include "amdgpu_family.h" 24#include "amd_shared.h"
25#include <drm/drmP.h> 25#include <drm/drmP.h>
26#include "amdgpu.h" 26#include "amdgpu.h"
27#include <linux/module.h> 27#include <linux/module.h>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
index 6a588371d54a..77f1d7c6ea3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c
@@ -897,7 +897,7 @@ bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev,
897 if ((id == ASIC_INTERNAL_ENGINE_SS) || 897 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
898 (id == ASIC_INTERNAL_MEMORY_SS)) 898 (id == ASIC_INTERNAL_MEMORY_SS))
899 ss->rate /= 100; 899 ss->rate /= 100;
900 if (adev->flags & AMDGPU_IS_APU) 900 if (adev->flags & AMD_IS_APU)
901 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); 901 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id);
902 return true; 902 return true;
903 } 903 }
@@ -1058,7 +1058,7 @@ void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev,
1058 SET_MEMORY_CLOCK_PS_ALLOCATION args; 1058 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1059 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 1059 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1060 1060
1061 if (adev->flags & AMDGPU_IS_APU) 1061 if (adev->flags & AMD_IS_APU)
1062 return; 1062 return;
1063 1063
1064 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 1064 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
index ceb444f6d418..02add0a508cb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
@@ -48,7 +48,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
48 resource_size_t vram_base; 48 resource_size_t vram_base;
49 resource_size_t size = 256 * 1024; /* ??? */ 49 resource_size_t size = 256 * 1024; /* ??? */
50 50
51 if (!(adev->flags & AMDGPU_IS_APU)) 51 if (!(adev->flags & AMD_IS_APU))
52 if (!amdgpu_card_posted(adev)) 52 if (!amdgpu_card_posted(adev))
53 return false; 53 return false;
54 54
@@ -184,7 +184,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
184 bool found = false; 184 bool found = false;
185 185
186 /* ATRM is for the discrete card only */ 186 /* ATRM is for the discrete card only */
187 if (adev->flags & AMDGPU_IS_APU) 187 if (adev->flags & AMD_IS_APU)
188 return false; 188 return false;
189 189
190 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 190 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
@@ -246,7 +246,7 @@ static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
246 246
247static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev) 247static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev)
248{ 248{
249 if (adev->flags & AMDGPU_IS_APU) 249 if (adev->flags & AMD_IS_APU)
250 return igp_read_bios_from_vram(adev); 250 return igp_read_bios_from_vram(adev);
251 else 251 else
252 return amdgpu_asic_read_disabled_bios(adev); 252 return amdgpu_asic_read_disabled_bios(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index a816580fb474..f7a67a142edc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -63,7 +63,7 @@ bool amdgpu_device_is_px(struct drm_device *dev)
63{ 63{
64 struct amdgpu_device *adev = dev->dev_private; 64 struct amdgpu_device *adev = dev->dev_private;
65 65
66 if (adev->flags & AMDGPU_IS_PX) 66 if (adev->flags & AMD_IS_PX)
67 return true; 67 return true;
68 return false; 68 return false;
69} 69}
@@ -1377,7 +1377,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
1377 adev->ddev = ddev; 1377 adev->ddev = ddev;
1378 adev->pdev = pdev; 1378 adev->pdev = pdev;
1379 adev->flags = flags; 1379 adev->flags = flags;
1380 adev->asic_type = flags & AMDGPU_ASIC_MASK; 1380 adev->asic_type = flags & AMD_ASIC_MASK;
1381 adev->is_atom_bios = false; 1381 adev->is_atom_bios = false;
1382 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT; 1382 adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
1383 adev->mc.gtt_size = 512 * 1024 * 1024; 1383 adev->mc.gtt_size = 512 * 1024 * 1024;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 115906f5fda0..c3f9b4968b81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -142,33 +142,33 @@ module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
142static struct pci_device_id pciidlist[] = { 142static struct pci_device_id pciidlist[] = {
143#ifdef CONFIG_DRM_AMDGPU_CIK 143#ifdef CONFIG_DRM_AMDGPU_CIK
144 /* Kaveri */ 144 /* Kaveri */
145 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 145 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
146 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 146 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
147 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 147 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
148 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 148 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
149 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 149 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
150 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 150 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
151 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 151 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
152 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 152 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
153 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 153 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
154 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 154 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
155 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 155 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
156 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 156 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
157 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 157 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
158 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 158 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
159 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 159 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
160 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 160 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
161 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 161 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
162 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 162 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
163 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 163 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
164 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 164 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
165 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 165 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
166 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMDGPU_IS_APU}, 166 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
167 /* Bonaire */ 167 /* Bonaire */
168 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 168 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
169 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 169 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
170 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 170 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
171 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMDGPU_IS_MOBILITY}, 171 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
172 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 172 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
173 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 173 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
174 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 174 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
@@ -190,39 +190,39 @@ static struct pci_device_id pciidlist[] = {
190 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 190 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
191 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 191 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
192 /* Kabini */ 192 /* Kabini */
193 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 193 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
194 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 194 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
195 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 195 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
196 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 196 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
197 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 197 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
198 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 198 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
199 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 199 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
200 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 200 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
201 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 201 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
202 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 202 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
203 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 203 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
204 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 204 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
205 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 205 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
206 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 206 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
207 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 207 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
208 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMDGPU_IS_APU}, 208 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
209 /* mullins */ 209 /* mullins */
210 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 210 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
211 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 211 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
212 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 212 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
213 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 213 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
214 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 214 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
215 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 215 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
216 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 216 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
217 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 217 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
218 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 218 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
219 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 219 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
220 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 220 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
221 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 221 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
222 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 222 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
223 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 223 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
224 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 224 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
225 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMDGPU_IS_MOBILITY|AMDGPU_IS_APU}, 225 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
226#endif 226#endif
227 /* topaz */ 227 /* topaz */
228 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 228 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
@@ -241,11 +241,11 @@ static struct pci_device_id pciidlist[] = {
241 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 241 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
242 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 242 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
243 /* carrizo */ 243 /* carrizo */
244 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 244 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
245 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 245 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
246 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 246 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
247 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 247 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
248 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMDGPU_IS_APU}, 248 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
249 249
250 {0, 0, 0} 250 {0, 0, 0}
251}; 251};
@@ -281,7 +281,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev,
281 unsigned long flags = ent->driver_data; 281 unsigned long flags = ent->driver_data;
282 int ret; 282 int ret;
283 283
284 if ((flags & AMDGPU_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 284 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
285 DRM_INFO("This hardware requires experimental hardware support.\n" 285 DRM_INFO("This hardware requires experimental hardware support.\n"
286 "See modparam exp_hw_support\n"); 286 "See modparam exp_hw_support\n");
287 return -ENODEV; 287 return -ENODEV;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h
index cceeb33c447a..e3a4f7048042 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.h
@@ -31,7 +31,7 @@
31#include <linux/firmware.h> 31#include <linux/firmware.h>
32#include <linux/platform_device.h> 32#include <linux/platform_device.h>
33 33
34#include "amdgpu_family.h" 34#include "amd_shared.h"
35 35
36/* General customization: 36/* General customization:
37 */ 37 */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h
deleted file mode 100644
index 0698764354a2..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_family.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29/* this file defines the CHIP_ and family flags used in the pciids,
30 * its is common between kms and non-kms because duplicating it and
31 * changing one place is fail.
32 */
33#ifndef AMDGPU_FAMILY_H
34#define AMDGPU_FAMILY_H
35/*
36 * Supported ASIC types
37 */
38enum amdgpu_asic_type {
39 CHIP_BONAIRE = 0,
40 CHIP_KAVERI,
41 CHIP_KABINI,
42 CHIP_HAWAII,
43 CHIP_MULLINS,
44 CHIP_TOPAZ,
45 CHIP_TONGA,
46 CHIP_CARRIZO,
47 CHIP_LAST,
48};
49
50/*
51 * Chip flags
52 */
53enum amdgpu_chip_flags {
54 AMDGPU_ASIC_MASK = 0x0000ffffUL,
55 AMDGPU_FLAGS_MASK = 0xffff0000UL,
56 AMDGPU_IS_MOBILITY = 0x00010000UL,
57 AMDGPU_IS_APU = 0x00020000UL,
58 AMDGPU_IS_PX = 0x00040000UL,
59 AMDGPU_EXP_HW_SUPPORT = 0x00080000UL,
60};
61
62#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 93000af92283..53da3d8a868c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -96,8 +96,8 @@ int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
96 96
97 if ((amdgpu_runtime_pm != 0) && 97 if ((amdgpu_runtime_pm != 0) &&
98 amdgpu_has_atpx() && 98 amdgpu_has_atpx() &&
99 ((flags & AMDGPU_IS_APU) == 0)) 99 ((flags & AMD_IS_APU) == 0))
100 flags |= AMDGPU_IS_PX; 100 flags |= AMD_IS_PX;
101 101
102 /* amdgpu_device_init should report only fatal error 102 /* amdgpu_device_init should report only fatal error
103 * like memory allocation failure or iomapping failure, 103 * like memory allocation failure or iomapping failure,
@@ -451,7 +451,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
451 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 451 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
452 dev_info._pad = 0; 452 dev_info._pad = 0;
453 dev_info.ids_flags = 0; 453 dev_info.ids_flags = 0;
454 if (adev->flags & AMDGPU_IS_APU) 454 if (adev->flags & AMD_IS_APU)
455 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 455 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
456 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 456 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
457 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 457 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 8da64245b31b..88ca79fc55bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -462,7 +462,7 @@ int amdgpu_bo_unpin(struct amdgpu_bo *bo)
462int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 462int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
463{ 463{
464 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 464 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
465 if (0 && (adev->flags & AMDGPU_IS_APU)) { 465 if (0 && (adev->flags & AMD_IS_APU)) {
466 /* Useless to evict on IGP chips */ 466 /* Useless to evict on IGP chips */
467 return 0; 467 return 0;
468 } 468 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index ed13baa7c976..25b329f4b2d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -82,7 +82,7 @@ static ssize_t amdgpu_set_dpm_state(struct device *dev,
82 mutex_unlock(&adev->pm.mutex); 82 mutex_unlock(&adev->pm.mutex);
83 83
84 /* Can't set dpm state when the card is off */ 84 /* Can't set dpm state when the card is off */
85 if (!(adev->flags & AMDGPU_IS_PX) || 85 if (!(adev->flags & AMD_IS_PX) ||
86 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 86 (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
87 amdgpu_pm_compute_clocks(adev); 87 amdgpu_pm_compute_clocks(adev);
88fail: 88fail:
@@ -538,7 +538,7 @@ static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
538 /* vce just modifies an existing state so force a change */ 538 /* vce just modifies an existing state so force a change */
539 if (ps->vce_active != adev->pm.dpm.vce_active) 539 if (ps->vce_active != adev->pm.dpm.vce_active)
540 goto force; 540 goto force;
541 if (adev->flags & AMDGPU_IS_APU) { 541 if (adev->flags & AMD_IS_APU) {
542 /* for APUs if the num crtcs changed but state is the same, 542 /* for APUs if the num crtcs changed but state is the same,
543 * all we need to do is update the display configuration. 543 * all we need to do is update the display configuration.
544 */ 544 */
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
index ae8caca61e04..cd6edc40c9cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c
@@ -812,7 +812,7 @@ amdgpu_atombios_encoder_setup_dig_transmitter(struct drm_encoder *encoder, int a
812 else 812 else
813 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 813 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
814 814
815 if ((adev->flags & AMDGPU_IS_APU) && 815 if ((adev->flags & AMD_IS_APU) &&
816 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { 816 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
817 if (is_dp || 817 if (is_dp ||
818 !amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) { 818 !amdgpu_dig_monitor_is_duallink(encoder, amdgpu_encoder->pixel_clock)) {
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index b3b66a0d5ff7..4b6ce74753cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -838,7 +838,7 @@ static u32 cik_get_xclk(struct amdgpu_device *adev)
838{ 838{
839 u32 reference_clock = adev->clock.spll.reference_freq; 839 u32 reference_clock = adev->clock.spll.reference_freq;
840 840
841 if (adev->flags & AMDGPU_IS_APU) { 841 if (adev->flags & AMD_IS_APU) {
842 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) 842 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK)
843 return reference_clock / 2; 843 return reference_clock / 2;
844 } else { 844 } else {
@@ -1235,7 +1235,7 @@ static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
1235 if (reset_mask & AMDGPU_RESET_VMC) 1235 if (reset_mask & AMDGPU_RESET_VMC)
1236 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; 1236 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK;
1237 1237
1238 if (!(adev->flags & AMDGPU_IS_APU)) { 1238 if (!(adev->flags & AMD_IS_APU)) {
1239 if (reset_mask & AMDGPU_RESET_MC) 1239 if (reset_mask & AMDGPU_RESET_MC)
1240 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; 1240 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK;
1241 } 1241 }
@@ -1411,7 +1411,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
1411 dev_warn(adev->dev, "Wait for MC idle timed out !\n"); 1411 dev_warn(adev->dev, "Wait for MC idle timed out !\n");
1412 } 1412 }
1413 1413
1414 if (adev->flags & AMDGPU_IS_APU) 1414 if (adev->flags & AMD_IS_APU)
1415 kv_save_regs_for_reset(adev, &kv_save); 1415 kv_save_regs_for_reset(adev, &kv_save);
1416 1416
1417 /* disable BM */ 1417 /* disable BM */
@@ -1429,7 +1429,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
1429 } 1429 }
1430 1430
1431 /* does asic init need to be run first??? */ 1431 /* does asic init need to be run first??? */
1432 if (adev->flags & AMDGPU_IS_APU) 1432 if (adev->flags & AMD_IS_APU)
1433 kv_restore_regs_for_reset(adev, &kv_save); 1433 kv_restore_regs_for_reset(adev, &kv_save);
1434} 1434}
1435 1435
@@ -1570,7 +1570,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
1570 if (amdgpu_pcie_gen2 == 0) 1570 if (amdgpu_pcie_gen2 == 0)
1571 return; 1571 return;
1572 1572
1573 if (adev->flags & AMDGPU_IS_APU) 1573 if (adev->flags & AMD_IS_APU)
1574 return; 1574 return;
1575 1575
1576 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1576 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
@@ -1730,7 +1730,7 @@ static void cik_program_aspm(struct amdgpu_device *adev)
1730 return; 1730 return;
1731 1731
1732 /* XXX double check APUs */ 1732 /* XXX double check APUs */
1733 if (adev->flags & AMDGPU_IS_APU) 1733 if (adev->flags & AMD_IS_APU)
1734 return; 1734 return;
1735 1735
1736 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1736 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index e70a26f587a0..a72254a5120e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -803,11 +803,11 @@ static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
803 buffer_alloc = 2; 803 buffer_alloc = 2;
804 } else if (mode->crtc_hdisplay < 4096) { 804 } else if (mode->crtc_hdisplay < 4096) {
805 mem_cfg = 0; 805 mem_cfg = 0;
806 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 806 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
807 } else { 807 } else {
808 DRM_DEBUG_KMS("Mode too big for LB!\n"); 808 DRM_DEBUG_KMS("Mode too big for LB!\n");
809 mem_cfg = 0; 809 mem_cfg = 0;
810 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 810 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
811 } 811 }
812 } else { 812 } else {
813 mem_cfg = 1; 813 mem_cfg = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index dcb402ee048a..70eee807421f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -801,11 +801,11 @@ static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
801 buffer_alloc = 2; 801 buffer_alloc = 2;
802 } else if (mode->crtc_hdisplay < 4096) { 802 } else if (mode->crtc_hdisplay < 4096) {
803 mem_cfg = 0; 803 mem_cfg = 0;
804 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 804 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
805 } else { 805 } else {
806 DRM_DEBUG_KMS("Mode too big for LB!\n"); 806 DRM_DEBUG_KMS("Mode too big for LB!\n");
807 mem_cfg = 0; 807 mem_cfg = 0;
808 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 808 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
809 } 809 }
810 } else { 810 } else {
811 mem_cfg = 1; 811 mem_cfg = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index cc050a329c49..c86911c2ea2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -770,11 +770,11 @@ static u32 dce_v8_0_line_buffer_adjust(struct amdgpu_device *adev,
770 buffer_alloc = 2; 770 buffer_alloc = 2;
771 } else if (mode->crtc_hdisplay < 4096) { 771 } else if (mode->crtc_hdisplay < 4096) {
772 tmp = 0; 772 tmp = 0;
773 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 773 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
774 } else { 774 } else {
775 DRM_DEBUG_KMS("Mode too big for LB!\n"); 775 DRM_DEBUG_KMS("Mode too big for LB!\n");
776 tmp = 0; 776 tmp = 0;
777 buffer_alloc = (adev->flags & AMDGPU_IS_APU) ? 2 : 4; 777 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
778 } 778 }
779 } else { 779 } else {
780 tmp = 1; 780 tmp = 1;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 0d8bf2cb1956..54a2bf8d4e8d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2173,7 +2173,7 @@ static void gfx_v7_0_gpu_init(struct amdgpu_device *adev)
2173 2173
2174 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 2174 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2175 adev->gfx.config.mem_max_burst_length_bytes = 256; 2175 adev->gfx.config.mem_max_burst_length_bytes = 256;
2176 if (adev->flags & AMDGPU_IS_APU) { 2176 if (adev->flags & AMD_IS_APU) {
2177 /* Get memory bank mapping mode. */ 2177 /* Get memory bank mapping mode. */
2178 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 2178 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2179 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 2179 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
@@ -3758,7 +3758,7 @@ static int gfx_v7_0_rlc_init(struct amdgpu_device *adev)
3758 int r; 3758 int r;
3759 3759
3760 /* allocate rlc buffers */ 3760 /* allocate rlc buffers */
3761 if (adev->flags & AMDGPU_IS_APU) { 3761 if (adev->flags & AMD_IS_APU) {
3762 if (adev->asic_type == CHIP_KAVERI) { 3762 if (adev->asic_type == CHIP_KAVERI) {
3763 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list; 3763 adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;
3764 adev->gfx.rlc.reg_list_size = 3764 adev->gfx.rlc.reg_list_size =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 20e2cfd521d5..17df5c265552 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -2078,7 +2078,7 @@ static void gfx_v8_0_gpu_init(struct amdgpu_device *adev)
2078 2078
2079 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; 2079 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
2080 adev->gfx.config.mem_max_burst_length_bytes = 256; 2080 adev->gfx.config.mem_max_burst_length_bytes = 256;
2081 if (adev->flags & AMDGPU_IS_APU) { 2081 if (adev->flags & AMD_IS_APU) {
2082 /* Get memory bank mapping mode. */ 2082 /* Get memory bank mapping mode. */
2083 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING); 2083 tmp = RREG32(mmMC_FUS_DRAM0_BANK_ADDR_MAPPING);
2084 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP); 2084 dimm00_addr_map = REG_GET_FIELD(tmp, MC_FUS_DRAM0_BANK_ADDR_MAPPING, DIMM0ADDRMAP);
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index ae37fce36520..10218828face 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -636,7 +636,7 @@ static int gmc_v7_0_vm_init(struct amdgpu_device *adev)
636 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; 636 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
637 637
638 /* base offset of vram pages */ 638 /* base offset of vram pages */
639 if (adev->flags & AMDGPU_IS_APU) { 639 if (adev->flags & AMD_IS_APU) {
640 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 640 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
641 tmp <<= 22; 641 tmp <<= 22;
642 adev->vm_manager.vram_base_offset = tmp; 642 adev->vm_manager.vram_base_offset = tmp;
@@ -841,7 +841,7 @@ static int gmc_v7_0_early_init(void *handle)
841 gmc_v7_0_set_gart_funcs(adev); 841 gmc_v7_0_set_gart_funcs(adev);
842 gmc_v7_0_set_irq_funcs(adev); 842 gmc_v7_0_set_irq_funcs(adev);
843 843
844 if (adev->flags & AMDGPU_IS_APU) { 844 if (adev->flags & AMD_IS_APU) {
845 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 845 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
846 } else { 846 } else {
847 u32 tmp = RREG32(mmMC_SEQ_MISC0); 847 u32 tmp = RREG32(mmMC_SEQ_MISC0);
@@ -957,7 +957,7 @@ static int gmc_v7_0_hw_init(void *handle)
957 957
958 gmc_v7_0_mc_program(adev); 958 gmc_v7_0_mc_program(adev);
959 959
960 if (!(adev->flags & AMDGPU_IS_APU)) { 960 if (!(adev->flags & AMD_IS_APU)) {
961 r = gmc_v7_0_mc_load_microcode(adev); 961 r = gmc_v7_0_mc_load_microcode(adev);
962 if (r) { 962 if (r) {
963 DRM_ERROR("Failed to load MC firmware!\n"); 963 DRM_ERROR("Failed to load MC firmware!\n");
@@ -1172,7 +1172,7 @@ static int gmc_v7_0_soft_reset(void *handle)
1172 1172
1173 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1173 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1174 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1174 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1175 if (!(adev->flags & AMDGPU_IS_APU)) 1175 if (!(adev->flags & AMD_IS_APU))
1176 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1176 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1177 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1177 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1178 } 1178 }
@@ -1282,7 +1282,7 @@ static int gmc_v7_0_set_clockgating_state(void *handle,
1282 if (state == AMD_CG_STATE_GATE) 1282 if (state == AMD_CG_STATE_GATE)
1283 gate = true; 1283 gate = true;
1284 1284
1285 if (!(adev->flags & AMDGPU_IS_APU)) { 1285 if (!(adev->flags & AMD_IS_APU)) {
1286 gmc_v7_0_enable_mc_mgcg(adev, gate); 1286 gmc_v7_0_enable_mc_mgcg(adev, gate);
1287 gmc_v7_0_enable_mc_ls(adev, gate); 1287 gmc_v7_0_enable_mc_ls(adev, gate);
1288 } 1288 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 8135963a66be..3b54ed84bde6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -737,7 +737,7 @@ static int gmc_v8_0_vm_init(struct amdgpu_device *adev)
737 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS; 737 adev->vm_manager.nvm = AMDGPU_NUM_OF_VMIDS;
738 738
739 /* base offset of vram pages */ 739 /* base offset of vram pages */
740 if (adev->flags & AMDGPU_IS_APU) { 740 if (adev->flags & AMD_IS_APU) {
741 u64 tmp = RREG32(mmMC_VM_FB_OFFSET); 741 u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
742 tmp <<= 22; 742 tmp <<= 22;
743 adev->vm_manager.vram_base_offset = tmp; 743 adev->vm_manager.vram_base_offset = tmp;
@@ -816,7 +816,7 @@ static int gmc_v8_0_early_init(void *handle)
816 gmc_v8_0_set_gart_funcs(adev); 816 gmc_v8_0_set_gart_funcs(adev);
817 gmc_v8_0_set_irq_funcs(adev); 817 gmc_v8_0_set_irq_funcs(adev);
818 818
819 if (adev->flags & AMDGPU_IS_APU) { 819 if (adev->flags & AMD_IS_APU) {
820 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; 820 adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
821 } else { 821 } else {
822 u32 tmp = RREG32(mmMC_SEQ_MISC0); 822 u32 tmp = RREG32(mmMC_SEQ_MISC0);
@@ -934,7 +934,7 @@ static int gmc_v8_0_hw_init(void *handle)
934 934
935 gmc_v8_0_mc_program(adev); 935 gmc_v8_0_mc_program(adev);
936 936
937 if (!(adev->flags & AMDGPU_IS_APU)) { 937 if (!(adev->flags & AMD_IS_APU)) {
938 r = gmc_v8_0_mc_load_microcode(adev); 938 r = gmc_v8_0_mc_load_microcode(adev);
939 if (r) { 939 if (r) {
940 DRM_ERROR("Failed to load MC firmware!\n"); 940 DRM_ERROR("Failed to load MC firmware!\n");
@@ -1147,7 +1147,7 @@ static int gmc_v8_0_soft_reset(void *handle)
1147 1147
1148 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1148 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK |
1149 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) { 1149 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) {
1150 if (!(adev->flags & AMDGPU_IS_APU)) 1150 if (!(adev->flags & AMD_IS_APU))
1151 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, 1151 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1152 SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 1152 SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
1153 } 1153 }
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index d1064ca3670e..5a5a40c331cf 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -205,7 +205,7 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev)
205 u32 tmp; 205 u32 tmp;
206 unsigned ret; 206 unsigned ret;
207 207
208 if (adev->flags & AMDGPU_IS_APU) 208 if (adev->flags & AMD_IS_APU)
209 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) & 209 tmp = (RREG32_SMC(ixVCE_HARVEST_FUSE_MACRO__ADDRESS) &
210 VCE_HARVEST_FUSE_MACRO__MASK) >> 210 VCE_HARVEST_FUSE_MACRO__MASK) >>
211 VCE_HARVEST_FUSE_MACRO__SHIFT; 211 VCE_HARVEST_FUSE_MACRO__SHIFT;
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0f4a4f438f5e..2095f57c27e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -261,7 +261,7 @@ static u32 vi_get_xclk(struct amdgpu_device *adev)
261 u32 reference_clock = adev->clock.spll.reference_freq; 261 u32 reference_clock = adev->clock.spll.reference_freq;
262 u32 tmp; 262 u32 tmp;
263 263
264 if (adev->flags & AMDGPU_IS_APU) 264 if (adev->flags & AMD_IS_APU)
265 return reference_clock; 265 return reference_clock;
266 266
267 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 267 tmp = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
@@ -771,7 +771,7 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
771 srbm_soft_reset = 771 srbm_soft_reset =
772 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1); 772 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_VCE1, 1);
773 773
774 if (!(adev->flags & AMDGPU_IS_APU)) { 774 if (!(adev->flags & AMD_IS_APU)) {
775 if (reset_mask & AMDGPU_RESET_MC) 775 if (reset_mask & AMDGPU_RESET_MC)
776 srbm_soft_reset = 776 srbm_soft_reset =
777 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1); 777 REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
@@ -991,7 +991,7 @@ static void vi_pcie_gen3_enable(struct amdgpu_device *adev)
991 if (amdgpu_pcie_gen2 == 0) 991 if (amdgpu_pcie_gen2 == 0)
992 return; 992 return;
993 993
994 if (adev->flags & AMDGPU_IS_APU) 994 if (adev->flags & AMD_IS_APU)
995 return; 995 return;
996 996
997 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 997 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
@@ -1019,7 +1019,7 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1019 u32 tmp; 1019 u32 tmp;
1020 1020
1021 /* not necessary on CZ */ 1021 /* not necessary on CZ */
1022 if (adev->flags & AMDGPU_IS_APU) 1022 if (adev->flags & AMD_IS_APU)
1023 return; 1023 return;
1024 1024
1025 tmp = RREG32(mmBIF_DOORBELL_APER_EN); 1025 tmp = RREG32(mmBIF_DOORBELL_APER_EN);
@@ -1268,7 +1268,7 @@ static int vi_common_early_init(void *handle)
1268 bool smc_enabled = false; 1268 bool smc_enabled = false;
1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1270 1270
1271 if (adev->flags & AMDGPU_IS_APU) { 1271 if (adev->flags & AMD_IS_APU) {
1272 adev->smc_rreg = &cz_smc_rreg; 1272 adev->smc_rreg = &cz_smc_rreg;
1273 adev->smc_wreg = &cz_smc_wreg; 1273 adev->smc_wreg = &cz_smc_wreg;
1274 } else { 1274 } else {
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 369848159803..3b8d2fc04149 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -34,6 +34,33 @@
34#define AMD_FAMILY_VI 130 /* Iceland, Tonga */ 34#define AMD_FAMILY_VI 130 /* Iceland, Tonga */
35#define AMD_FAMILY_CZ 135 /* Carrizo */ 35#define AMD_FAMILY_CZ 135 /* Carrizo */
36 36
37/*
38 * Supported ASIC types
39 */
40enum amd_asic_type {
41 CHIP_BONAIRE = 0,
42 CHIP_KAVERI,
43 CHIP_KABINI,
44 CHIP_HAWAII,
45 CHIP_MULLINS,
46 CHIP_TOPAZ,
47 CHIP_TONGA,
48 CHIP_CARRIZO,
49 CHIP_LAST,
50};
51
52/*
53 * Chip flags
54 */
55enum amd_chip_flags {
56 AMD_ASIC_MASK = 0x0000ffffUL,
57 AMD_FLAGS_MASK = 0xffff0000UL,
58 AMD_IS_MOBILITY = 0x00010000UL,
59 AMD_IS_APU = 0x00020000UL,
60 AMD_IS_PX = 0x00040000UL,
61 AMD_EXP_HW_SUPPORT = 0x00080000UL,
62};
63
37enum amd_ip_block_type { 64enum amd_ip_block_type {
38 AMD_IP_BLOCK_TYPE_COMMON, 65 AMD_IP_BLOCK_TYPE_COMMON,
39 AMD_IP_BLOCK_TYPE_GMC, 66 AMD_IP_BLOCK_TYPE_GMC,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 12:52:13 -0400