diff options
author | Chunming Zhou <David1.Zhou@amd.com> | 2016-01-14 22:05:21 -0500 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2016-02-10 14:16:49 -0500 |
commit | 2f4b9400336effee61cbf7f55b7dc35a39096ae1 (patch) | |
tree | 11ae55e1f51747ebb2d59d51afb9afb0f34925fa | |
parent | a8480309df2aa8b39e8f67b5202db8cebaff4b72 (diff) |
drm/amdgpu: clean up hw semaphore support in driver
No longer used.
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu.h | 21 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c | 102 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 64 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | 237 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 36 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 24 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | 3 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 26 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 34 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 42 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 27 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 28 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 29 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 29 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 29 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 2 |
19 files changed, 17 insertions, 724 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 20c9539abc36..7e4568ee8c6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile | |||
@@ -20,7 +20,7 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \ | |||
20 | amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ | 20 | amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ |
21 | amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \ | 21 | amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o amdgpu_test.o \ |
22 | amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ | 22 | amdgpu_pm.o atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ |
23 | atombios_encoders.o amdgpu_semaphore.o amdgpu_sa.o atombios_i2c.o \ | 23 | atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ |
24 | amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ | 24 | amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \ |
25 | amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o | 25 | amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o |
26 | 26 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7410d5bd37b9..745a9a1ae54b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h | |||
@@ -638,31 +638,10 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, | |||
638 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, | 638 | int amdgpu_mode_dumb_mmap(struct drm_file *filp, |
639 | struct drm_device *dev, | 639 | struct drm_device *dev, |
640 | uint32_t handle, uint64_t *offset_p); | 640 | uint32_t handle, uint64_t *offset_p); |
641 | |||
642 | /* | ||
643 | * Semaphores. | ||
644 | */ | ||
645 | struct amdgpu_semaphore { | ||
646 | struct amdgpu_sa_bo *sa_bo; | ||
647 | signed waiters; | ||
648 | uint64_t gpu_addr; | ||
649 | }; | ||
650 | |||
651 | int amdgpu_semaphore_create(struct amdgpu_device *adev, | ||
652 | struct amdgpu_semaphore **semaphore); | ||
653 | bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, | ||
654 | struct amdgpu_semaphore *semaphore); | ||
655 | bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, | ||
656 | struct amdgpu_semaphore *semaphore); | ||
657 | void amdgpu_semaphore_free(struct amdgpu_device *adev, | ||
658 | struct amdgpu_semaphore **semaphore, | ||
659 | struct fence *fence); | ||
660 | |||
661 | /* | 641 | /* |
662 | * Synchronization | 642 | * Synchronization |
663 | */ | 643 | */ |
664 | struct amdgpu_sync { | 644 | struct amdgpu_sync { |
665 | struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; | ||
666 | struct fence *sync_to[AMDGPU_MAX_RINGS]; | 645 | struct fence *sync_to[AMDGPU_MAX_RINGS]; |
667 | DECLARE_HASHTABLE(fences, 4); | 646 | DECLARE_HASHTABLE(fences, 4); |
668 | struct fence *last_vm_update; | 647 | struct fence *last_vm_update; |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9c1af8976bef..11573fd1f053 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | |||
@@ -81,7 +81,6 @@ int amdgpu_exp_hw_support = 0; | |||
81 | int amdgpu_enable_scheduler = 1; | 81 | int amdgpu_enable_scheduler = 1; |
82 | int amdgpu_sched_jobs = 32; | 82 | int amdgpu_sched_jobs = 32; |
83 | int amdgpu_sched_hw_submission = 2; | 83 | int amdgpu_sched_hw_submission = 2; |
84 | int amdgpu_enable_semaphores = 0; | ||
85 | int amdgpu_powerplay = -1; | 84 | int amdgpu_powerplay = -1; |
86 | 85 | ||
87 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); | 86 | MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); |
@@ -162,9 +161,6 @@ module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); | |||
162 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); | 161 | MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); |
163 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); | 162 | module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); |
164 | 163 | ||
165 | MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))"); | ||
166 | module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644); | ||
167 | |||
168 | #ifdef CONFIG_DRM_AMD_POWERPLAY | 164 | #ifdef CONFIG_DRM_AMD_POWERPLAY |
169 | MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); | 165 | MODULE_PARM_DESC(powerplay, "Powerplay component (1 = enable, 0 = disable, -1 = auto (default))"); |
170 | module_param_named(powerplay, amdgpu_powerplay, int, 0444); | 166 | module_param_named(powerplay, amdgpu_powerplay, int, 0444); |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c deleted file mode 100644 index 1caaf201b708..000000000000 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_semaphore.c +++ /dev/null | |||
@@ -1,102 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright 2011 Christian König. | ||
3 | * All Rights Reserved. | ||
4 | * | ||
5 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
6 | * copy of this software and associated documentation files (the | ||
7 | * "Software"), to deal in the Software without restriction, including | ||
8 | * without limitation the rights to use, copy, modify, merge, publish, | ||
9 | * distribute, sub license, and/or sell copies of the Software, and to | ||
10 | * permit persons to whom the Software is furnished to do so, subject to | ||
11 | * the following conditions: | ||
12 | * | ||
13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL | ||
16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, | ||
17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR | ||
18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE | ||
19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. | ||
20 | * | ||
21 | * The above copyright notice and this permission notice (including the | ||
22 | * next paragraph) shall be included in all copies or substantial portions | ||
23 | * of the Software. | ||
24 | * | ||
25 | */ | ||
26 | /* | ||
27 | * Authors: | ||
28 | * Christian König <deathsimple@vodafone.de> | ||
29 | */ | ||
30 | #include <drm/drmP.h> | ||
31 | #include "amdgpu.h" | ||
32 | #include "amdgpu_trace.h" | ||
33 | |||
34 | int amdgpu_semaphore_create(struct amdgpu_device *adev, | ||
35 | struct amdgpu_semaphore **semaphore) | ||
36 | { | ||
37 | int r; | ||
38 | |||
39 | *semaphore = kmalloc(sizeof(struct amdgpu_semaphore), GFP_KERNEL); | ||
40 | if (*semaphore == NULL) { | ||
41 | return -ENOMEM; | ||
42 | } | ||
43 | r = amdgpu_sa_bo_new(&adev->ring_tmp_bo, | ||
44 | &(*semaphore)->sa_bo, 8, 8); | ||
45 | if (r) { | ||
46 | kfree(*semaphore); | ||
47 | *semaphore = NULL; | ||
48 | return r; | ||
49 | } | ||
50 | (*semaphore)->waiters = 0; | ||
51 | (*semaphore)->gpu_addr = amdgpu_sa_bo_gpu_addr((*semaphore)->sa_bo); | ||
52 | |||
53 | *((uint64_t *)amdgpu_sa_bo_cpu_addr((*semaphore)->sa_bo)) = 0; | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | |||
58 | bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, | ||
59 | struct amdgpu_semaphore *semaphore) | ||
60 | { | ||
61 | trace_amdgpu_semaphore_signale(ring->idx, semaphore); | ||
62 | |||
63 | if (amdgpu_ring_emit_semaphore(ring, semaphore, false)) { | ||
64 | --semaphore->waiters; | ||
65 | |||
66 | /* for debugging lockup only, used by sysfs debug files */ | ||
67 | ring->last_semaphore_signal_addr = semaphore->gpu_addr; | ||
68 | return true; | ||
69 | } | ||
70 | return false; | ||
71 | } | ||
72 | |||
73 | bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, | ||
74 | struct amdgpu_semaphore *semaphore) | ||
75 | { | ||
76 | trace_amdgpu_semaphore_wait(ring->idx, semaphore); | ||
77 | |||
78 | if (amdgpu_ring_emit_semaphore(ring, semaphore, true)) { | ||
79 | ++semaphore->waiters; | ||
80 | |||
81 | /* for debugging lockup only, used by sysfs debug files */ | ||
82 | ring->last_semaphore_wait_addr = semaphore->gpu_addr; | ||
83 | return true; | ||
84 | } | ||
85 | return false; | ||
86 | } | ||
87 | |||
88 | void amdgpu_semaphore_free(struct amdgpu_device *adev, | ||
89 | struct amdgpu_semaphore **semaphore, | ||
90 | struct fence *fence) | ||
91 | { | ||
92 | if (semaphore == NULL || *semaphore == NULL) { | ||
93 | return; | ||
94 | } | ||
95 | if ((*semaphore)->waiters > 0) { | ||
96 | dev_err(adev->dev, "semaphore %p has more waiters than signalers," | ||
97 | " hardware lockup imminent!\n", *semaphore); | ||
98 | } | ||
99 | amdgpu_sa_bo_free(adev, &(*semaphore)->sa_bo, fence); | ||
100 | kfree(*semaphore); | ||
101 | *semaphore = NULL; | ||
102 | } | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 181ce39ef5e5..a6fee511aab5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | |||
@@ -48,9 +48,6 @@ void amdgpu_sync_create(struct amdgpu_sync *sync) | |||
48 | { | 48 | { |
49 | unsigned i; | 49 | unsigned i; |
50 | 50 | ||
51 | for (i = 0; i < AMDGPU_NUM_SYNCS; ++i) | ||
52 | sync->semaphores[i] = NULL; | ||
53 | |||
54 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | 51 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
55 | sync->sync_to[i] = NULL; | 52 | sync->sync_to[i] = NULL; |
56 | 53 | ||
@@ -153,13 +150,13 @@ static void *amdgpu_sync_get_owner(struct fence *f) | |||
153 | } | 150 | } |
154 | 151 | ||
155 | /** | 152 | /** |
156 | * amdgpu_sync_resv - use the semaphores to sync to a reservation object | 153 | * amdgpu_sync_resv - sync to a reservation object |
157 | * | 154 | * |
158 | * @sync: sync object to add fences from reservation object to | 155 | * @sync: sync object to add fences from reservation object to |
159 | * @resv: reservation object with embedded fence | 156 | * @resv: reservation object with embedded fence |
160 | * @shared: true if we should only sync to the exclusive fence | 157 | * @shared: true if we should only sync to the exclusive fence |
161 | * | 158 | * |
162 | * Sync to the fence using the semaphore objects | 159 | * Sync to the fence |
163 | */ | 160 | */ |
164 | int amdgpu_sync_resv(struct amdgpu_device *adev, | 161 | int amdgpu_sync_resv(struct amdgpu_device *adev, |
165 | struct amdgpu_sync *sync, | 162 | struct amdgpu_sync *sync, |
@@ -250,9 +247,6 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync) | |||
250 | kfree(e); | 247 | kfree(e); |
251 | } | 248 | } |
252 | 249 | ||
253 | if (amdgpu_enable_semaphores) | ||
254 | return 0; | ||
255 | |||
256 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | 250 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
257 | struct fence *fence = sync->sync_to[i]; | 251 | struct fence *fence = sync->sync_to[i]; |
258 | if (!fence) | 252 | if (!fence) |
@@ -279,12 +273,10 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, | |||
279 | struct amdgpu_ring *ring) | 273 | struct amdgpu_ring *ring) |
280 | { | 274 | { |
281 | struct amdgpu_device *adev = ring->adev; | 275 | struct amdgpu_device *adev = ring->adev; |
282 | unsigned count = 0; | ||
283 | int i, r; | 276 | int i, r; |
284 | 277 | ||
285 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { | 278 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { |
286 | struct amdgpu_ring *other = adev->rings[i]; | 279 | struct amdgpu_ring *other = adev->rings[i]; |
287 | struct amdgpu_semaphore *semaphore; | ||
288 | struct amdgpu_fence *fence; | 280 | struct amdgpu_fence *fence; |
289 | 281 | ||
290 | if (!sync->sync_to[i]) | 282 | if (!sync->sync_to[i]) |
@@ -292,64 +284,19 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, | |||
292 | 284 | ||
293 | fence = to_amdgpu_fence(sync->sync_to[i]); | 285 | fence = to_amdgpu_fence(sync->sync_to[i]); |
294 | 286 | ||
295 | /* check if we really need to sync */ | ||
296 | if (!amdgpu_enable_scheduler && | ||
297 | !amdgpu_fence_need_sync(fence, ring)) | ||
298 | continue; | ||
299 | |||
300 | /* prevent GPU deadlocks */ | 287 | /* prevent GPU deadlocks */ |
301 | if (!other->ready) { | 288 | if (!other->ready) { |
302 | dev_err(adev->dev, "Syncing to a disabled ring!"); | 289 | dev_err(adev->dev, "Syncing to a disabled ring!"); |
303 | return -EINVAL; | 290 | return -EINVAL; |
304 | } | 291 | } |
305 | 292 | ||
306 | if (amdgpu_enable_scheduler || !amdgpu_enable_semaphores) { | 293 | if (amdgpu_enable_scheduler) { |
307 | r = fence_wait(sync->sync_to[i], true); | 294 | r = fence_wait(sync->sync_to[i], true); |
308 | if (r) | 295 | if (r) |
309 | return r; | 296 | return r; |
310 | continue; | 297 | continue; |
311 | } | 298 | } |
312 | 299 | ||
313 | if (count >= AMDGPU_NUM_SYNCS) { | ||
314 | /* not enough room, wait manually */ | ||
315 | r = fence_wait(&fence->base, false); | ||
316 | if (r) | ||
317 | return r; | ||
318 | continue; | ||
319 | } | ||
320 | r = amdgpu_semaphore_create(adev, &semaphore); | ||
321 | if (r) | ||
322 | return r; | ||
323 | |||
324 | sync->semaphores[count++] = semaphore; | ||
325 | |||
326 | /* allocate enough space for sync command */ | ||
327 | r = amdgpu_ring_alloc(other, 16); | ||
328 | if (r) | ||
329 | return r; | ||
330 | |||
331 | /* emit the signal semaphore */ | ||
332 | if (!amdgpu_semaphore_emit_signal(other, semaphore)) { | ||
333 | /* signaling wasn't successful wait manually */ | ||
334 | amdgpu_ring_undo(other); | ||
335 | r = fence_wait(&fence->base, false); | ||
336 | if (r) | ||
337 | return r; | ||
338 | continue; | ||
339 | } | ||
340 | |||
341 | /* we assume caller has already allocated space on waiters ring */ | ||
342 | if (!amdgpu_semaphore_emit_wait(ring, semaphore)) { | ||
343 | /* waiting wasn't successful wait manually */ | ||
344 | amdgpu_ring_undo(other); | ||
345 | r = fence_wait(&fence->base, false); | ||
346 | if (r) | ||
347 | return r; | ||
348 | continue; | ||
349 | } | ||
350 | |||
351 | amdgpu_ring_commit(other); | ||
352 | amdgpu_fence_note_sync(fence, ring); | ||
353 | } | 300 | } |
354 | 301 | ||
355 | return 0; | 302 | return 0; |
@@ -362,7 +309,7 @@ int amdgpu_sync_rings(struct amdgpu_sync *sync, | |||
362 | * @sync: sync object to use | 309 | * @sync: sync object to use |
363 | * @fence: fence to use for the free | 310 | * @fence: fence to use for the free |
364 | * | 311 | * |
365 | * Free the sync object by freeing all semaphores in it. | 312 | * Free the sync object. |
366 | */ | 313 | */ |
367 | void amdgpu_sync_free(struct amdgpu_device *adev, | 314 | void amdgpu_sync_free(struct amdgpu_device *adev, |
368 | struct amdgpu_sync *sync, | 315 | struct amdgpu_sync *sync, |
@@ -378,9 +325,6 @@ void amdgpu_sync_free(struct amdgpu_device *adev, | |||
378 | kfree(e); | 325 | kfree(e); |
379 | } | 326 | } |
380 | 327 | ||
381 | for (i = 0; i < AMDGPU_NUM_SYNCS; ++i) | ||
382 | amdgpu_semaphore_free(adev, &sync->semaphores[i], fence); | ||
383 | |||
384 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) | 328 | for (i = 0; i < AMDGPU_MAX_RINGS; ++i) |
385 | fence_put(sync->sync_to[i]); | 329 | fence_put(sync->sync_to[i]); |
386 | 330 | ||
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c index 4865615e9c06..05a53f4fc334 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_test.c | |||
@@ -238,144 +238,10 @@ void amdgpu_test_moves(struct amdgpu_device *adev) | |||
238 | amdgpu_do_test_moves(adev); | 238 | amdgpu_do_test_moves(adev); |
239 | } | 239 | } |
240 | 240 | ||
241 | static int amdgpu_test_create_and_emit_fence(struct amdgpu_device *adev, | ||
242 | struct amdgpu_ring *ring, | ||
243 | struct fence **fence) | ||
244 | { | ||
245 | uint32_t handle = ring->idx ^ 0xdeafbeef; | ||
246 | int r; | ||
247 | |||
248 | if (ring == &adev->uvd.ring) { | ||
249 | r = amdgpu_uvd_get_create_msg(ring, handle, NULL); | ||
250 | if (r) { | ||
251 | DRM_ERROR("Failed to get dummy create msg\n"); | ||
252 | return r; | ||
253 | } | ||
254 | |||
255 | r = amdgpu_uvd_get_destroy_msg(ring, handle, fence); | ||
256 | if (r) { | ||
257 | DRM_ERROR("Failed to get dummy destroy msg\n"); | ||
258 | return r; | ||
259 | } | ||
260 | |||
261 | } else if (ring == &adev->vce.ring[0] || | ||
262 | ring == &adev->vce.ring[1]) { | ||
263 | r = amdgpu_vce_get_create_msg(ring, handle, NULL); | ||
264 | if (r) { | ||
265 | DRM_ERROR("Failed to get dummy create msg\n"); | ||
266 | return r; | ||
267 | } | ||
268 | |||
269 | r = amdgpu_vce_get_destroy_msg(ring, handle, fence); | ||
270 | if (r) { | ||
271 | DRM_ERROR("Failed to get dummy destroy msg\n"); | ||
272 | return r; | ||
273 | } | ||
274 | } else { | ||
275 | struct amdgpu_fence *a_fence = NULL; | ||
276 | r = amdgpu_ring_lock(ring, 64); | ||
277 | if (r) { | ||
278 | DRM_ERROR("Failed to lock ring A %d\n", ring->idx); | ||
279 | return r; | ||
280 | } | ||
281 | amdgpu_fence_emit(ring, AMDGPU_FENCE_OWNER_UNDEFINED, &a_fence); | ||
282 | amdgpu_ring_unlock_commit(ring); | ||
283 | *fence = &a_fence->base; | ||
284 | } | ||
285 | return 0; | ||
286 | } | ||
287 | |||
288 | void amdgpu_test_ring_sync(struct amdgpu_device *adev, | 241 | void amdgpu_test_ring_sync(struct amdgpu_device *adev, |
289 | struct amdgpu_ring *ringA, | 242 | struct amdgpu_ring *ringA, |
290 | struct amdgpu_ring *ringB) | 243 | struct amdgpu_ring *ringB) |
291 | { | 244 | { |
292 | struct fence *fence1 = NULL, *fence2 = NULL; | ||
293 | struct amdgpu_semaphore *semaphore = NULL; | ||
294 | int r; | ||
295 | |||
296 | r = amdgpu_semaphore_create(adev, &semaphore); | ||
297 | if (r) { | ||
298 | DRM_ERROR("Failed to create semaphore\n"); | ||
299 | goto out_cleanup; | ||
300 | } | ||
301 | |||
302 | r = amdgpu_ring_lock(ringA, 64); | ||
303 | if (r) { | ||
304 | DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); | ||
305 | goto out_cleanup; | ||
306 | } | ||
307 | amdgpu_semaphore_emit_wait(ringA, semaphore); | ||
308 | amdgpu_ring_unlock_commit(ringA); | ||
309 | |||
310 | r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence1); | ||
311 | if (r) | ||
312 | goto out_cleanup; | ||
313 | |||
314 | r = amdgpu_ring_lock(ringA, 64); | ||
315 | if (r) { | ||
316 | DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); | ||
317 | goto out_cleanup; | ||
318 | } | ||
319 | amdgpu_semaphore_emit_wait(ringA, semaphore); | ||
320 | amdgpu_ring_unlock_commit(ringA); | ||
321 | |||
322 | r = amdgpu_test_create_and_emit_fence(adev, ringA, &fence2); | ||
323 | if (r) | ||
324 | goto out_cleanup; | ||
325 | |||
326 | mdelay(1000); | ||
327 | |||
328 | if (fence_is_signaled(fence1)) { | ||
329 | DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n"); | ||
330 | goto out_cleanup; | ||
331 | } | ||
332 | |||
333 | r = amdgpu_ring_lock(ringB, 64); | ||
334 | if (r) { | ||
335 | DRM_ERROR("Failed to lock ring B %p\n", ringB); | ||
336 | goto out_cleanup; | ||
337 | } | ||
338 | amdgpu_semaphore_emit_signal(ringB, semaphore); | ||
339 | amdgpu_ring_unlock_commit(ringB); | ||
340 | |||
341 | r = fence_wait(fence1, false); | ||
342 | if (r) { | ||
343 | DRM_ERROR("Failed to wait for sync fence 1\n"); | ||
344 | goto out_cleanup; | ||
345 | } | ||
346 | |||
347 | mdelay(1000); | ||
348 | |||
349 | if (fence_is_signaled(fence2)) { | ||
350 | DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n"); | ||
351 | goto out_cleanup; | ||
352 | } | ||
353 | |||
354 | r = amdgpu_ring_lock(ringB, 64); | ||
355 | if (r) { | ||
356 | DRM_ERROR("Failed to lock ring B %p\n", ringB); | ||
357 | goto out_cleanup; | ||
358 | } | ||
359 | amdgpu_semaphore_emit_signal(ringB, semaphore); | ||
360 | amdgpu_ring_unlock_commit(ringB); | ||
361 | |||
362 | r = fence_wait(fence2, false); | ||
363 | if (r) { | ||
364 | DRM_ERROR("Failed to wait for sync fence 1\n"); | ||
365 | goto out_cleanup; | ||
366 | } | ||
367 | |||
368 | out_cleanup: | ||
369 | amdgpu_semaphore_free(adev, &semaphore, NULL); | ||
370 | |||
371 | if (fence1) | ||
372 | fence_put(fence1); | ||
373 | |||
374 | if (fence2) | ||
375 | fence_put(fence2); | ||
376 | |||
377 | if (r) | ||
378 | printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); | ||
379 | } | 245 | } |
380 | 246 | ||
381 | static void amdgpu_test_ring_sync2(struct amdgpu_device *adev, | 247 | static void amdgpu_test_ring_sync2(struct amdgpu_device *adev, |
@@ -383,109 +249,6 @@ static void amdgpu_test_ring_sync2(struct amdgpu_device *adev, | |||
383 | struct amdgpu_ring *ringB, | 249 | struct amdgpu_ring *ringB, |
384 | struct amdgpu_ring *ringC) | 250 | struct amdgpu_ring *ringC) |
385 | { | 251 | { |
386 | struct fence *fenceA = NULL, *fenceB = NULL; | ||
387 | struct amdgpu_semaphore *semaphore = NULL; | ||
388 | bool sigA, sigB; | ||
389 | int i, r; | ||
390 | |||
391 | r = amdgpu_semaphore_create(adev, &semaphore); | ||
392 | if (r) { | ||
393 | DRM_ERROR("Failed to create semaphore\n"); | ||
394 | goto out_cleanup; | ||
395 | } | ||
396 | |||
397 | r = amdgpu_ring_lock(ringA, 64); | ||
398 | if (r) { | ||
399 | DRM_ERROR("Failed to lock ring A %d\n", ringA->idx); | ||
400 | goto out_cleanup; | ||
401 | } | ||
402 | amdgpu_semaphore_emit_wait(ringA, semaphore); | ||
403 | amdgpu_ring_unlock_commit(ringA); | ||
404 | |||
405 | r = amdgpu_test_create_and_emit_fence(adev, ringA, &fenceA); | ||
406 | if (r) | ||
407 | goto out_cleanup; | ||
408 | |||
409 | r = amdgpu_ring_lock(ringB, 64); | ||
410 | if (r) { | ||
411 | DRM_ERROR("Failed to lock ring B %d\n", ringB->idx); | ||
412 | goto out_cleanup; | ||
413 | } | ||
414 | amdgpu_semaphore_emit_wait(ringB, semaphore); | ||
415 | amdgpu_ring_unlock_commit(ringB); | ||
416 | r = amdgpu_test_create_and_emit_fence(adev, ringB, &fenceB); | ||
417 | if (r) | ||
418 | goto out_cleanup; | ||
419 | |||
420 | mdelay(1000); | ||
421 | |||
422 | if (fence_is_signaled(fenceA)) { | ||
423 | DRM_ERROR("Fence A signaled without waiting for semaphore.\n"); | ||
424 | goto out_cleanup; | ||
425 | } | ||
426 | if (fence_is_signaled(fenceB)) { | ||
427 | DRM_ERROR("Fence B signaled without waiting for semaphore.\n"); | ||
428 | goto out_cleanup; | ||
429 | } | ||
430 | |||
431 | r = amdgpu_ring_lock(ringC, 64); | ||
432 | if (r) { | ||
433 | DRM_ERROR("Failed to lock ring B %p\n", ringC); | ||
434 | goto out_cleanup; | ||
435 | } | ||
436 | amdgpu_semaphore_emit_signal(ringC, semaphore); | ||
437 | amdgpu_ring_unlock_commit(ringC); | ||
438 | |||
439 | for (i = 0; i < 30; ++i) { | ||
440 | mdelay(100); | ||
441 | sigA = fence_is_signaled(fenceA); | ||
442 | sigB = fence_is_signaled(fenceB); | ||
443 | if (sigA || sigB) | ||
444 | break; | ||
445 | } | ||
446 | |||
447 | if (!sigA && !sigB) { | ||
448 | DRM_ERROR("Neither fence A nor B has been signaled\n"); | ||
449 | goto out_cleanup; | ||
450 | } else if (sigA && sigB) { | ||
451 | DRM_ERROR("Both fence A and B has been signaled\n"); | ||
452 | goto out_cleanup; | ||
453 | } | ||
454 | |||
455 | DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B'); | ||
456 | |||
457 | r = amdgpu_ring_lock(ringC, 64); | ||
458 | if (r) { | ||
459 | DRM_ERROR("Failed to lock ring B %p\n", ringC); | ||
460 | goto out_cleanup; | ||
461 | } | ||
462 | amdgpu_semaphore_emit_signal(ringC, semaphore); | ||
463 | amdgpu_ring_unlock_commit(ringC); | ||
464 | |||
465 | mdelay(1000); | ||
466 | |||
467 | r = fence_wait(fenceA, false); | ||
468 | if (r) { | ||
469 | DRM_ERROR("Failed to wait for sync fence A\n"); | ||
470 | goto out_cleanup; | ||
471 | } | ||
472 | r = fence_wait(fenceB, false); | ||
473 | if (r) { | ||
474 | DRM_ERROR("Failed to wait for sync fence B\n"); | ||
475 | goto out_cleanup; | ||
476 | } | ||
477 | |||
478 | out_cleanup: | ||
479 | amdgpu_semaphore_free(adev, &semaphore, NULL); | ||
480 | |||
481 | if (fenceA) | ||
482 | fence_put(fenceA); | ||
483 | |||
484 | if (fenceB) | ||
485 | fence_put(fenceB); | ||
486 | |||
487 | if (r) | ||
488 | printk(KERN_WARNING "Error while testing ring sync (%d).\n", r); | ||
489 | } | 252 | } |
490 | 253 | ||
491 | static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA, | 254 | static bool amdgpu_test_sync_possible(struct amdgpu_ring *ringA, |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 8f9834ab1bd5..2b94c6391086 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | |||
@@ -247,42 +247,6 @@ TRACE_EVENT(amdgpu_bo_list_set, | |||
247 | TP_printk("list=%p, bo=%p", __entry->list, __entry->bo) | 247 | TP_printk("list=%p, bo=%p", __entry->list, __entry->bo) |
248 | ); | 248 | ); |
249 | 249 | ||
250 | DECLARE_EVENT_CLASS(amdgpu_semaphore_request, | ||
251 | |||
252 | TP_PROTO(int ring, struct amdgpu_semaphore *sem), | ||
253 | |||
254 | TP_ARGS(ring, sem), | ||
255 | |||
256 | TP_STRUCT__entry( | ||
257 | __field(int, ring) | ||
258 | __field(signed, waiters) | ||
259 | __field(uint64_t, gpu_addr) | ||
260 | ), | ||
261 | |||
262 | TP_fast_assign( | ||
263 | __entry->ring = ring; | ||
264 | __entry->waiters = sem->waiters; | ||
265 | __entry->gpu_addr = sem->gpu_addr; | ||
266 | ), | ||
267 | |||
268 | TP_printk("ring=%u, waiters=%d, addr=%010Lx", __entry->ring, | ||
269 | __entry->waiters, __entry->gpu_addr) | ||
270 | ); | ||
271 | |||
272 | DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_signale, | ||
273 | |||
274 | TP_PROTO(int ring, struct amdgpu_semaphore *sem), | ||
275 | |||
276 | TP_ARGS(ring, sem) | ||
277 | ); | ||
278 | |||
279 | DEFINE_EVENT(amdgpu_semaphore_request, amdgpu_semaphore_wait, | ||
280 | |||
281 | TP_PROTO(int ring, struct amdgpu_semaphore *sem), | ||
282 | |||
283 | TP_ARGS(ring, sem) | ||
284 | ); | ||
285 | |||
286 | #endif | 250 | #endif |
287 | 251 | ||
288 | /* This part must be outside protection */ | 252 | /* This part must be outside protection */ |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index a745eeeb5d82..e882fbfacb12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | |||
@@ -743,30 +743,6 @@ out: | |||
743 | } | 743 | } |
744 | 744 | ||
745 | /** | 745 | /** |
746 | * amdgpu_vce_ring_emit_semaphore - emit a semaphore command | ||
747 | * | ||
748 | * @ring: engine to use | ||
749 | * @semaphore: address of semaphore | ||
750 | * @emit_wait: true=emit wait, false=emit signal | ||
751 | * | ||
752 | */ | ||
753 | bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
754 | struct amdgpu_semaphore *semaphore, | ||
755 | bool emit_wait) | ||
756 | { | ||
757 | uint64_t addr = semaphore->gpu_addr; | ||
758 | |||
759 | amdgpu_ring_write(ring, VCE_CMD_SEMAPHORE); | ||
760 | amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); | ||
761 | amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); | ||
762 | amdgpu_ring_write(ring, 0x01003000 | (emit_wait ? 1 : 0)); | ||
763 | if (!emit_wait) | ||
764 | amdgpu_ring_write(ring, VCE_CMD_END); | ||
765 | |||
766 | return true; | ||
767 | } | ||
768 | |||
769 | /** | ||
770 | * amdgpu_vce_ring_emit_ib - execute indirect buffer | 746 | * amdgpu_vce_ring_emit_ib - execute indirect buffer |
771 | * | 747 | * |
772 | * @ring: engine to use | 748 | * @ring: engine to use |
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h index ba2da8ee5906..5538cf725c85 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h | |||
@@ -34,9 +34,6 @@ int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, | |||
34 | struct fence **fence); | 34 | struct fence **fence); |
35 | void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); | 35 | void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); |
36 | int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); | 36 | int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); |
37 | bool amdgpu_vce_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
38 | struct amdgpu_semaphore *semaphore, | ||
39 | bool emit_wait); | ||
40 | void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); | 37 | void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); |
41 | void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, | 38 | void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, |
42 | unsigned flags); | 39 | unsigned flags); |
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 5f712ceddf08..41e637a0338f 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |||
@@ -295,30 +295,6 @@ static void cik_sdma_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq | |||
295 | } | 295 | } |
296 | 296 | ||
297 | /** | 297 | /** |
298 | * cik_sdma_ring_emit_semaphore - emit a semaphore on the dma ring | ||
299 | * | ||
300 | * @ring: amdgpu_ring structure holding ring information | ||
301 | * @semaphore: amdgpu semaphore object | ||
302 | * @emit_wait: wait or signal semaphore | ||
303 | * | ||
304 | * Add a DMA semaphore packet to the ring wait on or signal | ||
305 | * other rings (CIK). | ||
306 | */ | ||
307 | static bool cik_sdma_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
308 | struct amdgpu_semaphore *semaphore, | ||
309 | bool emit_wait) | ||
310 | { | ||
311 | u64 addr = semaphore->gpu_addr; | ||
312 | u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S; | ||
313 | |||
314 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); | ||
315 | amdgpu_ring_write(ring, addr & 0xfffffff8); | ||
316 | amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff); | ||
317 | |||
318 | return true; | ||
319 | } | ||
320 | |||
321 | /** | ||
322 | * cik_sdma_gfx_stop - stop the gfx async dma engines | 298 | * cik_sdma_gfx_stop - stop the gfx async dma engines |
323 | * | 299 | * |
324 | * @adev: amdgpu_device pointer | 300 | * @adev: amdgpu_device pointer |
@@ -1297,7 +1273,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { | |||
1297 | .parse_cs = NULL, | 1273 | .parse_cs = NULL, |
1298 | .emit_ib = cik_sdma_ring_emit_ib, | 1274 | .emit_ib = cik_sdma_ring_emit_ib, |
1299 | .emit_fence = cik_sdma_ring_emit_fence, | 1275 | .emit_fence = cik_sdma_ring_emit_fence, |
1300 | .emit_semaphore = cik_sdma_ring_emit_semaphore, | 1276 | .emit_semaphore = NULL, |
1301 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, | 1277 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
1302 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, | 1278 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, |
1303 | .test_ring = cik_sdma_ring_test_ring, | 1279 | .test_ring = cik_sdma_ring_test_ring, |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 6c76139de1c9..709ab0b8771d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | |||
@@ -2516,36 +2516,6 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring, | |||
2516 | amdgpu_ring_write(ring, upper_32_bits(seq)); | 2516 | amdgpu_ring_write(ring, upper_32_bits(seq)); |
2517 | } | 2517 | } |
2518 | 2518 | ||
2519 | /** | ||
2520 | * gfx_v7_0_ring_emit_semaphore - emit a semaphore on the CP ring | ||
2521 | * | ||
2522 | * @ring: amdgpu ring buffer object | ||
2523 | * @semaphore: amdgpu semaphore object | ||
2524 | * @emit_wait: Is this a sempahore wait? | ||
2525 | * | ||
2526 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | ||
2527 | * from running ahead of semaphore waits. | ||
2528 | */ | ||
2529 | static bool gfx_v7_0_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
2530 | struct amdgpu_semaphore *semaphore, | ||
2531 | bool emit_wait) | ||
2532 | { | ||
2533 | uint64_t addr = semaphore->gpu_addr; | ||
2534 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; | ||
2535 | |||
2536 | amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); | ||
2537 | amdgpu_ring_write(ring, addr & 0xffffffff); | ||
2538 | amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel); | ||
2539 | |||
2540 | if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { | ||
2541 | /* Prevent the PFP from running ahead of the semaphore wait */ | ||
2542 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | ||
2543 | amdgpu_ring_write(ring, 0x0); | ||
2544 | } | ||
2545 | |||
2546 | return true; | ||
2547 | } | ||
2548 | |||
2549 | /* | 2519 | /* |
2550 | * IB stuff | 2520 | * IB stuff |
2551 | */ | 2521 | */ |
@@ -5567,7 +5537,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { | |||
5567 | .parse_cs = NULL, | 5537 | .parse_cs = NULL, |
5568 | .emit_ib = gfx_v7_0_ring_emit_ib_gfx, | 5538 | .emit_ib = gfx_v7_0_ring_emit_ib_gfx, |
5569 | .emit_fence = gfx_v7_0_ring_emit_fence_gfx, | 5539 | .emit_fence = gfx_v7_0_ring_emit_fence_gfx, |
5570 | .emit_semaphore = gfx_v7_0_ring_emit_semaphore, | 5540 | .emit_semaphore = NULL, |
5571 | .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, | 5541 | .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, |
5572 | .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, | 5542 | .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, |
5573 | .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, | 5543 | .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, |
@@ -5583,7 +5553,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { | |||
5583 | .parse_cs = NULL, | 5553 | .parse_cs = NULL, |
5584 | .emit_ib = gfx_v7_0_ring_emit_ib_compute, | 5554 | .emit_ib = gfx_v7_0_ring_emit_ib_compute, |
5585 | .emit_fence = gfx_v7_0_ring_emit_fence_compute, | 5555 | .emit_fence = gfx_v7_0_ring_emit_fence_compute, |
5586 | .emit_semaphore = gfx_v7_0_ring_emit_semaphore, | 5556 | .emit_semaphore = NULL, |
5587 | .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, | 5557 | .emit_vm_flush = gfx_v7_0_ring_emit_vm_flush, |
5588 | .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, | 5558 | .emit_gds_switch = gfx_v7_0_ring_emit_gds_switch, |
5589 | .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, | 5559 | .emit_hdp_flush = gfx_v7_0_ring_emit_hdp_flush, |
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 8f8ec37ecd88..aa20f626249a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | |||
@@ -4762,44 +4762,6 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, | |||
4762 | 4762 | ||
4763 | } | 4763 | } |
4764 | 4764 | ||
4765 | /** | ||
4766 | * gfx_v8_0_ring_emit_semaphore - emit a semaphore on the CP ring | ||
4767 | * | ||
4768 | * @ring: amdgpu ring buffer object | ||
4769 | * @semaphore: amdgpu semaphore object | ||
4770 | * @emit_wait: Is this a sempahore wait? | ||
4771 | * | ||
4772 | * Emits a semaphore signal/wait packet to the CP ring and prevents the PFP | ||
4773 | * from running ahead of semaphore waits. | ||
4774 | */ | ||
4775 | static bool gfx_v8_0_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
4776 | struct amdgpu_semaphore *semaphore, | ||
4777 | bool emit_wait) | ||
4778 | { | ||
4779 | uint64_t addr = semaphore->gpu_addr; | ||
4780 | unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; | ||
4781 | |||
4782 | if (ring->adev->asic_type == CHIP_TOPAZ || | ||
4783 | ring->adev->asic_type == CHIP_TONGA || | ||
4784 | ring->adev->asic_type == CHIP_FIJI) | ||
4785 | /* we got a hw semaphore bug in VI TONGA, return false to switch back to sw fence wait */ | ||
4786 | return false; | ||
4787 | else { | ||
4788 | amdgpu_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 2)); | ||
4789 | amdgpu_ring_write(ring, lower_32_bits(addr)); | ||
4790 | amdgpu_ring_write(ring, upper_32_bits(addr)); | ||
4791 | amdgpu_ring_write(ring, sel); | ||
4792 | } | ||
4793 | |||
4794 | if (emit_wait && (ring->type == AMDGPU_RING_TYPE_GFX)) { | ||
4795 | /* Prevent the PFP from running ahead of the semaphore wait */ | ||
4796 | amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0)); | ||
4797 | amdgpu_ring_write(ring, 0x0); | ||
4798 | } | ||
4799 | |||
4800 | return true; | ||
4801 | } | ||
4802 | |||
4803 | static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, | 4765 | static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring, |
4804 | unsigned vm_id, uint64_t pd_addr) | 4766 | unsigned vm_id, uint64_t pd_addr) |
4805 | { | 4767 | { |
@@ -5145,7 +5107,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { | |||
5145 | .parse_cs = NULL, | 5107 | .parse_cs = NULL, |
5146 | .emit_ib = gfx_v8_0_ring_emit_ib_gfx, | 5108 | .emit_ib = gfx_v8_0_ring_emit_ib_gfx, |
5147 | .emit_fence = gfx_v8_0_ring_emit_fence_gfx, | 5109 | .emit_fence = gfx_v8_0_ring_emit_fence_gfx, |
5148 | .emit_semaphore = gfx_v8_0_ring_emit_semaphore, | 5110 | .emit_semaphore = NULL, |
5149 | .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, | 5111 | .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, |
5150 | .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, | 5112 | .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, |
5151 | .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, | 5113 | .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, |
@@ -5161,7 +5123,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { | |||
5161 | .parse_cs = NULL, | 5123 | .parse_cs = NULL, |
5162 | .emit_ib = gfx_v8_0_ring_emit_ib_compute, | 5124 | .emit_ib = gfx_v8_0_ring_emit_ib_compute, |
5163 | .emit_fence = gfx_v8_0_ring_emit_fence_compute, | 5125 | .emit_fence = gfx_v8_0_ring_emit_fence_compute, |
5164 | .emit_semaphore = gfx_v8_0_ring_emit_semaphore, | 5126 | .emit_semaphore = NULL, |
5165 | .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, | 5127 | .emit_vm_flush = gfx_v8_0_ring_emit_vm_flush, |
5166 | .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, | 5128 | .emit_gds_switch = gfx_v8_0_ring_emit_gds_switch, |
5167 | .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, | 5129 | .emit_hdp_flush = gfx_v8_0_ring_emit_hdp_flush, |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 2cf50180cc51..9bf3313ca9b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | |||
@@ -335,31 +335,6 @@ static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se | |||
335 | } | 335 | } |
336 | 336 | ||
337 | /** | 337 | /** |
338 | * sdma_v2_4_ring_emit_semaphore - emit a semaphore on the dma ring | ||
339 | * | ||
340 | * @ring: amdgpu_ring structure holding ring information | ||
341 | * @semaphore: amdgpu semaphore object | ||
342 | * @emit_wait: wait or signal semaphore | ||
343 | * | ||
344 | * Add a DMA semaphore packet to the ring wait on or signal | ||
345 | * other rings (VI). | ||
346 | */ | ||
347 | static bool sdma_v2_4_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
348 | struct amdgpu_semaphore *semaphore, | ||
349 | bool emit_wait) | ||
350 | { | ||
351 | u64 addr = semaphore->gpu_addr; | ||
352 | u32 sig = emit_wait ? 0 : 1; | ||
353 | |||
354 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | | ||
355 | SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); | ||
356 | amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); | ||
357 | amdgpu_ring_write(ring, upper_32_bits(addr)); | ||
358 | |||
359 | return true; | ||
360 | } | ||
361 | |||
362 | /** | ||
363 | * sdma_v2_4_gfx_stop - stop the gfx async dma engines | 338 | * sdma_v2_4_gfx_stop - stop the gfx async dma engines |
364 | * | 339 | * |
365 | * @adev: amdgpu_device pointer | 340 | * @adev: amdgpu_device pointer |
@@ -1302,7 +1277,7 @@ static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = { | |||
1302 | .parse_cs = NULL, | 1277 | .parse_cs = NULL, |
1303 | .emit_ib = sdma_v2_4_ring_emit_ib, | 1278 | .emit_ib = sdma_v2_4_ring_emit_ib, |
1304 | .emit_fence = sdma_v2_4_ring_emit_fence, | 1279 | .emit_fence = sdma_v2_4_ring_emit_fence, |
1305 | .emit_semaphore = sdma_v2_4_ring_emit_semaphore, | 1280 | .emit_semaphore = NULL, |
1306 | .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, | 1281 | .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush, |
1307 | .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, | 1282 | .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush, |
1308 | .test_ring = sdma_v2_4_ring_test_ring, | 1283 | .test_ring = sdma_v2_4_ring_test_ring, |
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index ad54c46751b0..93930ae1ff44 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | |||
@@ -444,32 +444,6 @@ static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 se | |||
444 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); | 444 | amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0)); |
445 | } | 445 | } |
446 | 446 | ||
447 | |||
448 | /** | ||
449 | * sdma_v3_0_ring_emit_semaphore - emit a semaphore on the dma ring | ||
450 | * | ||
451 | * @ring: amdgpu_ring structure holding ring information | ||
452 | * @semaphore: amdgpu semaphore object | ||
453 | * @emit_wait: wait or signal semaphore | ||
454 | * | ||
455 | * Add a DMA semaphore packet to the ring wait on or signal | ||
456 | * other rings (VI). | ||
457 | */ | ||
458 | static bool sdma_v3_0_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
459 | struct amdgpu_semaphore *semaphore, | ||
460 | bool emit_wait) | ||
461 | { | ||
462 | u64 addr = semaphore->gpu_addr; | ||
463 | u32 sig = emit_wait ? 0 : 1; | ||
464 | |||
465 | amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SEM) | | ||
466 | SDMA_PKT_SEMAPHORE_HEADER_SIGNAL(sig)); | ||
467 | amdgpu_ring_write(ring, lower_32_bits(addr) & 0xfffffff8); | ||
468 | amdgpu_ring_write(ring, upper_32_bits(addr)); | ||
469 | |||
470 | return true; | ||
471 | } | ||
472 | |||
473 | /** | 447 | /** |
474 | * sdma_v3_0_gfx_stop - stop the gfx async dma engines | 448 | * sdma_v3_0_gfx_stop - stop the gfx async dma engines |
475 | * | 449 | * |
@@ -1570,7 +1544,7 @@ static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = { | |||
1570 | .parse_cs = NULL, | 1544 | .parse_cs = NULL, |
1571 | .emit_ib = sdma_v3_0_ring_emit_ib, | 1545 | .emit_ib = sdma_v3_0_ring_emit_ib, |
1572 | .emit_fence = sdma_v3_0_ring_emit_fence, | 1546 | .emit_fence = sdma_v3_0_ring_emit_fence, |
1573 | .emit_semaphore = sdma_v3_0_ring_emit_semaphore, | 1547 | .emit_semaphore = NULL, |
1574 | .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, | 1548 | .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush, |
1575 | .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, | 1549 | .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush, |
1576 | .test_ring = sdma_v3_0_ring_test_ring, | 1550 | .test_ring = sdma_v3_0_ring_test_ring, |
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 5e9f73af83a8..1ee5d5307e15 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | |||
@@ -439,33 +439,6 @@ static void uvd_v4_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq | |||
439 | } | 439 | } |
440 | 440 | ||
441 | /** | 441 | /** |
442 | * uvd_v4_2_ring_emit_semaphore - emit semaphore command | ||
443 | * | ||
444 | * @ring: amdgpu_ring pointer | ||
445 | * @semaphore: semaphore to emit commands for | ||
446 | * @emit_wait: true if we should emit a wait command | ||
447 | * | ||
448 | * Emit a semaphore command (either wait or signal) to the UVD ring. | ||
449 | */ | ||
450 | static bool uvd_v4_2_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
451 | struct amdgpu_semaphore *semaphore, | ||
452 | bool emit_wait) | ||
453 | { | ||
454 | uint64_t addr = semaphore->gpu_addr; | ||
455 | |||
456 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); | ||
457 | amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); | ||
458 | |||
459 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); | ||
460 | amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); | ||
461 | |||
462 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); | ||
463 | amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); | ||
464 | |||
465 | return true; | ||
466 | } | ||
467 | |||
468 | /** | ||
469 | * uvd_v4_2_ring_test_ring - register write test | 442 | * uvd_v4_2_ring_test_ring - register write test |
470 | * | 443 | * |
471 | * @ring: amdgpu_ring pointer | 444 | * @ring: amdgpu_ring pointer |
@@ -882,7 +855,7 @@ static const struct amdgpu_ring_funcs uvd_v4_2_ring_funcs = { | |||
882 | .parse_cs = amdgpu_uvd_ring_parse_cs, | 855 | .parse_cs = amdgpu_uvd_ring_parse_cs, |
883 | .emit_ib = uvd_v4_2_ring_emit_ib, | 856 | .emit_ib = uvd_v4_2_ring_emit_ib, |
884 | .emit_fence = uvd_v4_2_ring_emit_fence, | 857 | .emit_fence = uvd_v4_2_ring_emit_fence, |
885 | .emit_semaphore = uvd_v4_2_ring_emit_semaphore, | 858 | .emit_semaphore = NULL, |
886 | .test_ring = uvd_v4_2_ring_test_ring, | 859 | .test_ring = uvd_v4_2_ring_test_ring, |
887 | .test_ib = uvd_v4_2_ring_test_ib, | 860 | .test_ib = uvd_v4_2_ring_test_ib, |
888 | .insert_nop = amdgpu_ring_insert_nop, | 861 | .insert_nop = amdgpu_ring_insert_nop, |
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 38864f562981..a928f51091c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | |||
@@ -483,33 +483,6 @@ static void uvd_v5_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq | |||
483 | } | 483 | } |
484 | 484 | ||
485 | /** | 485 | /** |
486 | * uvd_v5_0_ring_emit_semaphore - emit semaphore command | ||
487 | * | ||
488 | * @ring: amdgpu_ring pointer | ||
489 | * @semaphore: semaphore to emit commands for | ||
490 | * @emit_wait: true if we should emit a wait command | ||
491 | * | ||
492 | * Emit a semaphore command (either wait or signal) to the UVD ring. | ||
493 | */ | ||
494 | static bool uvd_v5_0_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
495 | struct amdgpu_semaphore *semaphore, | ||
496 | bool emit_wait) | ||
497 | { | ||
498 | uint64_t addr = semaphore->gpu_addr; | ||
499 | |||
500 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); | ||
501 | amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); | ||
502 | |||
503 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); | ||
504 | amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); | ||
505 | |||
506 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); | ||
507 | amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); | ||
508 | |||
509 | return true; | ||
510 | } | ||
511 | |||
512 | /** | ||
513 | * uvd_v5_0_ring_test_ring - register write test | 486 | * uvd_v5_0_ring_test_ring - register write test |
514 | * | 487 | * |
515 | * @ring: amdgpu_ring pointer | 488 | * @ring: amdgpu_ring pointer |
@@ -821,7 +794,7 @@ static const struct amdgpu_ring_funcs uvd_v5_0_ring_funcs = { | |||
821 | .parse_cs = amdgpu_uvd_ring_parse_cs, | 794 | .parse_cs = amdgpu_uvd_ring_parse_cs, |
822 | .emit_ib = uvd_v5_0_ring_emit_ib, | 795 | .emit_ib = uvd_v5_0_ring_emit_ib, |
823 | .emit_fence = uvd_v5_0_ring_emit_fence, | 796 | .emit_fence = uvd_v5_0_ring_emit_fence, |
824 | .emit_semaphore = uvd_v5_0_ring_emit_semaphore, | 797 | .emit_semaphore = NULL, |
825 | .test_ring = uvd_v5_0_ring_test_ring, | 798 | .test_ring = uvd_v5_0_ring_test_ring, |
826 | .test_ib = uvd_v5_0_ring_test_ib, | 799 | .test_ib = uvd_v5_0_ring_test_ib, |
827 | .insert_nop = amdgpu_ring_insert_nop, | 800 | .insert_nop = amdgpu_ring_insert_nop, |
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 3d5913926436..b387356be3f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | |||
@@ -722,33 +722,6 @@ static void uvd_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq | |||
722 | } | 722 | } |
723 | 723 | ||
724 | /** | 724 | /** |
725 | * uvd_v6_0_ring_emit_semaphore - emit semaphore command | ||
726 | * | ||
727 | * @ring: amdgpu_ring pointer | ||
728 | * @semaphore: semaphore to emit commands for | ||
729 | * @emit_wait: true if we should emit a wait command | ||
730 | * | ||
731 | * Emit a semaphore command (either wait or signal) to the UVD ring. | ||
732 | */ | ||
733 | static bool uvd_v6_0_ring_emit_semaphore(struct amdgpu_ring *ring, | ||
734 | struct amdgpu_semaphore *semaphore, | ||
735 | bool emit_wait) | ||
736 | { | ||
737 | uint64_t addr = semaphore->gpu_addr; | ||
738 | |||
739 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_LOW, 0)); | ||
740 | amdgpu_ring_write(ring, (addr >> 3) & 0x000FFFFF); | ||
741 | |||
742 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_ADDR_HIGH, 0)); | ||
743 | amdgpu_ring_write(ring, (addr >> 23) & 0x000FFFFF); | ||
744 | |||
745 | amdgpu_ring_write(ring, PACKET0(mmUVD_SEMA_CMD, 0)); | ||
746 | amdgpu_ring_write(ring, 0x80 | (emit_wait ? 1 : 0)); | ||
747 | |||
748 | return true; | ||
749 | } | ||
750 | |||
751 | /** | ||
752 | * uvd_v6_0_ring_test_ring - register write test | 725 | * uvd_v6_0_ring_test_ring - register write test |
753 | * | 726 | * |
754 | * @ring: amdgpu_ring pointer | 727 | * @ring: amdgpu_ring pointer |
@@ -1062,7 +1035,7 @@ static const struct amdgpu_ring_funcs uvd_v6_0_ring_funcs = { | |||
1062 | .parse_cs = amdgpu_uvd_ring_parse_cs, | 1035 | .parse_cs = amdgpu_uvd_ring_parse_cs, |
1063 | .emit_ib = uvd_v6_0_ring_emit_ib, | 1036 | .emit_ib = uvd_v6_0_ring_emit_ib, |
1064 | .emit_fence = uvd_v6_0_ring_emit_fence, | 1037 | .emit_fence = uvd_v6_0_ring_emit_fence, |
1065 | .emit_semaphore = uvd_v6_0_ring_emit_semaphore, | 1038 | .emit_semaphore = NULL, |
1066 | .test_ring = uvd_v6_0_ring_test_ring, | 1039 | .test_ring = uvd_v6_0_ring_test_ring, |
1067 | .test_ib = uvd_v6_0_ring_test_ib, | 1040 | .test_ib = uvd_v6_0_ring_test_ib, |
1068 | .insert_nop = amdgpu_ring_insert_nop, | 1041 | .insert_nop = amdgpu_ring_insert_nop, |
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 52ac7a8f1e58..d3eadd07e7cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | |||
@@ -639,7 +639,7 @@ static const struct amdgpu_ring_funcs vce_v2_0_ring_funcs = { | |||
639 | .parse_cs = amdgpu_vce_ring_parse_cs, | 639 | .parse_cs = amdgpu_vce_ring_parse_cs, |
640 | .emit_ib = amdgpu_vce_ring_emit_ib, | 640 | .emit_ib = amdgpu_vce_ring_emit_ib, |
641 | .emit_fence = amdgpu_vce_ring_emit_fence, | 641 | .emit_fence = amdgpu_vce_ring_emit_fence, |
642 | .emit_semaphore = amdgpu_vce_ring_emit_semaphore, | 642 | .emit_semaphore = NULL, |
643 | .test_ring = amdgpu_vce_ring_test_ring, | 643 | .test_ring = amdgpu_vce_ring_test_ring, |
644 | .test_ib = amdgpu_vce_ring_test_ib, | 644 | .test_ib = amdgpu_vce_ring_test_ib, |
645 | .insert_nop = amdgpu_ring_insert_nop, | 645 | .insert_nop = amdgpu_ring_insert_nop, |
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index e99af81e4aec..75b55de3f957 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | |||
@@ -759,7 +759,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = { | |||
759 | .parse_cs = amdgpu_vce_ring_parse_cs, | 759 | .parse_cs = amdgpu_vce_ring_parse_cs, |
760 | .emit_ib = amdgpu_vce_ring_emit_ib, | 760 | .emit_ib = amdgpu_vce_ring_emit_ib, |
761 | .emit_fence = amdgpu_vce_ring_emit_fence, | 761 | .emit_fence = amdgpu_vce_ring_emit_fence, |
762 | .emit_semaphore = amdgpu_vce_ring_emit_semaphore, | 762 | .emit_semaphore = NULL, |
763 | .test_ring = amdgpu_vce_ring_test_ring, | 763 | .test_ring = amdgpu_vce_ring_test_ring, |
764 | .test_ib = amdgpu_vce_ring_test_ib, | 764 | .test_ib = amdgpu_vce_ring_test_ib, |
765 | .insert_nop = amdgpu_ring_insert_nop, | 765 | .insert_nop = amdgpu_ring_insert_nop, |