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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2016-03-18 08:26:34 -0400
committerVinod Koul <vinod.koul@intel.com>2016-04-04 12:42:00 -0400
commit2d4d689f3ec56ad1eca6c899f418aeb6c0cf43ca (patch)
treee5cca5d0988e059421dcbf39687dd3da6ad4c371
parentf55532a0c0b8bb6148f4e07853b876ef73bc69ca (diff)
dmaengine: hsu: allow more than 3 descriptors
Current code allows only up to 3 descriptors to be programmed to the hardware since it is used wrong calculations. Change % to min_t() to allow as many descriptors as user supplied. At once it could be programmed up to 4 descriptors due to hardware limitations. The issue was found under stress test, so it might not bother ordinary users. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/hsu/hsu.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/dma/hsu/hsu.c b/drivers/dma/hsu/hsu.c
index eef145edb936..6fce5ed2fc40 100644
--- a/drivers/dma/hsu/hsu.c
+++ b/drivers/dma/hsu/hsu.c
@@ -77,8 +77,8 @@ static void hsu_dma_chan_start(struct hsu_dma_chan *hsuc)
77 hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr); 77 hsu_chan_writel(hsuc, HSU_CH_MTSR, mtsr);
78 78
79 /* Set descriptors */ 79 /* Set descriptors */
80 count = (desc->nents - desc->active) % HSU_DMA_CHAN_NR_DESC; 80 count = desc->nents - desc->active;
81 for (i = 0; i < count; i++) { 81 for (i = 0; i < count && i < HSU_DMA_CHAN_NR_DESC; i++) {
82 hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr); 82 hsu_chan_writel(hsuc, HSU_CH_DxSAR(i), desc->sg[i].addr);
83 hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len); 83 hsu_chan_writel(hsuc, HSU_CH_DxTSR(i), desc->sg[i].len);
84 84