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authorAlex Elder <elder@linaro.org>2014-02-14 13:29:18 -0500
committerMatt Porter <mporter@linaro.org>2014-02-24 13:43:46 -0500
commit1f27f15258bfee2ae85240e9505186dd959d2892 (patch)
treecaa4d31936a8d94bc9585d9bb9033bb6b9cb9b77
parent6d0abeca3242a88cab8232e4acd7e2bf088f3bc2 (diff)
clk: bcm281xx: add initial clock framework support
Add code for device tree support of clocks in the BCM281xx family of SoCs. Machines in this family use peripheral clocks implemented by "Kona" clock control units (CCUs). (Other Broadcom SoC families use Kona style CCUs as well, but support for them is not yet upstream.) A BCM281xx SoC has multiple CCUs, each of which manages a set of clocks on the SoC. A Kona peripheral clock is composite clock that may include a gate, a parent clock multiplexor, and zero, one or two dividers. There is a variety of gate types, and many gates implement hardware-managed gating (often called "auto-gating"). Most dividers divide their input clock signal by an integer value (one or more). There are also "fractional" dividers which allow division by non-integer values. To accomodate such dividers, clock rates and dividers are generally maintained by the code in "scaled" form, which allows integer and fractional dividers to be handled in a uniform way. If present, the gate for a Kona peripheral clock must be enabled when a change is made to its multiplexor or one of its dividers. Additionally, dividers and multiplexors have trigger registers which must be used whenever the divider value or selected parent clock is changed. The same trigger is often used for a divider and multiplexor, and a BCM281xx peripheral clock occasionally has two triggers. The gate, dividers, and parent clock selector are treated in this code as "components" of a peripheral clock. Their functionality is implemented directly--e.g. the common clock framework gate implementation is not used for a Kona peripheral clock gate. (This has being considered though, and the intention is to evolve this code to leverage common code as much as possible.) The source code is divided into three general portions: drivers/clk/bcm/clk-kona.h drivers/clk/bcm/clk-kona.c These implement the basic Kona clock functionality, including the clk_ops methods and various routines to manipulate registers and interpret their values. This includes some functions used to set clocks to a desired initial state (though this feature is only partially implemented here). drivers/clk/bcm/clk-kona-setup.c This contains generic run-time initialization code for data structures representing Kona CCUs and clocks. This encapsulates the clock structure initialization that can't be done statically. Note that there is a great deal of validity-checking code here, making explicit certain assumptions in the code. This is mostly useful for adding new clock definitions and could possibly be disabled for production use. drivers/clk/bcm/clk-bcm281xx.c This file defines the specific CCUs used by BCM281XX family SoCs, as well as the specific clocks implemented by each. It declares a device tree clock match entry for each CCU defined. include/dt-bindings/clock/bcm281xx.h This file defines the selector (index) values used to identify a particular clock provided by a CCU. It consists entirely of C preprocessor constants, to be used by both the C source and device tree source files. Signed-off-by: Alex Elder <elder@linaro.org> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <mporter@linaro.org> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Matt Porter <mporter@linaro.org>
Diffstat
-rw-r--r--drivers/clk/Kconfig1
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/bcm/Kconfig9
-rw-r--r--drivers/clk/bcm/Makefile3
-rw-r--r--drivers/clk/bcm/clk-bcm281xx.c416
-rw-r--r--drivers/clk/bcm/clk-kona-setup.c769
-rw-r--r--drivers/clk/bcm/clk-kona.c1033
-rw-r--r--drivers/clk/bcm/clk-kona.h410
-rw-r--r--include/dt-bindings/clock/bcm281xx.h65
9 files changed, 2707 insertions, 0 deletions
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 7641965d208d..f9f605695e40 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -111,4 +111,5 @@ source "drivers/clk/qcom/Kconfig"
111 111
112endmenu 112endmenu
113 113
114source "drivers/clk/bcm/Kconfig"
114source "drivers/clk/mvebu/Kconfig" 115source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index a367a9831717..88af4a399d6c 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
29obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 29obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
30obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 30obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
31obj-$(CONFIG_COMMON_CLK_AT91) += at91/ 31obj-$(CONFIG_COMMON_CLK_AT91) += at91/
32obj-$(CONFIG_ARCH_BCM_MOBILE) += bcm/
32obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/ 33obj-$(CONFIG_ARCH_HI3xxx) += hisilicon/
33obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 34obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
34ifeq ($(CONFIG_COMMON_CLK), y) 35ifeq ($(CONFIG_COMMON_CLK), y)
diff --git a/drivers/clk/bcm/Kconfig b/drivers/clk/bcm/Kconfig
new file mode 100644
index 000000000000..a7262fb8ce55
--- /dev/null
+++ b/drivers/clk/bcm/Kconfig
@@ -0,0 +1,9 @@
1config CLK_BCM_KONA
2 bool "Broadcom Kona CCU clock support"
3 depends on ARCH_BCM_MOBILE
4 depends on COMMON_CLK
5 default y
6 help
7 Enable common clock framework support for Broadcom SoCs
8 using "Kona" style clock control units, including those
9 in the BCM281xx family.
diff --git a/drivers/clk/bcm/Makefile b/drivers/clk/bcm/Makefile
new file mode 100644
index 000000000000..cf93359aa862
--- /dev/null
+++ b/drivers/clk/bcm/Makefile
@@ -0,0 +1,3 @@
1obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
2obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
3obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
diff --git a/drivers/clk/bcm/clk-bcm281xx.c b/drivers/clk/bcm/clk-bcm281xx.c
new file mode 100644
index 000000000000..3c66de696aeb
--- /dev/null
+++ b/drivers/clk/bcm/clk-bcm281xx.c
@@ -0,0 +1,416 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include "clk-kona.h"
16#include "dt-bindings/clock/bcm281xx.h"
17
18/* bcm11351 CCU device tree "compatible" strings */
19#define BCM11351_DT_ROOT_CCU_COMPAT "brcm,bcm11351-root-ccu"
20#define BCM11351_DT_AON_CCU_COMPAT "brcm,bcm11351-aon-ccu"
21#define BCM11351_DT_HUB_CCU_COMPAT "brcm,bcm11351-hub-ccu"
22#define BCM11351_DT_MASTER_CCU_COMPAT "brcm,bcm11351-master-ccu"
23#define BCM11351_DT_SLAVE_CCU_COMPAT "brcm,bcm11351-slave-ccu"
24
25/* Root CCU clocks */
26
27static struct peri_clk_data frac_1m_data = {
28 .gate = HW_SW_GATE(0x214, 16, 0, 1),
29 .trig = TRIGGER(0x0e04, 0),
30 .div = FRAC_DIVIDER(0x0e00, 0, 22, 16),
31 .clocks = CLOCKS("ref_crystal"),
32};
33
34/* AON CCU clocks */
35
36static struct peri_clk_data hub_timer_data = {
37 .gate = HW_SW_GATE(0x0414, 16, 0, 1),
38 .clocks = CLOCKS("bbl_32k",
39 "frac_1m",
40 "dft_19_5m"),
41 .sel = SELECTOR(0x0a10, 0, 2),
42 .trig = TRIGGER(0x0a40, 4),
43};
44
45static struct peri_clk_data pmu_bsc_data = {
46 .gate = HW_SW_GATE(0x0418, 16, 0, 1),
47 .clocks = CLOCKS("ref_crystal",
48 "pmu_bsc_var",
49 "bbl_32k"),
50 .sel = SELECTOR(0x0a04, 0, 2),
51 .div = DIVIDER(0x0a04, 3, 4),
52 .trig = TRIGGER(0x0a40, 0),
53};
54
55static struct peri_clk_data pmu_bsc_var_data = {
56 .clocks = CLOCKS("var_312m",
57 "ref_312m"),
58 .sel = SELECTOR(0x0a00, 0, 2),
59 .div = DIVIDER(0x0a00, 4, 5),
60 .trig = TRIGGER(0x0a40, 2),
61};
62
63/* Hub CCU clocks */
64
65static struct peri_clk_data tmon_1m_data = {
66 .gate = HW_SW_GATE(0x04a4, 18, 2, 3),
67 .clocks = CLOCKS("ref_crystal",
68 "frac_1m"),
69 .sel = SELECTOR(0x0e74, 0, 2),
70 .trig = TRIGGER(0x0e84, 1),
71};
72
73/* Master CCU clocks */
74
75static struct peri_clk_data sdio1_data = {
76 .gate = HW_SW_GATE(0x0358, 18, 2, 3),
77 .clocks = CLOCKS("ref_crystal",
78 "var_52m",
79 "ref_52m",
80 "var_96m",
81 "ref_96m"),
82 .sel = SELECTOR(0x0a28, 0, 3),
83 .div = DIVIDER(0x0a28, 4, 14),
84 .trig = TRIGGER(0x0afc, 9),
85};
86
87static struct peri_clk_data sdio2_data = {
88 .gate = HW_SW_GATE(0x035c, 18, 2, 3),
89 .clocks = CLOCKS("ref_crystal",
90 "var_52m",
91 "ref_52m",
92 "var_96m",
93 "ref_96m"),
94 .sel = SELECTOR(0x0a2c, 0, 3),
95 .div = DIVIDER(0x0a2c, 4, 14),
96 .trig = TRIGGER(0x0afc, 10),
97};
98
99static struct peri_clk_data sdio3_data = {
100 .gate = HW_SW_GATE(0x0364, 18, 2, 3),
101 .clocks = CLOCKS("ref_crystal",
102 "var_52m",
103 "ref_52m",
104 "var_96m",
105 "ref_96m"),
106 .sel = SELECTOR(0x0a34, 0, 3),
107 .div = DIVIDER(0x0a34, 4, 14),
108 .trig = TRIGGER(0x0afc, 12),
109};
110
111static struct peri_clk_data sdio4_data = {
112 .gate = HW_SW_GATE(0x0360, 18, 2, 3),
113 .clocks = CLOCKS("ref_crystal",
114 "var_52m",
115 "ref_52m",
116 "var_96m",
117 "ref_96m"),
118 .sel = SELECTOR(0x0a30, 0, 3),
119 .div = DIVIDER(0x0a30, 4, 14),
120 .trig = TRIGGER(0x0afc, 11),
121};
122
123static struct peri_clk_data usb_ic_data = {
124 .gate = HW_SW_GATE(0x0354, 18, 2, 3),
125 .clocks = CLOCKS("ref_crystal",
126 "var_96m",
127 "ref_96m"),
128 .div = FIXED_DIVIDER(2),
129 .sel = SELECTOR(0x0a24, 0, 2),
130 .trig = TRIGGER(0x0afc, 7),
131};
132
133/* also called usbh_48m */
134static struct peri_clk_data hsic2_48m_data = {
135 .gate = HW_SW_GATE(0x0370, 18, 2, 3),
136 .clocks = CLOCKS("ref_crystal",
137 "var_96m",
138 "ref_96m"),
139 .sel = SELECTOR(0x0a38, 0, 2),
140 .div = FIXED_DIVIDER(2),
141 .trig = TRIGGER(0x0afc, 5),
142};
143
144/* also called usbh_12m */
145static struct peri_clk_data hsic2_12m_data = {
146 .gate = HW_SW_GATE(0x0370, 20, 4, 5),
147 .div = DIVIDER(0x0a38, 12, 2),
148 .clocks = CLOCKS("ref_crystal",
149 "var_96m",
150 "ref_96m"),
151 .pre_div = FIXED_DIVIDER(2),
152 .sel = SELECTOR(0x0a38, 0, 2),
153 .trig = TRIGGER(0x0afc, 5),
154};
155
156/* Slave CCU clocks */
157
158static struct peri_clk_data uartb_data = {
159 .gate = HW_SW_GATE(0x0400, 18, 2, 3),
160 .clocks = CLOCKS("ref_crystal",
161 "var_156m",
162 "ref_156m"),
163 .sel = SELECTOR(0x0a10, 0, 2),
164 .div = FRAC_DIVIDER(0x0a10, 4, 12, 8),
165 .trig = TRIGGER(0x0afc, 2),
166};
167
168static struct peri_clk_data uartb2_data = {
169 .gate = HW_SW_GATE(0x0404, 18, 2, 3),
170 .clocks = CLOCKS("ref_crystal",
171 "var_156m",
172 "ref_156m"),
173 .sel = SELECTOR(0x0a14, 0, 2),
174 .div = FRAC_DIVIDER(0x0a14, 4, 12, 8),
175 .trig = TRIGGER(0x0afc, 3),
176};
177
178static struct peri_clk_data uartb3_data = {
179 .gate = HW_SW_GATE(0x0408, 18, 2, 3),
180 .clocks = CLOCKS("ref_crystal",
181 "var_156m",
182 "ref_156m"),
183 .sel = SELECTOR(0x0a18, 0, 2),
184 .div = FRAC_DIVIDER(0x0a18, 4, 12, 8),
185 .trig = TRIGGER(0x0afc, 4),
186};
187
188static struct peri_clk_data uartb4_data = {
189 .gate = HW_SW_GATE(0x0408, 18, 2, 3),
190 .clocks = CLOCKS("ref_crystal",
191 "var_156m",
192 "ref_156m"),
193 .sel = SELECTOR(0x0a1c, 0, 2),
194 .div = FRAC_DIVIDER(0x0a1c, 4, 12, 8),
195 .trig = TRIGGER(0x0afc, 5),
196};
197
198static struct peri_clk_data ssp0_data = {
199 .gate = HW_SW_GATE(0x0410, 18, 2, 3),
200 .clocks = CLOCKS("ref_crystal",
201 "var_104m",
202 "ref_104m",
203 "var_96m",
204 "ref_96m"),
205 .sel = SELECTOR(0x0a20, 0, 3),
206 .div = DIVIDER(0x0a20, 4, 14),
207 .trig = TRIGGER(0x0afc, 6),
208};
209
210static struct peri_clk_data ssp2_data = {
211 .gate = HW_SW_GATE(0x0418, 18, 2, 3),
212 .clocks = CLOCKS("ref_crystal",
213 "var_104m",
214 "ref_104m",
215 "var_96m",
216 "ref_96m"),
217 .sel = SELECTOR(0x0a28, 0, 3),
218 .div = DIVIDER(0x0a28, 4, 14),
219 .trig = TRIGGER(0x0afc, 8),
220};
221
222static struct peri_clk_data bsc1_data = {
223 .gate = HW_SW_GATE(0x0458, 18, 2, 3),
224 .clocks = CLOCKS("ref_crystal",
225 "var_104m",
226 "ref_104m",
227 "var_13m",
228 "ref_13m"),
229 .sel = SELECTOR(0x0a64, 0, 3),
230 .trig = TRIGGER(0x0afc, 23),
231};
232
233static struct peri_clk_data bsc2_data = {
234 .gate = HW_SW_GATE(0x045c, 18, 2, 3),
235 .clocks = CLOCKS("ref_crystal",
236 "var_104m",
237 "ref_104m",
238 "var_13m",
239 "ref_13m"),
240 .sel = SELECTOR(0x0a68, 0, 3),
241 .trig = TRIGGER(0x0afc, 24),
242};
243
244static struct peri_clk_data bsc3_data = {
245 .gate = HW_SW_GATE(0x0484, 18, 2, 3),
246 .clocks = CLOCKS("ref_crystal",
247 "var_104m",
248 "ref_104m",
249 "var_13m",
250 "ref_13m"),
251 .sel = SELECTOR(0x0a84, 0, 3),
252 .trig = TRIGGER(0x0b00, 2),
253};
254
255static struct peri_clk_data pwm_data = {
256 .gate = HW_SW_GATE(0x0468, 18, 2, 3),
257 .clocks = CLOCKS("ref_crystal",
258 "var_104m"),
259 .sel = SELECTOR(0x0a70, 0, 2),
260 .div = DIVIDER(0x0a70, 4, 3),
261 .trig = TRIGGER(0x0afc, 15),
262};
263
264/*
265 * CCU setup routines
266 *
267 * These are called from kona_dt_ccu_setup() to initialize the array
268 * of clocks provided by the CCU. Once allocated, the entries in
269 * the array are initialized by calling kona_clk_setup() with the
270 * initialization data for each clock. They return 0 if successful
271 * or an error code otherwise.
272 */
273static int __init bcm281xx_root_ccu_clks_setup(struct ccu_data *ccu)
274{
275 struct clk **clks;
276 size_t count = BCM281XX_ROOT_CCU_CLOCK_COUNT;
277
278 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
279 if (!clks) {
280 pr_err("%s: failed to allocate root clocks\n", __func__);
281 return -ENOMEM;
282 }
283 ccu->data.clks = clks;
284 ccu->data.clk_num = count;
285
286 PERI_CLK_SETUP(clks, ccu, BCM281XX_ROOT_CCU_FRAC_1M, frac_1m);
287
288 return 0;
289}
290
291static int __init bcm281xx_aon_ccu_clks_setup(struct ccu_data *ccu)
292{
293 struct clk **clks;
294 size_t count = BCM281XX_AON_CCU_CLOCK_COUNT;
295
296 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
297 if (!clks) {
298 pr_err("%s: failed to allocate aon clocks\n", __func__);
299 return -ENOMEM;
300 }
301 ccu->data.clks = clks;
302 ccu->data.clk_num = count;
303
304 PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_HUB_TIMER, hub_timer);
305 PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC, pmu_bsc);
306 PERI_CLK_SETUP(clks, ccu, BCM281XX_AON_CCU_PMU_BSC_VAR, pmu_bsc_var);
307
308 return 0;
309}
310
311static int __init bcm281xx_hub_ccu_clks_setup(struct ccu_data *ccu)
312{
313 struct clk **clks;
314 size_t count = BCM281XX_HUB_CCU_CLOCK_COUNT;
315
316 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
317 if (!clks) {
318 pr_err("%s: failed to allocate hub clocks\n", __func__);
319 return -ENOMEM;
320 }
321 ccu->data.clks = clks;
322 ccu->data.clk_num = count;
323
324 PERI_CLK_SETUP(clks, ccu, BCM281XX_HUB_CCU_TMON_1M, tmon_1m);
325
326 return 0;
327}
328
329static int __init bcm281xx_master_ccu_clks_setup(struct ccu_data *ccu)
330{
331 struct clk **clks;
332 size_t count = BCM281XX_MASTER_CCU_CLOCK_COUNT;
333
334 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
335 if (!clks) {
336 pr_err("%s: failed to allocate master clocks\n", __func__);
337 return -ENOMEM;
338 }
339 ccu->data.clks = clks;
340 ccu->data.clk_num = count;
341
342 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO1, sdio1);
343 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO2, sdio2);
344 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO3, sdio3);
345 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_SDIO4, sdio4);
346 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_USB_IC, usb_ic);
347 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_48M, hsic2_48m);
348 PERI_CLK_SETUP(clks, ccu, BCM281XX_MASTER_CCU_HSIC2_12M, hsic2_12m);
349
350 return 0;
351}
352
353static int __init bcm281xx_slave_ccu_clks_setup(struct ccu_data *ccu)
354{
355 struct clk **clks;
356 size_t count = BCM281XX_SLAVE_CCU_CLOCK_COUNT;
357
358 clks = kzalloc(count * sizeof(*clks), GFP_KERNEL);
359 if (!clks) {
360 pr_err("%s: failed to allocate slave clocks\n", __func__);
361 return -ENOMEM;
362 }
363 ccu->data.clks = clks;
364 ccu->data.clk_num = count;
365
366 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB, uartb);
367 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB2, uartb2);
368 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB3, uartb3);
369 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_UARTB4, uartb4);
370 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP0, ssp0);
371 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_SSP2, ssp2);
372 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC1, bsc1);
373 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC2, bsc2);
374 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_BSC3, bsc3);
375 PERI_CLK_SETUP(clks, ccu, BCM281XX_SLAVE_CCU_PWM, pwm);
376
377 return 0;
378}
379
380/* Device tree match table callback functions */
381
382static void __init kona_dt_root_ccu_setup(struct device_node *node)
383{
384 kona_dt_ccu_setup(node, bcm281xx_root_ccu_clks_setup);
385}
386
387static void __init kona_dt_aon_ccu_setup(struct device_node *node)
388{
389 kona_dt_ccu_setup(node, bcm281xx_aon_ccu_clks_setup);
390}
391
392static void __init kona_dt_hub_ccu_setup(struct device_node *node)
393{
394 kona_dt_ccu_setup(node, bcm281xx_hub_ccu_clks_setup);
395}
396
397static void __init kona_dt_master_ccu_setup(struct device_node *node)
398{
399 kona_dt_ccu_setup(node, bcm281xx_master_ccu_clks_setup);
400}
401
402static void __init kona_dt_slave_ccu_setup(struct device_node *node)
403{
404 kona_dt_ccu_setup(node, bcm281xx_slave_ccu_clks_setup);
405}
406
407CLK_OF_DECLARE(bcm11351_root_ccu, BCM11351_DT_ROOT_CCU_COMPAT,
408 kona_dt_root_ccu_setup);
409CLK_OF_DECLARE(bcm11351_aon_ccu, BCM11351_DT_AON_CCU_COMPAT,
410 kona_dt_aon_ccu_setup);
411CLK_OF_DECLARE(bcm11351_hub_ccu, BCM11351_DT_HUB_CCU_COMPAT,
412 kona_dt_hub_ccu_setup);
413CLK_OF_DECLARE(bcm11351_master_ccu, BCM11351_DT_MASTER_CCU_COMPAT,
414 kona_dt_master_ccu_setup);
415CLK_OF_DECLARE(bcm11351_slave_ccu, BCM11351_DT_SLAVE_CCU_COMPAT,
416 kona_dt_slave_ccu_setup);
diff --git a/drivers/clk/bcm/clk-kona-setup.c b/drivers/clk/bcm/clk-kona-setup.c
new file mode 100644
index 000000000000..f1e88fe6bb4c
--- /dev/null
+++ b/drivers/clk/bcm/clk-kona-setup.c
@@ -0,0 +1,769 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/io.h>
16#include <linux/of_address.h>
17
18#include "clk-kona.h"
19
20/* These are used when a selector or trigger is found to be unneeded */
21#define selector_clear_exists(sel) ((sel)->width = 0)
22#define trigger_clear_exists(trig) FLAG_CLEAR(trig, TRIG, EXISTS)
23
24LIST_HEAD(ccu_list); /* The list of set up CCUs */
25
26/* Validity checking */
27
28static bool clk_requires_trigger(struct kona_clk *bcm_clk)
29{
30 struct peri_clk_data *peri = bcm_clk->peri;
31 struct bcm_clk_sel *sel;
32 struct bcm_clk_div *div;
33
34 if (bcm_clk->type != bcm_clk_peri)
35 return false;
36
37 sel = &peri->sel;
38 if (sel->parent_count && selector_exists(sel))
39 return true;
40
41 div = &peri->div;
42 if (!divider_exists(div))
43 return false;
44
45 /* Fixed dividers don't need triggers */
46 if (!divider_is_fixed(div))
47 return true;
48
49 div = &peri->pre_div;
50
51 return divider_exists(div) && !divider_is_fixed(div);
52}
53
54static bool peri_clk_data_offsets_valid(struct kona_clk *bcm_clk)
55{
56 struct peri_clk_data *peri;
57 struct bcm_clk_gate *gate;
58 struct bcm_clk_div *div;
59 struct bcm_clk_sel *sel;
60 struct bcm_clk_trig *trig;
61 const char *name;
62 u32 range;
63 u32 limit;
64
65 BUG_ON(bcm_clk->type != bcm_clk_peri);
66 peri = bcm_clk->peri;
67 name = bcm_clk->name;
68 range = bcm_clk->ccu->range;
69
70 limit = range - sizeof(u32);
71 limit = round_down(limit, sizeof(u32));
72
73 gate = &peri->gate;
74 if (gate_exists(gate)) {
75 if (gate->offset > limit) {
76 pr_err("%s: bad gate offset for %s (%u > %u)\n",
77 __func__, name, gate->offset, limit);
78 return false;
79 }
80 }
81
82 div = &peri->div;
83 if (divider_exists(div)) {
84 if (div->offset > limit) {
85 pr_err("%s: bad divider offset for %s (%u > %u)\n",
86 __func__, name, div->offset, limit);
87 return false;
88 }
89 }
90
91 div = &peri->pre_div;
92 if (divider_exists(div)) {
93 if (div->offset > limit) {
94 pr_err("%s: bad pre-divider offset for %s "
95 "(%u > %u)\n",
96 __func__, name, div->offset, limit);
97 return false;
98 }
99 }
100
101 sel = &peri->sel;
102 if (selector_exists(sel)) {
103 if (sel->offset > limit) {
104 pr_err("%s: bad selector offset for %s (%u > %u)\n",
105 __func__, name, sel->offset, limit);
106 return false;
107 }
108 }
109
110 trig = &peri->trig;
111 if (trigger_exists(trig)) {
112 if (trig->offset > limit) {
113 pr_err("%s: bad trigger offset for %s (%u > %u)\n",
114 __func__, name, trig->offset, limit);
115 return false;
116 }
117 }
118
119 trig = &peri->pre_trig;
120 if (trigger_exists(trig)) {
121 if (trig->offset > limit) {
122 pr_err("%s: bad pre-trigger offset for %s (%u > %u)\n",
123 __func__, name, trig->offset, limit);
124 return false;
125 }
126 }
127
128 return true;
129}
130
131/* A bit position must be less than the number of bits in a 32-bit register. */
132static bool bit_posn_valid(u32 bit_posn, const char *field_name,
133 const char *clock_name)
134{
135 u32 limit = BITS_PER_BYTE * sizeof(u32) - 1;
136
137 if (bit_posn > limit) {
138 pr_err("%s: bad %s bit for %s (%u > %u)\n", __func__,
139 field_name, clock_name, bit_posn, limit);
140 return false;
141 }
142 return true;
143}
144
145/*
146 * A bitfield must be at least 1 bit wide. Both the low-order and
147 * high-order bits must lie within a 32-bit register. We require
148 * fields to be less than 32 bits wide, mainly because we use
149 * shifting to produce field masks, and shifting a full word width
150 * is not well-defined by the C standard.
151 */
152static bool bitfield_valid(u32 shift, u32 width, const char *field_name,
153 const char *clock_name)
154{
155 u32 limit = BITS_PER_BYTE * sizeof(u32);
156
157 if (!width) {
158 pr_err("%s: bad %s field width 0 for %s\n", __func__,
159 field_name, clock_name);
160 return false;
161 }
162 if (shift + width > limit) {
163 pr_err("%s: bad %s for %s (%u + %u > %u)\n", __func__,
164 field_name, clock_name, shift, width, limit);
165 return false;
166 }
167 return true;
168}
169
170/*
171 * All gates, if defined, have a status bit, and for hardware-only
172 * gates, that's it. Gates that can be software controlled also
173 * have an enable bit. And a gate that can be hardware or software
174 * controlled will have a hardware/software select bit.
175 */
176static bool gate_valid(struct bcm_clk_gate *gate, const char *field_name,
177 const char *clock_name)
178{
179 if (!bit_posn_valid(gate->status_bit, "gate status", clock_name))
180 return false;
181
182 if (gate_is_sw_controllable(gate)) {
183 if (!bit_posn_valid(gate->en_bit, "gate enable", clock_name))
184 return false;
185
186 if (gate_is_hw_controllable(gate)) {
187 if (!bit_posn_valid(gate->hw_sw_sel_bit,
188 "gate hw/sw select",
189 clock_name))
190 return false;
191 }
192 } else {
193 BUG_ON(!gate_is_hw_controllable(gate));
194 }
195
196 return true;
197}
198
199/*
200 * A selector bitfield must be valid. Its parent_sel array must
201 * also be reasonable for the field.
202 */
203static bool sel_valid(struct bcm_clk_sel *sel, const char *field_name,
204 const char *clock_name)
205{
206 if (!bitfield_valid(sel->shift, sel->width, field_name, clock_name))
207 return false;
208
209 if (sel->parent_count) {
210 u32 max_sel;
211 u32 limit;
212
213 /*
214 * Make sure the selector field can hold all the
215 * selector values we expect to be able to use. A
216 * clock only needs to have a selector defined if it
217 * has more than one parent. And in that case the
218 * highest selector value will be in the last entry
219 * in the array.
220 */
221 max_sel = sel->parent_sel[sel->parent_count - 1];
222 limit = (1 << sel->width) - 1;
223 if (max_sel > limit) {
224 pr_err("%s: bad selector for %s "
225 "(%u needs > %u bits)\n",
226 __func__, clock_name, max_sel,
227 sel->width);
228 return false;
229 }
230 } else {
231 pr_warn("%s: ignoring selector for %s (no parents)\n",
232 __func__, clock_name);
233 selector_clear_exists(sel);
234 kfree(sel->parent_sel);
235 sel->parent_sel = NULL;
236 }
237
238 return true;
239}
240
241/*
242 * A fixed divider just needs to be non-zero. A variable divider
243 * has to have a valid divider bitfield, and if it has a fraction,
244 * the width of the fraction must not be no more than the width of
245 * the divider as a whole.
246 */
247static bool div_valid(struct bcm_clk_div *div, const char *field_name,
248 const char *clock_name)
249{
250 if (divider_is_fixed(div)) {
251 /* Any fixed divider value but 0 is OK */
252 if (div->fixed == 0) {
253 pr_err("%s: bad %s fixed value 0 for %s\n", __func__,
254 field_name, clock_name);
255 return false;
256 }
257 return true;
258 }
259 if (!bitfield_valid(div->shift, div->width, field_name, clock_name))
260 return false;
261
262 if (divider_has_fraction(div))
263 if (div->frac_width > div->width) {
264 pr_warn("%s: bad %s fraction width for %s (%u > %u)\n",
265 __func__, field_name, clock_name,
266 div->frac_width, div->width);
267 return false;
268 }
269
270 return true;
271}
272
273/*
274 * If a clock has two dividers, the combined number of fractional
275 * bits must be representable in a 32-bit unsigned value. This
276 * is because we scale up a dividend using both dividers before
277 * dividing to improve accuracy, and we need to avoid overflow.
278 */
279static bool kona_dividers_valid(struct kona_clk *bcm_clk)
280{
281 struct peri_clk_data *peri = bcm_clk->peri;
282 struct bcm_clk_div *div;
283 struct bcm_clk_div *pre_div;
284 u32 limit;
285
286 BUG_ON(bcm_clk->type != bcm_clk_peri);
287
288 if (!divider_exists(&peri->div) || !divider_exists(&peri->pre_div))
289 return true;
290
291 div = &peri->div;
292 pre_div = &peri->pre_div;
293 if (divider_is_fixed(div) || divider_is_fixed(pre_div))
294 return true;
295
296 limit = BITS_PER_BYTE * sizeof(u32);
297
298 return div->frac_width + pre_div->frac_width <= limit;
299}
300
301
302/* A trigger just needs to represent a valid bit position */
303static bool trig_valid(struct bcm_clk_trig *trig, const char *field_name,
304 const char *clock_name)
305{
306 return bit_posn_valid(trig->bit, field_name, clock_name);
307}
308
309/* Determine whether the set of peripheral clock registers are valid. */
310static bool
311peri_clk_data_valid(struct kona_clk *bcm_clk)
312{
313 struct peri_clk_data *peri;
314 struct bcm_clk_gate *gate;
315 struct bcm_clk_sel *sel;
316 struct bcm_clk_div *div;
317 struct bcm_clk_div *pre_div;
318 struct bcm_clk_trig *trig;
319 const char *name;
320
321 BUG_ON(bcm_clk->type != bcm_clk_peri);
322
323 /*
324 * First validate register offsets. This is the only place
325 * where we need something from the ccu, so we do these
326 * together.
327 */
328 if (!peri_clk_data_offsets_valid(bcm_clk))
329 return false;
330
331 peri = bcm_clk->peri;
332 name = bcm_clk->name;
333 gate = &peri->gate;
334 if (gate_exists(gate) && !gate_valid(gate, "gate", name))
335 return false;
336
337 sel = &peri->sel;
338 if (selector_exists(sel)) {
339 if (!sel_valid(sel, "selector", name))
340 return false;
341
342 } else if (sel->parent_count > 1) {
343 pr_err("%s: multiple parents but no selector for %s\n",
344 __func__, name);
345
346 return false;
347 }
348
349 div = &peri->div;
350 pre_div = &peri->pre_div;
351 if (divider_exists(div)) {
352 if (!div_valid(div, "divider", name))
353 return false;
354
355 if (divider_exists(pre_div))
356 if (!div_valid(pre_div, "pre-divider", name))
357 return false;
358 } else if (divider_exists(pre_div)) {
359 pr_err("%s: pre-divider but no divider for %s\n", __func__,
360 name);
361 return false;
362 }
363
364 trig = &peri->trig;
365 if (trigger_exists(trig)) {
366 if (!trig_valid(trig, "trigger", name))
367 return false;
368
369 if (trigger_exists(&peri->pre_trig)) {
370 if (!trig_valid(trig, "pre-trigger", name)) {
371 return false;
372 }
373 }
374 if (!clk_requires_trigger(bcm_clk)) {
375 pr_warn("%s: ignoring trigger for %s (not needed)\n",
376 __func__, name);
377 trigger_clear_exists(trig);
378 }
379 } else if (trigger_exists(&peri->pre_trig)) {
380 pr_err("%s: pre-trigger but no trigger for %s\n", __func__,
381 name);
382 return false;
383 } else if (clk_requires_trigger(bcm_clk)) {
384 pr_err("%s: required trigger missing for %s\n", __func__,
385 name);
386 return false;
387 }
388
389 return kona_dividers_valid(bcm_clk);
390}
391
392static bool kona_clk_valid(struct kona_clk *bcm_clk)
393{
394 switch (bcm_clk->type) {
395 case bcm_clk_peri:
396 if (!peri_clk_data_valid(bcm_clk))
397 return false;
398 break;
399 default:
400 pr_err("%s: unrecognized clock type (%d)\n", __func__,
401 (int)bcm_clk->type);
402 return false;
403 }
404 return true;
405}
406
407/*
408 * Scan an array of parent clock names to determine whether there
409 * are any entries containing BAD_CLK_NAME. Such entries are
410 * placeholders for non-supported clocks. Keep track of the
411 * position of each clock name in the original array.
412 *
413 * Allocates an array of pointers to to hold the names of all
414 * non-null entries in the original array, and returns a pointer to
415 * that array in *names. This will be used for registering the
416 * clock with the common clock code. On successful return,
417 * *count indicates how many entries are in that names array.
418 *
419 * If there is more than one entry in the resulting names array,
420 * another array is allocated to record the parent selector value
421 * for each (defined) parent clock. This is the value that
422 * represents this parent clock in the clock's source selector
423 * register. The position of the clock in the original parent array
424 * defines that selector value. The number of entries in this array
425 * is the same as the number of entries in the parent names array.
426 *
427 * The array of selector values is returned. If the clock has no
428 * parents, no selector is required and a null pointer is returned.
429 *
430 * Returns a null pointer if the clock names array supplied was
431 * null. (This is not an error.)
432 *
433 * Returns a pointer-coded error if an error occurs.
434 */
435static u32 *parent_process(const char *clocks[],
436 u32 *count, const char ***names)
437{
438 static const char **parent_names;
439 static u32 *parent_sel;
440 const char **clock;
441 u32 parent_count;
442 u32 bad_count = 0;
443 u32 orig_count;
444 u32 i;
445 u32 j;
446
447 *count = 0; /* In case of early return */
448 *names = NULL;
449 if (!clocks)
450 return NULL;
451
452 /*
453 * Count the number of names in the null-terminated array,
454 * and find out how many of those are actually clock names.
455 */
456 for (clock = clocks; *clock; clock++)
457 if (*clock == BAD_CLK_NAME)
458 bad_count++;
459 orig_count = (u32)(clock - clocks);
460 parent_count = orig_count - bad_count;
461
462 /* If all clocks are unsupported, we treat it as no clock */
463 if (!parent_count)
464 return NULL;
465
466 /* Avoid exceeding our parent clock limit */
467 if (parent_count > PARENT_COUNT_MAX) {
468 pr_err("%s: too many parents (%u > %u)\n", __func__,
469 parent_count, PARENT_COUNT_MAX);
470 return ERR_PTR(-EINVAL);
471 }
472
473 /*
474 * There is one parent name for each defined parent clock.
475 * We also maintain an array containing the selector value
476 * for each defined clock. If there's only one clock, the
477 * selector is not required, but we allocate space for the
478 * array anyway to keep things simple.
479 */
480 parent_names = kmalloc(parent_count * sizeof(parent_names), GFP_KERNEL);
481 if (!parent_names) {
482 pr_err("%s: error allocating %u parent names\n", __func__,
483 parent_count);
484 return ERR_PTR(-ENOMEM);
485 }
486
487 /* There is at least one parent, so allocate a selector array */
488
489 parent_sel = kmalloc(parent_count * sizeof(*parent_sel), GFP_KERNEL);
490 if (!parent_sel) {
491 pr_err("%s: error allocating %u parent selectors\n", __func__,
492 parent_count);
493 kfree(parent_names);
494
495 return ERR_PTR(-ENOMEM);
496 }
497
498 /* Now fill in the parent names and selector arrays */
499 for (i = 0, j = 0; i < orig_count; i++) {
500 if (clocks[i] != BAD_CLK_NAME) {
501 parent_names[j] = clocks[i];
502 parent_sel[j] = i;
503 j++;
504 }
505 }
506 *names = parent_names;
507 *count = parent_count;
508
509 return parent_sel;
510}
511
512static int
513clk_sel_setup(const char **clocks, struct bcm_clk_sel *sel,
514 struct clk_init_data *init_data)
515{
516 const char **parent_names = NULL;
517 u32 parent_count = 0;
518 u32 *parent_sel;
519
520 /*
521 * If a peripheral clock has multiple parents, the value
522 * used by the hardware to select that parent is represented
523 * by the parent clock's position in the "clocks" list. Some
524 * values don't have defined or supported clocks; these will
525 * have BAD_CLK_NAME entries in the parents[] array. The
526 * list is terminated by a NULL entry.
527 *
528 * We need to supply (only) the names of defined parent
529 * clocks when registering a clock though, so we use an
530 * array of parent selector values to map between the
531 * indexes the common clock code uses and the selector
532 * values we need.
533 */
534 parent_sel = parent_process(clocks, &parent_count, &parent_names);
535 if (IS_ERR(parent_sel)) {
536 int ret = PTR_ERR(parent_sel);
537
538 pr_err("%s: error processing parent clocks for %s (%d)\n",
539 __func__, init_data->name, ret);
540
541 return ret;
542 }
543
544 init_data->parent_names = parent_names;
545 init_data->num_parents = parent_count;
546
547 sel->parent_count = parent_count;
548 sel->parent_sel = parent_sel;
549
550 return 0;
551}
552
553static void clk_sel_teardown(struct bcm_clk_sel *sel,
554 struct clk_init_data *init_data)
555{
556 kfree(sel->parent_sel);
557 sel->parent_sel = NULL;
558 sel->parent_count = 0;
559
560 init_data->num_parents = 0;
561 kfree(init_data->parent_names);
562 init_data->parent_names = NULL;
563}
564
565static void peri_clk_teardown(struct peri_clk_data *data,
566 struct clk_init_data *init_data)
567{
568 clk_sel_teardown(&data->sel, init_data);
569 init_data->ops = NULL;
570}
571
572/*
573 * Caller is responsible for freeing the parent_names[] and
574 * parent_sel[] arrays in the peripheral clock's "data" structure
575 * that can be assigned if the clock has one or more parent clocks
576 * associated with it.
577 */
578static int peri_clk_setup(struct ccu_data *ccu, struct peri_clk_data *data,
579 struct clk_init_data *init_data)
580{
581 init_data->ops = &kona_peri_clk_ops;
582 init_data->flags = 0;
583
584 return clk_sel_setup(data->clocks, &data->sel, init_data);
585}
586
587static void bcm_clk_teardown(struct kona_clk *bcm_clk)
588{
589 switch (bcm_clk->type) {
590 case bcm_clk_peri:
591 peri_clk_teardown(bcm_clk->data, &bcm_clk->init_data);
592 break;
593 default:
594 break;
595 }
596 bcm_clk->data = NULL;
597 bcm_clk->type = bcm_clk_none;
598}
599
600static void kona_clk_teardown(struct clk *clk)
601{
602 struct clk_hw *hw;
603 struct kona_clk *bcm_clk;
604
605 if (!clk)
606 return;
607
608 hw = __clk_get_hw(clk);
609 if (!hw) {
610 pr_err("%s: clk %p has null hw pointer\n", __func__, clk);
611 return;
612 }
613 clk_unregister(clk);
614
615 bcm_clk = to_kona_clk(hw);
616 bcm_clk_teardown(bcm_clk);
617}
618
619struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name,
620 enum bcm_clk_type type, void *data)
621{
622 struct kona_clk *bcm_clk;
623 struct clk_init_data *init_data;
624 struct clk *clk = NULL;
625
626 bcm_clk = kzalloc(sizeof(*bcm_clk), GFP_KERNEL);
627 if (!bcm_clk) {
628 pr_err("%s: failed to allocate bcm_clk for %s\n", __func__,
629 name);
630 return NULL;
631 }
632 bcm_clk->ccu = ccu;
633 bcm_clk->name = name;
634
635 init_data = &bcm_clk->init_data;
636 init_data->name = name;
637 switch (type) {
638 case bcm_clk_peri:
639 if (peri_clk_setup(ccu, data, init_data))
640 goto out_free;
641 break;
642 default:
643 data = NULL;
644 break;
645 }
646 bcm_clk->type = type;
647 bcm_clk->data = data;
648
649 /* Make sure everything makes sense before we set it up */
650 if (!kona_clk_valid(bcm_clk)) {
651 pr_err("%s: clock data invalid for %s\n", __func__, name);
652 goto out_teardown;
653 }
654
655 bcm_clk->hw.init = init_data;
656 clk = clk_register(NULL, &bcm_clk->hw);
657 if (IS_ERR(clk)) {
658 pr_err("%s: error registering clock %s (%ld)\n", __func__,
659 name, PTR_ERR(clk));
660 goto out_teardown;
661 }
662 BUG_ON(!clk);
663
664 return clk;
665out_teardown:
666 bcm_clk_teardown(bcm_clk);
667out_free:
668 kfree(bcm_clk);
669
670 return NULL;
671}
672
673static void ccu_clks_teardown(struct ccu_data *ccu)
674{
675 u32 i;
676
677 for (i = 0; i < ccu->data.clk_num; i++)
678 kona_clk_teardown(ccu->data.clks[i]);
679 kfree(ccu->data.clks);
680}
681
682static void kona_ccu_teardown(struct ccu_data *ccu)
683{
684 if (!ccu)
685 return;
686
687 if (!ccu->base)
688 goto done;
689
690 of_clk_del_provider(ccu->node); /* safe if never added */
691 ccu_clks_teardown(ccu);
692 list_del(&ccu->links);
693 of_node_put(ccu->node);
694 iounmap(ccu->base);
695done:
696 kfree(ccu->name);
697 kfree(ccu);
698}
699
700/*
701 * Set up a CCU. Call the provided ccu_clks_setup callback to
702 * initialize the array of clocks provided by the CCU.
703 */
704void __init kona_dt_ccu_setup(struct device_node *node,
705 int (*ccu_clks_setup)(struct ccu_data *))
706{
707 struct ccu_data *ccu;
708 struct resource res = { 0 };
709 resource_size_t range;
710 int ret;
711
712 ccu = kzalloc(sizeof(*ccu), GFP_KERNEL);
713 if (ccu)
714 ccu->name = kstrdup(node->name, GFP_KERNEL);
715 if (!ccu || !ccu->name) {
716 pr_err("%s: unable to allocate CCU struct for %s\n",
717 __func__, node->name);
718 kfree(ccu);
719
720 return;
721 }
722
723 ret = of_address_to_resource(node, 0, &res);
724 if (ret) {
725 pr_err("%s: no valid CCU registers found for %s\n", __func__,
726 node->name);
727 goto out_err;
728 }
729
730 range = resource_size(&res);
731 if (range > (resource_size_t)U32_MAX) {
732 pr_err("%s: address range too large for %s\n", __func__,
733 node->name);
734 goto out_err;
735 }
736
737 ccu->range = (u32)range;
738 ccu->base = ioremap(res.start, ccu->range);
739 if (!ccu->base) {
740 pr_err("%s: unable to map CCU registers for %s\n", __func__,
741 node->name);
742 goto out_err;
743 }
744
745 spin_lock_init(&ccu->lock);
746 INIT_LIST_HEAD(&ccu->links);
747 ccu->node = of_node_get(node);
748
749 list_add_tail(&ccu->links, &ccu_list);
750
751 /* Set up clocks array (in ccu->data) */
752 if (ccu_clks_setup(ccu))
753 goto out_err;
754
755 ret = of_clk_add_provider(node, of_clk_src_onecell_get, &ccu->data);
756 if (ret) {
757 pr_err("%s: error adding ccu %s as provider (%d)\n", __func__,
758 node->name, ret);
759 goto out_err;
760 }
761
762 if (!kona_ccu_init(ccu))
763 pr_err("Broadcom %s initialization had errors\n", node->name);
764
765 return;
766out_err:
767 kona_ccu_teardown(ccu);
768 pr_err("Broadcom %s setup aborted\n", node->name);
769}
diff --git a/drivers/clk/bcm/clk-kona.c b/drivers/clk/bcm/clk-kona.c
new file mode 100644
index 000000000000..e3d339e08309
--- /dev/null
+++ b/drivers/clk/bcm/clk-kona.c
@@ -0,0 +1,1033 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include "clk-kona.h"
16
17#include <linux/delay.h>
18
19#define CCU_ACCESS_PASSWORD 0xA5A500
20#define CLK_GATE_DELAY_LOOP 2000
21
22/* Bitfield operations */
23
24/* Produces a mask of set bits covering a range of a 32-bit value */
25static inline u32 bitfield_mask(u32 shift, u32 width)
26{
27 return ((1 << width) - 1) << shift;
28}
29
30/* Extract the value of a bitfield found within a given register value */
31static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width)
32{
33 return (reg_val & bitfield_mask(shift, width)) >> shift;
34}
35
36/* Replace the value of a bitfield found within a given register value */
37static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val)
38{
39 u32 mask = bitfield_mask(shift, width);
40
41 return (reg_val & ~mask) | (val << shift);
42}
43
44/* Divider and scaling helpers */
45
46/*
47 * Implement DIV_ROUND_CLOSEST() for 64-bit dividend and both values
48 * unsigned. Note that unlike do_div(), the remainder is discarded
49 * and the return value is the quotient (not the remainder).
50 */
51u64 do_div_round_closest(u64 dividend, unsigned long divisor)
52{
53 u64 result;
54
55 result = dividend + ((u64)divisor >> 1);
56 (void)do_div(result, divisor);
57
58 return result;
59}
60
61/* Convert a divider into the scaled divisor value it represents. */
62static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div)
63{
64 return (u64)reg_div + ((u64)1 << div->frac_width);
65}
66
67/*
68 * Build a scaled divider value as close as possible to the
69 * given whole part (div_value) and fractional part (expressed
70 * in billionths).
71 */
72u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths)
73{
74 u64 combined;
75
76 BUG_ON(!div_value);
77 BUG_ON(billionths >= BILLION);
78
79 combined = (u64)div_value * BILLION + billionths;
80 combined <<= div->frac_width;
81
82 return do_div_round_closest(combined, BILLION);
83}
84
85/* The scaled minimum divisor representable by a divider */
86static inline u64
87scaled_div_min(struct bcm_clk_div *div)
88{
89 if (divider_is_fixed(div))
90 return (u64)div->fixed;
91
92 return scaled_div_value(div, 0);
93}
94
95/* The scaled maximum divisor representable by a divider */
96u64 scaled_div_max(struct bcm_clk_div *div)
97{
98 u32 reg_div;
99
100 if (divider_is_fixed(div))
101 return (u64)div->fixed;
102
103 reg_div = ((u32)1 << div->width) - 1;
104
105 return scaled_div_value(div, reg_div);
106}
107
108/*
109 * Convert a scaled divisor into its divider representation as
110 * stored in a divider register field.
111 */
112static inline u32
113divider(struct bcm_clk_div *div, u64 scaled_div)
114{
115 BUG_ON(scaled_div < scaled_div_min(div));
116 BUG_ON(scaled_div > scaled_div_max(div));
117
118 return (u32)(scaled_div - ((u64)1 << div->frac_width));
119}
120
121/* Return a rate scaled for use when dividing by a scaled divisor. */
122static inline u64
123scale_rate(struct bcm_clk_div *div, u32 rate)
124{
125 if (divider_is_fixed(div))
126 return (u64)rate;
127
128 return (u64)rate << div->frac_width;
129}
130
131/* CCU access */
132
133/* Read a 32-bit register value from a CCU's address space. */
134static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset)
135{
136 return readl(ccu->base + reg_offset);
137}
138
139/* Write a 32-bit register value into a CCU's address space. */
140static inline void
141__ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val)
142{
143 writel(reg_val, ccu->base + reg_offset);
144}
145
146static inline unsigned long ccu_lock(struct ccu_data *ccu)
147{
148 unsigned long flags;
149
150 spin_lock_irqsave(&ccu->lock, flags);
151
152 return flags;
153}
154static inline void ccu_unlock(struct ccu_data *ccu, unsigned long flags)
155{
156 spin_unlock_irqrestore(&ccu->lock, flags);
157}
158
159/*
160 * Enable/disable write access to CCU protected registers. The
161 * WR_ACCESS register for all CCUs is at offset 0.
162 */
163static inline void __ccu_write_enable(struct ccu_data *ccu)
164{
165 if (ccu->write_enabled) {
166 pr_err("%s: access already enabled for %s\n", __func__,
167 ccu->name);
168 return;
169 }
170 ccu->write_enabled = true;
171 __ccu_write(ccu, 0, CCU_ACCESS_PASSWORD | 1);
172}
173
174static inline void __ccu_write_disable(struct ccu_data *ccu)
175{
176 if (!ccu->write_enabled) {
177 pr_err("%s: access wasn't enabled for %s\n", __func__,
178 ccu->name);
179 return;
180 }
181
182 __ccu_write(ccu, 0, CCU_ACCESS_PASSWORD);
183 ccu->write_enabled = false;
184}
185
186/*
187 * Poll a register in a CCU's address space, returning when the
188 * specified bit in that register's value is set (or clear). Delay
189 * a microsecond after each read of the register. Returns true if
190 * successful, or false if we gave up trying.
191 *
192 * Caller must ensure the CCU lock is held.
193 */
194static inline bool
195__ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want)
196{
197 unsigned int tries;
198 u32 bit_mask = 1 << bit;
199
200 for (tries = 0; tries < CLK_GATE_DELAY_LOOP; tries++) {
201 u32 val;
202 bool bit_val;
203
204 val = __ccu_read(ccu, reg_offset);
205 bit_val = (val & bit_mask) != 0;
206 if (bit_val == want)
207 return true;
208 udelay(1);
209 }
210 return false;
211}
212
213/* Gate operations */
214
215/* Determine whether a clock is gated. CCU lock must be held. */
216static bool
217__is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate)
218{
219 u32 bit_mask;
220 u32 reg_val;
221
222 /* If there is no gate we can assume it's enabled. */
223 if (!gate_exists(gate))
224 return true;
225
226 bit_mask = 1 << gate->status_bit;
227 reg_val = __ccu_read(ccu, gate->offset);
228
229 return (reg_val & bit_mask) != 0;
230}
231
232/* Determine whether a clock is gated. */
233static bool
234is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate)
235{
236 long flags;
237 bool ret;
238
239 /* Avoid taking the lock if we can */
240 if (!gate_exists(gate))
241 return true;
242
243 flags = ccu_lock(ccu);
244 ret = __is_clk_gate_enabled(ccu, gate);
245 ccu_unlock(ccu, flags);
246
247 return ret;
248}
249
250/*
251 * Commit our desired gate state to the hardware.
252 * Returns true if successful, false otherwise.
253 */
254static bool
255__gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate)
256{
257 u32 reg_val;
258 u32 mask;
259 bool enabled = false;
260
261 BUG_ON(!gate_exists(gate));
262 if (!gate_is_sw_controllable(gate))
263 return true; /* Nothing we can change */
264
265 reg_val = __ccu_read(ccu, gate->offset);
266
267 /* For a hardware/software gate, set which is in control */
268 if (gate_is_hw_controllable(gate)) {
269 mask = (u32)1 << gate->hw_sw_sel_bit;
270 if (gate_is_sw_managed(gate))
271 reg_val |= mask;
272 else
273 reg_val &= ~mask;
274 }
275
276 /*
277 * If software is in control, enable or disable the gate.
278 * If hardware is, clear the enabled bit for good measure.
279 * If a software controlled gate can't be disabled, we're
280 * required to write a 0 into the enable bit (but the gate
281 * will be enabled).
282 */
283 mask = (u32)1 << gate->en_bit;
284 if (gate_is_sw_managed(gate) && (enabled = gate_is_enabled(gate)) &&
285 !gate_is_no_disable(gate))
286 reg_val |= mask;
287 else
288 reg_val &= ~mask;
289
290 __ccu_write(ccu, gate->offset, reg_val);
291
292 /* For a hardware controlled gate, we're done */
293 if (!gate_is_sw_managed(gate))
294 return true;
295
296 /* Otherwise wait for the gate to be in desired state */
297 return __ccu_wait_bit(ccu, gate->offset, gate->status_bit, enabled);
298}
299
300/*
301 * Initialize a gate. Our desired state (hardware/software select,
302 * and if software, its enable state) is committed to hardware
303 * without the usual checks to see if it's already set up that way.
304 * Returns true if successful, false otherwise.
305 */
306static bool gate_init(struct ccu_data *ccu, struct bcm_clk_gate *gate)
307{
308 if (!gate_exists(gate))
309 return true;
310 return __gate_commit(ccu, gate);
311}
312
313/*
314 * Set a gate to enabled or disabled state. Does nothing if the
315 * gate is not currently under software control, or if it is already
316 * in the requested state. Returns true if successful, false
317 * otherwise. CCU lock must be held.
318 */
319static bool
320__clk_gate(struct ccu_data *ccu, struct bcm_clk_gate *gate, bool enable)
321{
322 bool ret;
323
324 if (!gate_exists(gate) || !gate_is_sw_managed(gate))
325 return true; /* Nothing to do */
326
327 if (!enable && gate_is_no_disable(gate)) {
328 pr_warn("%s: invalid gate disable request (ignoring)\n",
329 __func__);
330 return true;
331 }
332
333 if (enable == gate_is_enabled(gate))
334 return true; /* No change */
335
336 gate_flip_enabled(gate);
337 ret = __gate_commit(ccu, gate);
338 if (!ret)
339 gate_flip_enabled(gate); /* Revert the change */
340
341 return ret;
342}
343
344/* Enable or disable a gate. Returns 0 if successful, -EIO otherwise */
345static int clk_gate(struct ccu_data *ccu, const char *name,
346 struct bcm_clk_gate *gate, bool enable)
347{
348 unsigned long flags;
349 bool success;
350
351 /*
352 * Avoid taking the lock if we can. We quietly ignore
353 * requests to change state that don't make sense.
354 */
355 if (!gate_exists(gate) || !gate_is_sw_managed(gate))
356 return 0;
357 if (!enable && gate_is_no_disable(gate))
358 return 0;
359
360 flags = ccu_lock(ccu);
361 __ccu_write_enable(ccu);
362
363 success = __clk_gate(ccu, gate, enable);
364
365 __ccu_write_disable(ccu);
366 ccu_unlock(ccu, flags);
367
368 if (success)
369 return 0;
370
371 pr_err("%s: failed to %s gate for %s\n", __func__,
372 enable ? "enable" : "disable", name);
373
374 return -EIO;
375}
376
377/* Trigger operations */
378
379/*
380 * Caller must ensure CCU lock is held and access is enabled.
381 * Returns true if successful, false otherwise.
382 */
383static bool __clk_trigger(struct ccu_data *ccu, struct bcm_clk_trig *trig)
384{
385 /* Trigger the clock and wait for it to finish */
386 __ccu_write(ccu, trig->offset, 1 << trig->bit);
387
388 return __ccu_wait_bit(ccu, trig->offset, trig->bit, false);
389}
390
391/* Divider operations */
392
393/* Read a divider value and return the scaled divisor it represents. */
394static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div)
395{
396 unsigned long flags;
397 u32 reg_val;
398 u32 reg_div;
399
400 if (divider_is_fixed(div))
401 return (u64)div->fixed;
402
403 flags = ccu_lock(ccu);
404 reg_val = __ccu_read(ccu, div->offset);
405 ccu_unlock(ccu, flags);
406
407 /* Extract the full divider field from the register value */
408 reg_div = bitfield_extract(reg_val, div->shift, div->width);
409
410 /* Return the scaled divisor value it represents */
411 return scaled_div_value(div, reg_div);
412}
413
414/*
415 * Convert a divider's scaled divisor value into its recorded form
416 * and commit it into the hardware divider register.
417 *
418 * Returns 0 on success. Returns -EINVAL for invalid arguments.
419 * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
420 */
421static int __div_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate,
422 struct bcm_clk_div *div, struct bcm_clk_trig *trig)
423{
424 bool enabled;
425 u32 reg_div;
426 u32 reg_val;
427 int ret = 0;
428
429 BUG_ON(divider_is_fixed(div));
430
431 /*
432 * If we're just initializing the divider, and no initial
433 * state was defined in the device tree, we just find out
434 * what its current value is rather than updating it.
435 */
436 if (div->scaled_div == BAD_SCALED_DIV_VALUE) {
437 reg_val = __ccu_read(ccu, div->offset);
438 reg_div = bitfield_extract(reg_val, div->shift, div->width);
439 div->scaled_div = scaled_div_value(div, reg_div);
440
441 return 0;
442 }
443
444 /* Convert the scaled divisor to the value we need to record */
445 reg_div = divider(div, div->scaled_div);
446
447 /* Clock needs to be enabled before changing the rate */
448 enabled = __is_clk_gate_enabled(ccu, gate);
449 if (!enabled && !__clk_gate(ccu, gate, true)) {
450 ret = -ENXIO;
451 goto out;
452 }
453
454 /* Replace the divider value and record the result */
455 reg_val = __ccu_read(ccu, div->offset);
456 reg_val = bitfield_replace(reg_val, div->shift, div->width, reg_div);
457 __ccu_write(ccu, div->offset, reg_val);
458
459 /* If the trigger fails we still want to disable the gate */
460 if (!__clk_trigger(ccu, trig))
461 ret = -EIO;
462
463 /* Disable the clock again if it was disabled to begin with */
464 if (!enabled && !__clk_gate(ccu, gate, false))
465 ret = ret ? ret : -ENXIO; /* return first error */
466out:
467 return ret;
468}
469
470/*
471 * Initialize a divider by committing our desired state to hardware
472 * without the usual checks to see if it's already set up that way.
473 * Returns true if successful, false otherwise.
474 */
475static bool div_init(struct ccu_data *ccu, struct bcm_clk_gate *gate,
476 struct bcm_clk_div *div, struct bcm_clk_trig *trig)
477{
478 if (!divider_exists(div) || divider_is_fixed(div))
479 return true;
480 return !__div_commit(ccu, gate, div, trig);
481}
482
483static int divider_write(struct ccu_data *ccu, struct bcm_clk_gate *gate,
484 struct bcm_clk_div *div, struct bcm_clk_trig *trig,
485 u64 scaled_div)
486{
487 unsigned long flags;
488 u64 previous;
489 int ret;
490
491 BUG_ON(divider_is_fixed(div));
492
493 previous = div->scaled_div;
494 if (previous == scaled_div)
495 return 0; /* No change */
496
497 div->scaled_div = scaled_div;
498
499 flags = ccu_lock(ccu);
500 __ccu_write_enable(ccu);
501
502 ret = __div_commit(ccu, gate, div, trig);
503
504 __ccu_write_disable(ccu);
505 ccu_unlock(ccu, flags);
506
507 if (ret)
508 div->scaled_div = previous; /* Revert the change */
509
510 return ret;
511
512}
513
514/* Common clock rate helpers */
515
516/*
517 * Implement the common clock framework recalc_rate method, taking
518 * into account a divider and an optional pre-divider. The
519 * pre-divider register pointer may be NULL.
520 */
521static unsigned long clk_recalc_rate(struct ccu_data *ccu,
522 struct bcm_clk_div *div, struct bcm_clk_div *pre_div,
523 unsigned long parent_rate)
524{
525 u64 scaled_parent_rate;
526 u64 scaled_div;
527 u64 result;
528
529 if (!divider_exists(div))
530 return parent_rate;
531
532 if (parent_rate > (unsigned long)LONG_MAX)
533 return 0; /* actually this would be a caller bug */
534
535 /*
536 * If there is a pre-divider, divide the scaled parent rate
537 * by the pre-divider value first. In this case--to improve
538 * accuracy--scale the parent rate by *both* the pre-divider
539 * value and the divider before actually computing the
540 * result of the pre-divider.
541 *
542 * If there's only one divider, just scale the parent rate.
543 */
544 if (pre_div && divider_exists(pre_div)) {
545 u64 scaled_rate;
546
547 scaled_rate = scale_rate(pre_div, parent_rate);
548 scaled_rate = scale_rate(div, scaled_rate);
549 scaled_div = divider_read_scaled(ccu, pre_div);
550 scaled_parent_rate = do_div_round_closest(scaled_rate,
551 scaled_div);
552 } else {
553 scaled_parent_rate = scale_rate(div, parent_rate);
554 }
555
556 /*
557 * Get the scaled divisor value, and divide the scaled
558 * parent rate by that to determine this clock's resulting
559 * rate.
560 */
561 scaled_div = divider_read_scaled(ccu, div);
562 result = do_div_round_closest(scaled_parent_rate, scaled_div);
563
564 return (unsigned long)result;
565}
566
567/*
568 * Compute the output rate produced when a given parent rate is fed
569 * into two dividers. The pre-divider can be NULL, and even if it's
570 * non-null it may be nonexistent. It's also OK for the divider to
571 * be nonexistent, and in that case the pre-divider is also ignored.
572 *
573 * If scaled_div is non-null, it is used to return the scaled divisor
574 * value used by the (downstream) divider to produce that rate.
575 */
576static long round_rate(struct ccu_data *ccu, struct bcm_clk_div *div,
577 struct bcm_clk_div *pre_div,
578 unsigned long rate, unsigned long parent_rate,
579 u64 *scaled_div)
580{
581 u64 scaled_parent_rate;
582 u64 min_scaled_div;
583 u64 max_scaled_div;
584 u64 best_scaled_div;
585 u64 result;
586
587 BUG_ON(!divider_exists(div));
588 BUG_ON(!rate);
589 BUG_ON(parent_rate > (u64)LONG_MAX);
590
591 /*
592 * If there is a pre-divider, divide the scaled parent rate
593 * by the pre-divider value first. In this case--to improve
594 * accuracy--scale the parent rate by *both* the pre-divider
595 * value and the divider before actually computing the
596 * result of the pre-divider.
597 *
598 * If there's only one divider, just scale the parent rate.
599 *
600 * For simplicity we treat the pre-divider as fixed (for now).
601 */
602 if (divider_exists(pre_div)) {
603 u64 scaled_rate;
604 u64 scaled_pre_div;
605
606 scaled_rate = scale_rate(pre_div, parent_rate);
607 scaled_rate = scale_rate(div, scaled_rate);
608 scaled_pre_div = divider_read_scaled(ccu, pre_div);
609 scaled_parent_rate = do_div_round_closest(scaled_rate,
610 scaled_pre_div);
611 } else {
612 scaled_parent_rate = scale_rate(div, parent_rate);
613 }
614
615 /*
616 * Compute the best possible divider and ensure it is in
617 * range. A fixed divider can't be changed, so just report
618 * the best we can do.
619 */
620 if (!divider_is_fixed(div)) {
621 best_scaled_div = do_div_round_closest(scaled_parent_rate,
622 rate);
623 min_scaled_div = scaled_div_min(div);
624 max_scaled_div = scaled_div_max(div);
625 if (best_scaled_div > max_scaled_div)
626 best_scaled_div = max_scaled_div;
627 else if (best_scaled_div < min_scaled_div)
628 best_scaled_div = min_scaled_div;
629 } else {
630 best_scaled_div = divider_read_scaled(ccu, div);
631 }
632
633 /* OK, figure out the resulting rate */
634 result = do_div_round_closest(scaled_parent_rate, best_scaled_div);
635
636 if (scaled_div)
637 *scaled_div = best_scaled_div;
638
639 return (long)result;
640}
641
642/* Common clock parent helpers */
643
644/*
645 * For a given parent selector (register field) value, find the
646 * index into a selector's parent_sel array that contains it.
647 * Returns the index, or BAD_CLK_INDEX if it's not found.
648 */
649static u8 parent_index(struct bcm_clk_sel *sel, u8 parent_sel)
650{
651 u8 i;
652
653 BUG_ON(sel->parent_count > (u32)U8_MAX);
654 for (i = 0; i < sel->parent_count; i++)
655 if (sel->parent_sel[i] == parent_sel)
656 return i;
657 return BAD_CLK_INDEX;
658}
659
660/*
661 * Fetch the current value of the selector, and translate that into
662 * its corresponding index in the parent array we registered with
663 * the clock framework.
664 *
665 * Returns parent array index that corresponds with the value found,
666 * or BAD_CLK_INDEX if the found value is out of range.
667 */
668static u8 selector_read_index(struct ccu_data *ccu, struct bcm_clk_sel *sel)
669{
670 unsigned long flags;
671 u32 reg_val;
672 u32 parent_sel;
673 u8 index;
674
675 /* If there's no selector, there's only one parent */
676 if (!selector_exists(sel))
677 return 0;
678
679 /* Get the value in the selector register */
680 flags = ccu_lock(ccu);
681 reg_val = __ccu_read(ccu, sel->offset);
682 ccu_unlock(ccu, flags);
683
684 parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);
685
686 /* Look up that selector's parent array index and return it */
687 index = parent_index(sel, parent_sel);
688 if (index == BAD_CLK_INDEX)
689 pr_err("%s: out-of-range parent selector %u (%s 0x%04x)\n",
690 __func__, parent_sel, ccu->name, sel->offset);
691
692 return index;
693}
694
695/*
696 * Commit our desired selector value to the hardware.
697 *
698 * Returns 0 on success. Returns -EINVAL for invalid arguments.
699 * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
700 */
701static int
702__sel_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate,
703 struct bcm_clk_sel *sel, struct bcm_clk_trig *trig)
704{
705 u32 parent_sel;
706 u32 reg_val;
707 bool enabled;
708 int ret = 0;
709
710 BUG_ON(!selector_exists(sel));
711
712 /*
713 * If we're just initializing the selector, and no initial
714 * state was defined in the device tree, we just find out
715 * what its current value is rather than updating it.
716 */
717 if (sel->clk_index == BAD_CLK_INDEX) {
718 u8 index;
719
720 reg_val = __ccu_read(ccu, sel->offset);
721 parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);
722 index = parent_index(sel, parent_sel);
723 if (index == BAD_CLK_INDEX)
724 return -EINVAL;
725 sel->clk_index = index;
726
727 return 0;
728 }
729
730 BUG_ON((u32)sel->clk_index >= sel->parent_count);
731 parent_sel = sel->parent_sel[sel->clk_index];
732
733 /* Clock needs to be enabled before changing the parent */
734 enabled = __is_clk_gate_enabled(ccu, gate);
735 if (!enabled && !__clk_gate(ccu, gate, true))
736 return -ENXIO;
737
738 /* Replace the selector value and record the result */
739 reg_val = __ccu_read(ccu, sel->offset);
740 reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel);
741 __ccu_write(ccu, sel->offset, reg_val);
742
743 /* If the trigger fails we still want to disable the gate */
744 if (!__clk_trigger(ccu, trig))
745 ret = -EIO;
746
747 /* Disable the clock again if it was disabled to begin with */
748 if (!enabled && !__clk_gate(ccu, gate, false))
749 ret = ret ? ret : -ENXIO; /* return first error */
750
751 return ret;
752}
753
754/*
755 * Initialize a selector by committing our desired state to hardware
756 * without the usual checks to see if it's already set up that way.
757 * Returns true if successful, false otherwise.
758 */
759static bool sel_init(struct ccu_data *ccu, struct bcm_clk_gate *gate,
760 struct bcm_clk_sel *sel, struct bcm_clk_trig *trig)
761{
762 if (!selector_exists(sel))
763 return true;
764 return !__sel_commit(ccu, gate, sel, trig);
765}
766
767/*
768 * Write a new value into a selector register to switch to a
769 * different parent clock. Returns 0 on success, or an error code
770 * (from __sel_commit()) otherwise.
771 */
772static int selector_write(struct ccu_data *ccu, struct bcm_clk_gate *gate,
773 struct bcm_clk_sel *sel, struct bcm_clk_trig *trig,
774 u8 index)
775{
776 unsigned long flags;
777 u8 previous;
778 int ret;
779
780 previous = sel->clk_index;
781 if (previous == index)
782 return 0; /* No change */
783
784 sel->clk_index = index;
785
786 flags = ccu_lock(ccu);
787 __ccu_write_enable(ccu);
788
789 ret = __sel_commit(ccu, gate, sel, trig);
790
791 __ccu_write_disable(ccu);
792 ccu_unlock(ccu, flags);
793
794 if (ret)
795 sel->clk_index = previous; /* Revert the change */
796
797 return ret;
798}
799
800/* Clock operations */
801
802static int kona_peri_clk_enable(struct clk_hw *hw)
803{
804 struct kona_clk *bcm_clk = to_kona_clk(hw);
805 struct bcm_clk_gate *gate = &bcm_clk->peri->gate;
806
807 return clk_gate(bcm_clk->ccu, bcm_clk->name, gate, true);
808}
809
810static void kona_peri_clk_disable(struct clk_hw *hw)
811{
812 struct kona_clk *bcm_clk = to_kona_clk(hw);
813 struct bcm_clk_gate *gate = &bcm_clk->peri->gate;
814
815 (void)clk_gate(bcm_clk->ccu, bcm_clk->name, gate, false);
816}
817
818static int kona_peri_clk_is_enabled(struct clk_hw *hw)
819{
820 struct kona_clk *bcm_clk = to_kona_clk(hw);
821 struct bcm_clk_gate *gate = &bcm_clk->peri->gate;
822
823 return is_clk_gate_enabled(bcm_clk->ccu, gate) ? 1 : 0;
824}
825
826static unsigned long kona_peri_clk_recalc_rate(struct clk_hw *hw,
827 unsigned long parent_rate)
828{
829 struct kona_clk *bcm_clk = to_kona_clk(hw);
830 struct peri_clk_data *data = bcm_clk->peri;
831
832 return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div,
833 parent_rate);
834}
835
836static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
837 unsigned long *parent_rate)
838{
839 struct kona_clk *bcm_clk = to_kona_clk(hw);
840 struct bcm_clk_div *div = &bcm_clk->peri->div;
841
842 if (!divider_exists(div))
843 return __clk_get_rate(hw->clk);
844
845 /* Quietly avoid a zero rate */
846 return round_rate(bcm_clk->ccu, div, &bcm_clk->peri->pre_div,
847 rate ? rate : 1, *parent_rate, NULL);
848}
849
850static int kona_peri_clk_set_parent(struct clk_hw *hw, u8 index)
851{
852 struct kona_clk *bcm_clk = to_kona_clk(hw);
853 struct peri_clk_data *data = bcm_clk->peri;
854 struct bcm_clk_sel *sel = &data->sel;
855 struct bcm_clk_trig *trig;
856 int ret;
857
858 BUG_ON(index >= sel->parent_count);
859
860 /* If there's only one parent we don't require a selector */
861 if (!selector_exists(sel))
862 return 0;
863
864 /*
865 * The regular trigger is used by default, but if there's a
866 * pre-trigger we want to use that instead.
867 */
868 trig = trigger_exists(&data->pre_trig) ? &data->pre_trig
869 : &data->trig;
870
871 ret = selector_write(bcm_clk->ccu, &data->gate, sel, trig, index);
872 if (ret == -ENXIO) {
873 pr_err("%s: gating failure for %s\n", __func__, bcm_clk->name);
874 ret = -EIO; /* Don't proliferate weird errors */
875 } else if (ret == -EIO) {
876 pr_err("%s: %strigger failed for %s\n", __func__,
877 trig == &data->pre_trig ? "pre-" : "",
878 bcm_clk->name);
879 }
880
881 return ret;
882}
883
884static u8 kona_peri_clk_get_parent(struct clk_hw *hw)
885{
886 struct kona_clk *bcm_clk = to_kona_clk(hw);
887 struct peri_clk_data *data = bcm_clk->peri;
888 u8 index;
889
890 index = selector_read_index(bcm_clk->ccu, &data->sel);
891
892 /* Not all callers would handle an out-of-range value gracefully */
893 return index == BAD_CLK_INDEX ? 0 : index;
894}
895
896static int kona_peri_clk_set_rate(struct clk_hw *hw, unsigned long rate,
897 unsigned long parent_rate)
898{
899 struct kona_clk *bcm_clk = to_kona_clk(hw);
900 struct peri_clk_data *data = bcm_clk->peri;
901 struct bcm_clk_div *div = &data->div;
902 u64 scaled_div = 0;
903 int ret;
904
905 if (parent_rate > (unsigned long)LONG_MAX)
906 return -EINVAL;
907
908 if (rate == __clk_get_rate(hw->clk))
909 return 0;
910
911 if (!divider_exists(div))
912 return rate == parent_rate ? 0 : -EINVAL;
913
914 /*
915 * A fixed divider can't be changed. (Nor can a fixed
916 * pre-divider be, but for now we never actually try to
917 * change that.) Tolerate a request for a no-op change.
918 */
919 if (divider_is_fixed(&data->div))
920 return rate == parent_rate ? 0 : -EINVAL;
921
922 /*
923 * Get the scaled divisor value needed to achieve a clock
924 * rate as close as possible to what was requested, given
925 * the parent clock rate supplied.
926 */
927 (void)round_rate(bcm_clk->ccu, div, &data->pre_div,
928 rate ? rate : 1, parent_rate, &scaled_div);
929
930 /*
931 * We aren't updating any pre-divider at this point, so
932 * we'll use the regular trigger.
933 */
934 ret = divider_write(bcm_clk->ccu, &data->gate, &data->div,
935 &data->trig, scaled_div);
936 if (ret == -ENXIO) {
937 pr_err("%s: gating failure for %s\n", __func__, bcm_clk->name);
938 ret = -EIO; /* Don't proliferate weird errors */
939 } else if (ret == -EIO) {
940 pr_err("%s: trigger failed for %s\n", __func__, bcm_clk->name);
941 }
942
943 return ret;
944}
945
946struct clk_ops kona_peri_clk_ops = {
947 .enable = kona_peri_clk_enable,
948 .disable = kona_peri_clk_disable,
949 .is_enabled = kona_peri_clk_is_enabled,
950 .recalc_rate = kona_peri_clk_recalc_rate,
951 .round_rate = kona_peri_clk_round_rate,
952 .set_parent = kona_peri_clk_set_parent,
953 .get_parent = kona_peri_clk_get_parent,
954 .set_rate = kona_peri_clk_set_rate,
955};
956
957/* Put a peripheral clock into its initial state */
958static bool __peri_clk_init(struct kona_clk *bcm_clk)
959{
960 struct ccu_data *ccu = bcm_clk->ccu;
961 struct peri_clk_data *peri = bcm_clk->peri;
962 const char *name = bcm_clk->name;
963 struct bcm_clk_trig *trig;
964
965 BUG_ON(bcm_clk->type != bcm_clk_peri);
966
967 if (!gate_init(ccu, &peri->gate)) {
968 pr_err("%s: error initializing gate for %s\n", __func__, name);
969 return false;
970 }
971 if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) {
972 pr_err("%s: error initializing divider for %s\n", __func__,
973 name);
974 return false;
975 }
976
977 /*
978 * For the pre-divider and selector, the pre-trigger is used
979 * if it's present, otherwise we just use the regular trigger.
980 */
981 trig = trigger_exists(&peri->pre_trig) ? &peri->pre_trig
982 : &peri->trig;
983
984 if (!div_init(ccu, &peri->gate, &peri->pre_div, trig)) {
985 pr_err("%s: error initializing pre-divider for %s\n", __func__,
986 name);
987 return false;
988 }
989
990 if (!sel_init(ccu, &peri->gate, &peri->sel, trig)) {
991 pr_err("%s: error initializing selector for %s\n", __func__,
992 name);
993 return false;
994 }
995
996 return true;
997}
998
999static bool __kona_clk_init(struct kona_clk *bcm_clk)
1000{
1001 switch (bcm_clk->type) {
1002 case bcm_clk_peri:
1003 return __peri_clk_init(bcm_clk);
1004 default:
1005 BUG();
1006 }
1007 return -EINVAL;
1008}
1009
1010/* Set a CCU and all its clocks into their desired initial state */
1011bool __init kona_ccu_init(struct ccu_data *ccu)
1012{
1013 unsigned long flags;
1014 unsigned int which;
1015 struct clk **clks = ccu->data.clks;
1016 bool success = true;
1017
1018 flags = ccu_lock(ccu);
1019 __ccu_write_enable(ccu);
1020
1021 for (which = 0; which < ccu->data.clk_num; which++) {
1022 struct kona_clk *bcm_clk;
1023
1024 if (!clks[which])
1025 continue;
1026 bcm_clk = to_kona_clk(__clk_get_hw(clks[which]));
1027 success &= __kona_clk_init(bcm_clk);
1028 }
1029
1030 __ccu_write_disable(ccu);
1031 ccu_unlock(ccu, flags);
1032 return success;
1033}
diff --git a/drivers/clk/bcm/clk-kona.h b/drivers/clk/bcm/clk-kona.h
new file mode 100644
index 000000000000..5e139adc3dc5
--- /dev/null
+++ b/drivers/clk/bcm/clk-kona.h
@@ -0,0 +1,410 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _CLK_KONA_H
16#define _CLK_KONA_H
17
18#include <linux/kernel.h>
19#include <linux/list.h>
20#include <linux/spinlock.h>
21#include <linux/slab.h>
22#include <linux/device.h>
23#include <linux/of.h>
24#include <linux/clk-provider.h>
25
26#define BILLION 1000000000
27
28/* The common clock framework uses u8 to represent a parent index */
29#define PARENT_COUNT_MAX ((u32)U8_MAX)
30
31#define BAD_CLK_INDEX U8_MAX /* Can't ever be valid */
32#define BAD_CLK_NAME ((const char *)-1)
33
34#define BAD_SCALED_DIV_VALUE U64_MAX
35
36/*
37 * Utility macros for object flag management. If possible, flags
38 * should be defined such that 0 is the desired default value.
39 */
40#define FLAG(type, flag) BCM_CLK_ ## type ## _FLAGS_ ## flag
41#define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
42#define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
43#define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
44#define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
45
46/* Clock field state tests */
47
48#define gate_exists(gate) FLAG_TEST(gate, GATE, EXISTS)
49#define gate_is_enabled(gate) FLAG_TEST(gate, GATE, ENABLED)
50#define gate_is_hw_controllable(gate) FLAG_TEST(gate, GATE, HW)
51#define gate_is_sw_controllable(gate) FLAG_TEST(gate, GATE, SW)
52#define gate_is_sw_managed(gate) FLAG_TEST(gate, GATE, SW_MANAGED)
53#define gate_is_no_disable(gate) FLAG_TEST(gate, GATE, NO_DISABLE)
54
55#define gate_flip_enabled(gate) FLAG_FLIP(gate, GATE, ENABLED)
56
57#define divider_exists(div) FLAG_TEST(div, DIV, EXISTS)
58#define divider_is_fixed(div) FLAG_TEST(div, DIV, FIXED)
59#define divider_has_fraction(div) (!divider_is_fixed(div) && \
60 (div)->frac_width > 0)
61
62#define selector_exists(sel) ((sel)->width != 0)
63#define trigger_exists(trig) FLAG_TEST(trig, TRIG, EXISTS)
64
65/* Clock type, used to tell common block what it's part of */
66enum bcm_clk_type {
67 bcm_clk_none, /* undefined clock type */
68 bcm_clk_bus,
69 bcm_clk_core,
70 bcm_clk_peri
71};
72
73/*
74 * Each CCU defines a mapped area of memory containing registers
75 * used to manage clocks implemented by the CCU. Access to memory
76 * within the CCU's space is serialized by a spinlock. Before any
77 * (other) address can be written, a special access "password" value
78 * must be written to its WR_ACCESS register (located at the base
79 * address of the range). We keep track of the name of each CCU as
80 * it is set up, and maintain them in a list.
81 */
82struct ccu_data {
83 void __iomem *base; /* base of mapped address space */
84 spinlock_t lock; /* serialization lock */
85 bool write_enabled; /* write access is currently enabled */
86 struct list_head links; /* for ccu_list */
87 struct device_node *node;
88 struct clk_onecell_data data;
89 const char *name;
90 u32 range; /* byte range of address space */
91};
92
93/*
94 * Gating control and status is managed by a 32-bit gate register.
95 *
96 * There are several types of gating available:
97 * - (no gate)
98 * A clock with no gate is assumed to be always enabled.
99 * - hardware-only gating (auto-gating)
100 * Enabling or disabling clocks with this type of gate is
101 * managed automatically by the hardware. Such clocks can be
102 * considered by the software to be enabled. The current status
103 * of auto-gated clocks can be read from the gate status bit.
104 * - software-only gating
105 * Auto-gating is not available for this type of clock.
106 * Instead, software manages whether it's enabled by setting or
107 * clearing the enable bit. The current gate status of a gate
108 * under software control can be read from the gate status bit.
109 * To ensure a change to the gating status is complete, the
110 * status bit can be polled to verify that the gate has entered
111 * the desired state.
112 * - selectable hardware or software gating
113 * Gating for this type of clock can be configured to be either
114 * under software or hardware control. Which type is in use is
115 * determined by the hw_sw_sel bit of the gate register.
116 */
117struct bcm_clk_gate {
118 u32 offset; /* gate register offset */
119 u32 status_bit; /* 0: gate is disabled; 0: gatge is enabled */
120 u32 en_bit; /* 0: disable; 1: enable */
121 u32 hw_sw_sel_bit; /* 0: hardware gating; 1: software gating */
122 u32 flags; /* BCM_CLK_GATE_FLAGS_* below */
123};
124
125/*
126 * Gate flags:
127 * HW means this gate can be auto-gated
128 * SW means the state of this gate can be software controlled
129 * NO_DISABLE means this gate is (only) enabled if under software control
130 * SW_MANAGED means the status of this gate is under software control
131 * ENABLED means this software-managed gate is *supposed* to be enabled
132 */
133#define BCM_CLK_GATE_FLAGS_EXISTS ((u32)1 << 0) /* Gate is valid */
134#define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
135#define BCM_CLK_GATE_FLAGS_SW ((u32)1 << 2) /* Software control */
136#define BCM_CLK_GATE_FLAGS_NO_DISABLE ((u32)1 << 3) /* HW or enabled */
137#define BCM_CLK_GATE_FLAGS_SW_MANAGED ((u32)1 << 4) /* SW now in control */
138#define BCM_CLK_GATE_FLAGS_ENABLED ((u32)1 << 5) /* If SW_MANAGED */
139
140/*
141 * Gate initialization macros.
142 *
143 * Any gate initially under software control will be enabled.
144 */
145
146/* A hardware/software gate initially under software control */
147#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
148 { \
149 .offset = (_offset), \
150 .status_bit = (_status_bit), \
151 .en_bit = (_en_bit), \
152 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
153 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
154 FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)| \
155 FLAG(GATE, EXISTS), \
156 }
157
158/* A hardware/software gate initially under hardware control */
159#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
160 { \
161 .offset = (_offset), \
162 .status_bit = (_status_bit), \
163 .en_bit = (_en_bit), \
164 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
165 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
166 FLAG(GATE, EXISTS), \
167 }
168
169/* A hardware-or-enabled gate (enabled if not under hardware control) */
170#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \
171 { \
172 .offset = (_offset), \
173 .status_bit = (_status_bit), \
174 .en_bit = (_en_bit), \
175 .hw_sw_sel_bit = (_hw_sw_sel_bit), \
176 .flags = FLAG(GATE, HW)|FLAG(GATE, SW)| \
177 FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS), \
178 }
179
180/* A software-only gate */
181#define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \
182 { \
183 .offset = (_offset), \
184 .status_bit = (_status_bit), \
185 .en_bit = (_en_bit), \
186 .flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)| \
187 FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS), \
188 }
189
190/* A hardware-only gate */
191#define HW_ONLY_GATE(_offset, _status_bit) \
192 { \
193 .offset = (_offset), \
194 .status_bit = (_status_bit), \
195 .flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS), \
196 }
197
198/*
199 * Each clock can have zero, one, or two dividers which change the
200 * output rate of the clock. Each divider can be either fixed or
201 * variable. If there are two dividers, they are the "pre-divider"
202 * and the "regular" or "downstream" divider. If there is only one,
203 * there is no pre-divider.
204 *
205 * A fixed divider is any non-zero (positive) value, and it
206 * indicates how the input rate is affected by the divider.
207 *
208 * The value of a variable divider is maintained in a sub-field of a
209 * 32-bit divider register. The position of the field in the
210 * register is defined by its offset and width. The value recorded
211 * in this field is always 1 less than the value it represents.
212 *
213 * In addition, a variable divider can indicate that some subset
214 * of its bits represent a "fractional" part of the divider. Such
215 * bits comprise the low-order portion of the divider field, and can
216 * be viewed as representing the portion of the divider that lies to
217 * the right of the decimal point. Most variable dividers have zero
218 * fractional bits. Variable dividers with non-zero fraction width
219 * still record a value 1 less than the value they represent; the
220 * added 1 does *not* affect the low-order bit in this case, it
221 * affects the bits above the fractional part only. (Often in this
222 * code a divider field value is distinguished from the value it
223 * represents by referring to the latter as a "divisor".)
224 *
225 * In order to avoid dealing with fractions, divider arithmetic is
226 * performed using "scaled" values. A scaled value is one that's
227 * been left-shifted by the fractional width of a divider. Dividing
228 * a scaled value by a scaled divisor produces the desired quotient
229 * without loss of precision and without any other special handling
230 * for fractions.
231 *
232 * The recorded value of a variable divider can be modified. To
233 * modify either divider (or both), a clock must be enabled (i.e.,
234 * using its gate). In addition, a trigger register (described
235 * below) must be used to commit the change, and polled to verify
236 * the change is complete.
237 */
238struct bcm_clk_div {
239 union {
240 struct { /* variable divider */
241 u32 offset; /* divider register offset */
242 u32 shift; /* field shift */
243 u32 width; /* field width */
244 u32 frac_width; /* field fraction width */
245
246 u64 scaled_div; /* scaled divider value */
247 };
248 u32 fixed; /* non-zero fixed divider value */
249 };
250 u32 flags; /* BCM_CLK_DIV_FLAGS_* below */
251};
252
253/*
254 * Divider flags:
255 * EXISTS means this divider exists
256 * FIXED means it is a fixed-rate divider
257 */
258#define BCM_CLK_DIV_FLAGS_EXISTS ((u32)1 << 0) /* Divider is valid */
259#define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
260
261/* Divider initialization macros */
262
263/* A fixed (non-zero) divider */
264#define FIXED_DIVIDER(_value) \
265 { \
266 .fixed = (_value), \
267 .flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED), \
268 }
269
270/* A divider with an integral divisor */
271#define DIVIDER(_offset, _shift, _width) \
272 { \
273 .offset = (_offset), \
274 .shift = (_shift), \
275 .width = (_width), \
276 .scaled_div = BAD_SCALED_DIV_VALUE, \
277 .flags = FLAG(DIV, EXISTS), \
278 }
279
280/* A divider whose divisor has an integer and fractional part */
281#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \
282 { \
283 .offset = (_offset), \
284 .shift = (_shift), \
285 .width = (_width), \
286 .frac_width = (_frac_width), \
287 .scaled_div = BAD_SCALED_DIV_VALUE, \
288 .flags = FLAG(DIV, EXISTS), \
289 }
290
291/*
292 * Clocks may have multiple "parent" clocks. If there is more than
293 * one, a selector must be specified to define which of the parent
294 * clocks is currently in use. The selected clock is indicated in a
295 * sub-field of a 32-bit selector register. The range of
296 * representable selector values typically exceeds the number of
297 * available parent clocks. Occasionally the reset value of a
298 * selector field is explicitly set to a (specific) value that does
299 * not correspond to a defined input clock.
300 *
301 * We register all known parent clocks with the common clock code
302 * using a packed array (i.e., no empty slots) of (parent) clock
303 * names, and refer to them later using indexes into that array.
304 * We maintain an array of selector values indexed by common clock
305 * index values in order to map between these common clock indexes
306 * and the selector values used by the hardware.
307 *
308 * Like dividers, a selector can be modified, but to do so a clock
309 * must be enabled, and a trigger must be used to commit the change.
310 */
311struct bcm_clk_sel {
312 u32 offset; /* selector register offset */
313 u32 shift; /* field shift */
314 u32 width; /* field width */
315
316 u32 parent_count; /* number of entries in parent_sel[] */
317 u32 *parent_sel; /* array of parent selector values */
318 u8 clk_index; /* current selected index in parent_sel[] */
319};
320
321/* Selector initialization macro */
322#define SELECTOR(_offset, _shift, _width) \
323 { \
324 .offset = (_offset), \
325 .shift = (_shift), \
326 .width = (_width), \
327 .clk_index = BAD_CLK_INDEX, \
328 }
329
330/*
331 * Making changes to a variable divider or a selector for a clock
332 * requires the use of a trigger. A trigger is defined by a single
333 * bit within a register. To signal a change, a 1 is written into
334 * that bit. To determine when the change has been completed, that
335 * trigger bit is polled; the read value will be 1 while the change
336 * is in progress, and 0 when it is complete.
337 *
338 * Occasionally a clock will have more than one trigger. In this
339 * case, the "pre-trigger" will be used when changing a clock's
340 * selector and/or its pre-divider.
341 */
342struct bcm_clk_trig {
343 u32 offset; /* trigger register offset */
344 u32 bit; /* trigger bit */
345 u32 flags; /* BCM_CLK_TRIG_FLAGS_* below */
346};
347
348/*
349 * Trigger flags:
350 * EXISTS means this trigger exists
351 */
352#define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
353
354/* Trigger initialization macro */
355#define TRIGGER(_offset, _bit) \
356 { \
357 .offset = (_offset), \
358 .bit = (_bit), \
359 .flags = FLAG(TRIG, EXISTS), \
360 }
361
362struct peri_clk_data {
363 struct bcm_clk_gate gate;
364 struct bcm_clk_trig pre_trig;
365 struct bcm_clk_div pre_div;
366 struct bcm_clk_trig trig;
367 struct bcm_clk_div div;
368 struct bcm_clk_sel sel;
369 const char *clocks[]; /* must be last; use CLOCKS() to declare */
370};
371#define CLOCKS(...) { __VA_ARGS__, NULL, }
372#define NO_CLOCKS { NULL, } /* Must use of no parent clocks */
373
374struct kona_clk {
375 struct clk_hw hw;
376 struct clk_init_data init_data;
377 const char *name; /* name of this clock */
378 struct ccu_data *ccu; /* ccu this clock is associated with */
379 enum bcm_clk_type type;
380 union {
381 void *data;
382 struct peri_clk_data *peri;
383 };
384};
385#define to_kona_clk(_hw) \
386 container_of(_hw, struct kona_clk, hw)
387
388/* Exported globals */
389
390extern struct clk_ops kona_peri_clk_ops;
391
392/* Help functions */
393
394#define PERI_CLK_SETUP(clks, ccu, id, name) \
395 clks[id] = kona_clk_setup(ccu, #name, bcm_clk_peri, &name ## _data)
396
397/* Externally visible functions */
398
399extern u64 do_div_round_closest(u64 dividend, unsigned long divisor);
400extern u64 scaled_div_max(struct bcm_clk_div *div);
401extern u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value,
402 u32 billionths);
403
404extern struct clk *kona_clk_setup(struct ccu_data *ccu, const char *name,
405 enum bcm_clk_type type, void *data);
406extern void __init kona_dt_ccu_setup(struct device_node *node,
407 int (*ccu_clks_setup)(struct ccu_data *));
408extern bool __init kona_ccu_init(struct ccu_data *ccu);
409
410#endif /* _CLK_KONA_H */
diff --git a/include/dt-bindings/clock/bcm281xx.h b/include/dt-bindings/clock/bcm281xx.h
new file mode 100644
index 000000000000..e0096940886d
--- /dev/null
+++ b/include/dt-bindings/clock/bcm281xx.h
@@ -0,0 +1,65 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 * Copyright 2013 Linaro Limited
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation version 2.
8 *
9 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
10 * kind, whether express or implied; without even the implied warranty
11 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef _CLOCK_BCM281XX_H
16#define _CLOCK_BCM281XX_H
17
18/*
19 * This file defines the values used to specify clocks provided by
20 * the clock control units (CCUs) on Broadcom BCM281XX family SoCs.
21 */
22
23/* root CCU clock ids */
24
25#define BCM281XX_ROOT_CCU_FRAC_1M 0
26#define BCM281XX_ROOT_CCU_CLOCK_COUNT 1
27
28/* aon CCU clock ids */
29
30#define BCM281XX_AON_CCU_HUB_TIMER 0
31#define BCM281XX_AON_CCU_PMU_BSC 1
32#define BCM281XX_AON_CCU_PMU_BSC_VAR 2
33#define BCM281XX_AON_CCU_CLOCK_COUNT 3
34
35/* hub CCU clock ids */
36
37#define BCM281XX_HUB_CCU_TMON_1M 0
38#define BCM281XX_HUB_CCU_CLOCK_COUNT 1
39
40/* master CCU clock ids */
41
42#define BCM281XX_MASTER_CCU_SDIO1 0
43#define BCM281XX_MASTER_CCU_SDIO2 1
44#define BCM281XX_MASTER_CCU_SDIO3 2
45#define BCM281XX_MASTER_CCU_SDIO4 3
46#define BCM281XX_MASTER_CCU_USB_IC 4
47#define BCM281XX_MASTER_CCU_HSIC2_48M 5
48#define BCM281XX_MASTER_CCU_HSIC2_12M 6
49#define BCM281XX_MASTER_CCU_CLOCK_COUNT 7
50
51/* slave CCU clock ids */
52
53#define BCM281XX_SLAVE_CCU_UARTB 0
54#define BCM281XX_SLAVE_CCU_UARTB2 1
55#define BCM281XX_SLAVE_CCU_UARTB3 2
56#define BCM281XX_SLAVE_CCU_UARTB4 3
57#define BCM281XX_SLAVE_CCU_SSP0 4
58#define BCM281XX_SLAVE_CCU_SSP2 5
59#define BCM281XX_SLAVE_CCU_BSC1 6
60#define BCM281XX_SLAVE_CCU_BSC2 7
61#define BCM281XX_SLAVE_CCU_BSC3 8
62#define BCM281XX_SLAVE_CCU_PWM 9
63#define BCM281XX_SLAVE_CCU_CLOCK_COUNT 10
64
65#endif /* _CLOCK_BCM281XX_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-11 09:30:33 -0400