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authorMaruthi Srinivas Bayyavarapu <Maruthi.Bayyavarapu@amd.com>2016-04-26 11:05:36 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-08-31 15:21:10 -0400
commit1919696eedc1ed5c3ace229576e4fa322fb256dd (patch)
tree3c445d54c57ecc1c577ab45ebd6785611acf2849
parent84b77336eea3690b4261c05707a7aba23b61fbad (diff)
drm/amdgpu: enable SI DPM
Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/si.c8
3 files changed, 15 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 5ebea9dcc6bf..dc6df075bafc 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -30,7 +30,7 @@ amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
30 ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \ 30 ci_smc.o ci_dpm.o dce_v8_0.o gfx_v7_0.o cik_sdma.o uvd_v4_2.o vce_v2_0.o \
31 amdgpu_amdkfd_gfx_v7.o 31 amdgpu_amdkfd_gfx_v7.o
32 32
33amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o 33amdgpu-$(CONFIG_DRM_AMDGPU_SI)+= si.o gmc_v6_0.o gfx_v6_0.o si_ih.o si_dma.o dce_v6_0.o si_dpm.o si_smc.o
34 34
35amdgpu-y += \ 35amdgpu-y += \
36 vi.o 36 vi.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index ecc4141cd716..1e7f160f23d8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -30,6 +30,7 @@
30#include "amdgpu_pm.h" 30#include "amdgpu_pm.h"
31#include <drm/amdgpu_drm.h> 31#include <drm/amdgpu_drm.h>
32#include "amdgpu_powerplay.h" 32#include "amdgpu_powerplay.h"
33#include "si_dpm.h"
33#include "cik_dpm.h" 34#include "cik_dpm.h"
34#include "vi_dpm.h" 35#include "vi_dpm.h"
35 36
@@ -59,6 +60,15 @@ static int amdgpu_powerplay_init(struct amdgpu_device *adev)
59 amd_pp->pp_handle = (void *)adev; 60 amd_pp->pp_handle = (void *)adev;
60 61
61 switch (adev->asic_type) { 62 switch (adev->asic_type) {
63#ifdef CONFIG_DRM_AMDGPU_SI
64 case CHIP_TAHITI:
65 case CHIP_PITCAIRN:
66 case CHIP_VERDE:
67 case CHIP_OLAND:
68 case CHIP_HAINAN:
69 amd_pp->ip_funcs = &si_dpm_ip_funcs;
70 break;
71#endif
62#ifdef CONFIG_DRM_AMDGPU_CIK 72#ifdef CONFIG_DRM_AMDGPU_CIK
63 case CHIP_BONAIRE: 73 case CHIP_BONAIRE:
64 case CHIP_HAWAII: 74 case CHIP_HAWAII:
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index c905470d7e81..fee76b8a536f 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1117,6 +1117,7 @@ static u32 si_get_xclk(struct amdgpu_device *adev)
1117 1117
1118 return reference_clock; 1118 return reference_clock;
1119} 1119}
1120
1120//xxx:not implemented 1121//xxx:not implemented
1121static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1122static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1122{ 1123{
@@ -1850,14 +1851,13 @@ static const struct amdgpu_ip_block_version verde_ip_blocks[] =
1850 .rev = 0, 1851 .rev = 0,
1851 .funcs = &si_ih_ip_funcs, 1852 .funcs = &si_ih_ip_funcs,
1852 }, 1853 },
1853/* { 1854 {
1854 .type = AMD_IP_BLOCK_TYPE_SMC, 1855 .type = AMD_IP_BLOCK_TYPE_SMC,
1855 .major = 6, 1856 .major = 6,
1856 .minor = 0, 1857 .minor = 0,
1857 .rev = 0, 1858 .rev = 0,
1858 .funcs = &si_null_ip_funcs, 1859 .funcs = &amdgpu_pp_ip_funcs,
1859 }, 1860 },
1860 */
1861 { 1861 {
1862 .type = AMD_IP_BLOCK_TYPE_DCE, 1862 .type = AMD_IP_BLOCK_TYPE_DCE,
1863 .major = 6, 1863 .major = 6,
@@ -1925,7 +1925,7 @@ static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
1925 .major = 6, 1925 .major = 6,
1926 .minor = 0, 1926 .minor = 0,
1927 .rev = 0, 1927 .rev = 0,
1928 .funcs = &si_null_ip_funcs, 1928 .funcs = &amdgpu_pp_ip_funcs,
1929 }, 1929 },
1930 { 1930 {
1931 .type = AMD_IP_BLOCK_TYPE_GFX, 1931 .type = AMD_IP_BLOCK_TYPE_GFX,