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authorArnd Bergmann <arnd@arndb.de>2016-05-09 10:29:36 -0400
committerArnd Bergmann <arnd@arndb.de>2016-05-09 10:29:36 -0400
commit182e0842b0109aa934f1fe76b96d3a79efec3912 (patch)
tree556e4ea796c6ef7bcb04448997a374dd072ff4bb
parentb7dcc6d01ffcaab262d52af0b91110463ee045f5 (diff)
parent601bac7638fa693204dc70035d2651474704967c (diff)
Merge tag 'v4.6-next-soc' of https://github.com/mbgg/linux-mediatek into next/drivers
Merge "ARM: mediatek soc updates for v4.7" from Matthias Brugger: - re-organize pmic wrapper code for easier and cleaner addiont of new SoCs and pmic wrappers - add support for pmic wrapper mt6323 - add support for SoC mt2701 - enable gpt6 arch timer on mt7623 * tag 'v4.6-next-soc' of https://github.com/mbgg/linux-mediatek: ARM: mediatek: enable gpt6 on boot up to make arch timer work on mt7623 soc: mediatek: PMIC wrap: add MT2701/7623 support soc: mediatek: PMIC wrap: add mt6323 slave support soc: mediatek: PMIC wrap: add a slave specific struct soc: mediatek: PMIC wrap: remove pwrap_is_mt8135() and pwrap_is_mt8173() soc: mediatek: PMIC wrap: move wdt_src into the pmic_wrapper_type struct soc: mediatek: PMIC wrap: SPI_WRITE needs a different bitmask for MT2701/7623 soc: mediatek: PMIC wrap: WRAP_INT_EN needs a different bitmask for MT2701/7623 soc: mediatek: PMIC wrap: split SoC specific init into callback soc: mediatek: PMIC wrap: add wrapper callbacks for init_reg_clock soc: mediatek: PMIC wrap: don't duplicate the wrapper data
Diffstat
-rw-r--r--arch/arm/mach-mediatek/mediatek.c1
-rw-r--r--drivers/soc/mediatek/mtk-pmic-wrap.c544
2 files changed, 414 insertions, 131 deletions
diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
index 9c2e38d30f47..a6e3c98b95ed 100644
--- a/arch/arm/mach-mediatek/mediatek.c
+++ b/arch/arm/mach-mediatek/mediatek.c
@@ -29,6 +29,7 @@ static void __init mediatek_timer_init(void)
29 void __iomem *gpt_base; 29 void __iomem *gpt_base;
30 30
31 if (of_machine_is_compatible("mediatek,mt6589") || 31 if (of_machine_is_compatible("mediatek,mt6589") ||
32 of_machine_is_compatible("mediatek,mt7623") ||
32 of_machine_is_compatible("mediatek,mt8135") || 33 of_machine_is_compatible("mediatek,mt8135") ||
33 of_machine_is_compatible("mediatek,mt8127")) { 34 of_machine_is_compatible("mediatek,mt8127")) {
34 /* turn on GPT6 which ungates arch timer clocks */ 35 /* turn on GPT6 which ungates arch timer clocks */
diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
index 0d9b19a78d27..3c3e56df526e 100644
--- a/drivers/soc/mediatek/mtk-pmic-wrap.c
+++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
@@ -52,6 +52,7 @@
52#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a 52#define PWRAP_DEW_WRITE_TEST_VAL 0xa55a
53 53
54/* macro for manual command */ 54/* macro for manual command */
55#define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
55#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13) 56#define PWRAP_MAN_CMD_SPI_WRITE (1 << 13)
56#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8) 57#define PWRAP_MAN_CMD_OP_CSH (0x0 << 8)
57#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8) 58#define PWRAP_MAN_CMD_OP_CSL (0x1 << 8)
@@ -69,33 +70,75 @@
69 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \ 70 PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
70 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE) 71 PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
71 72
72/* macro for slave device wrapper registers */ 73/* defines for slave device wrapper registers */
73#define PWRAP_DEW_BASE 0xbc00 74enum dew_regs {
74#define PWRAP_DEW_EVENT_OUT_EN (PWRAP_DEW_BASE + 0x0) 75 PWRAP_DEW_BASE,
75#define PWRAP_DEW_DIO_EN (PWRAP_DEW_BASE + 0x2) 76 PWRAP_DEW_DIO_EN,
76#define PWRAP_DEW_EVENT_SRC_EN (PWRAP_DEW_BASE + 0x4) 77 PWRAP_DEW_READ_TEST,
77#define PWRAP_DEW_EVENT_SRC (PWRAP_DEW_BASE + 0x6) 78 PWRAP_DEW_WRITE_TEST,
78#define PWRAP_DEW_EVENT_FLAG (PWRAP_DEW_BASE + 0x8) 79 PWRAP_DEW_CRC_EN,
79#define PWRAP_DEW_READ_TEST (PWRAP_DEW_BASE + 0xa) 80 PWRAP_DEW_CRC_VAL,
80#define PWRAP_DEW_WRITE_TEST (PWRAP_DEW_BASE + 0xc) 81 PWRAP_DEW_MON_GRP_SEL,
81#define PWRAP_DEW_CRC_EN (PWRAP_DEW_BASE + 0xe) 82 PWRAP_DEW_CIPHER_KEY_SEL,
82#define PWRAP_DEW_CRC_VAL (PWRAP_DEW_BASE + 0x10) 83 PWRAP_DEW_CIPHER_IV_SEL,
83#define PWRAP_DEW_MON_GRP_SEL (PWRAP_DEW_BASE + 0x12) 84 PWRAP_DEW_CIPHER_RDY,
84#define PWRAP_DEW_MON_FLAG_SEL (PWRAP_DEW_BASE + 0x14) 85 PWRAP_DEW_CIPHER_MODE,
85#define PWRAP_DEW_EVENT_TEST (PWRAP_DEW_BASE + 0x16) 86 PWRAP_DEW_CIPHER_SWRST,
86#define PWRAP_DEW_CIPHER_KEY_SEL (PWRAP_DEW_BASE + 0x18) 87
87#define PWRAP_DEW_CIPHER_IV_SEL (PWRAP_DEW_BASE + 0x1a) 88 /* MT6397 only regs */
88#define PWRAP_DEW_CIPHER_LOAD (PWRAP_DEW_BASE + 0x1c) 89 PWRAP_DEW_EVENT_OUT_EN,
89#define PWRAP_DEW_CIPHER_START (PWRAP_DEW_BASE + 0x1e) 90 PWRAP_DEW_EVENT_SRC_EN,
90#define PWRAP_DEW_CIPHER_RDY (PWRAP_DEW_BASE + 0x20) 91 PWRAP_DEW_EVENT_SRC,
91#define PWRAP_DEW_CIPHER_MODE (PWRAP_DEW_BASE + 0x22) 92 PWRAP_DEW_EVENT_FLAG,
92#define PWRAP_DEW_CIPHER_SWRST (PWRAP_DEW_BASE + 0x24) 93 PWRAP_DEW_MON_FLAG_SEL,
93#define PWRAP_MT8173_DEW_CIPHER_IV0 (PWRAP_DEW_BASE + 0x26) 94 PWRAP_DEW_EVENT_TEST,
94#define PWRAP_MT8173_DEW_CIPHER_IV1 (PWRAP_DEW_BASE + 0x28) 95 PWRAP_DEW_CIPHER_LOAD,
95#define PWRAP_MT8173_DEW_CIPHER_IV2 (PWRAP_DEW_BASE + 0x2a) 96 PWRAP_DEW_CIPHER_START,
96#define PWRAP_MT8173_DEW_CIPHER_IV3 (PWRAP_DEW_BASE + 0x2c) 97
97#define PWRAP_MT8173_DEW_CIPHER_IV4 (PWRAP_DEW_BASE + 0x2e) 98 /* MT6323 only regs */
98#define PWRAP_MT8173_DEW_CIPHER_IV5 (PWRAP_DEW_BASE + 0x30) 99 PWRAP_DEW_CIPHER_EN,
100 PWRAP_DEW_RDDMY_NO,
101};
102
103static const u32 mt6323_regs[] = {
104 [PWRAP_DEW_BASE] = 0x0000,
105 [PWRAP_DEW_DIO_EN] = 0x018a,
106 [PWRAP_DEW_READ_TEST] = 0x018c,
107 [PWRAP_DEW_WRITE_TEST] = 0x018e,
108 [PWRAP_DEW_CRC_EN] = 0x0192,
109 [PWRAP_DEW_CRC_VAL] = 0x0194,
110 [PWRAP_DEW_MON_GRP_SEL] = 0x0196,
111 [PWRAP_DEW_CIPHER_KEY_SEL] = 0x0198,
112 [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
113 [PWRAP_DEW_CIPHER_EN] = 0x019c,
114 [PWRAP_DEW_CIPHER_RDY] = 0x019e,
115 [PWRAP_DEW_CIPHER_MODE] = 0x01a0,
116 [PWRAP_DEW_CIPHER_SWRST] = 0x01a2,
117 [PWRAP_DEW_RDDMY_NO] = 0x01a4,
118};
119
120static const u32 mt6397_regs[] = {
121 [PWRAP_DEW_BASE] = 0xbc00,
122 [PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
123 [PWRAP_DEW_DIO_EN] = 0xbc02,
124 [PWRAP_DEW_EVENT_SRC_EN] = 0xbc04,
125 [PWRAP_DEW_EVENT_SRC] = 0xbc06,
126 [PWRAP_DEW_EVENT_FLAG] = 0xbc08,
127 [PWRAP_DEW_READ_TEST] = 0xbc0a,
128 [PWRAP_DEW_WRITE_TEST] = 0xbc0c,
129 [PWRAP_DEW_CRC_EN] = 0xbc0e,
130 [PWRAP_DEW_CRC_VAL] = 0xbc10,
131 [PWRAP_DEW_MON_GRP_SEL] = 0xbc12,
132 [PWRAP_DEW_MON_FLAG_SEL] = 0xbc14,
133 [PWRAP_DEW_EVENT_TEST] = 0xbc16,
134 [PWRAP_DEW_CIPHER_KEY_SEL] = 0xbc18,
135 [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
136 [PWRAP_DEW_CIPHER_LOAD] = 0xbc1c,
137 [PWRAP_DEW_CIPHER_START] = 0xbc1e,
138 [PWRAP_DEW_CIPHER_RDY] = 0xbc20,
139 [PWRAP_DEW_CIPHER_MODE] = 0xbc22,
140 [PWRAP_DEW_CIPHER_SWRST] = 0xbc24,
141};
99 142
100enum pwrap_regs { 143enum pwrap_regs {
101 PWRAP_MUX_SEL, 144 PWRAP_MUX_SEL,
@@ -158,6 +201,13 @@ enum pwrap_regs {
158 PWRAP_DCM_EN, 201 PWRAP_DCM_EN,
159 PWRAP_DCM_DBC_PRD, 202 PWRAP_DCM_DBC_PRD,
160 203
204 /* MT2701 only regs */
205 PWRAP_ADC_CMD_ADDR,
206 PWRAP_PWRAP_ADC_CMD,
207 PWRAP_ADC_RDY_ADDR,
208 PWRAP_ADC_RDATA_ADDR1,
209 PWRAP_ADC_RDATA_ADDR2,
210
161 /* MT8135 only regs */ 211 /* MT8135 only regs */
162 PWRAP_CSHEXT, 212 PWRAP_CSHEXT,
163 PWRAP_EVENT_IN_EN, 213 PWRAP_EVENT_IN_EN,
@@ -194,6 +244,92 @@ enum pwrap_regs {
194 PWRAP_CIPHER_EN, 244 PWRAP_CIPHER_EN,
195}; 245};
196 246
247static int mt2701_regs[] = {
248 [PWRAP_MUX_SEL] = 0x0,
249 [PWRAP_WRAP_EN] = 0x4,
250 [PWRAP_DIO_EN] = 0x8,
251 [PWRAP_SIDLY] = 0xc,
252 [PWRAP_RDDMY] = 0x18,
253 [PWRAP_SI_CK_CON] = 0x1c,
254 [PWRAP_CSHEXT_WRITE] = 0x20,
255 [PWRAP_CSHEXT_READ] = 0x24,
256 [PWRAP_CSLEXT_START] = 0x28,
257 [PWRAP_CSLEXT_END] = 0x2c,
258 [PWRAP_STAUPD_PRD] = 0x30,
259 [PWRAP_STAUPD_GRPEN] = 0x34,
260 [PWRAP_STAUPD_MAN_TRIG] = 0x38,
261 [PWRAP_STAUPD_STA] = 0x3c,
262 [PWRAP_WRAP_STA] = 0x44,
263 [PWRAP_HARB_INIT] = 0x48,
264 [PWRAP_HARB_HPRIO] = 0x4c,
265 [PWRAP_HIPRIO_ARB_EN] = 0x50,
266 [PWRAP_HARB_STA0] = 0x54,
267 [PWRAP_HARB_STA1] = 0x58,
268 [PWRAP_MAN_EN] = 0x5c,
269 [PWRAP_MAN_CMD] = 0x60,
270 [PWRAP_MAN_RDATA] = 0x64,
271 [PWRAP_MAN_VLDCLR] = 0x68,
272 [PWRAP_WACS0_EN] = 0x6c,
273 [PWRAP_INIT_DONE0] = 0x70,
274 [PWRAP_WACS0_CMD] = 0x74,
275 [PWRAP_WACS0_RDATA] = 0x78,
276 [PWRAP_WACS0_VLDCLR] = 0x7c,
277 [PWRAP_WACS1_EN] = 0x80,
278 [PWRAP_INIT_DONE1] = 0x84,
279 [PWRAP_WACS1_CMD] = 0x88,
280 [PWRAP_WACS1_RDATA] = 0x8c,
281 [PWRAP_WACS1_VLDCLR] = 0x90,
282 [PWRAP_WACS2_EN] = 0x94,
283 [PWRAP_INIT_DONE2] = 0x98,
284 [PWRAP_WACS2_CMD] = 0x9c,
285 [PWRAP_WACS2_RDATA] = 0xa0,
286 [PWRAP_WACS2_VLDCLR] = 0xa4,
287 [PWRAP_INT_EN] = 0xa8,
288 [PWRAP_INT_FLG_RAW] = 0xac,
289 [PWRAP_INT_FLG] = 0xb0,
290 [PWRAP_INT_CLR] = 0xb4,
291 [PWRAP_SIG_ADR] = 0xb8,
292 [PWRAP_SIG_MODE] = 0xbc,
293 [PWRAP_SIG_VALUE] = 0xc0,
294 [PWRAP_SIG_ERRVAL] = 0xc4,
295 [PWRAP_CRC_EN] = 0xc8,
296 [PWRAP_TIMER_EN] = 0xcc,
297 [PWRAP_TIMER_STA] = 0xd0,
298 [PWRAP_WDT_UNIT] = 0xd4,