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authorTom St Denis <tom.stdenis@amd.com>2016-03-28 08:21:52 -0400
committerAlex Deucher <alexander.deucher@amd.com>2016-05-04 20:30:06 -0400
commit16a7989ac62a4d491d44a295577a7e75b7e3b0bb (patch)
treeeddfbeec7e6ad3f51b271b4c31340d5286797b93
parenta72d5604ead32d282fefbc018ca63a3bf878e2c2 (diff)
drm/amd/amdgpu: Drop print_status callbacks.
First patch in series to move to user mode debug tools we're removing the print_status callbacks. These functions were unused at the moment anyway. Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c8
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c10
-rw-r--r--drivers/gpu/drm/amd/amdgpu/ci_dpm.c210
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c6
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_ih.c34
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik_sdma.c56
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_dpm.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cz_ih.c34
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v10_0.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v11_0.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/dce_v8_0.c12
-rw-r--r--drivers/gpu/drm/amd/amdgpu/fiji_dpm.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c253
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c182
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c113
-rw-r--r--drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c110
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_dpm.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/iceland_ih.c34
-rw-r--r--drivers/gpu/drm/amd/amdgpu/kv_dpm.c57
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c54
-rw-r--r--drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c56
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_dpm.c1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/tonga_ih.c34
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c112
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c115
-rw-r--r--drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c107
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v2_0.c70
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vce_v3_0.c68
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vi.c6
-rw-r--r--drivers/gpu/drm/amd/include/amd_shared.h2
-rw-r--r--drivers/gpu/drm/amd/powerplay/amd_powerplay.c5
31 files changed, 0 insertions, 1776 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index d6b0bff510aa..da764e193fb9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -463,13 +463,6 @@ static int acp_soft_reset(void *handle)
463 return 0; 463 return 0;
464} 464}
465 465
466static void acp_print_status(void *handle)
467{
468 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
469
470 dev_info(adev->dev, "ACP STATUS\n");
471}
472
473static int acp_set_clockgating_state(void *handle, 466static int acp_set_clockgating_state(void *handle,
474 enum amd_clockgating_state state) 467 enum amd_clockgating_state state)
475{ 468{
@@ -494,7 +487,6 @@ const struct amd_ip_funcs acp_ip_funcs = {
494 .is_idle = acp_is_idle, 487 .is_idle = acp_is_idle,
495 .wait_for_idle = acp_wait_for_idle, 488 .wait_for_idle = acp_wait_for_idle,
496 .soft_reset = acp_soft_reset, 489 .soft_reset = acp_soft_reset,
497 .print_status = acp_print_status,
498 .set_clockgating_state = acp_set_clockgating_state, 490 .set_clockgating_state = acp_set_clockgating_state,
499 .set_powergating_state = acp_set_powergating_state, 491 .set_powergating_state = acp_set_powergating_state,
500}; 492};
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
index f315995e931e..be565955bcc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
@@ -303,15 +303,6 @@ static int amdgpu_pp_soft_reset(void *handle)
303 return ret; 303 return ret;
304} 304}
305 305
306static void amdgpu_pp_print_status(void *handle)
307{
308 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
309
310 if (adev->powerplay.ip_funcs->print_status)
311 adev->powerplay.ip_funcs->print_status(
312 adev->powerplay.pp_handle);
313}
314
315const struct amd_ip_funcs amdgpu_pp_ip_funcs = { 306const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
316 .early_init = amdgpu_pp_early_init, 307 .early_init = amdgpu_pp_early_init,
317 .late_init = amdgpu_pp_late_init, 308 .late_init = amdgpu_pp_late_init,
@@ -324,7 +315,6 @@ const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
324 .is_idle = amdgpu_pp_is_idle, 315 .is_idle = amdgpu_pp_is_idle,
325 .wait_for_idle = amdgpu_pp_wait_for_idle, 316 .wait_for_idle = amdgpu_pp_wait_for_idle,
326 .soft_reset = amdgpu_pp_soft_reset, 317 .soft_reset = amdgpu_pp_soft_reset,
327 .print_status = amdgpu_pp_print_status,
328 .set_clockgating_state = amdgpu_pp_set_clockgating_state, 318 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
329 .set_powergating_state = amdgpu_pp_set_powergating_state, 319 .set_powergating_state = amdgpu_pp_set_powergating_state,
330}; 320};
diff --git a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
index 1f9109d3348b..90f83b21b38c 100644
--- a/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/ci_dpm.c
@@ -6309,215 +6309,6 @@ static int ci_dpm_wait_for_idle(void *handle)
6309 return 0; 6309 return 0;
6310} 6310}
6311 6311
6312static void ci_dpm_print_status(void *handle)
6313{
6314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6315
6316 dev_info(adev->dev, "CIK DPM registers\n");
6317 dev_info(adev->dev, " BIOS_SCRATCH_4=0x%08X\n",
6318 RREG32(mmBIOS_SCRATCH_4));
6319 dev_info(adev->dev, " MC_ARB_DRAM_TIMING=0x%08X\n",
6320 RREG32(mmMC_ARB_DRAM_TIMING));
6321 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2=0x%08X\n",
6322 RREG32(mmMC_ARB_DRAM_TIMING2));
6323 dev_info(adev->dev, " MC_ARB_BURST_TIME=0x%08X\n",
6324 RREG32(mmMC_ARB_BURST_TIME));
6325 dev_info(adev->dev, " MC_ARB_DRAM_TIMING_1=0x%08X\n",
6326 RREG32(mmMC_ARB_DRAM_TIMING_1));
6327 dev_info(adev->dev, " MC_ARB_DRAM_TIMING2_1=0x%08X\n",
6328 RREG32(mmMC_ARB_DRAM_TIMING2_1));
6329 dev_info(adev->dev, " MC_CG_CONFIG=0x%08X\n",
6330 RREG32(mmMC_CG_CONFIG));
6331 dev_info(adev->dev, " MC_ARB_CG=0x%08X\n",
6332 RREG32(mmMC_ARB_CG));
6333 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
6334 RREG32_DIDT(ixDIDT_SQ_CTRL0));
6335 dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n",
6336 RREG32_DIDT(ixDIDT_DB_CTRL0));
6337 dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n",
6338 RREG32_DIDT(ixDIDT_TD_CTRL0));
6339 dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n",
6340 RREG32_DIDT(ixDIDT_TCP_CTRL0));
6341 dev_info(adev->dev, " CG_THERMAL_INT=0x%08X\n",
6342 RREG32_SMC(ixCG_THERMAL_INT));
6343 dev_info(adev->dev, " CG_THERMAL_CTRL=0x%08X\n",
6344 RREG32_SMC(ixCG_THERMAL_CTRL));
6345 dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n",
6346 RREG32_SMC(ixGENERAL_PWRMGT));
6347 dev_info(adev->dev, " MC_SEQ_CNTL_3=0x%08X\n",
6348 RREG32(mmMC_SEQ_CNTL_3));
6349 dev_info(adev->dev, " LCAC_MC0_CNTL=0x%08X\n",
6350 RREG32_SMC(ixLCAC_MC0_CNTL));
6351 dev_info(adev->dev, " LCAC_MC1_CNTL=0x%08X\n",
6352 RREG32_SMC(ixLCAC_MC1_CNTL));
6353 dev_info(adev->dev, " LCAC_CPL_CNTL=0x%08X\n",
6354 RREG32_SMC(ixLCAC_CPL_CNTL));
6355 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n",
6356 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
6357 dev_info(adev->dev, " BIF_LNCNT_RESET=0x%08X\n",
6358 RREG32(mmBIF_LNCNT_RESET));
6359 dev_info(adev->dev, " FIRMWARE_FLAGS=0x%08X\n",
6360 RREG32_SMC(ixFIRMWARE_FLAGS));
6361 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL=0x%08X\n",
6362 RREG32_SMC(ixCG_SPLL_FUNC_CNTL));
6363 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n",
6364 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_2));
6365 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_3=0x%08X\n",
6366 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_3));
6367 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_4=0x%08X\n",
6368 RREG32_SMC(ixCG_SPLL_FUNC_CNTL_4));
6369 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM=0x%08X\n",
6370 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM));
6371 dev_info(adev->dev, " CG_SPLL_SPREAD_SPECTRUM_2=0x%08X\n",
6372 RREG32_SMC(ixCG_SPLL_SPREAD_SPECTRUM_2));
6373 dev_info(adev->dev, " DLL_CNTL=0x%08X\n",
6374 RREG32(mmDLL_CNTL));
6375 dev_info(adev->dev, " MCLK_PWRMGT_CNTL=0x%08X\n",
6376 RREG32(mmMCLK_PWRMGT_CNTL));
6377 dev_info(adev->dev, " MPLL_AD_FUNC_CNTL=0x%08X\n",
6378 RREG32(mmMPLL_AD_FUNC_CNTL));
6379 dev_info(adev->dev, " MPLL_DQ_FUNC_CNTL=0x%08X\n",
6380 RREG32(mmMPLL_DQ_FUNC_CNTL));
6381 dev_info(adev->dev, " MPLL_FUNC_CNTL=0x%08X\n",
6382 RREG32(mmMPLL_FUNC_CNTL));
6383 dev_info(adev->dev, " MPLL_FUNC_CNTL_1=0x%08X\n",
6384 RREG32(mmMPLL_FUNC_CNTL_1));
6385 dev_info(adev->dev, " MPLL_FUNC_CNTL_2=0x%08X\n",
6386 RREG32(mmMPLL_FUNC_CNTL_2));
6387 dev_info(adev->dev, " MPLL_SS1=0x%08X\n",
6388 RREG32(mmMPLL_SS1));
6389 dev_info(adev->dev, " MPLL_SS2=0x%08X\n",
6390 RREG32(mmMPLL_SS2));
6391 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL=0x%08X\n",
6392 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL));
6393 dev_info(adev->dev, " CG_DISPLAY_GAP_CNTL2=0x%08X\n",
6394 RREG32_SMC(ixCG_DISPLAY_GAP_CNTL2));
6395 dev_info(adev->dev, " CG_STATIC_SCREEN_PARAMETER=0x%08X\n",
6396 RREG32_SMC(ixCG_STATIC_SCREEN_PARAMETER));
6397 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n",
6398 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
6399 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_1=0x%08X\n",
6400 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_1));
6401 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_2=0x%08X\n",
6402 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_2));
6403 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_3=0x%08X\n",
6404 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_3));
6405 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_4=0x%08X\n",
6406 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_4));
6407 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_5=0x%08X\n",
6408 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_5));
6409 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_6=0x%08X\n",
6410 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_6));
6411 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_7=0x%08X\n",
6412 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_7));
6413 dev_info(adev->dev, " RCU_UC_EVENTS=0x%08X\n",
6414 RREG32_SMC(ixRCU_UC_EVENTS));
6415 dev_info(adev->dev, " DPM_TABLE_475=0x%08X\n",
6416 RREG32_SMC(ixDPM_TABLE_475));
6417 dev_info(adev->dev, " MC_SEQ_RAS_TIMING_LP=0x%08X\n",
6418 RREG32(mmMC_SEQ_RAS_TIMING_LP));
6419 dev_info(adev->dev, " MC_SEQ_RAS_TIMING=0x%08X\n",
6420 RREG32(mmMC_SEQ_RAS_TIMING));
6421 dev_info(adev->dev, " MC_SEQ_CAS_TIMING_LP=0x%08X\n",
6422 RREG32(mmMC_SEQ_CAS_TIMING_LP));
6423 dev_info(adev->dev, " MC_SEQ_CAS_TIMING=0x%08X\n",
6424 RREG32(mmMC_SEQ_CAS_TIMING));
6425 dev_info(adev->dev, " MC_SEQ_DLL_STBY_LP=0x%08X\n",
6426 RREG32(mmMC_SEQ_DLL_STBY_LP));
6427 dev_info(adev->dev, " MC_SEQ_DLL_STBY=0x%08X\n",
6428 RREG32(mmMC_SEQ_DLL_STBY));
6429 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0_LP=0x%08X\n",
6430 RREG32(mmMC_SEQ_G5PDX_CMD0_LP));
6431 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD0=0x%08X\n",
6432 RREG32(mmMC_SEQ_G5PDX_CMD0));
6433 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1_LP=0x%08X\n",
6434 RREG32(mmMC_SEQ_G5PDX_CMD1_LP));
6435 dev_info(adev->dev, " MC_SEQ_G5PDX_CMD1=0x%08X\n",
6436 RREG32(mmMC_SEQ_G5PDX_CMD1));
6437 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL_LP=0x%08X\n",
6438 RREG32(mmMC_SEQ_G5PDX_CTRL_LP));
6439 dev_info(adev->dev, " MC_SEQ_G5PDX_CTRL=0x%08X\n",
6440 RREG32(mmMC_SEQ_G5PDX_CTRL));
6441 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD_LP=0x%08X\n",
6442 RREG32(mmMC_SEQ_PMG_DVS_CMD_LP));
6443 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CMD=0x%08X\n",
6444 RREG32(mmMC_SEQ_PMG_DVS_CMD));
6445 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL_LP=0x%08X\n",
6446 RREG32(mmMC_SEQ_PMG_DVS_CTL_LP));
6447 dev_info(adev->dev, " MC_SEQ_PMG_DVS_CTL=0x%08X\n",
6448 RREG32(mmMC_SEQ_PMG_DVS_CTL));
6449 dev_info(adev->dev, " MC_SEQ_MISC_TIMING_LP=0x%08X\n",
6450 RREG32(mmMC_SEQ_MISC_TIMING_LP));
6451 dev_info(adev->dev, " MC_SEQ_MISC_TIMING=0x%08X\n",
6452 RREG32(mmMC_SEQ_MISC_TIMING));
6453 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2_LP=0x%08X\n",
6454 RREG32(mmMC_SEQ_MISC_TIMING2_LP));
6455 dev_info(adev->dev, " MC_SEQ_MISC_TIMING2=0x%08X\n",
6456 RREG32(mmMC_SEQ_MISC_TIMING2));
6457 dev_info(adev->dev, " MC_SEQ_PMG_CMD_EMRS_LP=0x%08X\n",
6458 RREG32(mmMC_SEQ_PMG_CMD_EMRS_LP));
6459 dev_info(adev->dev, " MC_PMG_CMD_EMRS=0x%08X\n",
6460 RREG32(mmMC_PMG_CMD_EMRS));
6461 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS_LP=0x%08X\n",
6462 RREG32(mmMC_SEQ_PMG_CMD_MRS_LP));
6463 dev_info(adev->dev, " MC_PMG_CMD_MRS=0x%08X\n",
6464 RREG32(mmMC_PMG_CMD_MRS));
6465 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS1_LP=0x%08X\n",
6466 RREG32(mmMC_SEQ_PMG_CMD_MRS1_LP));
6467 dev_info(adev->dev, " MC_PMG_CMD_MRS1=0x%08X\n",
6468 RREG32(mmMC_PMG_CMD_MRS1));
6469 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0_LP=0x%08X\n",
6470 RREG32(mmMC_SEQ_WR_CTL_D0_LP));
6471 dev_info(adev->dev, " MC_SEQ_WR_CTL_D0=0x%08X\n",
6472 RREG32(mmMC_SEQ_WR_CTL_D0));
6473 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1_LP=0x%08X\n",
6474 RREG32(mmMC_SEQ_WR_CTL_D1_LP));
6475 dev_info(adev->dev, " MC_SEQ_WR_CTL_D1=0x%08X\n",
6476 RREG32(mmMC_SEQ_WR_CTL_D1));
6477 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0_LP=0x%08X\n",
6478 RREG32(mmMC_SEQ_RD_CTL_D0_LP));
6479 dev_info(adev->dev, " MC_SEQ_RD_CTL_D0=0x%08X\n",
6480 RREG32(mmMC_SEQ_RD_CTL_D0));
6481 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1_LP=0x%08X\n",
6482 RREG32(mmMC_SEQ_RD_CTL_D1_LP));
6483 dev_info(adev->dev, " MC_SEQ_RD_CTL_D1=0x%08X\n",
6484 RREG32(mmMC_SEQ_RD_CTL_D1));
6485 dev_info(adev->dev, " MC_SEQ_PMG_TIMING_LP=0x%08X\n",
6486 RREG32(mmMC_SEQ_PMG_TIMING_LP));
6487 dev_info(adev->dev, " MC_SEQ_PMG_TIMING=0x%08X\n",
6488 RREG32(mmMC_SEQ_PMG_TIMING));
6489 dev_info(adev->dev, " MC_SEQ_PMG_CMD_MRS2_LP=0x%08X\n",
6490 RREG32(mmMC_SEQ_PMG_CMD_MRS2_LP));
6491 dev_info(adev->dev, " MC_PMG_CMD_MRS2=0x%08X\n",
6492 RREG32(mmMC_PMG_CMD_MRS2));
6493 dev_info(adev->dev, " MC_SEQ_WR_CTL_2_LP=0x%08X\n",
6494 RREG32(mmMC_SEQ_WR_CTL_2_LP));
6495 dev_info(adev->dev, " MC_SEQ_WR_CTL_2=0x%08X\n",
6496 RREG32(mmMC_SEQ_WR_CTL_2));
6497 dev_info(adev->dev, " PCIE_LC_SPEED_CNTL=0x%08X\n",
6498 RREG32_PCIE(ixPCIE_LC_SPEED_CNTL));
6499 dev_info(adev->dev, " PCIE_LC_LINK_WIDTH_CNTL=0x%08X\n",
6500 RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL));
6501 dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n",
6502 RREG32(mmSMC_IND_INDEX_0));
6503 dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n",
6504 RREG32(mmSMC_IND_DATA_0));
6505 dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n",
6506 RREG32(mmSMC_IND_ACCESS_CNTL));
6507 dev_info(adev->dev, " SMC_RESP_0=0x%08X\n",
6508 RREG32(mmSMC_RESP_0));
6509 dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n",
6510 RREG32(mmSMC_MESSAGE_0));
6511 dev_info(adev->dev, " SMC_SYSCON_RESET_CNTL=0x%08X\n",
6512 RREG32_SMC(ixSMC_SYSCON_RESET_CNTL));
6513 dev_info(adev->dev, " SMC_SYSCON_CLOCK_CNTL_0=0x%08X\n",
6514 RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0));
6515 dev_info(adev->dev, " SMC_SYSCON_MISC_CNTL=0x%08X\n",
6516 RREG32_SMC(ixSMC_SYSCON_MISC_CNTL));
6517 dev_info(adev->dev, " SMC_PC_C=0x%08X\n",
6518 RREG32_SMC(ixSMC_PC_C));
6519}
6520
6521static int ci_dpm_soft_reset(void *handle) 6312static int ci_dpm_soft_reset(void *handle)
6522{ 6313{
6523 return 0; 6314 return 0;
@@ -6625,7 +6416,6 @@ const struct amd_ip_funcs ci_dpm_ip_funcs = {
6625 .is_idle = ci_dpm_is_idle, 6416 .is_idle = ci_dpm_is_idle,
6626 .wait_for_idle = ci_dpm_wait_for_idle, 6417 .wait_for_idle = ci_dpm_wait_for_idle,
6627 .soft_reset = ci_dpm_soft_reset, 6418 .soft_reset = ci_dpm_soft_reset,
6628 .print_status = ci_dpm_print_status,
6629 .set_clockgating_state = ci_dpm_set_clockgating_state, 6419 .set_clockgating_state = ci_dpm_set_clockgating_state,
6630 .set_powergating_state = ci_dpm_set_powergating_state, 6420 .set_powergating_state = ci_dpm_set_powergating_state,
6631}; 6421};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 009598bc4df8..c6127d66de11 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -2214,11 +2214,6 @@ static int cik_common_wait_for_idle(void *handle)
2214 return 0; 2214 return 0;
2215} 2215}
2216 2216
2217static void cik_common_print_status(void *handle)
2218{
2219
2220}
2221
2222static int cik_common_soft_reset(void *handle) 2217static int cik_common_soft_reset(void *handle)
2223{ 2218{
2224 /* XXX hard reset?? */ 2219 /* XXX hard reset?? */
@@ -2249,7 +2244,6 @@ const struct amd_ip_funcs cik_common_ip_funcs = {
2249 .is_idle = cik_common_is_idle, 2244 .is_idle = cik_common_is_idle,
2250 .wait_for_idle = cik_common_wait_for_idle, 2245 .wait_for_idle = cik_common_wait_for_idle,
2251 .soft_reset = cik_common_soft_reset, 2246 .soft_reset = cik_common_soft_reset,
2252 .print_status = cik_common_print_status,
2253 .set_clockgating_state = cik_common_set_clockgating_state, 2247 .set_clockgating_state = cik_common_set_clockgating_state,
2254 .set_powergating_state = cik_common_set_powergating_state, 2248 .set_powergating_state = cik_common_set_powergating_state,
2255}; 2249};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index 30c9b3beeef9..f2f14fe26784 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -372,35 +372,6 @@ static int cik_ih_wait_for_idle(void *handle)
372 return -ETIMEDOUT; 372 return -ETIMEDOUT;
373} 373}
374 374
375static void cik_ih_print_status(void *handle)
376{
377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
378
379 dev_info(adev->dev, "CIK IH registers\n");
380 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
381 RREG32(mmSRBM_STATUS));
382 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
383 RREG32(mmSRBM_STATUS2));
384 dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
385 RREG32(mmINTERRUPT_CNTL));
386 dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
387 RREG32(mmINTERRUPT_CNTL2));
388 dev_info(adev->dev, " IH_CNTL=0x%08X\n",
389 RREG32(mmIH_CNTL));
390 dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
391 RREG32(mmIH_RB_CNTL));
392 dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
393 RREG32(mmIH_RB_BASE));
394 dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
395 RREG32(mmIH_RB_WPTR_ADDR_LO));
396 dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
397 RREG32(mmIH_RB_WPTR_ADDR_HI));
398 dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
399 RREG32(mmIH_RB_RPTR));
400 dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
401 RREG32(mmIH_RB_WPTR));
402}
403
404static int cik_ih_soft_reset(void *handle) 375static int cik_ih_soft_reset(void *handle)
405{ 376{
406 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -412,8 +383,6 @@ static int cik_ih_soft_reset(void *handle)
412 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 383 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK;
413 384
414 if (srbm_soft_reset) { 385 if (srbm_soft_reset) {
415 cik_ih_print_status((void *)adev);
416
417 tmp = RREG32(mmSRBM_SOFT_RESET); 386 tmp = RREG32(mmSRBM_SOFT_RESET);
418 tmp |= srbm_soft_reset; 387 tmp |= srbm_soft_reset;
419 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 388 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -428,8 +397,6 @@ static int cik_ih_soft_reset(void *handle)
428 397
429 /* Wait a little for things to settle down */ 398 /* Wait a little for things to settle down */
430 udelay(50); 399 udelay(50);
431
432 cik_ih_print_status((void *)adev);
433 } 400 }
434 401
435 return 0; 402 return 0;
@@ -459,7 +426,6 @@ const struct amd_ip_funcs cik_ih_ip_funcs = {
459 .is_idle = cik_ih_is_idle, 426 .is_idle = cik_ih_is_idle,
460 .wait_for_idle = cik_ih_wait_for_idle, 427 .wait_for_idle = cik_ih_wait_for_idle,
461 .soft_reset = cik_ih_soft_reset, 428 .soft_reset = cik_ih_soft_reset,
462 .print_status = cik_ih_print_status,
463 .set_clockgating_state = cik_ih_set_clockgating_state, 429 .set_clockgating_state = cik_ih_set_clockgating_state,
464 .set_powergating_state = cik_ih_set_powergating_state, 430 .set_powergating_state = cik_ih_set_powergating_state,
465}; 431};
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 3edf26acd65b..b7ed9d376001 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1064,57 +1064,6 @@ static int cik_sdma_wait_for_idle(void *handle)
1064 return -ETIMEDOUT; 1064 return -ETIMEDOUT;
1065} 1065}
1066 1066
1067static void cik_sdma_print_status(void *handle)
1068{
1069 int i, j;
1070 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071
1072 dev_info(adev->dev, "CIK SDMA registers\n");
1073 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1074 RREG32(mmSRBM_STATUS2));
1075 for (i = 0; i < adev->sdma.num_instances; i++) {
1076 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1077 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1078 dev_info(adev->dev, " SDMA%d_ME_CNTL=0x%08X\n",
1079 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1080 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1081 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1082 dev_info(adev->dev, " SDMA%d_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
1083 i, RREG32(mmSDMA0_SEM_INCOMPLETE_TIMER_CNTL + sdma_offsets[i]));
1084 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1085 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1086 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1087 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1088 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1089 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1090 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1091 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1092 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1093 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1095 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1097 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1098 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1099 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1100 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1101 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1102 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
1103 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
1104 mutex_lock(&adev->srbm_mutex);
1105 for (j = 0; j < 16; j++) {
1106 cik_srbm_select(adev, 0, 0, 0, j);
1107 dev_info(adev->dev, " VM %d:\n", j);
1108 dev_info(adev->dev, " SDMA0_GFX_VIRTUAL_ADDR=0x%08X\n",
1109 RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1110 dev_info(adev->dev, " SDMA0_GFX_APE1_CNTL=0x%08X\n",
1111 RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1112 }
1113 cik_srbm_select(adev, 0, 0, 0, 0);
1114 mutex_unlock(&adev->srbm_mutex);
1115 }
1116}
1117
1118static int cik_sdma_soft_reset(void *handle) 1067static int cik_sdma_soft_reset(void *handle)
1119{ 1068{
1120 u32 srbm_soft_reset = 0; 1069 u32 srbm_soft_reset = 0;
@@ -1137,8 +1086,6 @@ static int cik_sdma_soft_reset(void *handle)
1137 } 1086 }
1138 1087
1139 if (srbm_soft_reset) { 1088 if (srbm_soft_reset) {
1140 cik_sdma_print_status((void *)adev);
1141
1142 tmp = RREG32(mmSRBM_SOFT_RESET); 1089 tmp = RREG32(mmSRBM_SOFT_RESET);
1143 tmp |= srbm_soft_reset; 1090 tmp |= srbm_soft_reset;
1144 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1091 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1153,8 +1100,6 @@ static int cik_sdma_soft_reset(void *handle)
1153 1100
1154 /* Wait a little for things to settle down */ 1101 /* Wait a little for things to settle down */
1155 udelay(50); 1102 udelay(50);
1156
1157 cik_sdma_print_status((void *)adev);
1158 } 1103 }
1159 1104
1160 return 0; 1105 return 0;
@@ -1289,7 +1234,6 @@ const struct amd_ip_funcs cik_sdma_ip_funcs = {
1289 .is_idle = cik_sdma_is_idle, 1234 .is_idle = cik_sdma_is_idle,
1290 .wait_for_idle = cik_sdma_wait_for_idle, 1235 .wait_for_idle = cik_sdma_wait_for_idle,
1291 .soft_reset = cik_sdma_soft_reset, 1236 .soft_reset = cik_sdma_soft_reset,
1292 .print_status = cik_sdma_print_status,
1293 .set_clockgating_state = cik_sdma_set_clockgating_state, 1237 .set_clockgating_state = cik_sdma_set_clockgating_state,
1294 .set_powergating_state = cik_sdma_set_powergating_state, 1238 .set_powergating_state = cik_sdma_set_powergating_state,
1295}; 1239};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
index e7ef2261ff4a..bf1847b28d9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_dpm.c
@@ -2241,7 +2241,6 @@ const struct amd_ip_funcs cz_dpm_ip_funcs = {
2241 .is_idle = NULL, 2241 .is_idle = NULL,
2242 .wait_for_idle = NULL, 2242 .wait_for_idle = NULL,
2243 .soft_reset = NULL, 2243 .soft_reset = NULL,
2244 .print_status = NULL,
2245 .set_clockgating_state = cz_dpm_set_clockgating_state, 2244 .set_clockgating_state = cz_dpm_set_clockgating_state,
2246 .set_powergating_state = cz_dpm_set_powergating_state, 2245 .set_powergating_state = cz_dpm_set_powergating_state,
2247}; 2246};
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index c79638f8e732..23bd9122b15d 100644
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -351,35 +351,6 @@ static int cz_ih_wait_for_idle(void *handle)
351 return -ETIMEDOUT; 351 return -ETIMEDOUT;
352} 352}
353 353
354static void cz_ih_print_status(void *handle)
355{
356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
357
358 dev_info(adev->dev, "CZ IH registers\n");
359 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
360 RREG32(mmSRBM_STATUS));
361 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
362 RREG32(mmSRBM_STATUS2));
363 dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
364 RREG32(mmINTERRUPT_CNTL));
365 dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
366 RREG32(mmINTERRUPT_CNTL2));
367 dev_info(adev->dev, " IH_CNTL=0x%08X\n",
368 RREG32(mmIH_CNTL));
369 dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
370 RREG32(mmIH_RB_CNTL));
371 dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
372 RREG32(mmIH_RB_BASE));
373 dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
374 RREG32(mmIH_RB_WPTR_ADDR_LO));
375 dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
376 RREG32(mmIH_RB_WPTR_ADDR_HI));
377 dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
378 RREG32(mmIH_RB_RPTR));
379 dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
380 RREG32(mmIH_RB_WPTR));
381}
382
383static int cz_ih_soft_reset(void *handle) 354static int cz_ih_soft_reset(void *handle)
384{ 355{
385 u32 srbm_soft_reset = 0; 356 u32 srbm_soft_reset = 0;
@@ -391,8 +362,6 @@ static int cz_ih_soft_reset(void *handle)
391 SOFT_RESET_IH, 1); 362 SOFT_RESET_IH, 1);
392 363
393 if (srbm_soft_reset) { 364 if (srbm_soft_reset) {
394 cz_ih_print_status((void *)adev);
395
396 tmp = RREG32(mmSRBM_SOFT_RESET); 365 tmp = RREG32(mmSRBM_SOFT_RESET);
397 tmp |= srbm_soft_reset; 366 tmp |= srbm_soft_reset;
398 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 367 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -407,8 +376,6 @@ static int cz_ih_soft_reset(void *handle)
407 376
408 /* Wait a little for things to settle down */ 377 /* Wait a little for things to settle down */
409 udelay(50); 378 udelay(50);
410
411 cz_ih_print_status((void *)adev);
412 } 379 }
413 380
414 return 0; 381 return 0;
@@ -440,7 +407,6 @@ const struct amd_ip_funcs cz_ih_ip_funcs = {
440 .is_idle = cz_ih_is_idle, 407 .is_idle = cz_ih_is_idle,
441 .wait_for_idle = cz_ih_wait_for_idle, 408 .wait_for_idle = cz_ih_wait_for_idle,
442 .soft_reset = cz_ih_soft_reset, 409 .soft_reset = cz_ih_soft_reset,
443 .print_status = cz_ih_print_status,
444 .set_clockgating_state = cz_ih_set_clockgating_state, 410 .set_clockgating_state = cz_ih_set_clockgating_state,
445 .set_powergating_state = cz_ih_set_powergating_state, 411 .set_powergating_state = cz_ih_set_powergating_state,
446}; 412};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 6de2ce535e37..f7f67f385b04 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -3130,14 +3130,6 @@ static int dce_v10_0_wait_for_idle(void *handle)
3130 return 0; 3130 return 0;
3131} 3131}
3132 3132
3133static void dce_v10_0_print_status(void *handle)
3134{
3135 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3136
3137 dev_info(adev->dev, "DCE 10.x registers\n");
3138 /* XXX todo */
3139}
3140
3141static int dce_v10_0_soft_reset(void *handle) 3133static int dce_v10_0_soft_reset(void *handle)
3142{ 3134{
3143 u32 srbm_soft_reset = 0, tmp; 3135 u32 srbm_soft_reset = 0, tmp;
@@ -3147,8 +3139,6 @@ static int dce_v10_0_soft_reset(void *handle)
3147 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3139 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3148 3140
3149 if (srbm_soft_reset) { 3141 if (srbm_soft_reset) {
3150 dce_v10_0_print_status((void *)adev);
3151
3152 tmp = RREG32(mmSRBM_SOFT_RESET); 3142 tmp = RREG32(mmSRBM_SOFT_RESET);
3153 tmp |= srbm_soft_reset; 3143 tmp |= srbm_soft_reset;
3154 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3144 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -3163,7 +3153,6 @@ static int dce_v10_0_soft_reset(void *handle)
3163 3153
3164 /* Wait a little for things to settle down */ 3154 /* Wait a little for things to settle down */
3165 udelay(50); 3155 udelay(50);
3166 dce_v10_0_print_status((void *)adev);
3167 } 3156 }
3168 return 0; 3157 return 0;
3169} 3158}
@@ -3512,7 +3501,6 @@ const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3512 .is_idle = dce_v10_0_is_idle, 3501 .is_idle = dce_v10_0_is_idle,
3513 .wait_for_idle = dce_v10_0_wait_for_idle, 3502 .wait_for_idle = dce_v10_0_wait_for_idle,
3514 .soft_reset = dce_v10_0_soft_reset, 3503 .soft_reset = dce_v10_0_soft_reset,
3515 .print_status = dce_v10_0_print_status,
3516 .set_clockgating_state = dce_v10_0_set_clockgating_state, 3504 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3517 .set_powergating_state = dce_v10_0_set_powergating_state, 3505 .set_powergating_state = dce_v10_0_set_powergating_state,
3518}; 3506};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index d28873c5f5b3..e4f3dc791030 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -3193,14 +3193,6 @@ static int dce_v11_0_wait_for_idle(void *handle)
3193 return 0; 3193 return 0;
3194} 3194}
3195 3195
3196static void dce_v11_0_print_status(void *handle)
3197{
3198 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3199
3200 dev_info(adev->dev, "DCE 10.x registers\n");
3201 /* XXX todo */
3202}
3203
3204static int dce_v11_0_soft_reset(void *handle) 3196static int dce_v11_0_soft_reset(void *handle)
3205{ 3197{
3206 u32 srbm_soft_reset = 0, tmp; 3198 u32 srbm_soft_reset = 0, tmp;
@@ -3210,8 +3202,6 @@ static int dce_v11_0_soft_reset(void *handle)
3210 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3202 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3211 3203
3212 if (srbm_soft_reset) { 3204 if (srbm_soft_reset) {
3213 dce_v11_0_print_status((void *)adev);
3214
3215 tmp = RREG32(mmSRBM_SOFT_RESET); 3205 tmp = RREG32(mmSRBM_SOFT_RESET);
3216 tmp |= srbm_soft_reset; 3206 tmp |= srbm_soft_reset;
3217 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3207 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -3226,7 +3216,6 @@ static int dce_v11_0_soft_reset(void *handle)
3226 3216
3227 /* Wait a little for things to settle down */ 3217 /* Wait a little for things to settle down */
3228 udelay(50); 3218 udelay(50);
3229 dce_v11_0_print_status((void *)adev);
3230 } 3219 }
3231 return 0; 3220 return 0;
3232} 3221}
@@ -3575,7 +3564,6 @@ const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3575 .is_idle = dce_v11_0_is_idle, 3564 .is_idle = dce_v11_0_is_idle,
3576 .wait_for_idle = dce_v11_0_wait_for_idle, 3565 .wait_for_idle = dce_v11_0_wait_for_idle,
3577 .soft_reset = dce_v11_0_soft_reset, 3566 .soft_reset = dce_v11_0_soft_reset,
3578 .print_status = dce_v11_0_print_status,
3579 .set_clockgating_state = dce_v11_0_set_clockgating_state, 3567 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3580 .set_powergating_state = dce_v11_0_set_powergating_state, 3568 .set_powergating_state = dce_v11_0_set_powergating_state,
3581}; 3569};
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index e56b55d8c280..429e98affba6 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -3038,14 +3038,6 @@ static int dce_v8_0_wait_for_idle(void *handle)
3038 return 0; 3038 return 0;
3039} 3039}
3040 3040
3041static void dce_v8_0_print_status(void *handle)
3042{
3043 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3044
3045 dev_info(adev->dev, "DCE 8.x registers\n");
3046 /* XXX todo */
3047}
3048
3049static int dce_v8_0_soft_reset(void *handle) 3041static int dce_v8_0_soft_reset(void *handle)
3050{ 3042{
3051 u32 srbm_soft_reset = 0, tmp; 3043 u32 srbm_soft_reset = 0, tmp;
@@ -3055,8 +3047,6 @@ static int dce_v8_0_soft_reset(void *handle)
3055 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 3047 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3056 3048
3057 if (srbm_soft_reset) { 3049 if (srbm_soft_reset) {
3058 dce_v8_0_print_status((void *)adev);
3059
3060 tmp = RREG32(mmSRBM_SOFT_RESET); 3050 tmp = RREG32(mmSRBM_SOFT_RESET);
3061 tmp |= srbm_soft_reset; 3051 tmp |= srbm_soft_reset;
3062 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 3052 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -3071,7 +3061,6 @@ static int dce_v8_0_soft_reset(void *handle)
3071 3061
3072 /* Wait a little for things to settle down */ 3062 /* Wait a little for things to settle down */
3073 udelay(50); 3063 udelay(50);
3074 dce_v8_0_print_status((void *)adev);
3075 } 3064 }
3076 return 0; 3065 return 0;
3077} 3066}
@@ -3442,7 +3431,6 @@ const struct amd_ip_funcs dce_v8_0_ip_funcs = {
3442 .is_idle = dce_v8_0_is_idle, 3431 .is_idle = dce_v8_0_is_idle,
3443 .wait_for_idle = dce_v8_0_wait_for_idle, 3432 .wait_for_idle = dce_v8_0_wait_for_idle,
3444 .soft_reset = dce_v8_0_soft_reset, 3433 .soft_reset = dce_v8_0_soft_reset,
3445 .print_status = dce_v8_0_print_status,
3446 .set_clockgating_state = dce_v8_0_set_clockgating_state, 3434 .set_clockgating_state = dce_v8_0_set_clockgating_state,
3447 .set_powergating_state = dce_v8_0_set_powergating_state, 3435 .set_powergating_state = dce_v8_0_set_powergating_state,
3448}; 3436};
diff --git a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
index 4b0e45a27129..6d133450d3cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/fiji_dpm.c
@@ -154,7 +154,6 @@ const struct amd_ip_funcs fiji_dpm_ip_funcs = {
154 .is_idle = NULL, 154 .is_idle = NULL,
155 .wait_for_idle = NULL, 155 .wait_for_idle = NULL,
156 .soft_reset = NULL, 156 .soft_reset = NULL,
157 .print_status = NULL,
158 .set_clockgating_state = fiji_dpm_set_clockgating_state, 157 .set_clockgating_state = fiji_dpm_set_clockgating_state,
159 .set_powergating_state = fiji_dpm_set_powergating_state, 158 .set_powergating_state = fiji_dpm_set_powergating_state,
160}; 159};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 86657e3e06c3..6686c9c3005d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -4572,256 +4572,6 @@ static int gfx_v7_0_wait_for_idle(void *handle)
4572 return -ETIMEDOUT; 4572 return -ETIMEDOUT;
4573} 4573}
4574 4574
4575static void gfx_v7_0_print_status(void *handle)
4576{
4577 int i;
4578 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4579
4580 dev_info(adev->dev, "GFX 7.x registers\n");
4581 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
4582 RREG32(mmGRBM_STATUS));
4583 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
4584 RREG32(mmGRBM_STATUS2));
4585 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4586 RREG32(mmGRBM_STATUS_SE0));
4587 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4588 RREG32(mmGRBM_STATUS_SE1));
4589 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4590 RREG32(mmGRBM_STATUS_SE2));
4591 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4592 RREG32(mmGRBM_STATUS_SE3));
4593 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4594 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4595 RREG32(mmCP_STALLED_STAT1));
4596 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4597 RREG32(mmCP_STALLED_STAT2));
4598 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4599 RREG32(mmCP_STALLED_STAT3));
4600 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4601 RREG32(mmCP_CPF_BUSY_STAT));
4602 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4603 RREG32(mmCP_CPF_STALLED_STAT1));
4604 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4605 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4606 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4607 RREG32(mmCP_CPC_STALLED_STAT1));
4608 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4609
4610 for (i = 0; i < 32; i++) {
4611 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
4612 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4613 }
4614 for (i = 0; i < 16; i++) {
4615 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
4616 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4617 }
4618 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4619 dev_info(adev->dev, " se: %d\n", i);
4620 gfx_v7_0_select_se_sh(adev, i, 0xffffffff);
4621 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
4622 RREG32(mmPA_SC_RASTER_CONFIG));
4623 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
4624 RREG32(mmPA_SC_RASTER_CONFIG_1));
4625 }
4626 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4627
4628 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
4629 RREG32(mmGB_ADDR_CONFIG));
4630 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
4631 RREG32(mmHDP_ADDR_CONFIG));
4632 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
4633 RREG32(mmDMIF_ADDR_CALC));
4634
4635 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
4636 RREG32(mmCP_MEQ_THRESHOLDS));
4637 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
4638 RREG32(mmSX_DEBUG_1));
4639 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
4640 RREG32(mmTA_CNTL_AUX));
4641 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
4642 RREG32(mmSPI_CONFIG_CNTL));
4643 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
4644 RREG32(mmSQ_CONFIG));
4645 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
4646 RREG32(mmDB_DEBUG));
4647 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
4648 RREG32(mmDB_DEBUG2));
4649 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
4650 RREG32(mmDB_DEBUG3));
4651 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
4652 RREG32(mmCB_HW_CONTROL));
4653 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
4654 RREG32(mmSPI_CONFIG_CNTL_1));
4655 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
4656 RREG32(mmPA_SC_FIFO_SIZE));
4657 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
4658 RREG32(mmVGT_NUM_INSTANCES));
4659 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
4660 RREG32(mmCP_PERFMON_CNTL));
4661 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4662 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4663 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
4664 RREG32(mmVGT_CACHE_INVALIDATION));
4665 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
4666 RREG32(mmVGT_GS_VERTEX_REUSE));
4667 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4668 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4669 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
4670 RREG32(mmPA_CL_ENHANCE));
4671 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
4672 RREG32(mmPA_SC_ENHANCE));
4673
4674 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
4675 RREG32(mmCP_ME_CNTL));
4676 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
4677 RREG32(mmCP_MAX_CONTEXT));
4678 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
4679 RREG32(mmCP_ENDIAN_SWAP));
4680 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
4681 RREG32(mmCP_DEVICE_ID));
4682
4683 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4684 RREG32(mmCP_SEM_WAIT_TIMER));
4685 if (adev->asic_type != CHIP_HAWAII)
4686 dev_info(adev->dev, " CP_SEM_INCOMPLETE_TIMER_CNTL=0x%08X\n",
4687 RREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL));
4688
4689 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4690 RREG32(mmCP_RB_WPTR_DELAY));
4691 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4692 RREG32(mmCP_RB_VMID));
4693 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4694 RREG32(mmCP_RB0_CNTL));
4695 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4696 RREG32(mmCP_RB0_WPTR));
4697 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4698 RREG32(mmCP_RB0_RPTR_ADDR));
4699 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4700 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4701 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4702 RREG32(mmCP_RB0_CNTL));
4703 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4704 RREG32(mmCP_RB0_BASE));
4705 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4706 RREG32(mmCP_RB0_BASE_HI));
4707 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4708 RREG32(mmCP_MEC_CNTL));
4709 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4710 RREG32(mmCP_CPF_DEBUG));
4711
4712 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4713 RREG32(mmSCRATCH_ADDR));
4714 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4715 RREG32(mmSCRATCH_UMSK));
4716
4717 /* init the pipes */
4718 mutex_lock(&adev->srbm_mutex);
4719 for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
4720 int me = (i < 4) ? 1 : 2;
4721 int pipe = (i < 4) ? i : (i - 4);
4722 int queue;
4723
4724 dev_info(adev->dev, " me: %d, pipe: %d\n", me, pipe);
4725 cik_srbm_select(adev, me, pipe, 0, 0);
4726 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR=0x%08X\n",
4727 RREG32(mmCP_HPD_EOP_BASE_ADDR));
4728 dev_info(adev->dev, " CP_HPD_EOP_BASE_ADDR_HI=0x%08X\n",
4729 RREG32(mmCP_HPD_EOP_BASE_ADDR_HI));
4730 dev_info(adev->dev, " CP_HPD_EOP_VMID=0x%08X\n",
4731 RREG32(mmCP_HPD_EOP_VMID));
4732 dev_info(adev->dev, " CP_HPD_EOP_CONTROL=0x%08X\n",
4733 RREG32(mmCP_HPD_EOP_CONTROL));
4734
4735 for (queue = 0; queue < 8; queue++) {
4736 cik_srbm_select(adev, me, pipe, queue, 0);
4737 dev_info(adev->dev, " queue: %d\n", queue);
4738 dev_info(adev->dev, " CP_PQ_WPTR_POLL_CNTL=0x%08X\n",
4739 RREG32(mmCP_PQ_WPTR_POLL_CNTL));
4740 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
4741 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
4742 dev_info(adev->dev, " CP_HQD_ACTIVE=0x%08X\n",
4743 RREG32(mmCP_HQD_ACTIVE));
4744 dev_info(adev->dev, " CP_HQD_DEQUEUE_REQUEST=0x%08X\n",
4745 RREG32(mmCP_HQD_DEQUEUE_REQUEST));
4746 dev_info(adev->dev, " CP_HQD_PQ_RPTR=0x%08X\n",
4747 RREG32(mmCP_HQD_PQ_RPTR));
4748 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
4749 RREG32(mmCP_HQD_PQ_WPTR));
4750 dev_info(adev->dev, " CP_HQD_PQ_BASE=0x%08X\n",
4751 RREG32(mmCP_HQD_PQ_BASE));
4752 dev_info(adev->dev, " CP_HQD_PQ_BASE_HI=0x%08X\n",
4753 RREG32(mmCP_HQD_PQ_BASE_HI));
4754 dev_info(adev->dev, " CP_HQD_PQ_CONTROL=0x%08X\n",
4755 RREG32(mmCP_HQD_PQ_CONTROL));
4756 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR=0x%08X\n",
4757 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR));
4758 dev_info(adev->dev, " CP_HQD_PQ_WPTR_POLL_ADDR_HI=0x%08X\n",
4759 RREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI));
4760 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR=0x%08X\n",
4761 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR));
4762 dev_info(adev->dev, " CP_HQD_PQ_RPTR_REPORT_ADDR_HI=0x%08X\n",
4763 RREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI));
4764 dev_info(adev->dev, " CP_HQD_PQ_DOORBELL_CONTROL=0x%08X\n",
4765 RREG32(mmCP_HQD_PQ_DOORBELL_CONTROL));
4766 dev_info(adev->dev, " CP_HQD_PQ_WPTR=0x%08X\n",
4767 RREG32(mmCP_HQD_PQ_WPTR));
4768 dev_info(adev->dev, " CP_HQD_VMID=0x%08X\n",
4769 RREG32(mmCP_HQD_VMID));
4770 dev_info(adev->dev, " CP_MQD_BASE_ADDR=0x%08X\n",
4771 RREG32(mmCP_MQD_BASE_ADDR));
4772 dev_info(adev->dev, " CP_MQD_BASE_ADDR_HI=0x%08X\n",
4773 RREG32(mmCP_MQD_BASE_ADDR_HI));
4774 dev_info(adev->dev, " CP_MQD_CONTROL=0x%08X\n",
4775 RREG32(mmCP_MQD_CONTROL));
4776 }
4777 }
4778 cik_srbm_select(adev, 0, 0, 0, 0);
4779 mutex_unlock(&adev->srbm_mutex);
4780
4781 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4782 RREG32(mmCP_INT_CNTL_RING0));
4783 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4784 RREG32(mmRLC_LB_CNTL));
4785 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4786 RREG32(mmRLC_CNTL));
4787 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4788 RREG32(mmRLC_CGCG_CGLS_CTRL));
4789 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4790 RREG32(mmRLC_LB_CNTR_INIT));
4791 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4792 RREG32(mmRLC_LB_CNTR_MAX));
4793 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4794 RREG32(mmRLC_LB_INIT_CU_MASK));
4795 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4796 RREG32(mmRLC_LB_PARAMS));
4797 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4798 RREG32(mmRLC_LB_CNTL));
4799 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4800 RREG32(mmRLC_MC_CNTL));
4801 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4802 RREG32(mmRLC_UCODE_CNTL));
4803
4804 if (adev->asic_type == CHIP_BONAIRE)
4805 dev_info(adev->dev, " RLC_DRIVER_CPDMA_STATUS=0x%08X\n",
4806 RREG32(mmRLC_DRIVER_CPDMA_STATUS));
4807
4808 mutex_lock(&adev->srbm_mutex);
4809 for (i = 0; i < 16; i++) {
4810 cik_srbm_select(adev, 0, 0, 0, i);
4811 dev_info(adev->dev, " VM %d:\n", i);
4812 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4813 RREG32(mmSH_MEM_CONFIG));
4814 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4815 RREG32(mmSH_MEM_APE1_BASE));
4816 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
4817 RREG32(mmSH_MEM_APE1_LIMIT));
4818 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
4819 RREG32(mmSH_MEM_BASES));
4820 }
4821 cik_srbm_select(adev, 0, 0, 0, 0);
4822 mutex_unlock(&adev->srbm_mutex);
4823}
4824
4825static int gfx_v7_0_soft_reset(void *handle) 4575static int gfx_v7_0_soft_reset(void *handle)
4826{ 4576{
4827 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4577 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
@@ -4855,7 +4605,6 @@ static int gfx_v7_0_soft_reset(void *handle)
4855 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 4605 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK;
4856 4606
4857 if (grbm_soft_reset || srbm_soft_reset) { 4607 if (grbm_soft_reset || srbm_soft_reset) {
4858 gfx_v7_0_print_status((void *)adev);
4859 /* disable CG/PG */ 4608 /* disable CG/PG */
4860 gfx_v7_0_fini_pg(adev); 4609 gfx_v7_0_fini_pg(adev);
4861 gfx_v7_0_update_cg(adev, false); 4610 gfx_v7_0_update_cg(adev, false);
@@ -4898,7 +4647,6 @@ static int gfx_v7_0_soft_reset(void *handle)
4898 } 4647 }
4899 /* Wait a little for things to settle down */ 4648 /* Wait a little for things to settle down */
4900 udelay(50); 4649 udelay(50);
4901 gfx_v7_0_print_status((void *)adev);
4902 } 4650 }
4903 return 0; 4651 return 0;
4904} 4652}
@@ -5161,7 +4909,6 @@ const struct amd_ip_funcs gfx_v7_0_ip_funcs = {
5161 .is_idle = gfx_v7_0_is_idle, 4909 .is_idle = gfx_v7_0_is_idle,
5162 .wait_for_idle = gfx_v7_0_wait_for_idle, 4910 .wait_for_idle = gfx_v7_0_wait_for_idle,
5163 .soft_reset = gfx_v7_0_soft_reset, 4911 .soft_reset = gfx_v7_0_soft_reset,
5164 .print_status = gfx_v7_0_print_status,
5165 .set_clockgating_state = gfx_v7_0_set_clockgating_state, 4912 .set_clockgating_state = gfx_v7_0_set_clockgating_state,
5166 .set_powergating_state = gfx_v7_0_set_powergating_state, 4913 .set_powergating_state = gfx_v7_0_set_powergating_state,
5167}; 4914};
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index aeb9caee5c1a..021c17e50d51 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4826,185 +4826,6 @@ static int gfx_v8_0_wait_for_idle(void *handle)
4826 return -ETIMEDOUT; 4826 return -ETIMEDOUT;
4827} 4827}
4828 4828
4829static void gfx_v8_0_print_status(void *handle)
4830{
4831 int i;
4832 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4833
4834 dev_info(adev->dev, "GFX 8.x registers\n");
4835 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n",
4836 RREG32(mmGRBM_STATUS));
4837 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n",
4838 RREG32(mmGRBM_STATUS2));
4839 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n",
4840 RREG32(mmGRBM_STATUS_SE0));
4841 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n",
4842 RREG32(mmGRBM_STATUS_SE1));
4843 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n",
4844 RREG32(mmGRBM_STATUS_SE2));
4845 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n",
4846 RREG32(mmGRBM_STATUS_SE3));
4847 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT));
4848 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n",
4849 RREG32(mmCP_STALLED_STAT1));
4850 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n",
4851 RREG32(mmCP_STALLED_STAT2));
4852 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n",
4853 RREG32(mmCP_STALLED_STAT3));
4854 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n",
4855 RREG32(mmCP_CPF_BUSY_STAT));
4856 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n",
4857 RREG32(mmCP_CPF_STALLED_STAT1));
4858 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS));
4859 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT));
4860 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n",
4861 RREG32(mmCP_CPC_STALLED_STAT1));
4862 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS));
4863
4864 for (i = 0; i < 32; i++) {
4865 dev_info(adev->dev, " GB_TILE_MODE%d=0x%08X\n",
4866 i, RREG32(mmGB_TILE_MODE0 + (i * 4)));
4867 }
4868 for (i = 0; i < 16; i++) {
4869 dev_info(adev->dev, " GB_MACROTILE_MODE%d=0x%08X\n",
4870 i, RREG32(mmGB_MACROTILE_MODE0 + (i * 4)));
4871 }
4872 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4873 dev_info(adev->dev, " se: %d\n", i);
4874 gfx_v8_0_select_se_sh(adev, i, 0xffffffff);
4875 dev_info(adev->dev, " PA_SC_RASTER_CONFIG=0x%08X\n",
4876 RREG32(mmPA_SC_RASTER_CONFIG));
4877 dev_info(adev->dev, " PA_SC_RASTER_CONFIG_1=0x%08X\n",
4878 RREG32(mmPA_SC_RASTER_CONFIG_1));
4879 }
4880 gfx_v8_0_select_se_sh(adev, 0xffffffff, 0xffffffff);
4881
4882 dev_info(adev->dev, " GB_ADDR_CONFIG=0x%08X\n",
4883 RREG32(mmGB_ADDR_CONFIG));
4884 dev_info(adev->dev, " HDP_ADDR_CONFIG=0x%08X\n",
4885 RREG32(mmHDP_ADDR_CONFIG));
4886 dev_info(adev->dev, " DMIF_ADDR_CALC=0x%08X\n",
4887 RREG32(mmDMIF_ADDR_CALC));
4888
4889 dev_info(adev->dev, " CP_MEQ_THRESHOLDS=0x%08X\n",
4890 RREG32(mmCP_MEQ_THRESHOLDS));
4891 dev_info(adev->dev, " SX_DEBUG_1=0x%08X\n",
4892 RREG32(mmSX_DEBUG_1));
4893 dev_info(adev->dev, " TA_CNTL_AUX=0x%08X\n",
4894 RREG32(mmTA_CNTL_AUX));
4895 dev_info(adev->dev, " SPI_CONFIG_CNTL=0x%08X\n",
4896 RREG32(mmSPI_CONFIG_CNTL));
4897 dev_info(adev->dev, " SQ_CONFIG=0x%08X\n",
4898 RREG32(mmSQ_CONFIG));
4899 dev_info(adev->dev, " DB_DEBUG=0x%08X\n",
4900 RREG32(mmDB_DEBUG));
4901 dev_info(adev->dev, " DB_DEBUG2=0x%08X\n",
4902 RREG32(mmDB_DEBUG2));
4903 dev_info(adev->dev, " DB_DEBUG3=0x%08X\n",
4904 RREG32(mmDB_DEBUG3));
4905 dev_info(adev->dev, " CB_HW_CONTROL=0x%08X\n",
4906 RREG32(mmCB_HW_CONTROL));
4907 dev_info(adev->dev, " SPI_CONFIG_CNTL_1=0x%08X\n",
4908 RREG32(mmSPI_CONFIG_CNTL_1));
4909 dev_info(adev->dev, " PA_SC_FIFO_SIZE=0x%08X\n",
4910 RREG32(mmPA_SC_FIFO_SIZE));
4911 dev_info(adev->dev, " VGT_NUM_INSTANCES=0x%08X\n",
4912 RREG32(mmVGT_NUM_INSTANCES));
4913 dev_info(adev->dev, " CP_PERFMON_CNTL=0x%08X\n",
4914 RREG32(mmCP_PERFMON_CNTL));
4915 dev_info(adev->dev, " PA_SC_FORCE_EOV_MAX_CNTS=0x%08X\n",
4916 RREG32(mmPA_SC_FORCE_EOV_MAX_CNTS));
4917 dev_info(adev->dev, " VGT_CACHE_INVALIDATION=0x%08X\n",
4918 RREG32(mmVGT_CACHE_INVALIDATION));
4919 dev_info(adev->dev, " VGT_GS_VERTEX_REUSE=0x%08X\n",
4920 RREG32(mmVGT_GS_VERTEX_REUSE));
4921 dev_info(adev->dev, " PA_SC_LINE_STIPPLE_STATE=0x%08X\n",
4922 RREG32(mmPA_SC_LINE_STIPPLE_STATE));
4923 dev_info(adev->dev, " PA_CL_ENHANCE=0x%08X\n",
4924 RREG32(mmPA_CL_ENHANCE));
4925 dev_info(adev->dev, " PA_SC_ENHANCE=0x%08X\n",
4926 RREG32(mmPA_SC_ENHANCE));
4927
4928 dev_info(adev->dev, " CP_ME_CNTL=0x%08X\n",
4929 RREG32(mmCP_ME_CNTL));
4930 dev_info(adev->dev, " CP_MAX_CONTEXT=0x%08X\n",
4931 RREG32(mmCP_MAX_CONTEXT));
4932 dev_info(adev->dev, " CP_ENDIAN_SWAP=0x%08X\n",
4933 RREG32(mmCP_ENDIAN_SWAP));
4934 dev_info(adev->dev, " CP_DEVICE_ID=0x%08X\n",
4935 RREG32(mmCP_DEVICE_ID));
4936
4937 dev_info(adev->dev, " CP_SEM_WAIT_TIMER=0x%08X\n",
4938 RREG32(mmCP_SEM_WAIT_TIMER));
4939
4940 dev_info(adev->dev, " CP_RB_WPTR_DELAY=0x%08X\n",
4941 RREG32(mmCP_RB_WPTR_DELAY));
4942 dev_info(adev->dev, " CP_RB_VMID=0x%08X\n",
4943 RREG32(mmCP_RB_VMID));
4944 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4945 RREG32(mmCP_RB0_CNTL));
4946 dev_info(adev->dev, " CP_RB0_WPTR=0x%08X\n",
4947 RREG32(mmCP_RB0_WPTR));
4948 dev_info(adev->dev, " CP_RB0_RPTR_ADDR=0x%08X\n",
4949 RREG32(mmCP_RB0_RPTR_ADDR));
4950 dev_info(adev->dev, " CP_RB0_RPTR_ADDR_HI=0x%08X\n",
4951 RREG32(mmCP_RB0_RPTR_ADDR_HI));
4952 dev_info(adev->dev, " CP_RB0_CNTL=0x%08X\n",
4953 RREG32(mmCP_RB0_CNTL));
4954 dev_info(adev->dev, " CP_RB0_BASE=0x%08X\n",
4955 RREG32(mmCP_RB0_BASE));
4956 dev_info(adev->dev, " CP_RB0_BASE_HI=0x%08X\n",
4957 RREG32(mmCP_RB0_BASE_HI));
4958 dev_info(adev->dev, " CP_MEC_CNTL=0x%08X\n",
4959 RREG32(mmCP_MEC_CNTL));
4960 dev_info(adev->dev, " CP_CPF_DEBUG=0x%08X\n",
4961 RREG32(mmCP_CPF_DEBUG));
4962
4963 dev_info(adev->dev, " SCRATCH_ADDR=0x%08X\n",
4964 RREG32(mmSCRATCH_ADDR));
4965 dev_info(adev->dev, " SCRATCH_UMSK=0x%08X\n",
4966 RREG32(mmSCRATCH_UMSK));
4967
4968 dev_info(adev->dev, " CP_INT_CNTL_RING0=0x%08X\n",
4969 RREG32(mmCP_INT_CNTL_RING0));
4970 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4971 RREG32(mmRLC_LB_CNTL));
4972 dev_info(adev->dev, " RLC_CNTL=0x%08X\n",
4973 RREG32(mmRLC_CNTL));
4974 dev_info(adev->dev, " RLC_CGCG_CGLS_CTRL=0x%08X\n",
4975 RREG32(mmRLC_CGCG_CGLS_CTRL));
4976 dev_info(adev->dev, " RLC_LB_CNTR_INIT=0x%08X\n",
4977 RREG32(mmRLC_LB_CNTR_INIT));
4978 dev_info(adev->dev, " RLC_LB_CNTR_MAX=0x%08X\n",
4979 RREG32(mmRLC_LB_CNTR_MAX));
4980 dev_info(adev->dev, " RLC_LB_INIT_CU_MASK=0x%08X\n",
4981 RREG32(mmRLC_LB_INIT_CU_MASK));
4982 dev_info(adev->dev, " RLC_LB_PARAMS=0x%08X\n",
4983 RREG32(mmRLC_LB_PARAMS));
4984 dev_info(adev->dev, " RLC_LB_CNTL=0x%08X\n",
4985 RREG32(mmRLC_LB_CNTL));
4986 dev_info(adev->dev, " RLC_MC_CNTL=0x%08X\n",
4987 RREG32(mmRLC_MC_CNTL));
4988 dev_info(adev->dev, " RLC_UCODE_CNTL=0x%08X\n",
4989 RREG32(mmRLC_UCODE_CNTL));
4990
4991 mutex_lock(&adev->srbm_mutex);
4992 for (i = 0; i < 16; i++) {
4993 vi_srbm_select(adev, 0, 0, 0, i);
4994 dev_info(adev->dev, " VM %d:\n", i);
4995 dev_info(adev->dev, " SH_MEM_CONFIG=0x%08X\n",
4996 RREG32(mmSH_MEM_CONFIG));
4997 dev_info(adev->dev, " SH_MEM_APE1_BASE=0x%08X\n",
4998 RREG32(mmSH_MEM_APE1_BASE));
4999 dev_info(adev->dev, " SH_MEM_APE1_LIMIT=0x%08X\n",
5000 RREG32(mmSH_MEM_APE1_LIMIT));
5001 dev_info(adev->dev, " SH_MEM_BASES=0x%08X\n",
5002 RREG32(mmSH_MEM_BASES));
5003 }
5004 vi_srbm_select(adev, 0, 0, 0, 0);
5005 mutex_unlock(&adev->srbm_mutex);
5006}
5007
5008static int gfx_v8_0_soft_reset(void *handle) 4829static int gfx_v8_0_soft_reset(void *handle)
5009{ 4830{
5010 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 4831 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
@@ -5045,7 +4866,6 @@ static int gfx_v8_0_soft_reset(void *handle)
5045 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1); 4866 SRBM_SOFT_RESET, SOFT_RESET_GRBM, 1);
5046 4867
5047 if (grbm_soft_reset || srbm_soft_reset) { 4868 if (grbm_soft_reset || srbm_soft_reset) {
5048 gfx_v8_0_print_status((void *)adev);
5049 /* stop the rlc */ 4869 /* stop the rlc */
5050 gfx_v8_0_rlc_stop(adev); 4870 gfx_v8_0_rlc_stop(adev);
5051 4871
@@ -5105,7 +4925,6 @@ static int gfx_v8_0_soft_reset(void *handle)
5105 4925
5106 /* Wait a little for things to settle down */ 4926 /* Wait a little for things to settle down */
5107 udelay(50); 4927 udelay(50);
5108 gfx_v8_0_print_status((void *)adev);
5109 } 4928 }
5110 return 0; 4929 return 0;
5111} 4930}
@@ -6256,7 +6075,6 @@ const struct amd_ip_funcs gfx_v8_0_ip_funcs = {
6256 .is_idle = gfx_v8_0_is_idle, 6075 .is_idle = gfx_v8_0_is_idle,
6257 .wait_for_idle = gfx_v8_0_wait_for_idle, 6076 .wait_for_idle = gfx_v8_0_wait_for_idle,
6258 .soft_reset = gfx_v8_0_soft_reset, 6077 .soft_reset = gfx_v8_0_soft_reset,
6259 .print_status = gfx_v8_0_print_status,
6260 .set_clockgating_state = gfx_v8_0_set_clockgating_state, 6078 .set_clockgating_state = gfx_v8_0_set_clockgating_state,
6261 .set_powergating_state = gfx_v8_0_set_powergating_state, 6079 .set_powergating_state = gfx_v8_0_set_powergating_state,
6262}; 6080};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 05b0353d3880..3b620a8e8682 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -1114,114 +1114,6 @@ static int gmc_v7_0_wait_for_idle(void *handle)
1114 1114
1115} 1115}
1116 1116
1117static void gmc_v7_0_print_status(void *handle)
1118{
1119 int i, j;
1120 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1121
1122 dev_info(adev->dev, "GMC 8.x registers\n");
1123 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1124 RREG32(mmSRBM_STATUS));
1125 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1126 RREG32(mmSRBM_STATUS2));
1127
1128 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1129 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1130 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1131 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1132 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1133 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1134 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1135 RREG32(mmVM_L2_CNTL));
1136 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1137 RREG32(mmVM_L2_CNTL2));
1138 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1139 RREG32(mmVM_L2_CNTL3));
1140 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1141 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1142 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1143 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1144 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1145 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1146 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1147 RREG32(mmVM_CONTEXT0_CNTL2));
1148 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1149 RREG32(mmVM_CONTEXT0_CNTL));
1150 dev_info(adev->dev, " 0x15D4=0x%08X\n",
1151 RREG32(0x575));
1152 dev_info(adev->dev, " 0x15D8=0x%08X\n",
1153 RREG32(0x576));
1154 dev_info(adev->dev, " 0x15DC=0x%08X\n",
1155 RREG32(0x577));
1156 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1157 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1158 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1159 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1160 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1161 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1162 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1163 RREG32(mmVM_CONTEXT1_CNTL2));
1164 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1165 RREG32(mmVM_CONTEXT1_CNTL));
1166 for (i = 0; i < 16; i++) {
1167 if (i < 8)
1168 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1169 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1170 else
1171 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1172 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1173 }
1174 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1175 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1176 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1177 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1178 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1179 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1180 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1181 RREG32(mmMC_VM_FB_LOCATION));
1182 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1183 RREG32(mmMC_VM_AGP_BASE));
1184 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1185 RREG32(mmMC_VM_AGP_TOP));
1186 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1187 RREG32(mmMC_VM_AGP_BOT));
1188
1189 if (adev->asic_type == CHIP_KAVERI) {
1190 dev_info(adev->dev, " CHUB_CONTROL=0x%08X\n",
1191 RREG32(mmCHUB_CONTROL));
1192 }
1193
1194 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1195 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1196 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1197 RREG32(mmHDP_NONSURFACE_BASE));
1198 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1199 RREG32(mmHDP_NONSURFACE_INFO));
1200 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1201 RREG32(mmHDP_NONSURFACE_SIZE));
1202 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1203 RREG32(mmHDP_MISC_CNTL));
1204 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1205 RREG32(mmHDP_HOST_PATH_CNTL));
1206
1207 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1208 dev_info(adev->dev, " %d:\n", i);
1209 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1210 0xb05 + j, RREG32(0xb05 + j));
1211 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1212 0xb06 + j, RREG32(0xb06 + j));
1213 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1214 0xb07 + j, RREG32(0xb07 + j));
1215 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1216 0xb08 + j, RREG32(0xb08 + j));
1217 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1218 0xb09 + j, RREG32(0xb09 + j));
1219 }
1220
1221 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1222 RREG32(mmBIF_FB_EN));
1223}
1224
1225static int gmc_v7_0_soft_reset(void *handle) 1117static int gmc_v7_0_soft_reset(void *handle)
1226{ 1118{
1227 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1119 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -1241,8 +1133,6 @@ static int gmc_v7_0_soft_reset(void *handle)
1241 } 1133 }
1242 1134
1243 if (srbm_soft_reset) { 1135 if (srbm_soft_reset) {
1244 gmc_v7_0_print_status((void *)adev);
1245
1246 gmc_v7_0_mc_stop(adev, &save); 1136 gmc_v7_0_mc_stop(adev, &save);
1247 if (gmc_v7_0_wait_for_idle(adev)) { 1137 if (gmc_v7_0_wait_for_idle(adev)) {
1248 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1138 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
@@ -1266,8 +1156,6 @@ static int gmc_v7_0_soft_reset(void *handle)
1266 1156
1267 gmc_v7_0_mc_resume(adev, &save); 1157 gmc_v7_0_mc_resume(adev, &save);
1268 udelay(50); 1158 udelay(50);
1269
1270 gmc_v7_0_print_status((void *)adev);
1271 } 1159 }
1272 1160
1273 return 0; 1161 return 0;
@@ -1381,7 +1269,6 @@ const struct amd_ip_funcs gmc_v7_0_ip_funcs = {
1381 .is_idle = gmc_v7_0_is_idle, 1269 .is_idle = gmc_v7_0_is_idle,
1382 .wait_for_idle = gmc_v7_0_wait_for_idle, 1270 .wait_for_idle = gmc_v7_0_wait_for_idle,
1383 .soft_reset = gmc_v7_0_soft_reset, 1271 .soft_reset = gmc_v7_0_soft_reset,
1384 .print_status = gmc_v7_0_print_status,
1385 .set_clockgating_state = gmc_v7_0_set_clockgating_state, 1272 .set_clockgating_state = gmc_v7_0_set_clockgating_state,
1386 .set_powergating_state = gmc_v7_0_set_powergating_state, 1273 .set_powergating_state = gmc_v7_0_set_powergating_state,
1387}; 1274};
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index e6715ec2489f..c0de22f7311d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -1117,111 +1117,6 @@ static int gmc_v8_0_wait_for_idle(void *handle)
1117 1117
1118} 1118}
1119 1119
1120static void gmc_v8_0_print_status(void *handle)
1121{
1122 int i, j;
1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124
1125 dev_info(adev->dev, "GMC 8.x registers\n");
1126 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
1127 RREG32(mmSRBM_STATUS));
1128 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1129 RREG32(mmSRBM_STATUS2));
1130
1131 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1132 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR));
1133 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1134 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS));
1135 dev_info(adev->dev, " MC_VM_MX_L1_TLB_CNTL=0x%08X\n",
1136 RREG32(mmMC_VM_MX_L1_TLB_CNTL));
1137 dev_info(adev->dev, " VM_L2_CNTL=0x%08X\n",
1138 RREG32(mmVM_L2_CNTL));
1139 dev_info(adev->dev, " VM_L2_CNTL2=0x%08X\n",
1140 RREG32(mmVM_L2_CNTL2));
1141 dev_info(adev->dev, " VM_L2_CNTL3=0x%08X\n",
1142 RREG32(mmVM_L2_CNTL3));
1143 dev_info(adev->dev, " VM_L2_CNTL4=0x%08X\n",
1144 RREG32(mmVM_L2_CNTL4));
1145 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_START_ADDR=0x%08X\n",
1146 RREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR));
1147 dev_info(adev->dev, " VM_CONTEXT0_PAGE_TABLE_END_ADDR=0x%08X\n",
1148 RREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR));
1149 dev_info(adev->dev, " VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1150 RREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR));
1151 dev_info(adev->dev, " VM_CONTEXT0_CNTL2=0x%08X\n",
1152 RREG32(mmVM_CONTEXT0_CNTL2));
1153 dev_info(adev->dev, " VM_CONTEXT0_CNTL=0x%08X\n",
1154 RREG32(mmVM_CONTEXT0_CNTL));
1155 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR=0x%08X\n",
1156 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR));
1157 dev_info(adev->dev, " VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR=0x%08X\n",
1158 RREG32(mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR));
1159 dev_info(adev->dev, " mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET=0x%08X\n",
1160 RREG32(mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET));
1161 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_START_ADDR=0x%08X\n",
1162 RREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR));
1163 dev_info(adev->dev, " VM_CONTEXT1_PAGE_TABLE_END_ADDR=0x%08X\n",
1164 RREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR));
1165 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR=0x%08X\n",
1166 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR));
1167 dev_info(adev->dev, " VM_CONTEXT1_CNTL2=0x%08X\n",
1168 RREG32(mmVM_CONTEXT1_CNTL2));
1169 dev_info(adev->dev, " VM_CONTEXT1_CNTL=0x%08X\n",
1170 RREG32(mmVM_CONTEXT1_CNTL));
1171 for (i = 0; i < 16; i++) {
1172 if (i < 8)
1173 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1174 i, RREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i));
1175 else
1176 dev_info(adev->dev, " VM_CONTEXT%d_PAGE_TABLE_BASE_ADDR=0x%08X\n",
1177 i, RREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8));
1178 }
1179 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_LOW_ADDR=0x%08X\n",
1180 RREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR));
1181 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_HIGH_ADDR=0x%08X\n",
1182 RREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR));
1183 dev_info(adev->dev, " MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR=0x%08X\n",
1184 RREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR));
1185 dev_info(adev->dev, " MC_VM_FB_LOCATION=0x%08X\n",
1186 RREG32(mmMC_VM_FB_LOCATION));
1187 dev_info(adev->dev, " MC_VM_AGP_BASE=0x%08X\n",
1188 RREG32(mmMC_VM_AGP_BASE));
1189 dev_info(adev->dev, " MC_VM_AGP_TOP=0x%08X\n",
1190 RREG32(mmMC_VM_AGP_TOP));
1191 dev_info(adev->dev, " MC_VM_AGP_BOT=0x%08X\n",
1192 RREG32(mmMC_VM_AGP_BOT));
1193
1194 dev_info(adev->dev, " HDP_REG_COHERENCY_FLUSH_CNTL=0x%08X\n",
1195 RREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL));
1196 dev_info(adev->dev, " HDP_NONSURFACE_BASE=0x%08X\n",
1197 RREG32(mmHDP_NONSURFACE_BASE));
1198 dev_info(adev->dev, " HDP_NONSURFACE_INFO=0x%08X\n",
1199 RREG32(mmHDP_NONSURFACE_INFO));
1200 dev_info(adev->dev, " HDP_NONSURFACE_SIZE=0x%08X\n",
1201 RREG32(mmHDP_NONSURFACE_SIZE));
1202 dev_info(adev->dev, " HDP_MISC_CNTL=0x%08X\n",
1203 RREG32(mmHDP_MISC_CNTL));
1204 dev_info(adev->dev, " HDP_HOST_PATH_CNTL=0x%08X\n",
1205 RREG32(mmHDP_HOST_PATH_CNTL));
1206
1207 for (i = 0, j = 0; i < 32; i++, j += 0x6) {
1208 dev_info(adev->dev, " %d:\n", i);
1209 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1210 0xb05 + j, RREG32(0xb05 + j));
1211 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1212 0xb06 + j, RREG32(0xb06 + j));
1213 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1214 0xb07 + j, RREG32(0xb07 + j));
1215 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1216 0xb08 + j, RREG32(0xb08 + j));
1217 dev_info(adev->dev, " 0x%04X=0x%08X\n",
1218 0xb09 + j, RREG32(0xb09 + j));
1219 }
1220
1221 dev_info(adev->dev, " BIF_FB_EN=0x%08X\n",
1222 RREG32(mmBIF_FB_EN));
1223}
1224
1225static int gmc_v8_0_soft_reset(void *handle) 1120static int gmc_v8_0_soft_reset(void *handle)
1226{ 1121{
1227 struct amdgpu_mode_mc_save save; 1122 struct amdgpu_mode_mc_save save;
@@ -1241,8 +1136,6 @@ static int gmc_v8_0_soft_reset(void *handle)
1241 } 1136 }
1242 1137
1243 if (srbm_soft_reset) { 1138 if (srbm_soft_reset) {
1244 gmc_v8_0_print_status((void *)adev);
1245
1246 gmc_v8_0_mc_stop(adev, &save); 1139 gmc_v8_0_mc_stop(adev, &save);
1247 if (gmc_v8_0_wait_for_idle(adev)) { 1140 if (gmc_v8_0_wait_for_idle(adev)) {
1248 dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); 1141 dev_warn(adev->dev, "Wait for GMC idle timed out !\n");
@@ -1266,8 +1159,6 @@ static int gmc_v8_0_soft_reset(void *handle)
1266 1159
1267 gmc_v8_0_mc_resume(adev, &save); 1160 gmc_v8_0_mc_resume(adev, &save);
1268 udelay(50); 1161 udelay(50);
1269
1270 gmc_v8_0_print_status((void *)adev);
1271 } 1162 }
1272 1163
1273 return 0; 1164 return 0;
@@ -1540,7 +1431,6 @@ const struct amd_ip_funcs gmc_v8_0_ip_funcs = {
1540 .is_idle = gmc_v8_0_is_idle, 1431 .is_idle = gmc_v8_0_is_idle,
1541 .wait_for_idle = gmc_v8_0_wait_for_idle, 1432 .wait_for_idle = gmc_v8_0_wait_for_idle,
1542 .soft_reset = gmc_v8_0_soft_reset, 1433 .soft_reset = gmc_v8_0_soft_reset,
1543 .print_status = gmc_v8_0_print_status,
1544 .set_clockgating_state = gmc_v8_0_set_clockgating_state, 1434 .set_clockgating_state = gmc_v8_0_set_clockgating_state,
1545 .set_powergating_state = gmc_v8_0_set_powergating_state, 1435 .set_powergating_state = gmc_v8_0_set_powergating_state,
1546}; 1436};
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
index 208d55f41c7f..57a96132a8a2 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_dpm.c
@@ -168,7 +168,6 @@ const struct amd_ip_funcs iceland_dpm_ip_funcs = {
168 .is_idle = NULL, 168 .is_idle = NULL,
169 .wait_for_idle = NULL, 169 .wait_for_idle = NULL,
170 .soft_reset = NULL, 170 .soft_reset = NULL,
171 .print_status = NULL,
172 .set_clockgating_state = iceland_dpm_set_clockgating_state, 171 .set_clockgating_state = iceland_dpm_set_clockgating_state,
173 .set_powergating_state = iceland_dpm_set_powergating_state, 172 .set_powergating_state = iceland_dpm_set_powergating_state,
174}; 173};
diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index 679e7394a495..5c4001e2538e 100644
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -351,35 +351,6 @@ static int iceland_ih_wait_for_idle(void *handle)
351 return -ETIMEDOUT; 351 return -ETIMEDOUT;
352} 352}
353 353
354static void iceland_ih_print_status(void *handle)
355{
356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
357
358 dev_info(adev->dev, "ICELAND IH registers\n");
359 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
360 RREG32(mmSRBM_STATUS));
361 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
362 RREG32(mmSRBM_STATUS2));
363 dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
364 RREG32(mmINTERRUPT_CNTL));
365 dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
366 RREG32(mmINTERRUPT_CNTL2));
367 dev_info(adev->dev, " IH_CNTL=0x%08X\n",
368 RREG32(mmIH_CNTL));
369 dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
370 RREG32(mmIH_RB_CNTL));
371 dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
372 RREG32(mmIH_RB_BASE));
373 dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
374 RREG32(mmIH_RB_WPTR_ADDR_LO));
375 dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
376 RREG32(mmIH_RB_WPTR_ADDR_HI));
377 dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
378 RREG32(mmIH_RB_RPTR));
379 dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
380 RREG32(mmIH_RB_WPTR));
381}
382
383static int iceland_ih_soft_reset(void *handle) 354static int iceland_ih_soft_reset(void *handle)
384{ 355{
385 u32 srbm_soft_reset = 0; 356 u32 srbm_soft_reset = 0;
@@ -391,8 +362,6 @@ static int iceland_ih_soft_reset(void *handle)
391 SOFT_RESET_IH, 1); 362 SOFT_RESET_IH, 1);
392 363
393 if (srbm_soft_reset) { 364 if (srbm_soft_reset) {
394 iceland_ih_print_status((void *)adev);
395
396 tmp = RREG32(mmSRBM_SOFT_RESET); 365 tmp = RREG32(mmSRBM_SOFT_RESET);
397 tmp |= srbm_soft_reset; 366 tmp |= srbm_soft_reset;
398 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 367 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -407,8 +376,6 @@ static int iceland_ih_soft_reset(void *handle)
407 376
408 /* Wait a little for things to settle down */ 377 /* Wait a little for things to settle down */
409 udelay(50); 378 udelay(50);
410
411 iceland_ih_print_status((void *)adev);
412 } 379 }
413 380
414 return 0; 381 return 0;
@@ -438,7 +405,6 @@ const struct amd_ip_funcs iceland_ih_ip_funcs = {
438 .is_idle = iceland_ih_is_idle, 405 .is_idle = iceland_ih_is_idle,
439 .wait_for_idle = iceland_ih_wait_for_idle, 406 .wait_for_idle = iceland_ih_wait_for_idle,
440 .soft_reset = iceland_ih_soft_reset, 407 .soft_reset = iceland_ih_soft_reset,
441 .print_status = iceland_ih_print_status,
442 .set_clockgating_state = iceland_ih_set_clockgating_state, 408 .set_clockgating_state = iceland_ih_set_clockgating_state,
443 .set_powergating_state = iceland_ih_set_powergating_state, 409 .set_powergating_state = iceland_ih_set_powergating_state,
444}; 410};
diff --git a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
index 654d76723bc3..4bd1e551cccd 100644
--- a/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/kv_dpm.c
@@ -3147,62 +3147,6 @@ static int kv_dpm_wait_for_idle(void *handle)
3147 return 0; 3147 return 0;
3148} 3148}
3149 3149
3150static void kv_dpm_print_status(void *handle)
3151{
3152 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3153
3154 dev_info(adev->dev, "KV/KB DPM registers\n");
3155 dev_info(adev->dev, " DIDT_SQ_CTRL0=0x%08X\n",
3156 RREG32_DIDT(ixDIDT_SQ_CTRL0));
3157 dev_info(adev->dev, " DIDT_DB_CTRL0=0x%08X\n",
3158 RREG32_DIDT(ixDIDT_DB_CTRL0));
3159 dev_info(adev->dev, " DIDT_TD_CTRL0=0x%08X\n",
3160 RREG32_DIDT(ixDIDT_TD_CTRL0));
3161 dev_info(adev->dev, " DIDT_TCP_CTRL0=0x%08X\n",
3162 RREG32_DIDT(ixDIDT_TCP_CTRL0));
3163 dev_info(adev->dev, " LCAC_SX0_OVR_SEL=0x%08X\n",
3164 RREG32_SMC(ixLCAC_SX0_OVR_SEL));
3165 dev_info(adev->dev, " LCAC_SX0_OVR_VAL=0x%08X\n",
3166 RREG32_SMC(ixLCAC_SX0_OVR_VAL));
3167 dev_info(adev->dev, " LCAC_MC0_OVR_SEL=0x%08X\n",
3168 RREG32_SMC(ixLCAC_MC0_OVR_SEL));
3169 dev_info(adev->dev, " LCAC_MC0_OVR_VAL=0x%08X\n",
3170 RREG32_SMC(ixLCAC_MC0_OVR_VAL));
3171 dev_info(adev->dev, " LCAC_MC1_OVR_SEL=0x%08X\n",
3172 RREG32_SMC(ixLCAC_MC1_OVR_SEL));
3173 dev_info(adev->dev, " LCAC_MC1_OVR_VAL=0x%08X\n",
3174 RREG32_SMC(ixLCAC_MC1_OVR_VAL));
3175 dev_info(adev->dev, " LCAC_MC2_OVR_SEL=0x%08X\n",
3176 RREG32_SMC(ixLCAC_MC2_OVR_SEL));
3177 dev_info(adev->dev, " LCAC_MC2_OVR_VAL=0x%08X\n",
3178 RREG32_SMC(ixLCAC_MC2_OVR_VAL));
3179 dev_info(adev->dev, " LCAC_MC3_OVR_SEL=0x%08X\n",
3180 RREG32_SMC(ixLCAC_MC3_OVR_SEL));
3181 dev_info(adev->dev, " LCAC_MC3_OVR_VAL=0x%08X\n",
3182 RREG32_SMC(ixLCAC_MC3_OVR_VAL));
3183 dev_info(adev->dev, " LCAC_CPL_OVR_SEL=0x%08X\n",
3184 RREG32_SMC(ixLCAC_CPL_OVR_SEL));
3185 dev_info(adev->dev, " LCAC_CPL_OVR_VAL=0x%08X\n",
3186 RREG32_SMC(ixLCAC_CPL_OVR_VAL));
3187 dev_info(adev->dev, " CG_FREQ_TRAN_VOTING_0=0x%08X\n",
3188 RREG32_SMC(ixCG_FREQ_TRAN_VOTING_0));
3189 dev_info(adev->dev, " GENERAL_PWRMGT=0x%08X\n",
3190 RREG32_SMC(ixGENERAL_PWRMGT));
3191 dev_info(adev->dev, " SCLK_PWRMGT_CNTL=0x%08X\n",
3192 RREG32_SMC(ixSCLK_PWRMGT_CNTL));
3193 dev_info(adev->dev, " SMC_MESSAGE_0=0x%08X\n",
3194 RREG32(mmSMC_MESSAGE_0));
3195 dev_info(adev->dev, " SMC_RESP_0=0x%08X\n",
3196 RREG32(mmSMC_RESP_0));
3197 dev_info(adev->dev, " SMC_MSG_ARG_0=0x%08X\n",
3198 RREG32(mmSMC_MSG_ARG_0));
3199 dev_info(adev->dev, " SMC_IND_INDEX_0=0x%08X\n",
3200 RREG32(mmSMC_IND_INDEX_0));
3201 dev_info(adev->dev, " SMC_IND_DATA_0=0x%08X\n",
3202 RREG32(mmSMC_IND_DATA_0));
3203 dev_info(adev->dev, " SMC_IND_ACCESS_CNTL=0x%08X\n",
3204 RREG32(mmSMC_IND_ACCESS_CNTL));
3205}
3206 3150
3207static int kv_dpm_soft_reset(void *handle) 3151static int kv_dpm_soft_reset(void *handle)
3208{ 3152{
@@ -3311,7 +3255,6 @@ const struct amd_ip_funcs kv_dpm_ip_funcs = {
3311 .is_idle = kv_dpm_is_idle, 3255 .is_idle = kv_dpm_is_idle,
3312 .wait_for_idle = kv_dpm_wait_for_idle, 3256 .wait_for_idle = kv_dpm_wait_for_idle,
3313 .soft_reset = kv_dpm_soft_reset, 3257 .soft_reset = kv_dpm_soft_reset,
3314 .print_status = kv_dpm_print_status,
3315 .set_clockgating_state = kv_dpm_set_clockgating_state, 3258 .set_clockgating_state = kv_dpm_set_clockgating_state,
3316 .set_powergating_state = kv_dpm_set_powergating_state, 3259 .set_powergating_state = kv_dpm_set_powergating_state,
3317}; 3260};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 6f2e2a49ed3e..e6d3544fda06 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1080,55 +1080,6 @@ static int sdma_v2_4_wait_for_idle(void *handle)
1080 return -ETIMEDOUT; 1080 return -ETIMEDOUT;
1081} 1081}
1082 1082
1083static void sdma_v2_4_print_status(void *handle)
1084{
1085 int i, j;
1086 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1087
1088 dev_info(adev->dev, "VI SDMA registers\n");
1089 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1090 RREG32(mmSRBM_STATUS2));
1091 for (i = 0; i < adev->sdma.num_instances; i++) {
1092 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1093 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1094 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1095 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1096 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1097 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1098 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1099 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1100 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1101 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1102 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1103 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1104 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1105 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1106 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1107 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1108 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1109 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1110 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1111 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1112 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1113 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1114 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1115 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1116 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
1117 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
1118 mutex_lock(&adev->srbm_mutex);
1119 for (j = 0; j < 16; j++) {
1120 vi_srbm_select(adev, 0, 0, 0, j);
1121 dev_info(adev->dev, " VM %d:\n", j);
1122 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1123 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1124 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1125 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1126 }
1127 vi_srbm_select(adev, 0, 0, 0, 0);
1128 mutex_unlock(&adev->srbm_mutex);
1129 }
1130}
1131
1132static int sdma_v2_4_soft_reset(void *handle) 1083static int sdma_v2_4_soft_reset(void *handle)
1133{ 1084{
1134 u32 srbm_soft_reset = 0; 1085 u32 srbm_soft_reset = 0;
@@ -1151,8 +1102,6 @@ static int sdma_v2_4_soft_reset(void *handle)
1151 } 1102 }
1152 1103
1153 if (srbm_soft_reset) { 1104 if (srbm_soft_reset) {
1154 sdma_v2_4_print_status((void *)adev);
1155
1156 tmp = RREG32(mmSRBM_SOFT_RESET); 1105 tmp = RREG32(mmSRBM_SOFT_RESET);
1157 tmp |= srbm_soft_reset; 1106 tmp |= srbm_soft_reset;
1158 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1107 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1167,8 +1116,6 @@ static int sdma_v2_4_soft_reset(void *handle)
1167 1116
1168 /* Wait a little for things to settle down */ 1117 /* Wait a little for things to settle down */
1169 udelay(50); 1118 udelay(50);
1170
1171 sdma_v2_4_print_status((void *)adev);
1172 } 1119 }
1173 1120
1174 return 0; 1121 return 0;
@@ -1294,7 +1241,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1294 .is_idle = sdma_v2_4_is_idle, 1241 .is_idle = sdma_v2_4_is_idle,
1295 .wait_for_idle = sdma_v2_4_wait_for_idle, 1242 .wait_for_idle = sdma_v2_4_wait_for_idle,
1296 .soft_reset = sdma_v2_4_soft_reset, 1243 .soft_reset = sdma_v2_4_soft_reset,
1297 .print_status = sdma_v2_4_print_status,
1298 .set_clockgating_state = sdma_v2_4_set_clockgating_state, 1244 .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1299 .set_powergating_state = sdma_v2_4_set_powergating_state, 1245 .set_powergating_state = sdma_v2_4_set_powergating_state,
1300}; 1246};
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 1b5053f9b120..00b43700c956 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1314,57 +1314,6 @@ static int sdma_v3_0_wait_for_idle(void *handle)
1314 return -ETIMEDOUT; 1314 return -ETIMEDOUT;
1315} 1315}
1316 1316
1317static void sdma_v3_0_print_status(void *handle)
1318{
1319 int i, j;
1320 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1321
1322 dev_info(adev->dev, "VI SDMA registers\n");
1323 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
1324 RREG32(mmSRBM_STATUS2));
1325 for (i = 0; i < adev->sdma.num_instances; i++) {
1326 dev_info(adev->dev, " SDMA%d_STATUS_REG=0x%08X\n",
1327 i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
1328 dev_info(adev->dev, " SDMA%d_F32_CNTL=0x%08X\n",
1329 i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
1330 dev_info(adev->dev, " SDMA%d_CNTL=0x%08X\n",
1331 i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
1332 dev_info(adev->dev, " SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
1333 i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
1334 dev_info(adev->dev, " SDMA%d_GFX_IB_CNTL=0x%08X\n",
1335 i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
1336 dev_info(adev->dev, " SDMA%d_GFX_RB_CNTL=0x%08X\n",
1337 i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
1338 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR=0x%08X\n",
1339 i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
1340 dev_info(adev->dev, " SDMA%d_GFX_RB_WPTR=0x%08X\n",
1341 i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
1342 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
1343 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
1344 dev_info(adev->dev, " SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
1345 i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
1346 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE=0x%08X\n",
1347 i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
1348 dev_info(adev->dev, " SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
1349 i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
1350 dev_info(adev->dev, " SDMA%d_GFX_DOORBELL=0x%08X\n",
1351 i, RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]));
1352 dev_info(adev->dev, " SDMA%d_TILING_CONFIG=0x%08X\n",
1353 i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
1354 mutex_lock(&adev->srbm_mutex);
1355 for (j = 0; j < 16; j++) {
1356 vi_srbm_select(adev, 0, 0, 0, j);
1357 dev_info(adev->dev, " VM %d:\n", j);
1358 dev_info(adev->dev, " SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
1359 i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
1360 dev_info(adev->dev, " SDMA%d_GFX_APE1_CNTL=0x%08X\n",
1361 i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
1362 }
1363 vi_srbm_select(adev, 0, 0, 0, 0);
1364 mutex_unlock(&adev->srbm_mutex);
1365 }
1366}
1367
1368static int sdma_v3_0_soft_reset(void *handle) 1317static int sdma_v3_0_soft_reset(void *handle)
1369{ 1318{
1370 u32 srbm_soft_reset = 0; 1319 u32 srbm_soft_reset = 0;
@@ -1387,8 +1336,6 @@ static int sdma_v3_0_soft_reset(void *handle)
1387 } 1336 }
1388 1337
1389 if (srbm_soft_reset) { 1338 if (srbm_soft_reset) {
1390 sdma_v3_0_print_status((void *)adev);
1391
1392 tmp = RREG32(mmSRBM_SOFT_RESET); 1339 tmp = RREG32(mmSRBM_SOFT_RESET);
1393 tmp |= srbm_soft_reset; 1340 tmp |= srbm_soft_reset;
1394 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1341 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1403,8 +1350,6 @@ static int sdma_v3_0_soft_reset(void *handle)
1403 1350
1404 /* Wait a little for things to settle down */ 1351 /* Wait a little for things to settle down */
1405 udelay(50); 1352 udelay(50);
1406
1407 sdma_v3_0_print_status((void *)adev);
1408 } 1353 }
1409 1354
1410 return 0; 1355 return 0;
@@ -1608,7 +1553,6 @@ const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1608 .is_idle = sdma_v3_0_is_idle, 1553 .is_idle = sdma_v3_0_is_idle,
1609 .wait_for_idle = sdma_v3_0_wait_for_idle, 1554 .wait_for_idle = sdma_v3_0_wait_for_idle,
1610 .soft_reset = sdma_v3_0_soft_reset, 1555 .soft_reset = sdma_v3_0_soft_reset,
1611 .print_status = sdma_v3_0_print_status,
1612 .set_clockgating_state = sdma_v3_0_set_clockgating_state, 1556 .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1613 .set_powergating_state = sdma_v3_0_set_powergating_state, 1557 .set_powergating_state = sdma_v3_0_set_powergating_state,
1614}; 1558};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
index 0497784b3652..552f0f42a39f 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_dpm.c
@@ -154,7 +154,6 @@ const struct amd_ip_funcs tonga_dpm_ip_funcs = {
154 .is_idle = NULL, 154 .is_idle = NULL,
155 .wait_for_idle = NULL, 155 .wait_for_idle = NULL,
156 .soft_reset = NULL, 156 .soft_reset = NULL,
157 .print_status = NULL,
158 .set_clockgating_state = tonga_dpm_set_clockgating_state, 157 .set_clockgating_state = tonga_dpm_set_clockgating_state,
159 .set_powergating_state = tonga_dpm_set_powergating_state, 158 .set_powergating_state = tonga_dpm_set_powergating_state,
160}; 159};
diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index b6f7d7bff929..dd9e5e36fec9 100644
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -374,35 +374,6 @@ static int tonga_ih_wait_for_idle(void *handle)
374 return -ETIMEDOUT; 374 return -ETIMEDOUT;
375} 375}
376 376
377static void tonga_ih_print_status(void *handle)
378{
379 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
380
381 dev_info(adev->dev, "TONGA IH registers\n");
382 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n",
383 RREG32(mmSRBM_STATUS));
384 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n",
385 RREG32(mmSRBM_STATUS2));
386 dev_info(adev->dev, " INTERRUPT_CNTL=0x%08X\n",
387 RREG32(mmINTERRUPT_CNTL));
388 dev_info(adev->dev, " INTERRUPT_CNTL2=0x%08X\n",
389 RREG32(mmINTERRUPT_CNTL2));
390 dev_info(adev->dev, " IH_CNTL=0x%08X\n",
391 RREG32(mmIH_CNTL));
392 dev_info(adev->dev, " IH_RB_CNTL=0x%08X\n",
393 RREG32(mmIH_RB_CNTL));
394 dev_info(adev->dev, " IH_RB_BASE=0x%08X\n",
395 RREG32(mmIH_RB_BASE));
396 dev_info(adev->dev, " IH_RB_WPTR_ADDR_LO=0x%08X\n",
397 RREG32(mmIH_RB_WPTR_ADDR_LO));
398 dev_info(adev->dev, " IH_RB_WPTR_ADDR_HI=0x%08X\n",
399 RREG32(mmIH_RB_WPTR_ADDR_HI));
400 dev_info(adev->dev, " IH_RB_RPTR=0x%08X\n",
401 RREG32(mmIH_RB_RPTR));
402 dev_info(adev->dev, " IH_RB_WPTR=0x%08X\n",
403 RREG32(mmIH_RB_WPTR));
404}
405
406static int tonga_ih_soft_reset(void *handle) 377static int tonga_ih_soft_reset(void *handle)
407{ 378{
408 u32 srbm_soft_reset = 0; 379 u32 srbm_soft_reset = 0;
@@ -414,8 +385,6 @@ static int tonga_ih_soft_reset(void *handle)
414 SOFT_RESET_IH, 1); 385 SOFT_RESET_IH, 1);
415 386
416 if (srbm_soft_reset) { 387 if (srbm_soft_reset) {
417 tonga_ih_print_status(adev);
418
419 tmp = RREG32(mmSRBM_SOFT_RESET); 388 tmp = RREG32(mmSRBM_SOFT_RESET);
420 tmp |= srbm_soft_reset; 389 tmp |= srbm_soft_reset;
421 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 390 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -430,8 +399,6 @@ static int tonga_ih_soft_reset(void *handle)
430 399
431 /* Wait a little for things to settle down */ 400 /* Wait a little for things to settle down */
432 udelay(50); 401 udelay(50);
433
434 tonga_ih_print_status(adev);
435 } 402 }
436 403
437 return 0; 404 return 0;
@@ -461,7 +428,6 @@ const struct amd_ip_funcs tonga_ih_ip_funcs = {
461 .is_idle = tonga_ih_is_idle, 428 .is_idle = tonga_ih_is_idle,
462 .wait_for_idle = tonga_ih_wait_for_idle, 429 .wait_for_idle = tonga_ih_wait_for_idle,
463 .soft_reset = tonga_ih_soft_reset, 430 .soft_reset = tonga_ih_soft_reset,
464 .print_status = tonga_ih_print_status,
465 .set_clockgating_state = tonga_ih_set_clockgating_state, 431 .set_clockgating_state = tonga_ih_set_clockgating_state,
466 .set_powergating_state = tonga_ih_set_powergating_state, 432 .set_powergating_state = tonga_ih_set_powergating_state,
467}; 433};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index c257cfae61c0..abd37a7eb4c6 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -680,117 +680,6 @@ static int uvd_v4_2_soft_reset(void *handle)
680 return uvd_v4_2_start(adev); 680 return uvd_v4_2_start(adev);
681} 681}
682 682
683static void uvd_v4_2_print_status(void *handle)
684{
685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
686 dev_info(adev->dev, "UVD 4.2 registers\n");
687 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
688 RREG32(mmUVD_SEMA_ADDR_LOW));
689 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
690 RREG32(mmUVD_SEMA_ADDR_HIGH));
691 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
692 RREG32(mmUVD_SEMA_CMD));
693 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
694 RREG32(mmUVD_GPCOM_VCPU_CMD));
695 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
696 RREG32(mmUVD_GPCOM_VCPU_DATA0));
697 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
698 RREG32(mmUVD_GPCOM_VCPU_DATA1));
699 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
700 RREG32(mmUVD_ENGINE_CNTL));
701 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
702 RREG32(mmUVD_UDEC_ADDR_CONFIG));
703 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
704 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
705 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
706 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
707 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
708 RREG32(mmUVD_SEMA_CNTL));
709 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
710 RREG32(mmUVD_LMI_EXT40_ADDR));
711 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
712 RREG32(mmUVD_CTX_INDEX));
713 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
714 RREG32(mmUVD_CTX_DATA));
715 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
716 RREG32(mmUVD_CGC_GATE));
717 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
718 RREG32(mmUVD_CGC_CTRL));
719 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
720 RREG32(mmUVD_LMI_CTRL2));
721 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
722 RREG32(mmUVD_MASTINT_EN));
723 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
724 RREG32(mmUVD_LMI_ADDR_EXT));
725 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
726 RREG32(mmUVD_LMI_CTRL));
727 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
728 RREG32(mmUVD_LMI_SWAP_CNTL));
729 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
730 RREG32(mmUVD_MP_SWAP_CNTL));
731 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
732 RREG32(mmUVD_MPC_SET_MUXA0));
733 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
734 RREG32(mmUVD_MPC_SET_MUXA1));
735 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
736 RREG32(mmUVD_MPC_SET_MUXB0));
737 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
738 RREG32(mmUVD_MPC_SET_MUXB1));
739 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
740 RREG32(mmUVD_MPC_SET_MUX));
741 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
742 RREG32(mmUVD_MPC_SET_ALU));
743 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
744 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
745 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
746 RREG32(mmUVD_VCPU_CACHE_SIZE0));
747 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
748 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
749 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
750 RREG32(mmUVD_VCPU_CACHE_SIZE1));
751 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
752 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
753 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
754 RREG32(mmUVD_VCPU_CACHE_SIZE2));
755 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
756 RREG32(mmUVD_VCPU_CNTL));
757 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
758 RREG32(mmUVD_SOFT_RESET));
759 dev_info(adev->dev, " UVD_RBC_IB_BASE=0x%08X\n",
760 RREG32(mmUVD_RBC_IB_BASE));
761 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
762 RREG32(mmUVD_RBC_IB_SIZE));
763 dev_info(adev->dev, " UVD_RBC_RB_BASE=0x%08X\n",
764 RREG32(mmUVD_RBC_RB_BASE));
765 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
766 RREG32(mmUVD_RBC_RB_RPTR));
767 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
768 RREG32(mmUVD_RBC_RB_WPTR));
769 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
770 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
771 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
772 RREG32(mmUVD_RBC_RB_CNTL));
773 dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
774 RREG32(mmUVD_STATUS));
775 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
776 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
777 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
778 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
779 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
780 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
781 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
782 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
783 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
784 RREG32(mmUVD_CONTEXT_ID));
785 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
786 RREG32(mmUVD_UDEC_ADDR_CONFIG));
787 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
788 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
789 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
790 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
791
792}
793
794static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev, 683static int uvd_v4_2_set_interrupt_state(struct amdgpu_device *adev,
795 struct amdgpu_irq_src *source, 684 struct amdgpu_irq_src *source,
796 unsigned type, 685 unsigned type,
@@ -861,7 +750,6 @@ const struct amd_ip_funcs uvd_v4_2_ip_funcs = {
861 .is_idle = uvd_v4_2_is_idle, 750 .is_idle = uvd_v4_2_is_idle,
862 .wait_for_idle = uvd_v4_2_wait_for_idle, 751 .wait_for_idle = uvd_v4_2_wait_for_idle,
863 .soft_reset = uvd_v4_2_soft_reset, 752 .soft_reset = uvd_v4_2_soft_reset,
864 .print_status = uvd_v4_2_print_status,
865 .set_clockgating_state = uvd_v4_2_set_clockgating_state, 753 .set_clockgating_state = uvd_v4_2_set_clockgating_state,
866 .set_powergating_state = uvd_v4_2_set_powergating_state, 754 .set_powergating_state = uvd_v4_2_set_powergating_state,
867}; 755};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index 5f0d4f76e228..1c1a0e2c7e0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -624,120 +624,6 @@ static int uvd_v5_0_soft_reset(void *handle)
624 return uvd_v5_0_start(adev); 624 return uvd_v5_0_start(adev);
625} 625}
626 626
627static void uvd_v5_0_print_status(void *handle)
628{
629 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
630 dev_info(adev->dev, "UVD 5.0 registers\n");
631 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
632 RREG32(mmUVD_SEMA_ADDR_LOW));
633 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
634 RREG32(mmUVD_SEMA_ADDR_HIGH));
635 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
636 RREG32(mmUVD_SEMA_CMD));
637 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
638 RREG32(mmUVD_GPCOM_VCPU_CMD));
639 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
640 RREG32(mmUVD_GPCOM_VCPU_DATA0));
641 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
642 RREG32(mmUVD_GPCOM_VCPU_DATA1));
643 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
644 RREG32(mmUVD_ENGINE_CNTL));
645 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
646 RREG32(mmUVD_UDEC_ADDR_CONFIG));
647 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
648 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
649 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
650 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
651 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
652 RREG32(mmUVD_SEMA_CNTL));
653 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
654 RREG32(mmUVD_LMI_EXT40_ADDR));
655 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
656 RREG32(mmUVD_CTX_INDEX));
657 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
658 RREG32(mmUVD_CTX_DATA));
659 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
660 RREG32(mmUVD_CGC_GATE));
661 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
662 RREG32(mmUVD_CGC_CTRL));
663 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
664 RREG32(mmUVD_LMI_CTRL2));
665 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
666 RREG32(mmUVD_MASTINT_EN));
667 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
668 RREG32(mmUVD_LMI_ADDR_EXT));
669 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
670 RREG32(mmUVD_LMI_CTRL));
671 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
672 RREG32(mmUVD_LMI_SWAP_CNTL));
673 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
674 RREG32(mmUVD_MP_SWAP_CNTL));
675 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
676 RREG32(mmUVD_MPC_SET_MUXA0));
677 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
678 RREG32(mmUVD_MPC_SET_MUXA1));
679 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
680 RREG32(mmUVD_MPC_SET_MUXB0));
681 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
682 RREG32(mmUVD_MPC_SET_MUXB1));
683 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
684 RREG32(mmUVD_MPC_SET_MUX));
685 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
686 RREG32(mmUVD_MPC_SET_ALU));
687 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
688 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
689 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
690 RREG32(mmUVD_VCPU_CACHE_SIZE0));
691 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
692 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
693 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
694 RREG32(mmUVD_VCPU_CACHE_SIZE1));
695 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
696 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
697 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
698 RREG32(mmUVD_VCPU_CACHE_SIZE2));
699 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
700 RREG32(mmUVD_VCPU_CNTL));
701 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
702 RREG32(mmUVD_SOFT_RESET));
703 dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_LOW=0x%08X\n",
704 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW));
705 dev_info(adev->dev, " UVD_LMI_RBC_IB_64BIT_BAR_HIGH=0x%08X\n",
706 RREG32(mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH));
707 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
708 RREG32(mmUVD_RBC_IB_SIZE));
709 dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_LOW=0x%08X\n",
710 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW));
711 dev_info(adev->dev, " UVD_LMI_RBC_RB_64BIT_BAR_HIGH=0x%08X\n",
712 RREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH));
713 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
714 RREG32(mmUVD_RBC_RB_RPTR));
715 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
716 RREG32(mmUVD_RBC_RB_WPTR));
717 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
718 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
719 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
720 RREG32(mmUVD_RBC_RB_CNTL));
721 dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
722 RREG32(mmUVD_STATUS));
723 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
724 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
725 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
726 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
727 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
728 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
729 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
730 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
731 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
732 RREG32(mmUVD_CONTEXT_ID));
733 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
734 RREG32(mmUVD_UDEC_ADDR_CONFIG));
735 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
736 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
737 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
738 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
739}
740
741static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev, 627static int uvd_v5_0_set_interrupt_state(struct amdgpu_device *adev,
742 struct amdgpu_irq_src *source, 628 struct amdgpu_irq_src *source,
743 unsigned type, 629 unsigned type,
@@ -916,7 +802,6 @@ const struct amd_ip_funcs uvd_v5_0_ip_funcs = {
916 .is_idle = uvd_v5_0_is_idle, 802 .is_idle = uvd_v5_0_is_idle,
917 .wait_for_idle = uvd_v5_0_wait_for_idle, 803 .wait_for_idle = uvd_v5_0_wait_for_idle,
918 .soft_reset = uvd_v5_0_soft_reset, 804 .soft_reset = uvd_v5_0_soft_reset,
919 .print_status = uvd_v5_0_print_status,
920 .set_clockgating_state = uvd_v5_0_set_clockgating_state, 805 .set_clockgating_state = uvd_v5_0_set_clockgating_state,
921 .set_powergating_state = uvd_v5_0_set_powergating_state, 806 .set_powergating_state = uvd_v5_0_set_powergating_state,
922}; 807};
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 7e7c3dad4c84..5665a4fd09ce 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -706,112 +706,6 @@ static int uvd_v6_0_soft_reset(void *handle)
706 return uvd_v6_0_start(adev); 706 return uvd_v6_0_start(adev);
707} 707}
708 708
709static void uvd_v6_0_print_status(void *handle)
710{
711 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
712 dev_info(adev->dev, "UVD 6.0 registers\n");
713 dev_info(adev->dev, " UVD_SEMA_ADDR_LOW=0x%08X\n",
714 RREG32(mmUVD_SEMA_ADDR_LOW));
715 dev_info(adev->dev, " UVD_SEMA_ADDR_HIGH=0x%08X\n",
716 RREG32(mmUVD_SEMA_ADDR_HIGH));
717 dev_info(adev->dev, " UVD_SEMA_CMD=0x%08X\n",
718 RREG32(mmUVD_SEMA_CMD));
719 dev_info(adev->dev, " UVD_GPCOM_VCPU_CMD=0x%08X\n",
720 RREG32(mmUVD_GPCOM_VCPU_CMD));
721 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA0=0x%08X\n",
722 RREG32(mmUVD_GPCOM_VCPU_DATA0));
723 dev_info(adev->dev, " UVD_GPCOM_VCPU_DATA1=0x%08X\n",
724 RREG32(mmUVD_GPCOM_VCPU_DATA1));
725 dev_info(adev->dev, " UVD_ENGINE_CNTL=0x%08X\n",
726 RREG32(mmUVD_ENGINE_CNTL));
727 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
728 RREG32(mmUVD_UDEC_ADDR_CONFIG));
729 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
730 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
731 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
732 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
733 dev_info(adev->dev, " UVD_SEMA_CNTL=0x%08X\n",
734 RREG32(mmUVD_SEMA_CNTL));
735 dev_info(adev->dev, " UVD_LMI_EXT40_ADDR=0x%08X\n",
736 RREG32(mmUVD_LMI_EXT40_ADDR));
737 dev_info(adev->dev, " UVD_CTX_INDEX=0x%08X\n",
738 RREG32(mmUVD_CTX_INDEX));
739 dev_info(adev->dev, " UVD_CTX_DATA=0x%08X\n",
740 RREG32(mmUVD_CTX_DATA));
741 dev_info(adev->dev, " UVD_CGC_GATE=0x%08X\n",
742 RREG32(mmUVD_CGC_GATE));
743 dev_info(adev->dev, " UVD_CGC_CTRL=0x%08X\n",
744 RREG32(mmUVD_CGC_CTRL));
745 dev_info(adev->dev, " UVD_LMI_CTRL2=0x%08X\n",
746 RREG32(mmUVD_LMI_CTRL2));
747 dev_info(adev->dev, " UVD_MASTINT_EN=0x%08X\n",
748 RREG32(mmUVD_MASTINT_EN));
749 dev_info(adev->dev, " UVD_LMI_ADDR_EXT=0x%08X\n",
750 RREG32(mmUVD_LMI_ADDR_EXT));
751 dev_info(adev->dev, " UVD_LMI_CTRL=0x%08X\n",
752 RREG32(mmUVD_LMI_CTRL));
753 dev_info(adev->dev, " UVD_LMI_SWAP_CNTL=0x%08X\n",
754 RREG32(mmUVD_LMI_SWAP_CNTL));
755 dev_info(adev->dev, " UVD_MP_SWAP_CNTL=0x%08X\n",
756 RREG32(mmUVD_MP_SWAP_CNTL));
757 dev_info(adev->dev, " UVD_MPC_SET_MUXA0=0x%08X\n",
758 RREG32(mmUVD_MPC_SET_MUXA0));
759 dev_info(adev->dev, " UVD_MPC_SET_MUXA1=0x%08X\n",
760 RREG32(mmUVD_MPC_SET_MUXA1));
761 dev_info(adev->dev, " UVD_MPC_SET_MUXB0=0x%08X\n",
762 RREG32(mmUVD_MPC_SET_MUXB0));
763 dev_info(adev->dev, " UVD_MPC_SET_MUXB1=0x%08X\n",
764 RREG32(mmUVD_MPC_SET_MUXB1));
765 dev_info(adev->dev, " UVD_MPC_SET_MUX=0x%08X\n",
766 RREG32(mmUVD_MPC_SET_MUX));
767 dev_info(adev->dev, " UVD_MPC_SET_ALU=0x%08X\n",
768 RREG32(mmUVD_MPC_SET_ALU));
769 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET0=0x%08X\n",
770 RREG32(mmUVD_VCPU_CACHE_OFFSET0));
771 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE0=0x%08X\n",
772 RREG32(mmUVD_VCPU_CACHE_SIZE0));
773 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET1=0x%08X\n",
774 RREG32(mmUVD_VCPU_CACHE_OFFSET1));
775 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE1=0x%08X\n",
776 RREG32(mmUVD_VCPU_CACHE_SIZE1));
777 dev_info(adev->dev, " UVD_VCPU_CACHE_OFFSET2=0x%08X\n",
778 RREG32(mmUVD_VCPU_CACHE_OFFSET2));
779 dev_info(adev->dev, " UVD_VCPU_CACHE_SIZE2=0x%08X\n",
780 RREG32(mmUVD_VCPU_CACHE_SIZE2));
781 dev_info(adev->dev, " UVD_VCPU_CNTL=0x%08X\n",
782 RREG32(mmUVD_VCPU_CNTL));
783 dev_info(adev->dev, " UVD_SOFT_RESET=0x%08X\n",
784 RREG32(mmUVD_SOFT_RESET));
785 dev_info(adev->dev, " UVD_RBC_IB_SIZE=0x%08X\n",
786 RREG32(mmUVD_RBC_IB_SIZE));
787 dev_info(adev->dev, " UVD_RBC_RB_RPTR=0x%08X\n",
788 RREG32(mmUVD_RBC_RB_RPTR));
789 dev_info(adev->dev, " UVD_RBC_RB_WPTR=0x%08X\n",
790 RREG32(mmUVD_RBC_RB_WPTR));
791 dev_info(adev->dev, " UVD_RBC_RB_WPTR_CNTL=0x%08X\n",
792 RREG32(mmUVD_RBC_RB_WPTR_CNTL));
793 dev_info(adev->dev, " UVD_RBC_RB_CNTL=0x%08X\n",
794 RREG32(mmUVD_RBC_RB_CNTL));
795 dev_info(adev->dev, " UVD_STATUS=0x%08X\n",
796 RREG32(mmUVD_STATUS));
797 dev_info(adev->dev, " UVD_SEMA_TIMEOUT_STATUS=0x%08X\n",
798 RREG32(mmUVD_SEMA_TIMEOUT_STATUS));
799 dev_info(adev->dev, " UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
800 RREG32(mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL));
801 dev_info(adev->dev, " UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL=0x%08X\n",
802 RREG32(mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL));
803 dev_info(adev->dev, " UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL=0x%08X\n",
804 RREG32(mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL));
805 dev_info(adev->dev, " UVD_CONTEXT_ID=0x%08X\n",
806 RREG32(mmUVD_CONTEXT_ID));
807 dev_info(adev->dev, " UVD_UDEC_ADDR_CONFIG=0x%08X\n",
808 RREG32(mmUVD_UDEC_ADDR_CONFIG));
809 dev_info(adev->dev, " UVD_UDEC_DB_ADDR_CONFIG=0x%08X\n",
810 RREG32(mmUVD_UDEC_DB_ADDR_CONFIG));
811 dev_info(adev->dev, " UVD_UDEC_DBW_ADDR_CONFIG=0x%08X\n",
812 RREG32(mmUVD_UDEC_DBW_ADDR_CONFIG));
813}
814
815static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev, 709static int uvd_v6_0_set_interrupt_state(struct amdgpu_device *adev,
816 struct amdgpu_irq_src *source, 710 struct amdgpu_irq_src *source,
817 unsigned type, 711 unsigned type,
@@ -993,7 +887,6 @@ const struct amd_ip_funcs uvd_v6_0_ip_funcs = {
993 .is_idle = uvd_v6_0_is_idle, 887 .is_idle = uvd_v6_0_is_idle,
994 .wait_for_idle = uvd_v6_0_wait_for_idle, 888 .wait_for_idle = uvd_v6_0_wait_for_idle,
995 .soft_reset = uvd_v6_0_soft_reset, 889 .soft_reset = uvd_v6_0_soft_reset,
996 .print_status = uvd_v6_0_print_status,
997 .set_clockgating_state = uvd_v6_0_set_clockgating_state, 890 .set_clockgating_state = uvd_v6_0_set_clockgating_state,
998 .set_powergating_state = uvd_v6_0_set_powergating_state, 891 .set_powergating_state = uvd_v6_0_set_powergating_state,
999}; 892};
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
index ab9ee2ad5f86..95f6e579427d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
@@ -495,75 +495,6 @@ static int vce_v2_0_soft_reset(void *handle)
495 return vce_v2_0_start(adev); 495 return vce_v2_0_start(adev);
496} 496}
497 497
498static void vce_v2_0_print_status(void *handle)
499{
500 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
501
502 dev_info(adev->dev, "VCE 2.0 registers\n");
503 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
504 RREG32(mmVCE_STATUS));
505 dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
506 RREG32(mmVCE_VCPU_CNTL));
507 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
508 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
509 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
510 RREG32(mmVCE_VCPU_CACHE_SIZE0));
511 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
512 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
513 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
514 RREG32(mmVCE_VCPU_CACHE_SIZE1));
515 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
516 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
517 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
518 RREG32(mmVCE_VCPU_CACHE_SIZE2));
519 dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
520 RREG32(mmVCE_SOFT_RESET));
521 dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
522 RREG32(mmVCE_RB_BASE_LO2));
523 dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
524 RREG32(mmVCE_RB_BASE_HI2));
525 dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
526 RREG32(mmVCE_RB_SIZE2));
527 dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
528 RREG32(mmVCE_RB_RPTR2));
529 dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
530 RREG32(mmVCE_RB_WPTR2));
531 dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
532 RREG32(mmVCE_RB_BASE_LO));
533 dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
534 RREG32(mmVCE_RB_BASE_HI));
535 dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
536 RREG32(mmVCE_RB_SIZE));
537 dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
538 RREG32(mmVCE_RB_RPTR));
539 dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
540 RREG32(mmVCE_RB_WPTR));
541 dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
542 RREG32(mmVCE_CLOCK_GATING_A));
543 dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
544 RREG32(mmVCE_CLOCK_GATING_B));
545 dev_info(adev->dev, " VCE_CGTT_CLK_OVERRIDE=0x%08X\n",
546 RREG32(mmVCE_CGTT_CLK_OVERRIDE));
547 dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
548 RREG32(mmVCE_UENC_CLOCK_GATING));
549 dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
550 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
551 dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
552 RREG32(mmVCE_SYS_INT_EN));
553 dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
554 RREG32(mmVCE_LMI_CTRL2));
555 dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
556 RREG32(mmVCE_LMI_CTRL));
557 dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
558 RREG32(mmVCE_LMI_VM_CTRL));
559 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
560 RREG32(mmVCE_LMI_SWAP_CNTL));
561 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
562 RREG32(mmVCE_LMI_SWAP_CNTL1));
563 dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
564 RREG32(mmVCE_LMI_CACHE_CTRL));
565}
566
567static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev, 498static int vce_v2_0_set_interrupt_state(struct amdgpu_device *adev,
568 struct amdgpu_irq_src *source, 499 struct amdgpu_irq_src *source,
569 unsigned type, 500 unsigned type,
@@ -647,7 +578,6 @@ const struct amd_ip_funcs vce_v2_0_ip_funcs = {
647 .is_idle = vce_v2_0_is_idle, 578 .is_idle = vce_v2_0_is_idle,
648 .wait_for_idle = vce_v2_0_wait_for_idle, 579 .wait_for_idle = vce_v2_0_wait_for_idle,
649 .soft_reset = vce_v2_0_soft_reset, 580 .soft_reset = vce_v2_0_soft_reset,
650 .print_status = vce_v2_0_print_status,
651 .set_clockgating_state = vce_v2_0_set_clockgating_state, 581 .set_clockgating_state = vce_v2_0_set_clockgating_state,
652 .set_powergating_state = vce_v2_0_set_powergating_state, 582 .set_powergating_state = vce_v2_0_set_powergating_state,
653}; 583};
diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index 58342853b69c..e1d6ae7e1629 100644
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -566,73 +566,6 @@ static int vce_v3_0_soft_reset(void *handle)
566 return vce_v3_0_start(adev); 566 return vce_v3_0_start(adev);
567} 567}
568 568
569static void vce_v3_0_print_status(void *handle)
570{
571 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
572
573 dev_info(adev->dev, "VCE 3.0 registers\n");
574 dev_info(adev->dev, " VCE_STATUS=0x%08X\n",
575 RREG32(mmVCE_STATUS));
576 dev_info(adev->dev, " VCE_VCPU_CNTL=0x%08X\n",
577 RREG32(mmVCE_VCPU_CNTL));
578 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET0=0x%08X\n",
579 RREG32(mmVCE_VCPU_CACHE_OFFSET0));
580 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE0=0x%08X\n",
581 RREG32(mmVCE_VCPU_CACHE_SIZE0));
582 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET1=0x%08X\n",
583 RREG32(mmVCE_VCPU_CACHE_OFFSET1));
584 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE1=0x%08X\n",
585 RREG32(mmVCE_VCPU_CACHE_SIZE1));
586 dev_info(adev->dev, " VCE_VCPU_CACHE_OFFSET2=0x%08X\n",
587 RREG32(mmVCE_VCPU_CACHE_OFFSET2));
588 dev_info(adev->dev, " VCE_VCPU_CACHE_SIZE2=0x%08X\n",
589 RREG32(mmVCE_VCPU_CACHE_SIZE2));
590 dev_info(adev->dev, " VCE_SOFT_RESET=0x%08X\n",
591 RREG32(mmVCE_SOFT_RESET));
592 dev_info(adev->dev, " VCE_RB_BASE_LO2=0x%08X\n",
593 RREG32(mmVCE_RB_BASE_LO2));
594 dev_info(adev->dev, " VCE_RB_BASE_HI2=0x%08X\n",
595 RREG32(mmVCE_RB_BASE_HI2));
596 dev_info(adev->dev, " VCE_RB_SIZE2=0x%08X\n",
597 RREG32(mmVCE_RB_SIZE2));
598 dev_info(adev->dev, " VCE_RB_RPTR2=0x%08X\n",
599 RREG32(mmVCE_RB_RPTR2));
600 dev_info(adev->dev, " VCE_RB_WPTR2=0x%08X\n",
601 RREG32(mmVCE_RB_WPTR2));
602 dev_info(adev->dev, " VCE_RB_BASE_LO=0x%08X\n",
603 RREG32(mmVCE_RB_BASE_LO));
604 dev_info(adev->dev, " VCE_RB_BASE_HI=0x%08X\n",
605 RREG32(mmVCE_RB_BASE_HI));
606 dev_info(adev->dev, " VCE_RB_SIZE=0x%08X\n",
607 RREG32(mmVCE_RB_SIZE));
608 dev_info(adev->dev, " VCE_RB_RPTR=0x%08X\n",
609 RREG32(mmVCE_RB_RPTR));
610 dev_info(adev->dev, " VCE_RB_WPTR=0x%08X\n",
611 RREG32(mmVCE_RB_WPTR));
612 dev_info(adev->dev, " VCE_CLOCK_GATING_A=0x%08X\n",
613 RREG32(mmVCE_CLOCK_GATING_A));
614 dev_info(adev->dev, " VCE_CLOCK_GATING_B=0x%08X\n",
615 RREG32(mmVCE_CLOCK_GATING_B));
616 dev_info(adev->dev, " VCE_UENC_CLOCK_GATING=0x%08X\n",
617 RREG32(mmVCE_UENC_CLOCK_GATING));
618 dev_info(adev->dev, " VCE_UENC_REG_CLOCK_GATING=0x%08X\n",
619 RREG32(mmVCE_UENC_REG_CLOCK_GATING));
620 dev_info(adev->dev, " VCE_SYS_INT_EN=0x%08X\n",
621 RREG32(mmVCE_SYS_INT_EN));
622 dev_info(adev->dev, " VCE_LMI_CTRL2=0x%08X\n",
623 RREG32(mmVCE_LMI_CTRL2));
624 dev_info(adev->dev, " VCE_LMI_CTRL=0x%08X\n",
625 RREG32(mmVCE_LMI_CTRL));
626 dev_info(adev->dev, " VCE_LMI_VM_CTRL=0x%08X\n",
627 RREG32(mmVCE_LMI_VM_CTRL));
628 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL=0x%08X\n",
629 RREG32(mmVCE_LMI_SWAP_CNTL));
630 dev_info(adev->dev, " VCE_LMI_SWAP_CNTL1=0x%08X\n",
631 RREG32(mmVCE_LMI_SWAP_CNTL1));
632 dev_info(adev->dev, " VCE_LMI_CACHE_CTRL=0x%08X\n",
633 RREG32(mmVCE_LMI_CACHE_CTRL));
634}
635
636static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, 569static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev,
637 struct amdgpu_irq_src *source, 570 struct amdgpu_irq_src *source,
638 unsigned type, 571 unsigned type,
@@ -752,7 +685,6 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = {
752 .is_idle = vce_v3_0_is_idle, 685 .is_idle = vce_v3_0_is_idle,
753 .wait_for_idle = vce_v3_0_wait_for_idle, 686 .wait_for_idle = vce_v3_0_wait_for_idle,
754 .soft_reset = vce_v3_0_soft_reset, 687 .soft_reset = vce_v3_0_soft_reset,
755 .print_status = vce_v3_0_print_status,
756 .set_clockgating_state = vce_v3_0_set_clockgating_state, 688 .set_clockgating_state = vce_v3_0_set_clockgating_state,
757 .set_powergating_state = vce_v3_0_set_powergating_state, 689 .set_powergating_state = vce_v3_0_set_powergating_state,
758}; 690};
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 0bd567d339a3..340a166da911 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1295,11 +1295,6 @@ static int vi_common_wait_for_idle(void *handle)
1295 return 0; 1295 return 0;
1296} 1296}
1297 1297
1298static void vi_common_print_status(void *handle)
1299{
1300 return;
1301}
1302
1303static int vi_common_soft_reset(void *handle) 1298static int vi_common_soft_reset(void *handle)
1304{ 1299{
1305 return 0; 1300 return 0;
@@ -1424,7 +1419,6 @@ const struct amd_ip_funcs vi_common_ip_funcs = {
1424 .is_idle = vi_common_is_idle, 1419 .is_idle = vi_common_is_idle,
1425 .wait_for_idle = vi_common_wait_for_idle, 1420 .wait_for_idle = vi_common_wait_for_idle,
1426 .soft_reset = vi_common_soft_reset, 1421 .soft_reset = vi_common_soft_reset,
1427 .print_status = vi_common_print_status,
1428 .set_clockgating_state = vi_common_set_clockgating_state, 1422 .set_clockgating_state = vi_common_set_clockgating_state,
1429 .set_powergating_state = vi_common_set_powergating_state, 1423 .set_powergating_state = vi_common_set_powergating_state,
1430}; 1424};
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index e56d8a378570..ea9ee4644139 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -165,8 +165,6 @@ struct amd_ip_funcs {
165 int (*wait_for_idle)(void *handle); 165 int (*wait_for_idle)(void *handle);
166 /* soft reset the IP block */ 166 /* soft reset the IP block */
167 int (*soft_reset)(void *handle); 167 int (*soft_reset)(void *handle);
168 /* dump the IP block status registers */
169 void (*print_status)(void *handle);
170 /* enable/disable cg for the IP block */ 168 /* enable/disable cg for the IP block */
171 int (*set_clockgating_state)(void *handle, 169 int (*set_clockgating_state)(void *handle,
172 enum amd_clockgating_state state); 170 enum amd_clockgating_state state);
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
index 0527ae3d10f9..aba587cfce81 100644
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c
@@ -180,10 +180,6 @@ static int pp_sw_reset(void *handle)
180 return 0; 180 return 0;
181} 181}
182 182
183static void pp_print_status(void *handle)
184{
185
186}
187 183
188static int pp_set_clockgating_state(void *handle, 184static int pp_set_clockgating_state(void *handle,
189 enum amd_clockgating_state state) 185 enum amd_clockgating_state state)
@@ -355,7 +351,6 @@ const struct amd_ip_funcs pp_ip_funcs = {
355 .is_idle = pp_is_idle, 351 .is_idle = pp_is_idle,
356 .wait_for_idle = pp_wait_for_idle, 352 .wait_for_idle = pp_wait_for_idle,
357 .soft_reset = pp_sw_reset, 353 .soft_reset = pp_sw_reset,
358 .print_status = pp_print_status,
359 .set_clockgating_state = pp_set_clockgating_state, 354 .set_clockgating_state = pp_set_clockgating_state,
360 .set_powergating_state = pp_set_powergating_state, 355 .set_powergating_state = pp_set_powergating_state,
361}; 356};
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-13 12:52:35 -0400