diff options
author | Grygorii Strashko <grygorii.strashko@ti.com> | 2015-10-01 15:20:37 -0400 |
---|---|---|
committer | Tero Kristo <t-kristo@ti.com> | 2015-11-24 04:30:27 -0500 |
commit | 167af5ef2cdba14ff14a13c91e5532ed479083d8 (patch) | |
tree | 89867e7fc6d21bf446607e31c1213554a710f69f | |
parent | 3a5b1dc4a3237870cfb53d31bc4cbc2a9c7aa16e (diff) |
clk: ti: drop locking code from mux/divider drivers
TI's mux and divider clock drivers do not require locking and they do
not initialize internal spinlocks. This code was occasionally
copy-posted from generic mux/divider drivers. So remove it.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
-rw-r--r-- | drivers/clk/ti/divider.c | 16 | ||||
-rw-r--r-- | drivers/clk/ti/mux.c | 15 |
2 files changed, 6 insertions, 25 deletions
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index 5b1726829e6d..df2558350fc1 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c | |||
@@ -214,7 +214,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
214 | { | 214 | { |
215 | struct clk_divider *divider; | 215 | struct clk_divider *divider; |
216 | unsigned int div, value; | 216 | unsigned int div, value; |
217 | unsigned long flags = 0; | ||
218 | u32 val; | 217 | u32 val; |
219 | 218 | ||
220 | if (!hw || !rate) | 219 | if (!hw || !rate) |
@@ -228,9 +227,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
228 | if (value > div_mask(divider)) | 227 | if (value > div_mask(divider)) |
229 | value = div_mask(divider); | 228 | value = div_mask(divider); |
230 | 229 | ||
231 | if (divider->lock) | ||
232 | spin_lock_irqsave(divider->lock, flags); | ||
233 | |||
234 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { | 230 | if (divider->flags & CLK_DIVIDER_HIWORD_MASK) { |
235 | val = div_mask(divider) << (divider->shift + 16); | 231 | val = div_mask(divider) << (divider->shift + 16); |
236 | } else { | 232 | } else { |
@@ -240,9 +236,6 @@ static int ti_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate, | |||
240 | val |= value << divider->shift; | 236 | val |= value << divider->shift; |
241 | ti_clk_ll_ops->clk_writel(val, divider->reg); | 237 | ti_clk_ll_ops->clk_writel(val, divider->reg); |
242 | 238 | ||
243 | if (divider->lock) | ||
244 | spin_unlock_irqrestore(divider->lock, flags); | ||
245 | |||
246 | return 0; | 239 | return 0; |
247 | } | 240 | } |
248 | 241 | ||
@@ -256,8 +249,7 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
256 | const char *parent_name, | 249 | const char *parent_name, |
257 | unsigned long flags, void __iomem *reg, | 250 | unsigned long flags, void __iomem *reg, |
258 | u8 shift, u8 width, u8 clk_divider_flags, | 251 | u8 shift, u8 width, u8 clk_divider_flags, |
259 | const struct clk_div_table *table, | 252 | const struct clk_div_table *table) |
260 | spinlock_t *lock) | ||
261 | { | 253 | { |
262 | struct clk_divider *div; | 254 | struct clk_divider *div; |
263 | struct clk *clk; | 255 | struct clk *clk; |
@@ -288,7 +280,6 @@ static struct clk *_register_divider(struct device *dev, const char *name, | |||
288 | div->shift = shift; | 280 | div->shift = shift; |
289 | div->width = width; | 281 | div->width = width; |
290 | div->flags = clk_divider_flags; | 282 | div->flags = clk_divider_flags; |
291 | div->lock = lock; | ||
292 | div->hw.init = &init; | 283 | div->hw.init = &init; |
293 | div->table = table; | 284 | div->table = table; |
294 | 285 | ||
@@ -421,7 +412,7 @@ struct clk *ti_clk_register_divider(struct ti_clk *setup) | |||
421 | 412 | ||
422 | clk = _register_divider(NULL, setup->name, div->parent, | 413 | clk = _register_divider(NULL, setup->name, div->parent, |
423 | flags, (void __iomem *)reg, div->bit_shift, | 414 | flags, (void __iomem *)reg, div->bit_shift, |
424 | width, div_flags, table, NULL); | 415 | width, div_flags, table); |
425 | 416 | ||
426 | if (IS_ERR(clk)) | 417 | if (IS_ERR(clk)) |
427 | kfree(table); | 418 | kfree(table); |
@@ -584,8 +575,7 @@ static void __init of_ti_divider_clk_setup(struct device_node *node) | |||
584 | goto cleanup; | 575 | goto cleanup; |
585 | 576 | ||
586 | clk = _register_divider(NULL, node->name, parent_name, flags, reg, | 577 | clk = _register_divider(NULL, node->name, parent_name, flags, reg, |
587 | shift, width, clk_divider_flags, table, | 578 | shift, width, clk_divider_flags, table); |
588 | NULL); | ||
589 | 579 | ||
590 | if (!IS_ERR(clk)) { | 580 | if (!IS_ERR(clk)) { |
591 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | 581 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index 69f08a1d047d..dab9ba88b9d6 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c | |||
@@ -69,7 +69,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
69 | { | 69 | { |
70 | struct clk_mux *mux = to_clk_mux(hw); | 70 | struct clk_mux *mux = to_clk_mux(hw); |
71 | u32 val; | 71 | u32 val; |
72 | unsigned long flags = 0; | ||
73 | 72 | ||
74 | if (mux->table) { | 73 | if (mux->table) { |
75 | index = mux->table[index]; | 74 | index = mux->table[index]; |
@@ -81,9 +80,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
81 | index++; | 80 | index++; |
82 | } | 81 | } |
83 | 82 | ||
84 | if (mux->lock) | ||
85 | spin_lock_irqsave(mux->lock, flags); | ||
86 | |||
87 | if (mux->flags & CLK_MUX_HIWORD_MASK) { | 83 | if (mux->flags & CLK_MUX_HIWORD_MASK) { |
88 | val = mux->mask << (mux->shift + 16); | 84 | val = mux->mask << (mux->shift + 16); |
89 | } else { | 85 | } else { |
@@ -93,9 +89,6 @@ static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index) | |||
93 | val |= index << mux->shift; | 89 | val |= index << mux->shift; |
94 | ti_clk_ll_ops->clk_writel(val, mux->reg); | 90 | ti_clk_ll_ops->clk_writel(val, mux->reg); |
95 | 91 | ||
96 | if (mux->lock) | ||
97 | spin_unlock_irqrestore(mux->lock, flags); | ||
98 | |||
99 | return 0; | 92 | return 0; |
100 | } | 93 | } |
101 | 94 | ||
@@ -109,7 +102,7 @@ static struct clk *_register_mux(struct device *dev, const char *name, | |||
109 | const char **parent_names, u8 num_parents, | 102 | const char **parent_names, u8 num_parents, |
110 | unsigned long flags, void __iomem *reg, | 103 | unsigned long flags, void __iomem *reg, |
111 | u8 shift, u32 mask, u8 clk_mux_flags, | 104 | u8 shift, u32 mask, u8 clk_mux_flags, |
112 | u32 *table, spinlock_t *lock) | 105 | u32 *table) |
113 | { | 106 | { |
114 | struct clk_mux *mux; | 107 | struct clk_mux *mux; |
115 | struct clk *clk; | 108 | struct clk *clk; |
@@ -133,7 +126,6 @@ static struct clk *_register_mux(struct device *dev, const char *name, | |||
133 | mux->shift = shift; | 126 | mux->shift = shift; |
134 | mux->mask = mask; | 127 | mux->mask = mask; |
135 | mux->flags = clk_mux_flags; | 128 | mux->flags = clk_mux_flags; |
136 | mux->lock = lock; | ||
137 | mux->table = table; | 129 | mux->table = table; |
138 | mux->hw.init = &init; | 130 | mux->hw.init = &init; |
139 | 131 | ||
@@ -175,7 +167,7 @@ struct clk *ti_clk_register_mux(struct ti_clk *setup) | |||
175 | 167 | ||
176 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, | 168 | return _register_mux(NULL, setup->name, mux->parents, mux->num_parents, |
177 | flags, (void __iomem *)reg, mux->bit_shift, mask, | 169 | flags, (void __iomem *)reg, mux->bit_shift, mask, |
178 | mux_flags, NULL, NULL); | 170 | mux_flags, NULL); |
179 | } | 171 | } |
180 | 172 | ||
181 | /** | 173 | /** |
@@ -227,8 +219,7 @@ static void of_mux_clk_setup(struct device_node *node) | |||
227 | mask = (1 << fls(mask)) - 1; | 219 | mask = (1 << fls(mask)) - 1; |
228 | 220 | ||
229 | clk = _register_mux(NULL, node->name, parent_names, num_parents, | 221 | clk = _register_mux(NULL, node->name, parent_names, num_parents, |
230 | flags, reg, shift, mask, clk_mux_flags, NULL, | 222 | flags, reg, shift, mask, clk_mux_flags, NULL); |
231 | NULL); | ||
232 | 223 | ||
233 | if (!IS_ERR(clk)) | 224 | if (!IS_ERR(clk)) |
234 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | 225 | of_clk_add_provider(node, of_clk_src_simple_get, clk); |