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authorYang Ling <gnaygnil@gmail.com>2016-05-19 00:29:30 -0400
committerRalf Baechle <ralf@linux-mips.org>2016-10-04 10:13:57 -0400
commit12e3280b33fe1ada85b84f67613d03e1b6d8dbf6 (patch)
tree64f4f14777dacb875c01400d057f532b77795f21
parenta1ca83869d4ea65afd5a6a403d5d5ec2c41ef60e (diff)
MIPS: Loongson1C: Add board support
Adds basic platform devices for Loongson1C, including serial port and ethernet. Signed-off-by: Yang Ling <gnaygnil@gmail.com> Cc: keguang.zhang@gmail.com Cc: chenhc@lemote.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/13304/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/Kconfig13
-rw-r--r--arch/mips/include/asm/mach-loongson32/irq.h41
-rw-r--r--arch/mips/include/asm/mach-loongson32/loongson1.h5
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-clk.h34
-rw-r--r--arch/mips/include/asm/mach-loongson32/regs-mux.h61
-rw-r--r--arch/mips/loongson32/Kconfig15
-rw-r--r--arch/mips/loongson32/Makefile6
-rw-r--r--arch/mips/loongson32/Platform1
-rw-r--r--arch/mips/loongson32/common/irq.c55
-rw-r--r--arch/mips/loongson32/common/platform.c19
-rw-r--r--arch/mips/loongson32/common/setup.c4
-rw-r--r--arch/mips/loongson32/ls1c/Makefile5
-rw-r--r--arch/mips/loongson32/ls1c/board.c28
13 files changed, 283 insertions, 4 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 212ff92920d2..6fba0eff858e 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1402,6 +1402,16 @@ config CPU_LOONGSON1B
1402 The Loongson 1B is a 32-bit SoC, which implements the MIPS32 1402 The Loongson 1B is a 32-bit SoC, which implements the MIPS32
1403 release 2 instruction set. 1403 release 2 instruction set.
1404 1404
1405config CPU_LOONGSON1C
1406 bool "Loongson 1C"
1407 depends on SYS_HAS_CPU_LOONGSON1C
1408 select CPU_LOONGSON1
1409 select ARCH_WANT_OPTIONAL_GPIOLIB
1410 select LEDS_GPIO_REGISTER
1411 help
1412 The Loongson 1C is a 32-bit SoC, which implements the MIPS32
1413 release 2 instruction set.
1414
1405config CPU_MIPS32_R1 1415config CPU_MIPS32_R1
1406 bool "MIPS32 Release 1" 1416 bool "MIPS32 Release 1"
1407 depends on SYS_HAS_CPU_MIPS32_R1 1417 depends on SYS_HAS_CPU_MIPS32_R1
@@ -1851,6 +1861,9 @@ config SYS_HAS_CPU_LOONGSON2F
1851config SYS_HAS_CPU_LOONGSON1B 1861config SYS_HAS_CPU_LOONGSON1B
1852 bool 1862 bool
1853 1863
1864config SYS_HAS_CPU_LOONGSON1C
1865 bool
1866
1854config SYS_HAS_CPU_MIPS32_R1 1867config SYS_HAS_CPU_MIPS32_R1
1855 bool 1868 bool
1856 1869
diff --git a/arch/mips/include/asm/mach-loongson32/irq.h b/arch/mips/include/asm/mach-loongson32/irq.h
index c1c744197de4..8c01b304b7ec 100644
--- a/arch/mips/include/asm/mach-loongson32/irq.h
+++ b/arch/mips/include/asm/mach-loongson32/irq.h
@@ -36,9 +36,14 @@
36#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x)) 36#define LS1X_IRQ(n, x) (LS1X_IRQ_BASE + (n << 5) + (x))
37 37
38#define LS1X_UART0_IRQ LS1X_IRQ(0, 2) 38#define LS1X_UART0_IRQ LS1X_IRQ(0, 2)
39#if defined(CONFIG_LOONGSON1_LS1B)
39#define LS1X_UART1_IRQ LS1X_IRQ(0, 3) 40#define LS1X_UART1_IRQ LS1X_IRQ(0, 3)
40#define LS1X_UART2_IRQ LS1X_IRQ(0, 4) 41#define LS1X_UART2_IRQ LS1X_IRQ(0, 4)
41#define LS1X_UART3_IRQ LS1X_IRQ(0, 5) 42#define LS1X_UART3_IRQ LS1X_IRQ(0, 5)
43#elif defined(CONFIG_LOONGSON1_LS1C)
44#define LS1X_UART1_IRQ LS1X_IRQ(0, 4)
45#define LS1X_UART2_IRQ LS1X_IRQ(0, 5)
46#endif
42#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6) 47#define LS1X_CAN0_IRQ LS1X_IRQ(0, 6)
43#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7) 48#define LS1X_CAN1_IRQ LS1X_IRQ(0, 7)
44#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8) 49#define LS1X_SPI0_IRQ LS1X_IRQ(0, 8)
@@ -47,6 +52,9 @@
47#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13) 52#define LS1X_DMA0_IRQ LS1X_IRQ(0, 13)
48#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14) 53#define LS1X_DMA1_IRQ LS1X_IRQ(0, 14)
49#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15) 54#define LS1X_DMA2_IRQ LS1X_IRQ(0, 15)
55#if defined(CONFIG_LOONGSON1_LS1C)
56#define LS1X_NAND_IRQ LS1X_IRQ(0, 16)
57#endif
50#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17) 58#define LS1X_PWM0_IRQ LS1X_IRQ(0, 17)
51#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18) 59#define LS1X_PWM1_IRQ LS1X_IRQ(0, 18)
52#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19) 60#define LS1X_PWM2_IRQ LS1X_IRQ(0, 19)
@@ -54,18 +62,49 @@
54#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21) 62#define LS1X_RTC_INT0_IRQ LS1X_IRQ(0, 21)
55#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22) 63#define LS1X_RTC_INT1_IRQ LS1X_IRQ(0, 22)
56#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23) 64#define LS1X_RTC_INT2_IRQ LS1X_IRQ(0, 23)
65#if defined(CONFIG_LOONGSON1_LS1B)
57#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24) 66#define LS1X_TOY_INT0_IRQ LS1X_IRQ(0, 24)
58#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25) 67#define LS1X_TOY_INT1_IRQ LS1X_IRQ(0, 25)
59#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26) 68#define LS1X_TOY_INT2_IRQ LS1X_IRQ(0, 26)
60#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27) 69#define LS1X_RTC_TICK_IRQ LS1X_IRQ(0, 27)
61#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28) 70#define LS1X_TOY_TICK_IRQ LS1X_IRQ(0, 28)
71#define LS1X_UART4_IRQ LS1X_IRQ(0, 29)
72#define LS1X_UART5_IRQ LS1X_IRQ(0, 30)
73#elif defined(CONFIG_LOONGSON1_LS1C)
74#define LS1X_UART3_IRQ LS1X_IRQ(0, 29)
75#define LS1X_ADC_IRQ LS1X_IRQ(0, 30)
76#define LS1X_SDIO_IRQ LS1X_IRQ(0, 31)
77#endif
62 78
63#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0) 79#define LS1X_EHCI_IRQ LS1X_IRQ(1, 0)
64#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1) 80#define LS1X_OHCI_IRQ LS1X_IRQ(1, 1)
81#if defined(CONFIG_LOONGSON1_LS1B)
65#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2) 82#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 2)
66#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3) 83#define LS1X_GMAC1_IRQ LS1X_IRQ(1, 3)
84#elif defined(CONFIG_LOONGSON1_LS1C)
85#define LS1X_OTG_IRQ LS1X_IRQ(1, 2)
86#define LS1X_GMAC0_IRQ LS1X_IRQ(1, 3)
87#define LS1X_CAM_IRQ LS1X_IRQ(1, 4)
88#define LS1X_UART4_IRQ LS1X_IRQ(1, 5)
89#define LS1X_UART5_IRQ LS1X_IRQ(1, 6)
90#define LS1X_UART6_IRQ LS1X_IRQ(1, 7)
91#define LS1X_UART7_IRQ LS1X_IRQ(1, 8)
92#define LS1X_UART8_IRQ LS1X_IRQ(1, 9)
93#define LS1X_UART9_IRQ LS1X_IRQ(1, 13)
94#define LS1X_UART10_IRQ LS1X_IRQ(1, 14)
95#define LS1X_UART11_IRQ LS1X_IRQ(1, 15)
96#define LS1X_I2C0_IRQ LS1X_IRQ(1, 17)
97#define LS1X_I2C1_IRQ LS1X_IRQ(1, 18)
98#define LS1X_I2C2_IRQ LS1X_IRQ(1, 19)
99#endif
67 100
68#define LS1X_IRQS (LS1X_IRQ(4, 31) + 1 - LS1X_IRQ_BASE) 101#if defined(CONFIG_LOONGSON1_LS1B)
102#define INTN 4
103#elif defined(CONFIG_LOONGSON1_LS1C)
104#define INTN 5
105#endif
106
107#define LS1X_IRQS (LS1X_IRQ(INTN, 31) + 1 - LS1X_IRQ_BASE)
69 108
70#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS) 109#define NR_IRQS (MIPS_CPU_IRQS + LS1X_IRQS)
71 110
diff --git a/arch/mips/include/asm/mach-loongson32/loongson1.h b/arch/mips/include/asm/mach-loongson32/loongson1.h
index 978f6df8970a..3584c40caf79 100644
--- a/arch/mips/include/asm/mach-loongson32/loongson1.h
+++ b/arch/mips/include/asm/mach-loongson32/loongson1.h
@@ -12,7 +12,11 @@
12#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H 12#ifndef __ASM_MACH_LOONGSON32_LOONGSON1_H
13#define __ASM_MACH_LOONGSON32_LOONGSON1_H 13#define __ASM_MACH_LOONGSON32_LOONGSON1_H
14 14
15#if defined(CONFIG_LOONGSON1_LS1B)
15#define DEFAULT_MEMSIZE 256 /* If no memsize provided */ 16#define DEFAULT_MEMSIZE 256 /* If no memsize provided */
17#elif defined(CONFIG_LOONGSON1_LS1C)
18#define DEFAULT_MEMSIZE 32
19#endif
16 20
17/* Loongson 1 Register Bases */ 21/* Loongson 1 Register Bases */
18#define LS1X_MUX_BASE 0x1fd00420 22#define LS1X_MUX_BASE 0x1fd00420
@@ -20,6 +24,7 @@
20#define LS1X_GPIO0_BASE 0x1fd010c0 24#define LS1X_GPIO0_BASE 0x1fd010c0
21#define LS1X_GPIO1_BASE 0x1fd010c4 25#define LS1X_GPIO1_BASE 0x1fd010c4
22#define LS1X_DMAC_BASE 0x1fd01160 26#define LS1X_DMAC_BASE 0x1fd01160
27#define LS1X_CBUS_BASE 0x1fd011c0
23#define LS1X_EHCI_BASE 0x1fe00000 28#define LS1X_EHCI_BASE 0x1fe00000
24#define LS1X_OHCI_BASE 0x1fe08000 29#define LS1X_OHCI_BASE 0x1fe08000
25#define LS1X_GMAC0_BASE 0x1fe10000 30#define LS1X_GMAC0_BASE 0x1fe10000
diff --git a/arch/mips/include/asm/mach-loongson32/regs-clk.h b/arch/mips/include/asm/mach-loongson32/regs-clk.h
index 4d56fc38f0c4..e5e8f118f34b 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-clk.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-clk.h
@@ -18,6 +18,7 @@
18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) 18#define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0)
19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) 19#define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4)
20 20
21#if defined(CONFIG_LOONGSON1_LS1B)
21/* Clock PLL Divisor Register Bits */ 22/* Clock PLL Divisor Register Bits */
22#define DIV_DC_EN BIT(31) 23#define DIV_DC_EN BIT(31)
23#define DIV_DC_RST BIT(30) 24#define DIV_DC_RST BIT(30)
@@ -48,4 +49,37 @@
48#define BYPASS_DDR_WIDTH 1 49#define BYPASS_DDR_WIDTH 1
49#define BYPASS_CPU_WIDTH 1 50#define BYPASS_CPU_WIDTH 1
50 51
52#elif defined(CONFIG_LOONGSON1_LS1C)
53/* PLL/SDRAM Frequency configuration register Bits */
54#define PLL_VALID BIT(31)
55#define FRAC_N GENMASK(23, 16)
56#define RST_TIME GENMASK(3, 2)
57#define SDRAM_DIV GENMASK(1, 0)
58
59/* CPU/CAMERA/DC Frequency configuration register Bits */
60#define DIV_DC_EN BIT(31)
61#define DIV_DC GENMASK(30, 24)
62#define DIV_CAM_EN BIT(23)
63#define DIV_CAM GENMASK(22, 16)
64#define DIV_CPU_EN BIT(15)
65#define DIV_CPU GENMASK(14, 8)
66#define DIV_DC_SEL_EN BIT(5)
67#define DIV_DC_SEL BIT(4)
68#define DIV_CAM_SEL_EN BIT(3)
69#define DIV_CAM_SEL BIT(2)
70#define DIV_CPU_SEL_EN BIT(1)
71#define DIV_CPU_SEL BIT(0)
72
73#define DIV_DC_SHIFT 24
74#define DIV_CAM_SHIFT 16
75#define DIV_CPU_SHIFT 8
76#define DIV_DDR_SHIFT 0
77
78#define DIV_DC_WIDTH 7
79#define DIV_CAM_WIDTH 7
80#define DIV_CPU_WIDTH 7
81#define DIV_DDR_WIDTH 2
82
83#endif
84
51#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */ 85#endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */
diff --git a/arch/mips/include/asm/mach-loongson32/regs-mux.h b/arch/mips/include/asm/mach-loongson32/regs-mux.h
index 7c394f93cb9e..4a0bdeb0eb9b 100644
--- a/arch/mips/include/asm/mach-loongson32/regs-mux.h
+++ b/arch/mips/include/asm/mach-loongson32/regs-mux.h
@@ -18,6 +18,7 @@
18#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0) 18#define LS1X_MUX_CTRL0 LS1X_MUX_REG(0x0)
19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4) 19#define LS1X_MUX_CTRL1 LS1X_MUX_REG(0x4)
20 20
21#if defined(CONFIG_LOONGSON1_LS1B)
21/* MUX CTRL0 Register Bits */ 22/* MUX CTRL0 Register Bits */
22#define UART0_USE_PWM23 BIT(28) 23#define UART0_USE_PWM23 BIT(28)
23#define UART0_USE_PWM01 BIT(27) 24#define UART0_USE_PWM01 BIT(27)
@@ -64,4 +65,64 @@
64#define GMAC1_USE_PWM23 BIT(1) 65#define GMAC1_USE_PWM23 BIT(1)
65#define GMAC0_USE_PWM01 BIT(0) 66#define GMAC0_USE_PWM01 BIT(0)
66 67
68#elif defined(CONFIG_LOONGSON1_LS1C)
69
70/* SHUT_CTRL Register Bits */
71#define UART_SPLIT GENMASK(31, 30)
72#define OUTPUT_CLK GENMASK(29, 26)
73#define ADC_SHUT BIT(25)
74#define SDIO_SHUT BIT(24)
75#define DMA2_SHUT BIT(23)
76#define DMA1_SHUT BIT(22)
77#define DMA0_SHUT BIT(21)
78#define SPI1_SHUT BIT(20)
79#define SPI0_SHUT BIT(19)
80#define I2C2_SHUT BIT(18)
81#define I2C1_SHUT BIT(17)
82#define I2C0_SHUT BIT(16)
83#define AC97_SHUT BIT(15)
84#define I2S_SHUT BIT(14)
85#define UART3_SHUT BIT(13)
86#define UART2_SHUT BIT(12)
87#define UART1_SHUT BIT(11)
88#define UART0_SHUT BIT(10)
89#define CAN1_SHUT BIT(9)
90#define CAN0_SHUT BIT(8)
91#define ECC_SHUT BIT(7)
92#define GMAC_SHUT BIT(6)
93#define USBHOST_SHUT BIT(5)
94#define USBOTG_SHUT BIT(4)
95#define SDRAM_SHUT BIT(3)
96#define SRAM_SHUT BIT(2)
97#define CAM_SHUT BIT(1)
98#define LCD_SHUT BIT(0)
99
100#define UART_SPLIT_SHIFT 30
101#define OUTPUT_CLK_SHIFT 26
102
103/* MISC_CTRL Register Bits */
104#define USBHOST_RSTN BIT(31)
105#define PHY_INTF_SELI GENMASK(30, 28)
106#define AC97_EN BIT(25)
107#define SDIO_DMA_EN GENMASK(24, 23)
108#define ADC_DMA_EN BIT(22)
109#define SDIO_USE_SPI1 BIT(17)
110#define SDIO_USE_SPI0 BIT(16)
111#define SRAM_CTRL GENMASK(15, 0)
112
113#define PHY_INTF_SELI_SHIFT 28
114#define SDIO_DMA_EN_SHIFT 23
115#define SRAM_CTRL_SHIFT 0
116
117#define LS1X_CBUS_REG(n, x) \
118 ((void __iomem *)KSEG1ADDR(LS1X_CBUS_BASE + (n * 0x04) + (x)))
119
120#define LS1X_CBUS_FIRST(n) LS1X_CBUS_REG(n, 0x00)
121#define LS1X_CBUS_SECOND(n) LS1X_CBUS_REG(n, 0x10)
122#define LS1X_CBUS_THIRD(n) LS1X_CBUS_REG(n, 0x20)
123#define LS1X_CBUS_FOURTHT(n) LS1X_CBUS_REG(n, 0x30)
124#define LS1X_CBUS_FIFTHT(n) LS1X_CBUS_REG(n, 0x40)
125
126#endif
127
67#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */ 128#endif /* __ASM_MACH_LOONGSON32_REGS_MUX_H */
diff --git a/arch/mips/loongson32/Kconfig b/arch/mips/loongson32/Kconfig
index 7704f20529d6..3c0c2f2096cd 100644
--- a/arch/mips/loongson32/Kconfig
+++ b/arch/mips/loongson32/Kconfig
@@ -19,6 +19,21 @@ config LOONGSON1_LS1B
19 select USE_GENERIC_EARLY_PRINTK_8250 19 select USE_GENERIC_EARLY_PRINTK_8250
20 select COMMON_CLK 20 select COMMON_CLK
21 21
22config LOONGSON1_LS1C
23 bool "Loongson LS1C board"
24 select CEVT_R4K if !MIPS_EXTERNAL_TIMER
25 select CSRC_R4K if !MIPS_EXTERNAL_TIMER
26 select SYS_HAS_CPU_LOONGSON1C
27 select DMA_NONCOHERENT
28 select BOOT_ELF32
29 select IRQ_MIPS_CPU
30 select SYS_SUPPORTS_32BIT_KERNEL
31 select SYS_SUPPORTS_LITTLE_ENDIAN
32 select SYS_SUPPORTS_HIGHMEM
33 select SYS_SUPPORTS_MIPS16
34 select SYS_HAS_EARLY_PRINTK
35 select USE_GENERIC_EARLY_PRINTK_8250
36 select COMMON_CLK
22endchoice 37endchoice
23 38
24menuconfig CEVT_CSRC_LS1X 39menuconfig CEVT_CSRC_LS1X
diff --git a/arch/mips/loongson32/Makefile b/arch/mips/loongson32/Makefile
index 5f4bd6e071ca..1ab2c5bbc066 100644
--- a/arch/mips/loongson32/Makefile
+++ b/arch/mips/loongson32/Makefile
@@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON32) += common/
9# 9#
10 10
11obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/ 11obj-$(CONFIG_LOONGSON1_LS1B) += ls1b/
12
13#
14# Loongson LS1C board
15#
16
17obj-$(CONFIG_LOONGSON1_LS1C) += ls1c/
diff --git a/arch/mips/loongson32/Platform b/arch/mips/loongson32/Platform
index ebb6dc290f0a..ffe01c6d0037 100644
--- a/arch/mips/loongson32/Platform
+++ b/arch/mips/loongson32/Platform
@@ -5,3 +5,4 @@ cflags-$(CONFIG_CPU_LOONGSON1) += \
5platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ 5platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
6cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32 6cflags-$(CONFIG_MACH_LOONGSON32) += -I$(srctree)/arch/mips/include/asm/mach-loongson32
7load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000 7load-$(CONFIG_LOONGSON1_LS1B) += 0xffffffff80100000
8load-$(CONFIG_LOONGSON1_LS1C) += 0xffffffff80100000
diff --git a/arch/mips/loongson32/common/irq.c b/arch/mips/loongson32/common/irq.c
index 455a7704a90f..635a4abe1f48 100644
--- a/arch/mips/loongson32/common/irq.c
+++ b/arch/mips/loongson32/common/irq.c
@@ -62,12 +62,58 @@ static void ls1x_irq_unmask(struct irq_data *d)
62 | (1 << bit), LS1X_INTC_INTIEN(n)); 62 | (1 << bit), LS1X_INTC_INTIEN(n));
63} 63}
64 64
65static int ls1x_irq_settype(struct irq_data *d, unsigned int type)
66{
67 unsigned int bit = (d->irq - LS1X_IRQ_BASE) & 0x1f;
68 unsigned int n = (d->irq - LS1X_IRQ_BASE) >> 5;
69
70 switch (type) {
71 case IRQ_TYPE_LEVEL_HIGH:
72 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
73 | (1 << bit), LS1X_INTC_INTPOL(n));
74 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
75 & ~(1 << bit), LS1X_INTC_INTEDGE(n));
76 break;
77 case IRQ_TYPE_LEVEL_LOW:
78 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
79 & ~(1 << bit), LS1X_INTC_INTPOL(n));
80 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
81 & ~(1 << bit), LS1X_INTC_INTEDGE(n));
82 break;
83 case IRQ_TYPE_EDGE_RISING:
84 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
85 | (1 << bit), LS1X_INTC_INTPOL(n));
86 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
87 | (1 << bit), LS1X_INTC_INTEDGE(n));
88 break;
89 case IRQ_TYPE_EDGE_FALLING:
90 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
91 & ~(1 << bit), LS1X_INTC_INTPOL(n));
92 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
93 | (1 << bit), LS1X_INTC_INTEDGE(n));
94 break;
95 case IRQ_TYPE_EDGE_BOTH:
96 __raw_writel(__raw_readl(LS1X_INTC_INTPOL(n))
97 & ~(1 << bit), LS1X_INTC_INTPOL(n));
98 __raw_writel(__raw_readl(LS1X_INTC_INTEDGE(n))
99 | (1 << bit), LS1X_INTC_INTEDGE(n));
100 break;
101 case IRQ_TYPE_NONE:
102 break;
103 default:
104 return -EINVAL;
105 }
106
107 return 0;
108}
109
65static struct irq_chip ls1x_irq_chip = { 110static struct irq_chip ls1x_irq_chip = {
66 .name = "LS1X-INTC", 111 .name = "LS1X-INTC",
67 .irq_ack = ls1x_irq_ack, 112 .irq_ack = ls1x_irq_ack,
68 .irq_mask = ls1x_irq_mask, 113 .irq_mask = ls1x_irq_mask,
69 .irq_mask_ack = ls1x_irq_mask_ack, 114 .irq_mask_ack = ls1x_irq_mask_ack,
70 .irq_unmask = ls1x_irq_unmask, 115 .irq_unmask = ls1x_irq_unmask,
116 .irq_set_type = ls1x_irq_settype,
71}; 117};
72 118
73static void ls1x_irq_dispatch(int n) 119static void ls1x_irq_dispatch(int n)
@@ -107,7 +153,7 @@ asmlinkage void plat_irq_dispatch(void)
107 153
108} 154}
109 155
110struct irqaction cascade_irqaction = { 156static struct irqaction cascade_irqaction = {
111 .handler = no_action, 157 .handler = no_action,
112 .name = "cascade", 158 .name = "cascade",
113 .flags = IRQF_NO_THREAD, 159 .flags = IRQF_NO_THREAD,
@@ -120,7 +166,7 @@ static void __init ls1x_irq_init(int base)
120 /* Disable interrupts and clear pending, 166 /* Disable interrupts and clear pending,
121 * setup all IRQs as high level triggered 167 * setup all IRQs as high level triggered
122 */ 168 */
123 for (n = 0; n < 4; n++) { 169 for (n = 0; n < INTN; n++) {
124 __raw_writel(0x0, LS1X_INTC_INTIEN(n)); 170 __raw_writel(0x0, LS1X_INTC_INTIEN(n));
125 __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n)); 171 __raw_writel(0xffffffff, LS1X_INTC_INTCLR(n));
126 __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n)); 172 __raw_writel(0xffffffff, LS1X_INTC_INTPOL(n));
@@ -129,7 +175,7 @@ static void __init ls1x_irq_init(int base)
129 } 175 }
130 176
131 177
132 for (n = base; n < LS1X_IRQS; n++) { 178 for (n = base; n < NR_IRQS; n++) {
133 irq_set_chip_and_handler(n, &ls1x_irq_chip, 179 irq_set_chip_and_handler(n, &ls1x_irq_chip,
134 handle_level_irq); 180 handle_level_irq);
135 } 181 }
@@ -138,6 +184,9 @@ static void __init ls1x_irq_init(int base)
138 setup_irq(INT1_IRQ, &cascade_irqaction); 184 setup_irq(INT1_IRQ, &cascade_irqaction);
139 setup_irq(INT2_IRQ, &cascade_irqaction); 185 setup_irq(INT2_IRQ, &cascade_irqaction);
140 setup_irq(INT3_IRQ, &cascade_irqaction); 186 setup_irq(INT3_IRQ, &cascade_irqaction);
187#if defined(CONFIG_LOONGSON1_LS1C)
188 setup_irq(INT4_IRQ, &cascade_irqaction);
189#endif
141} 190}
142 191
143void __init arch_init_irq(void) 192void __init arch_init_irq(void)
diff --git a/arch/mips/loongson32/common/platform.c b/arch/mips/loongson32/common/platform.c
index f2c714d8fb60..4d12e365dcb0 100644
--- a/arch/mips/loongson32/common/platform.c
+++ b/arch/mips/loongson32/common/platform.c
@@ -17,6 +17,7 @@
17#include <linux/stmmac.h> 17#include <linux/stmmac.h>
18#include <linux/usb/ehci_pdriver.h> 18#include <linux/usb/ehci_pdriver.h>
19 19
20#include <platform.h>
20#include <loongson1.h> 21#include <loongson1.h>
21#include <cpufreq.h> 22#include <cpufreq.h>
22#include <dma.h> 23#include <dma.h>
@@ -132,6 +133,7 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
132 133
133 val = __raw_readl(LS1X_MUX_CTRL1); 134 val = __raw_readl(LS1X_MUX_CTRL1);
134 135
136#if defined(CONFIG_LOONGSON1_LS1B)
135 plat_dat = dev_get_platdata(&pdev->dev); 137 plat_dat = dev_get_platdata(&pdev->dev);
136 if (plat_dat->bus_id) { 138 if (plat_dat->bus_id) {
137 __raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 | 139 __raw_writel(__raw_readl(LS1X_MUX_CTRL0) | GMAC1_USE_UART1 |
@@ -165,6 +167,17 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
165 val &= ~GMAC0_SHUT; 167 val &= ~GMAC0_SHUT;
166 } 168 }
167 __raw_writel(val, LS1X_MUX_CTRL1); 169 __raw_writel(val, LS1X_MUX_CTRL1);
170#elif defined(CONFIG_LOONGSON1_LS1C)
171 plat_dat = dev_get_platdata(&pdev->dev);
172
173 val &= ~PHY_INTF_SELI;
174 if (plat_dat->interface == PHY_INTERFACE_MODE_RMII)
175 val |= 0x4 << PHY_INTF_SELI_SHIFT;
176 __raw_writel(val, LS1X_MUX_CTRL1);
177
178 val = __raw_readl(LS1X_MUX_CTRL0);
179 __raw_writel(val & (~GMAC_SHUT), LS1X_MUX_CTRL0);
180#endif
168 181
169 return 0; 182 return 0;
170} 183}
@@ -172,7 +185,11 @@ int ls1x_eth_mux_init(struct platform_device *pdev, void *priv)
172static struct plat_stmmacenet_data ls1x_eth0_pdata = { 185static struct plat_stmmacenet_data ls1x_eth0_pdata = {
173 .bus_id = 0, 186 .bus_id = 0,
174 .phy_addr = -1, 187 .phy_addr = -1,
188#if defined(CONFIG_LOONGSON1_LS1B)
175 .interface = PHY_INTERFACE_MODE_MII, 189 .interface = PHY_INTERFACE_MODE_MII,
190#elif defined(CONFIG_LOONGSON1_LS1C)
191 .interface = PHY_INTERFACE_MODE_RMII,
192#endif
176 .mdio_bus_data = &ls1x_mdio_bus_data, 193 .mdio_bus_data = &ls1x_mdio_bus_data,
177 .dma_cfg = &ls1x_eth_dma_cfg, 194 .dma_cfg = &ls1x_eth_dma_cfg,
178 .has_gmac = 1, 195 .has_gmac = 1,
@@ -203,6 +220,7 @@ struct platform_device ls1x_eth0_pdev = {
203 }, 220 },
204}; 221};
205 222
223#ifdef CONFIG_LOONGSON1_LS1B
206static struct plat_stmmacenet_data ls1x_eth1_pdata = { 224static struct plat_stmmacenet_data ls1x_eth1_pdata = {
207 .bus_id = 1, 225 .bus_id = 1,
208 .phy_addr = -1, 226 .phy_addr = -1,
@@ -236,6 +254,7 @@ struct platform_device ls1x_eth1_pdev = {
236 .platform_data = &ls1x_eth1_pdata, 254 .platform_data = &ls1x_eth1_pdata,
237 }, 255 },
238}; 256};
257#endif /* CONFIG_LOONGSON1_LS1B */
239 258
240/* GPIO */ 259/* GPIO */
241static struct resource ls1x_gpio0_resources[] = { 260static struct resource ls1x_gpio0_resources[] = {
diff --git a/arch/mips/loongson32/common/setup.c b/arch/mips/loongson32/common/setup.c
index 62f41afee241..1640744288ee 100644
--- a/arch/mips/loongson32/common/setup.c
+++ b/arch/mips/loongson32/common/setup.c
@@ -22,7 +22,11 @@ const char *get_system_type(void)
22 22
23 switch (processor_id & PRID_REV_MASK) { 23 switch (processor_id & PRID_REV_MASK) {
24 case PRID_REV_LOONGSON1B: 24 case PRID_REV_LOONGSON1B:
25#if defined(CONFIG_LOONGSON1_LS1B)
25 return "LOONGSON LS1B"; 26 return "LOONGSON LS1B";
27#elif defined(CONFIG_LOONGSON1_LS1C)
28 return "LOONGSON LS1C";
29#endif
26 default: 30 default:
27 return "LOONGSON (unknown)"; 31 return "LOONGSON (unknown)";
28 } 32 }
diff --git a/arch/mips/loongson32/ls1c/Makefile b/arch/mips/loongson32/ls1c/Makefile
new file mode 100644
index 000000000000..891eac482b82
--- /dev/null
+++ b/arch/mips/loongson32/ls1c/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for loongson1B based machines.
3#
4
5obj-y += board.o
diff --git a/arch/mips/loongson32/ls1c/board.c b/arch/mips/loongson32/ls1c/board.c
new file mode 100644
index 000000000000..3d69bd63ad56
--- /dev/null
+++ b/arch/mips/loongson32/ls1c/board.c
@@ -0,0 +1,28 @@
1/*
2 * Copyright (c) 2016 Ling Yang <gnaygnil@gmail.com>
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#include <platform.h>
11
12static struct platform_device *ls1c_platform_devices[] __initdata = {
13 &ls1x_uart_pdev,
14 &ls1x_eth0_pdev,
15};
16
17static int __init ls1c_platform_init(void)
18{
19 int err;
20
21 ls1x_serial_set_uartclk(&ls1x_uart_pdev);
22
23 err = platform_add_devices(ls1c_platform_devices,
24 ARRAY_SIZE(ls1c_platform_devices));
25 return err;
26}
27
28arch_initcall(ls1c_platform_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-10 18:36:55 -0400