clk: xgene: Add missing parenthesis when clearing divider value

In the initial fix for non-zero divider shift value, the parenthesis
was missing after the negate operation. This patch adds the required
parenthesis. Otherwise, lower bits may be cleared unintentionally.

Signed-off-by: Loc Ho <lho@apm.com>
Acked-by: Toan Le <toanle@apm.com>
Fixes: 1382ea631ddd ("clk: xgene: Fix divider with non-zero shift value")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index bd7156baa08b..d73450b60b28 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -376,8 +376,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
                 /* Set new divider */
                 data = xgene_clk_read(pclk->param.divider_reg +
                                 pclk->param.reg_divider_offset);
-                data &= ~((1 << pclk->param.reg_divider_width) - 1)
-                                << pclk->param.reg_divider_shift;
+                data &= ~(((1 << pclk->param.reg_divider_width) - 1)
+                                << pclk->param.reg_divider_shift);
                 data |= divider;
                 xgene_clk_write(data, pclk->param.divider_reg +
                                         pclk->param.reg_divider_offset);