clk: xgene: Don't call __pa on ioremaped address

ioremaped addresses are not linearly mapped so the physical
address can not be figured out via __pa. More generally, there
is no guarantee that backing value of an ioremapped address
is a physical address at all. The value here is only used
for debugging so just drop the call to __pa on the ioremapped
address.

Fixes: 6ae5fd381251 ("clk: xgene: Silence sparse warnings")
Signed-off-by: Laura Abbott <labbott@redhat.com>
Acked-by: Loc Ho <lho@apm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

1 files changed, 4 insertions, 6 deletions

diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 5daddf5ecc4b..bc37030e38ba 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -463,22 +463,20 @@ static int xgene_clk_enable(struct clk_hw *hw)
         struct xgene_clk *pclk = to_xgene_clk(hw);
         unsigned long flags = 0;
         u32 data;
-        phys_addr_t reg;
 
         if (pclk->lock)
                 spin_lock_irqsave(pclk->lock, flags);
 
         if (pclk->param.csr_reg != NULL) {
                 pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
-                reg = __pa(pclk->param.csr_reg);
                 /* First enable the clock */
                 data = xgene_clk_read(pclk->param.csr_reg +
                                         pclk->param.reg_clk_offset);
                 data |= pclk->param.reg_clk_mask;
                 xgene_clk_write(data, pclk->param.csr_reg +
                                         pclk->param.reg_clk_offset);
-                pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
-                        clk_hw_get_name(hw), &reg,
+                pr_debug("%s clk offset 0x%08X mask 0x%08X value 0x%08X\n",
+                        clk_hw_get_name(hw),
                         pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
                         data);
 
@@ -488,8 +486,8 @@ static int xgene_clk_enable(struct clk_hw *hw)
                 data &= ~pclk->param.reg_csr_mask;
                 xgene_clk_write(data, pclk->param.csr_reg +
                                         pclk->param.reg_csr_offset);
-                pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
-                        clk_hw_get_name(hw), &reg,
+                pr_debug("%s csr offset 0x%08X mask 0x%08X value 0x%08X\n",
+                        clk_hw_get_name(hw),
                         pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
                         data);
         }