Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Olof Johansson:
 "Device tree contents continue to be the largest branches we submit.
  This time around, some of the contents worth pointing out is:

  New SoC platforms:
   - Freescale i.MX 7Solo
   - Broadcom BCM23550
   - Cirrus Logic EP7209 and EP7211 (clps711x platforms)_
   - Hisilicon HI3519
   - Renesas R8A7792

  Some of the other delta that is sticking out, line-count wise:
   - Exynos moves of IP blocks under an SoC bus, which causes a large
     delta due to indentation changes
   - a new Tegra K1 board: Apalis
   - a bunch of small updates to many Allwinner platforms; new hardware
     support, some cleanup, etc"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (426 commits)
  ARM: dts: sun8i: Add dts file for inet86dz board
  ARM: dts: sun8i: Add dts file for Polaroid MID2407PXE03 tablet
  ARM: dts: sun8i: Use sun8i-reference-design-tablet for ga10h dts
  ARM: dts: sun8i: Use sun8i-reference-design-tablet for polaroid mid2809pxe04
  ARM: dts: sun8i: reference-design-tablet: Add drivevbus-supply
  ARM: dts: Copy sun8i-q8-common.dtsi sun8i-reference-design-tablet.dtsi
  ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for utoo p66 dts
  ARM: dts: sun5i: Use sun5i-reference-design-tablet.dtsi for dit4350 dts
  ARM: dts: sun5i: reference-design-tablet: Remove mention of q8
  ARM: dts: sun5i: reference-design-tablet: Set lradc vref to avcc
  ARM: dts: sun5i: Rename sun5i-q8-common.dtsi sun5i-reference-design-tablet.dtsi
  ARM: dts: sun5i: Move q8 display bits to sun5i-a13-q8-tablet.dts
  ARM: dts: sunxi: Rename sunxi-q8-common.dtsi sunxi-reference-design-tablet.dtsi
  ARM: dts: at91: Don't build unnecessary dtbs
  ARM: dts: at91: sama5d3x: separate motherboard gmac and emac definitions
  ARM: dts: at91: at91sam9g25ek: fix isi endpoint node
  ARM: dts: at91: move isi definition to at91sam9g25ek
  ARM: dts: at91: fix i2c-gpio node name
  ARM: dts: at91: vinco: fix regulator name
  ARM: dts: at91: ariag25 : fix onewire node
  ...

413 files changed, 21016 insertions, 6944 deletions

diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
index 8240c023e202..e3f996920403 100644
--- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm11351-cpu-method.txt
@@ -5,7 +5,7 @@ CPUs in the following Broadcom SoCs:
   BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664
 
 The enable method is specified by defining the following required
-properties in the "cpus" device tree node:
+properties in the "cpu" device tree node:
   - enable-method = "brcm,bcm11351-cpu-method";
   - secondary-boot-reg = <...>;
 
@@ -19,8 +19,6 @@ Example:
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                enable-method = "brcm,bcm11351-cpu-method";
-                secondary-boot-reg = <0x3500417c>;
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -32,5 +30,7 @@ Example:
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
                         reg = <1>;
+                        enable-method = "brcm,bcm11351-cpu-method";
+                        secondary-boot-reg = <0x3500417c>;
                 };
         };
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
new file mode 100644
index 000000000000..a3af54c0e404
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550-cpu-method.txt
@@ -0,0 +1,36 @@
+Broadcom Kona Family CPU Enable Method
+--------------------------------------
+This binding defines the enable method used for starting secondary
+CPUs in the following Broadcom SoCs:
+  BCM23550
+
+The enable method is specified by defining the following required
+properties in the "cpu" device tree node:
+  - enable-method = "brcm,bcm23550";
+  - secondary-boot-reg = <...>;
+
+The secondary-boot-reg property is a u32 value that specifies the
+physical address of the register used to request the ROM holding pen
+code release a secondary CPU.  The value written to the register is
+formed by encoding the target CPU id into the low bits of the
+physical start address it should jump to.
+
+Example:
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                        enable-method = "brcm,bcm23550";
+                        secondary-boot-reg = <0x3500417c>;
+                };
+        };
diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt
new file mode 100644
index 000000000000..080baad923d6
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm23550.txt
@@ -0,0 +1,15 @@
+Broadcom BCM23550 device tree bindings
+--------------------------------------
+
+This document describes the device tree bindings for boards with the BCM23550
+SoC.
+
+Required root node property:
+  - compatible: brcm,bcm23550
+
+Example:
+        / {
+                model = "BCM23550 SoC";
+                compatible = "brcm,bcm23550";
+                [...]
+        }
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 3f0cbbb8395f..e6782d50cbcd 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -193,6 +193,8 @@ nodes to be present and contain the properties described below.
                             "allwinner,sun6i-a31"
                             "allwinner,sun8i-a23"
                             "arm,realview-smp"
+                            "brcm,bcm11351-cpu-method"
+                            "brcm,bcm23550"
                             "brcm,bcm-nsp-smp"
                             "brcm,brahma-b15"
                             "marvell,armada-375-smp"
@@ -204,6 +206,7 @@ nodes to be present and contain the properties described below.
                             "qcom,gcc-msm8660"
                             "qcom,kpss-acc-v1"
                             "qcom,kpss-acc-v2"
+                            "renesas,apmu"
                             "rockchip,rk3036-smp"
                             "rockchip,rk3066-smp"
                             "ste,dbx500-smp"
diff --git a/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
new file mode 100644
index 000000000000..115c5be0bd0b
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/hisilicon/hi3519-sysctrl.txt
@@ -0,0 +1,14 @@
+* Hisilicon Hi3519 System Controller Block
+
+This bindings use the following binding:
+Documentation/devicetree/bindings/mfd/syscon.txt
+
+Required properties:
+- compatible: "hisilicon,hi3519-sysctrl".
+- reg: the register region of this block
+
+Examples:
+sysctrl: system-controller@12010000 {
+        compatible = "hisilicon,hi3519-sysctrl", "syscon";
+        reg = <0x12010000 0x1000>;
+};
diff --git a/Documentation/devicetree/bindings/arm/olimex.txt b/Documentation/devicetree/bindings/arm/olimex.txt
index 007fb5c685a1..d726aeca56be 100644
--- a/Documentation/devicetree/bindings/arm/olimex.txt
+++ b/Documentation/devicetree/bindings/arm/olimex.txt
@@ -1,5 +1,9 @@
-Olimex i.MX Platforms Device Tree Bindings
-------------------------------------------
+Olimex Device Tree Bindings
+---------------------------
+
+SAM9-L9260 Board
+Required root node properties:
+    - compatible = "olimex,sam9-l9260", "atmel,at91sam9260";
 
 i.MX23 Olinuxino Low Cost Board
 Required root node properties:
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 715d960d5eea..666864517069 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -107,6 +107,9 @@ Rockchip platforms device tree bindings
     Required root node properties:
      - compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
 
+- Rockchip RK3229 Evaluation board:
+     - compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
 - Rockchip RK3399 evb:
     Required root node properties:
       - compatible = "rockchip,rk3399-evb", "rockchip,rk3399";
diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
index f5deace2b380..0ea7f14ef294 100644
--- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
@@ -47,6 +47,7 @@ Required root node properties:
         - "hardkernel,odroid-u3"  - for Exynos4412-based Hardkernel Odroid U3.
         - "hardkernel,odroid-x"   - for Exynos4412-based Hardkernel Odroid X.
         - "hardkernel,odroid-x2"  - for Exynos4412-based Hardkernel Odroid X2.
+        - "hardkernel,odroid-xu"  - for Exynos5410-based Hardkernel Odroid XU.
         - "hardkernel,odroid-xu3" - for Exynos5422-based Hardkernel Odroid XU3.
         - "hardkernel,odroid-xu3-lite" - for Exynos5422-based Hardkernel
                                          Odroid XU3 Lite board.
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 9cf67e48f222..6adb9d549fce 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -39,6 +39,8 @@ Boards:
     compatible = "renesas,ape6evm", "renesas,r8a73a4"
   - Atmark Techno Armadillo-800 EVA
     compatible = "renesas,armadillo800eva"
+  - Blanche (RTP0RC7792SEB00010S)
+    compatible = "renesas,blanche", "renesas,r8a7792"
   - BOCK-W
     compatible = "renesas,bockw", "renesas,r8a7778"
   - Genmai (RTK772100BC00000BR)
diff --git a/Documentation/devicetree/bindings/arm/tegra.txt b/Documentation/devicetree/bindings/arm/tegra.txt
index 73278c6d2dc3..b5a4342c1d46 100644
--- a/Documentation/devicetree/bindings/arm/tegra.txt
+++ b/Documentation/devicetree/bindings/arm/tegra.txt
@@ -32,7 +32,11 @@ board-specific compatible values:
   nvidia,whistler
   toradex,apalis_t30
   toradex,apalis_t30-eval
+  toradex,apalis-tk1
+  toradex,apalis-tk1-eval
   toradex,colibri_t20-512
+  toradex,colibri_t30
+  toradex,colibri_t30-eval-v3
   toradex,iris
 
 Trusted Foundations
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
index 079b42a81d7c..18090e7226b4 100644
--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -15,7 +15,7 @@ Required properties:
 - reg:          Memory map of eDMA CC
 - reg-names:    "edma3_cc"
 - interrupts:   Interrupt lines for CCINT, MPERR and CCERRINT.
-- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint"
+- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
 - ti,tptcs:     List of TPTCs associated with the eDMA in the following form:
                 <&tptc_phandle TC_priority_number>. The highest priority is 0.
 
@@ -48,7 +48,7 @@ edma: edma@49000000 {
         reg =   <0x49000000 0x10000>;
         reg-names = "edma3_cc";
         interrupts = <12 13 14>;
-        interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint";
+        interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
         dma-requests = <64>;
         #dma-cells = <2>;
 
diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
new file mode 100644
index 000000000000..3b4436e56865
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -0,0 +1,28 @@
+QCOM Secure Channel Manager (SCM)
+
+Qualcomm processors include an interface to communicate to the secure firmware.
+This interface allows for clients to request different types of actions.  These
+can include CPU power up/down, HDCP requests, loading of firmware, and other
+assorted actions.
+
+Required properties:
+- compatible: must contain one of the following:
+ * "qcom,scm-apq8064" for APQ8064 platforms
+ * "qcom,scm-msm8660" for MSM8660 platforms
+ * "qcom,scm-msm8690" for MSM8690 platforms
+ * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)
+- clocks: One to three clocks may be required based on compatible.
+ * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"
+ * Core, iface, and bus clocks required for "qcom,scm"
+- clock-names: Must contain "core" for the core clock, "iface" for the interface
+  clock and "bus" for the bus clock per the requirements of the compatible.
+
+Example for MSM8916:
+
+        firmware {
+                scm {
+                        compatible = "qcom,scm";
+                        clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
+                        clock-names = "core", "bus", "iface";
+                };
+        };
diff --git a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt
index 0f813dec5e08..f65b04fb7962 100644
--- a/Documentation/devicetree/bindings/iio/adc/at91_adc.txt
+++ b/Documentation/devicetree/bindings/iio/adc/at91_adc.txt
@@ -59,28 +59,24 @@ adc0: adc@fffb0000 {
         atmel,adc-res-names = "lowres", "highres";
         atmel,adc-use-res = "lowres";
 
-        trigger@0 {
-                reg = <0>;
+        trigger0 {
                 trigger-name = "external-rising";
                 trigger-value = <0x1>;
                 trigger-external;
         };
-        trigger@1 {
-                reg = <1>;
+        trigger1 {
                 trigger-name = "external-falling";
                 trigger-value = <0x2>;
                 trigger-external;
         };
 
-        trigger@2 {
-                reg = <2>;
+        trigger2 {
                 trigger-name = "external-any";
                 trigger-value = <0x3>;
                 trigger-external;
         };
 
-        trigger@3 {
-                reg = <3>;
+        trigger3 {
                 trigger-name = "continuous";
                 trigger-value = <0x6>;
         };
diff --git a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
index 0bf1ae243552..3742c152c467 100644
--- a/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
+++ b/Documentation/devicetree/bindings/phy/nvidia,tegra124-xusb-padctl.txt
@@ -124,7 +124,7 @@ For Tegra124 and Tegra132, the list of valid PHY nodes is given below:
   - functions: "usb3-ss", "sata"
 
 For Tegra210, the list of valid PHY nodes is given below:
-- utmi: utmi-0, utmi-1, utmi-2, utmi-3
+- usb2: usb2-0, usb2-1, usb2-2, usb2-3
   - functions: "snps", "xusb", "uart"
 - hsic: hsic-0, hsic-1
   - functions: "snps", "xusb"
diff --git a/Documentation/devicetree/bindings/power/renesas,apmu.txt b/Documentation/devicetree/bindings/power/renesas,apmu.txt
new file mode 100644
index 000000000000..84404c9edff7
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,apmu.txt
@@ -0,0 +1,31 @@
+DT bindings for the Renesas Advanced Power Management Unit
+
+Renesas R-Car line of SoCs utilize one or more APMU hardware units
+for CPU core power domain control including SMP boot and CPU Hotplug.
+
+Required properties:
+
+- compatible: Should be "renesas,<soctype>-apmu", "renesas,apmu" as fallback.
+              Examples with soctypes are:
+                - "renesas,r8a7790-apmu" (R-Car H2)
+                - "renesas,r8a7791-apmu" (R-Car M2-W)
+                - "renesas,r8a7792-apmu" (R-Car V2H)
+                - "renesas,r8a7793-apmu" (R-Car M2-N)
+                - "renesas,r8a7794-apmu" (R-Car E2)
+
+- reg: Base address and length of the I/O registers used by the APMU.
+
+- cpus: This node contains a list of CPU cores, which should match the order
+  of CPU cores used by the WUPCR and PSTR registers in the Advanced Power
+  Management Unit section of the device's datasheet.
+
+
+Example:
+
+This shows the r8a7791 APMU that can control CPU0 and CPU1.
+
+        apmu@e6152000 {
+                compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+                reg = <0 0xe6152000 0 0x188>;
+                cpus = <&cpu0 &cpu1>;
+        };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
index fb81179dce37..8007e839a716 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiecap.txt
@@ -2,28 +2,48 @@ TI SOC ECAP based APWM controller
 
 Required properties:
 - compatible: Must be "ti,<soc>-ecap".
-  for am33xx - compatible = "ti,am33xx-ecap";
-  for da850  - compatible = "ti,da850-ecap", "ti,am33xx-ecap";
+  for am33xx - compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
+  for am4372 - compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
+  for da850  - compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
+  for dra746 - compatible = "ti,dra746-ecap", "ti,am3352-ecap";
 - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
   the cells format. The PWM channel index ranges from 0 to 4. The only third
   cell flag supported by this binding is PWM_POLARITY_INVERTED.
 - reg: physical base address and size of the registers map.
 
 Optional properties:
-- ti,hwmods: Name of the hwmod associated to the ECAP:
-  "ecap<x>", <x> being the 0-based instance number from the HW spec
+- clocks: Handle to the ECAP's functional clock.
+- clock-names: Must be set to "fck".
 
 Example:
 
-ecap0: ecap@0 { /* ECAP on am33xx */
-        compatible = "ti,am33xx-ecap";
+ecap0: ecap@48300100 { /* ECAP on am33xx */
+        compatible = "ti,am3352-ecap", "ti,am33xx-ecap";
+        #pwm-cells = <3>;
+        reg = <0x48300100 0x80>;
+        clocks = <&l4ls_gclk>;
+        clock-names = "fck";
+};
+
+ecap0: ecap@48300100 { /* ECAP on am4372 */
+        compatible = "ti,am4372-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
         #pwm-cells = <3>;
         reg = <0x48300100 0x80>;
         ti,hwmods = "ecap0";
+        clocks = <&l4ls_gclk>;
+        clock-names = "fck";
+};
+
+ecap0: ecap@1f06000 { /* ECAP on da850 */
+        compatible = "ti,da850-ecap", "ti,am3352-ecap", "ti,am33xx-ecap";
+        #pwm-cells = <3>;
+        reg = <0x1f06000 0x80>;
 };
 
-ecap0: ecap@0 { /* ECAP on da850 */
-        compatible = "ti,da850-ecap", "ti,am33xx-ecap";
+ecap0: ecap@4843e100 {
+        compatible = "ti,dra746-ecap", "ti,am3352-ecap";
         #pwm-cells = <3>;
-        reg = <0x306000 0x80>;
+        reg = <0x4843e100 0x80>;
+        clocks = <&l4_root_clk_div>;
+        clock-names = "fck";
 };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
index 9c100b2c5b23..944fe356bb45 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tiehrpwm.txt
@@ -2,28 +2,48 @@ TI SOC EHRPWM based PWM controller
 
 Required properties:
 - compatible: Must be "ti,<soc>-ehrpwm".
-  for am33xx - compatible = "ti,am33xx-ehrpwm";
-  for da850  - compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+  for am33xx  - compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
+  for am4372  - compatible = "ti,am4372-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
+  for da850   - compatible = "ti,da850-ehrpwm", "ti-am3352-ehrpwm", "ti,am33xx-ehrpwm";
+  for dra746 - compatible = "ti,dra746-ehrpwm", "ti-am3352-ehrpwm";
 - #pwm-cells: should be 3. See pwm.txt in this directory for a description of
   the cells format. The only third cell flag supported by this binding is
   PWM_POLARITY_INVERTED.
 - reg: physical base address and size of the registers map.
 
 Optional properties:
-- ti,hwmods: Name of the hwmod associated to the EHRPWM:
-  "ehrpwm<x>", <x> being the 0-based instance number from the HW spec
+- clocks: Handle to the PWM's time-base and functional clock.
+- clock-names: Must be set to "tbclk" and "fck".
 
 Example:
 
-ehrpwm0: ehrpwm@0 { /* EHRPWM on am33xx */
-        compatible = "ti,am33xx-ehrpwm";
+ehrpwm0: pwm@48300200 { /* EHRPWM on am33xx */
+        compatible = "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
         #pwm-cells = <3>;
         reg = <0x48300200 0x100>;
+        clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+        clock-names = "tbclk", "fck";
+};
+
+ehrpwm0: pwm@48300200 { /* EHRPWM on am4372 */
+        compatible = "ti,am4372-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
+        #pwm-cells = <3>;
+        reg = <0x48300200 0x80>;
+        clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+        clock-names = "tbclk", "fck";
         ti,hwmods = "ehrpwm0";
 };
 
-ehrpwm0: ehrpwm@0 { /* EHRPWM on da850 */
-        compatible = "ti,da850-ehrpwm", "ti,am33xx-ehrpwm";
+ehrpwm0: pwm@1f00000 { /* EHRPWM on da850 */
+        compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm", "ti,am33xx-ehrpwm";
+        #pwm-cells = <3>;
+        reg = <0x1f00000 0x2000>;
+};
+
+ehrpwm0: pwm@4843e200 { /* EHRPWM on dra746 */
+        compatible = "ti,dra746-ehrpwm", "ti,am3352-ehrpwm";
         #pwm-cells = <3>;
-        reg = <0x300000 0x2000>;
+        reg = <0x4843e200 0x80>;
+        clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
+        clock-names = "tbclk", "fck";
 };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
index f7eae77f8354..1a5d7b71db89 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-tipwmss.txt
@@ -1,7 +1,11 @@
 TI SOC based PWM Subsystem
 
 Required properties:
-- compatible: Must be "ti,am33xx-pwmss";
+- compatible: Must be "ti,<soc>-pwmss".
+  for am33xx  - compatible = "ti,am33xx-pwmss";
+  for am4372  - compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
+  for dra746 - compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"
+
 - reg: physical base address and size of the registers map.
 - address-cells: Specify the number of u32 entries needed in child nodes.
                   Should set to 1.
@@ -16,7 +20,7 @@ Required properties:
 Also child nodes should also populated under PWMSS DT node.
 
 Example:
-pwmss0: pwmss@48300000 {
+epwmss0: epwmss@48300000 { /* PWMSS for am33xx */
         compatible = "ti,am33xx-pwmss";
         reg = <0x48300000 0x10>;
         ti,hwmods = "epwmss0";
@@ -29,3 +33,28 @@ pwmss0: pwmss@48300000 {
 
         /* child nodes go here */
 };
+
+epwmss0: epwmss@48300000 { /* PWMSS for am4372 */
+        compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"
+        reg = <0x48300000 0x10>;
+        ti,hwmods = "epwmss0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        status = "disabled";
+        ranges = <0x48300100 0x48300100 0x80   /* ECAP */
+                  0x48300180 0x48300180 0x80   /* EQEP */
+                  0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+        /* child nodes go here */
+};
+
+epwmss0: epwmss@4843e000 { /* PWMSS for DRA7xx */
+        compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+        reg = <0x4843e000 0x30>;
+        ti,hwmods = "epwmss0";
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges;
+
+        /* child nodes go here */
+};
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt
new file mode 100644
index 000000000000..4ea39e9186a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,wcnss.txt
@@ -0,0 +1,116 @@
+Qualcomm WCNSS Binding
+
+This binding describes the Qualcomm WCNSS hardware. It consists of control
+block and a BT, WiFi and FM radio block, all using SMD as command channels.
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be: "qcom,wcnss",
+
+- qcom,smd-channel:
+        Usage: required
+        Value type: <string>
+        Definition: standard SMD property specifying the SMD channel used for
+                    communication with the WiFi firmware.
+                    Should be "WCNSS_CTRL".
+
+- qcom,mmio:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: reference to a node specifying the wcnss "ccu" and "dxe"
+                    register blocks. The node must be compatible with one of
+                    the following:
+                    "qcom,riva",
+                    "qcom,pronto"
+
+= SUBNODES
+The subnodes of the wcnss node are optional and describe the individual blocks in
+the WCNSS.
+
+== Bluetooth
+The following properties are defined to the bluetooth node:
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be:
+                    "qcom,wcnss-bt"
+
+== WiFi
+The following properties are defined to the WiFi node:
+
+- compatible:
+        Usage: required
+        Value type: <string>
+        Definition: must be one of:
+                    "qcom,wcnss-wlan",
+
+- interrupts:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: should specify the "rx" and "tx" interrupts
+
+- interrupt-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: must contain "rx" and "tx"
+
+- qcom,smem-state:
+        Usage: required
+        Value type: <prop-encoded-array>
+        Definition: should reference the tx-enable and tx-rings-empty SMEM states
+
+- qcom,smem-state-names:
+        Usage: required
+        Value type: <stringlist>
+        Definition: must contain "tx-enable" and "tx-rings-empty"
+
+= EXAMPLE
+The following example represents a SMD node, with one edge representing the
+"pronto" subsystem, with the wcnss device and its wcn3680 BT and WiFi blocks
+described; as found on the 8974 platform.
+
+smd {
+        compatible = "qcom,smd";
+
+        pronto-edge {
+                interrupts = <0 142 1>;
+
+                qcom,ipc = <&apcs 8 17>;
+                qcom,smd-edge = <6>;
+
+                wcnss {
+                        compatible = "qcom,wcnss";
+                        qcom,smd-channels = "WCNSS_CTRL";
+
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        qcom,mmio = <&pronto>;
+
+                        bt {
+                                compatible = "qcom,wcnss-bt";
+                        };
+
+                        wlan {
+                                compatible = "qcom,wcnss-wlan";
+
+                                interrupts = <0 145 0>, <0 146 0>;
+                                interrupt-names = "tx", "rx";
+
+                                qcom,smem-state = <&apps_smsm 10>, <&apps_smsm 9>;
+                                qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+                        };
+                };
+        };
+};
+
+soc {
+        pronto: pronto {
+                compatible = "qcom,pronto";
+
+                reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
+                reg-names = "ccu", "dxe", "pmu";
+        };
+};
diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt
index 5883b73ea1b5..f4262ed60582 100644
--- a/Documentation/devicetree/bindings/usb/atmel-usb.txt
+++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt
@@ -113,13 +113,13 @@ usb2: gadget@fff78000 {
         clock-names = "hclk", "pclk";
         atmel,vbus-gpio = <&pioB 19 0>;
 
-        ep0 {
+        ep@0 {
                 reg = <0>;
                 atmel,fifo-size = <64>;
                 atmel,nb-banks = <1>;
         };
 
-        ep1 {
+        ep@1 {
                 reg = <1>;
                 atmel,fifo-size = <1024>;
                 atmel,nb-banks = <2>;
@@ -127,7 +127,7 @@ usb2: gadget@fff78000 {
                 atmel,can-isoc;
         };
 
-        ep2 {
+        ep@2 {
                 reg = <2>;
                 atmel,fifo-size = <1024>;
                 atmel,nb-banks = <2>;
@@ -135,21 +135,21 @@ usb2: gadget@fff78000 {
                 atmel,can-isoc;
         };
 
-        ep3 {
+        ep@3 {
                 reg = <3>;
                 atmel,fifo-size = <1024>;
                 atmel,nb-banks = <3>;
                 atmel,can-dma;
         };
 
-        ep4 {
+        ep@4 {
                 reg = <4>;
                 atmel,fifo-size = <1024>;
                 atmel,nb-banks = <3>;
                 atmel,can-dma;
         };
 
-        ep5 {
+        ep@5 {
                 reg = <5>;
                 atmel,fifo-size = <1024>;
                 atmel,nb-banks = <3>;
@@ -157,7 +157,7 @@ usb2: gadget@fff78000 {
                 atmel,can-isoc;
         };
 
-        ep6 {
+        ep@6 {
                 reg = <6>;
                 atmel,fifo-size = <1024>;
                 atmel,nb-banks = <3>;
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
index d28295a3e55f..3eee9e505400 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra124-xusb.txt
@@ -104,10 +104,10 @@ Example:
 
                 nvidia,xusb-padctl = <&padctl>;
 
-                phys = <&{/padctl@0,7009f000/pads/usb2/usb2-1}>, /* mini-PCIe USB */
-                       <&{/padctl@0,7009f000/pads/usb2/usb2-2}>, /* USB A */
-                       <&{/padctl@0,7009f000/pads/pcie/pcie-0}>; /* USB A */
-                phy-names = "utmi-1", "utmi-2", "usb3-0";
+                phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* mini-PCIe USB */
+                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB A */
+                       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB A */
+                phy-names = "usb2-1", "usb2-2", "usb3-0";
 
                 avddio-pex-supply = <&vdd_1v05_run>;
                 dvddio-pex-supply = <&vdd_1v05_run>;
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 414b42710a36..faacd52370d2 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -7,9 +7,10 @@ dtb-$(CONFIG_MACH_ARTPEC6) += \
 dtb-$(CONFIG_MACH_ASM9260) += \
         alphascale-asm9260-devkit.dtb
 # Keep at91 dtb files sorted alphabetically for each SoC
-dtb-$(CONFIG_SOC_SAM_V4_V5) += \
+dtb-$(CONFIG_SOC_AT91RM9200) += \
         at91rm9200ek.dtb \
-        mpa1600.dtb \
+        mpa1600.dtb
+dtb-$(CONFIG_SOC_AT91SAM9) += \
         animeo_ip.dtb \
         at91-qil_a9260.dtb \
         aks-cdu.dtb \
@@ -17,8 +18,10 @@ dtb-$(CONFIG_SOC_SAM_V4_V5) += \
         evk-pro3.dtb \
         tny_a9260.dtb \
         usb_a9260.dtb \
+        at91sam9260ek.dtb \
         at91sam9261ek.dtb \
         at91sam9263ek.dtb \
+        at91-sam9_l9260.dtb \
         tny_a9263.dtb \
         usb_a9263.dtb \
         at91-foxg20.dtb \
@@ -85,6 +88,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
         bcm47094-dlink-dir-885l.dtb \
         bcm94708.dtb \
         bcm94709.dtb \
+        bcm953012er.dtb \
         bcm953012k.dtb
 dtb-$(CONFIG_ARCH_BCM_63XX) += \
         bcm963138dvt.dtb
@@ -95,8 +99,11 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
         bcm958305k.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
         bcm28155-ap.dtb \
-        bcm21664-garnet.dtb
+        bcm21664-garnet.dtb \
+        bcm23550-sparrow.dtb
 dtb-$(CONFIG_ARCH_BCM_NSP) += \
+        bcm958525xmc.dtb \
+        bcm958625hr.dtb \
         bcm958625k.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
         berlin2-sony-nsz-gs7.dtb \
@@ -104,6 +111,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
         berlin2q-marvell-dmp.dtb
 dtb-$(CONFIG_ARCH_BRCMSTB) += \
         bcm7445-bcm97445svmb.dtb
+dtb-$(CONFIG_ARCH_CLPS711X) += \
+        ep7211-edb7211.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += \
         da850-enbw-cmc.dtb \
         da850-evm.dtb
@@ -134,6 +143,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
         exynos5250-snow-rev5.dtb \
         exynos5250-spring.dtb \
         exynos5260-xyref5260.dtb \
+        exynos5410-odroidxu.dtb \
         exynos5410-smdk5410.dtb \
         exynos5420-arndale-octa.dtb \
         exynos5420-peach-pit.dtb \
@@ -146,8 +156,6 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \
         exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += \
         hi3620-hi4511.dtb
-dtb-$(CONFIG_ARCH_HIX5HD2) += \
-        hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += \
         highbank.dtb \
         ecx-2000.dtb
@@ -155,6 +163,10 @@ dtb-$(CONFIG_ARCH_HIP01) += \
         hip01-ca9x2.dtb
 dtb-$(CONFIG_ARCH_HIP04) += \
         hip04-d01.dtb
+dtb-$(CONFIG_ARCH_HISI) += \
+        hi3519-demb.dtb
+dtb-$(CONFIG_ARCH_HIX5HD2) += \
+        hisi-x5hd2-dkb.dtb
 dtb-$(CONFIG_ARCH_INTEGRATOR) += \
         integratorap.dtb \
         integratorcp.dtb
@@ -356,6 +368,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-gw54xx.dtb \
         imx6q-gw551x.dtb \
         imx6q-gw552x.dtb \
+        imx6q-h100.dtb \
         imx6q-hummingboard.dtb \
         imx6q-icore-rqs.dtb \
         imx6q-marsboard.dtb \
@@ -377,6 +390,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
         imx6q-tx6q-1110.dtb \
         imx6q-tx6q-11x0-mb7.dtb \
         imx6q-udoo.dtb \
+        imx6q-utilite-pro.dtb \
         imx6q-wandboard.dtb \
         imx6q-wandboard-revb1.dtb \
         imx6qp-nitrogen6_max.dtb \
@@ -399,9 +413,11 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
         imx6ul-tx6ul-mainboard.dtb
 dtb-$(CONFIG_SOC_IMX7D) += \
         imx7d-cl-som-imx7.dtb \
+        imx7d-colibri-eval-v3.dtb \
         imx7d-nitrogen7.dtb \
         imx7d-sbc-imx7.dtb \
-        imx7d-sdb.dtb
+        imx7d-sdb.dtb \
+        imx7s-colibri-eval-v3.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
         ls1021a-qds.dtb \
         ls1021a-twr.dtb
@@ -416,7 +432,9 @@ dtb-$(CONFIG_SOC_VF610) += \
 dtb-$(CONFIG_ARCH_MXS) += \
         imx23-evk.dtb \
         imx23-olinuxino.dtb \
+        imx23-sansa.dtb \
         imx23-stmp378x_devb.dtb \
+        imx23-xfi3.dtb \
         imx28-apf28.dtb \
         imx28-apf28dev.dtb \
         imx28-apx4devkit.dtb \
@@ -572,7 +590,8 @@ dtb-$(CONFIG_ARCH_PRIMA2) += \
 dtb-$(CONFIG_ARCH_OXNAS) += \
         wd-mbwe.dtb
 dtb-$(CONFIG_ARCH_QCOM) += \
-        qcom-apq8064-arrow-db600c.dtb \
+        qcom-apq8060-dragonboard.dtb \
+        qcom-apq8064-arrow-sd-600eval.dtb \
         qcom-apq8064-cm-qs600.dtb \
         qcom-apq8064-ifc6410.dtb \
         qcom-apq8064-sony-xperia-yuga.dtb \
@@ -602,6 +621,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
         rk3066a-rayeager.dtb \
         rk3188-radxarock.dtb \
         rk3228-evb.dtb \
+        rk3229-evb.dtb \
         rk3288-evb-act8846.dtb \
         rk3288-evb-rk808.dtb \
         rk3288-firefly-beta.dtb \
@@ -638,6 +658,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
         r8a7790-lager.dtb \
         r8a7791-koelsch.dtb \
         r8a7791-porter.dtb \
+        r8a7792-blanche.dtb \
         r8a7793-gose.dtb \
         r8a7794-alt.dtb \
         r8a7794-silk.dtb \
@@ -728,6 +749,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
         sun6i-a31s-yones-toptech-bs1078-v2.dtb
 dtb-$(CONFIG_MACH_SUN7I) += \
         sun7i-a20-bananapi.dtb \
+        sun7i-a20-bananapi-m1-plus.dtb \
         sun7i-a20-bananapro.dtb \
         sun7i-a20-cubieboard2.dtb \
         sun7i-a20-cubietruck.dtb \
@@ -752,8 +774,10 @@ dtb-$(CONFIG_MACH_SUN7I) += \
 dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-a23-evb.dtb \
         sun8i-a23-gt90h-v4.dtb \
+        sun8i-a23-inet86dz.dtb \
         sun8i-a23-ippo-q8h-v5.dtb \
         sun8i-a23-ippo-q8h-v1.2.dtb \
+        sun8i-a23-polaroid-mid2407pxe03.dtb \
         sun8i-a23-polaroid-mid2809pxe04.dtb \
         sun8i-a23-q8-tablet.dtb \
         sun8i-a33-et-q8-v1.6.dtb \
@@ -763,10 +787,12 @@ dtb-$(CONFIG_MACH_SUN8I) += \
         sun8i-a33-sinlinx-sina33.dtb \
         sun8i-a83t-allwinner-h8homlet-v2.dtb \
         sun8i-a83t-cubietruck-plus.dtb \
+        sun8i-h3-bananapi-m2-plus.dtb \
         sun8i-h3-orangepi-2.dtb \
         sun8i-h3-orangepi-one.dtb \
         sun8i-h3-orangepi-pc.dtb \
-        sun8i-h3-orangepi-plus.dtb
+        sun8i-h3-orangepi-plus.dtb \
+        sun8i-r16-parrot.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
         sun9i-a80-optimus.dtb \
         sun9i-a80-cubieboard4.dtb
@@ -794,6 +820,7 @@ dtb-$(CONFIG_ARCH_TEGRA_114_SOC) += \
         tegra114-roth.dtb \
         tegra114-tn7.dtb
 dtb-$(CONFIG_ARCH_TEGRA_124_SOC) += \
+        tegra124-apalis-eval.dtb \
         tegra124-jetson-tk1.dtb \
         tegra124-nyan-big.dtb \
         tegra124-nyan-blaze.dtb \
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
index d9c50fbb49d2..5b1bf92d927c 100644
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -57,7 +57,7 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 0cc150b87b86..e247c15e5176 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -18,6 +18,10 @@
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
 
+        chosen {
+                stdout-path = &uart0;
+        };
+
         leds {
                 pinctrl-names = "default";
                 pinctrl-0 = <&user_leds_s0>;
@@ -318,7 +322,7 @@
                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
                         regulator-name = "vdd_mpu";
                         regulator-min-microvolt = <925000>;
-                        regulator-max-microvolt = <1325000>;
+                        regulator-max-microvolt = <1351500>;
                         regulator-boot-on;
                         regulator-always-on;
                 };
@@ -359,12 +363,8 @@
         phy-mode = "mii";
 };
 
-&cpsw_emac1 {
-        phy_id = <&davinci_mdio>, <1>;
-        phy-mode = "mii";
-};
-
 &mac {
+        slaves = <1>;
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&cpsw_default>;
         pinctrl-1 = <&cpsw_sleep>;
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 55c0e954b146..ca721670bd91 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -33,6 +33,17 @@
         status = "okay";
 };
 
+&cpu0_opp_table {
+        /*
+         * All PG 2.0 silicon may not support 1GHz but some of the early
+         * BeagleBone Blacks have PG 2.0 silicon which is guaranteed
+         * to support 1GHz OPP so enable it for PG 2.0 on this board.
+         */
+        oppnitro@1000000000 {
+                opp-supported-hw = <0x06 0x0100>;
+        };
+};
+
 &am33xx_pinmux {
         nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
                 pinctrl-single,pins = <
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 516673bb023d..5d28712ad253 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -640,7 +640,7 @@
                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
                         regulator-name = "vdd_mpu";
                         regulator-min-microvolt = <912500>;
-                        regulator-max-microvolt = <1312500>;
+                        regulator-max-microvolt = <1351500>;
                         regulator-boot-on;
                         regulator-always-on;
                 };
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 282fe1b37095..09308d66645b 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -560,7 +560,7 @@
                         /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
                         regulator-name = "vdd_mpu";
                         regulator-min-microvolt = <912500>;
-                        regulator-max-microvolt = <1312500>;
+                        regulator-max-microvolt = <1351500>;
                         regulator-boot-on;
                         regulator-always-on;
                 };
diff --git a/arch/arm/boot/dts/am335x-icev2.dts b/arch/arm/boot/dts/am335x-icev2.dts
index e271013e78a6..7d8b8fefdf08 100644
--- a/arch/arm/boot/dts/am335x-icev2.dts
+++ b/arch/arm/boot/dts/am335x-icev2.dts
@@ -206,6 +206,13 @@
                 gpio-controller;
                 #gpio-cells = <2>;
         };
+
+        pca9536: gpio@41 {
+                compatible = "ti,pca9536";
+                reg = <0x41>;
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
 };
 
 #include "tps65910.dtsi"
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 7fa295155543..98748c61ed99 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -45,19 +45,9 @@
                         device_type = "cpu";
                         reg = <0>;
 
-                        /*
-                         * To consider voltage drop between PMIC and SoC,
-                         * tolerance value is reduced to 2% from 4% and
-                         * voltage value is increased as a precaution.
-                         */
-                        operating-points = <
-                                /* kHz    uV */
-                                720000  1285000
-                                600000  1225000
-                                500000  1125000
-                                275000  1125000
-                        >;
-                        voltage-tolerance = <2>; /* 2 percentage */
+                        operating-points-v2 = <&cpu0_opp_table>;
+                        ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
+                        ti,syscon-rev = <&scm_conf 0x600>;
 
                         clocks = <&dpll_mpu_ck>;
                         clock-names = "cpu";
@@ -66,6 +56,78 @@
                 };
         };
 
+        cpu0_opp_table: opp_table0 {
+                compatible = "operating-points-v2";
+
+                /*
+                 * The three following nodes are marked with opp-suspend
+                 * because the can not be enabled simultaneously on a
+                 * single SoC.
+                 */
+                opp50@300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        opp-microvolt = <950000 931000 969000>;
+                        opp-supported-hw = <0x06 0x0010>;
+                        opp-suspend;
+                };
+
+                opp100@275000000 {
+                        opp-hz = /bits/ 64 <275000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x01 0x00FF>;
+                        opp-suspend;
+                };
+
+                opp100@300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x06 0x0020>;
+                        opp-suspend;
+                };
+
+                opp100@500000000 {
+                        opp-hz = /bits/ 64 <500000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x01 0xFFFF>;
+                };
+
+                opp100@600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0x06 0x0040>;
+                };
+
+                opp120@600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1200000 1176000 1224000>;
+                        opp-supported-hw = <0x01 0xFFFF>;
+                };
+
+                opp120@720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <1200000 1176000 1224000>;
+                        opp-supported-hw = <0x06 0x0080>;
+                };
+
+                oppturbo@720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <1260000 1234800 1285200>;
+                        opp-supported-hw = <0x01 0xFFFF>;
+                };
+
+                oppturbo@800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                        opp-microvolt = <1260000 1234800 1285200>;
+                        opp-supported-hw = <0x06 0x0100>;
+                };
+
+                oppnitro@1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <1325000 1298500 1351500>;
+                        opp-supported-hw = <0x04 0x0200>;
+                };
+        };
+
         pmu {
                 compatible = "arm,cortex-a8-pmu";
                 interrupts = <3>;
@@ -187,7 +249,7 @@
                         reg =   <0x49000000 0x10000>;
                         reg-names = "edma3_cc";
                         interrupts = <12 13 14>;
-                        interrupt-names = "edma3_ccint", "emda3_mperr",
+                        interrupt-names = "edma3_ccint", "edma3_mperr",
                                           "edma3_ccerrint";
                         dma-requests = <64>;
                         #dma-cells = <2>;
@@ -679,20 +741,24 @@
                                   0x48300200 0x48300200 0x80>; /* EHRPWM */
 
                         ecap0: ecap@48300100 {
-                                compatible = "ti,am33xx-ecap";
+                                compatible = "ti,am3352-ecap",
+                                             "ti,am33xx-ecap";
                                 #pwm-cells = <3>;
                                 reg = <0x48300100 0x80>;
+                                clocks = <&l4ls_gclk>;
+                                clock-names = "fck";
                                 interrupts = <31>;
                                 interrupt-names = "ecap0";
-                                ti,hwmods = "ecap0";
                                 status = "disabled";
                         };
 
                         ehrpwm0: pwm@48300200 {
-                                compatible = "ti,am33xx-ehrpwm";
+                                compatible = "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48300200 0x80>;
-                                ti,hwmods = "ehrpwm0";
+                                clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -709,20 +775,24 @@
                                   0x48302200 0x48302200 0x80>; /* EHRPWM */
 
                         ecap1: ecap@48302100 {
-                                compatible = "ti,am33xx-ecap";
+                                compatible = "ti,am3352-ecap",
+                                             "ti,am33xx-ecap";
                                 #pwm-cells = <3>;
                                 reg = <0x48302100 0x80>;
+                                clocks = <&l4ls_gclk>;
+                                clock-names = "fck";
                                 interrupts = <47>;
                                 interrupt-names = "ecap1";
-                                ti,hwmods = "ecap1";
                                 status = "disabled";
                         };
 
                         ehrpwm1: pwm@48302200 {
-                                compatible = "ti,am33xx-ehrpwm";
+                                compatible = "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48302200 0x80>;
-                                ti,hwmods = "ehrpwm1";
+                                clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -739,20 +809,24 @@
                                   0x48304200 0x48304200 0x80>; /* EHRPWM */
 
                         ecap2: ecap@48304100 {
-                                compatible = "ti,am33xx-ecap";
+                                compatible = "ti,am3352-ecap",
+                                             "ti,am33xx-ecap";
                                 #pwm-cells = <3>;
                                 reg = <0x48304100 0x80>;
+                                clocks = <&l4ls_gclk>;
+                                clock-names = "fck";
                                 interrupts = <61>;
                                 interrupt-names = "ecap2";
-                                ti,hwmods = "ecap2";
                                 status = "disabled";
                         };
 
                         ehrpwm2: pwm@48304200 {
-                                compatible = "ti,am33xx-ehrpwm";
+                                compatible = "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48304200 0x80>;
-                                ti,hwmods = "ehrpwm2";
+                                clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
diff --git a/arch/arm/boot/dts/am3517-craneboard.dts b/arch/arm/boot/dts/am3517-craneboard.dts
index cb7de1d4e05f..f9d8f3948c4a 100644
--- a/arch/arm/boot/dts/am3517-craneboard.dts
+++ b/arch/arm/boot/dts/am3517-craneboard.dts
@@ -20,7 +20,7 @@
                 reg = <0x80000000 0x10000000>;  /* 256 MB */
         };
 
-        vbat: fixedregulator@0 {
+        vbat: fixedregulator {
                 compatible = "regulator-fixed";
                 regulator-name = "vbat";
                 regulator-min-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index cd81ecf12731..0fadae5396e1 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -44,10 +44,49 @@
                         clocks = <&dpll_mpu_ck>;
                         clock-names = "cpu";
 
+                        operating-points-v2 = <&cpu0_opp_table>;
+                        ti,syscon-efuse = <&scm_conf 0x610 0x3f 0>;
+                        ti,syscon-rev = <&scm_conf 0x600>;
+
                         clock-latency = <300000>; /* From omap-cpufreq driver */
                 };
         };
 
+        cpu0_opp_table: opp_table0 {
+                compatible = "operating-points-v2";
+
+                opp50@300000000 {
+                        opp-hz = /bits/ 64 <300000000>;
+                        opp-microvolt = <950000 931000 969000>;
+                        opp-supported-hw = <0xFF 0x01>;
+                        opp-suspend;
+                };
+
+                opp100@600000000 {
+                        opp-hz = /bits/ 64 <600000000>;
+                        opp-microvolt = <1100000 1078000 1122000>;
+                        opp-supported-hw = <0xFF 0x04>;
+                };
+
+                opp120@720000000 {
+                        opp-hz = /bits/ 64 <720000000>;
+                        opp-microvolt = <1200000 1176000 1224000>;
+                        opp-supported-hw = <0xFF 0x08>;
+                };
+
+                oppturbo@800000000 {
+                        opp-hz = /bits/ 64 <800000000>;
+                        opp-microvolt = <1260000 1234800 1285200>;
+                        opp-supported-hw = <0xFF 0x10>;
+                };
+
+                oppnitro@1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <1325000 1298500 1351500>;
+                        opp-supported-hw = <0xFF 0x20>;
+                };
+        };
+
         gic: interrupt-controller@48241000 {
                 compatible = "arm,cortex-a9-gic";
                 interrupt-controller;
@@ -199,7 +238,7 @@
                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "edma3_ccint", "emda3_mperr",
+                        interrupt-names = "edma3_ccint", "edma3_mperr",
                                           "edma3_ccerrint";
                         dma-requests = <64>;
                         #dma-cells = <2>;
@@ -671,18 +710,24 @@
                         status = "disabled";
 
                         ecap0: ecap@48300100 {
-                                compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                                compatible = "ti,am4372-ecap",
+                                             "ti,am3352-ecap",
+                                             "ti,am33xx-ecap";
                                 #pwm-cells = <3>;
                                 reg = <0x48300100 0x80>;
-                                ti,hwmods = "ecap0";
+                                clocks = <&l4ls_gclk>;
+                                clock-names = "fck";
                                 status = "disabled";
                         };
 
                         ehrpwm0: pwm@48300200 {
-                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                compatible = "ti,am4372-ehrpwm",
+                                             "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48300200 0x80>;
-                                ti,hwmods = "ehrpwm0";
+                                clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -697,18 +742,24 @@
                         status = "disabled";
 
                         ecap1: ecap@48302100 {
-                                compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                                compatible = "ti,am4372-ecap",
+                                             "ti,am3352-ecap",
+                                             "ti,am33xx-ecap";
                                 #pwm-cells = <3>;
                                 reg = <0x48302100 0x80>;
-                                ti,hwmods = "ecap1";
+                                clocks = <&l4ls_gclk>;
+                                clock-names = "fck";
                                 status = "disabled";
                         };
 
                         ehrpwm1: pwm@48302200 {
-                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                compatible = "ti,am4372-ehrpwm",
+                                             "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48302200 0x80>;
-                                ti,hwmods = "ehrpwm1";
+                                clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -723,18 +774,24 @@
                         status = "disabled";
 
                         ecap2: ecap@48304100 {
-                                compatible = "ti,am4372-ecap","ti,am33xx-ecap";
+                                compatible = "ti,am4372-ecap",
+                                             "ti,am3352-ecap",
+                                             "ti,am33xx-ecap";
                                 #pwm-cells = <3>;
                                 reg = <0x48304100 0x80>;
-                                ti,hwmods = "ecap2";
+                                clocks = <&l4ls_gclk>;
+                                clock-names = "fck";
                                 status = "disabled";
                         };
 
                         ehrpwm2: pwm@48304200 {
-                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                compatible = "ti,am4372-ehrpwm",
+                                             "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48304200 0x80>;
-                                ti,hwmods = "ehrpwm2";
+                                clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -749,10 +806,13 @@
                         status = "disabled";
 
                         ehrpwm3: pwm@48306200 {
-                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                compatible = "ti,am4372-ehrpwm",
+                                             "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48306200 0x80>;
-                                ti,hwmods = "ehrpwm3";
+                                clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -767,10 +827,13 @@
                         status = "disabled";
 
                         ehrpwm4: pwm@48308200 {
-                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                compatible = "ti,am4372-ehrpwm",
+                                             "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x48308200 0x80>;
-                                ti,hwmods = "ehrpwm4";
+                                clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -785,10 +848,13 @@
                         status = "disabled";
 
                         ehrpwm5: pwm@4830a200 {
-                                compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
+                                compatible = "ti,am4372-ehrpwm",
+                                             "ti,am3352-ehrpwm",
+                                             "ti,am33xx-ehrpwm";
                                 #pwm-cells = <3>;
                                 reg = <0x4830a200 0x80>;
-                                ti,hwmods = "ehrpwm5";
+                                clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
+                                clock-names = "tbclk", "fck";
                                 status = "disabled";
                         };
                 };
@@ -842,6 +908,13 @@
                         dma-names = "tx", "rx";
                 };
 
+                rng: rng@48310000 {
+                        compatible = "ti,omap4-rng";
+                        ti,hwmods = "rng";
+                        reg = <0x48310000 0x2000>;
+                        interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                };
+
                 mcasp0: mcasp@48038000 {
                         compatible = "ti,am33xx-mcasp-audio";
                         ti,hwmods = "mcasp0";
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 5bcd3aa025bc..14677d599595 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -897,7 +897,7 @@
         pinctrl-0 = <&dss_pins>;
 
         port {
-                dpi_out: endpoint@0 {
+                dpi_out: endpoint {
                         remote-endpoint = <&lcd_in>;
                         data-lines = <24>;
                 };
@@ -975,3 +975,7 @@
         clock-names = "ext-clk", "int-clk";
         status = "okay";
 };
+
+&cpu {
+        cpu0-supply = <&dcdc2>;
+};
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index 76dcfc6d5f0d..12a69518383e 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -382,6 +382,7 @@
 };
 
 &mac {
+        slaves = <1>;
         pinctrl-names = "default", "sleep";
         pinctrl-0 = <&cpsw_default>;
         pinctrl-1 = <&cpsw_sleep>;
diff --git a/arch/arm/boot/dts/am437x-sbc-t43.dts b/arch/arm/boot/dts/am437x-sbc-t43.dts
index 5f750c0ed6c9..d23260d3a581 100644
--- a/arch/arm/boot/dts/am437x-sbc-t43.dts
+++ b/arch/arm/boot/dts/am437x-sbc-t43.dts
@@ -145,7 +145,7 @@
         pinctrl-0 = <&dss_pinctrl_default>;
 
         port {
-                dpi_lcd_out: endpoint@0 {
+                dpi_lcd_out: endpoint {
                         remote-endpoint = <&lcd_in>;
                         data-lines = <24>;
                 };
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 3549b8c9ac49..ad32e55532f8 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -754,7 +754,7 @@
         pinctrl-0 = <&dss_pins>;
 
         port {
-                dpi_out: endpoint@0 {
+                dpi_out: endpoint {
                         remote-endpoint = <&lcd_in>;
                         data-lines = <24>;
                 };
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 7630ba1d89e4..d1d73b725f47 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -104,6 +104,14 @@
                 clock-div = <1>;
         };
 
+        rng_fck: rng_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&sys_clkin_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+
         ehrpwm0_tbclk: ehrpwm0_tbclk@664 {
                 #clock-cells = <0>;
                 compatible = "ti,gate-clock";
diff --git a/arch/arm/boot/dts/am57xx-sbc-am57x.dts b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
index 988e99632d49..31f9be632406 100644
--- a/arch/arm/boot/dts/am57xx-sbc-am57x.dts
+++ b/arch/arm/boot/dts/am57xx-sbc-am57x.dts
@@ -128,7 +128,7 @@
         vdda_video-supply = <&ldoln_reg>;
 
         port {
-                dpi_lcd_out: endpoint@0 {
+                dpi_lcd_out: endpoint {
                         remote-endpoint = <&lcd_in>;
                         data-lines = <24>;
                 };
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 0962f2fa3f6e..9cc372b9fb9b 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -32,15 +32,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <18432000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -114,7 +105,7 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         atmel,vbus-gpio = <&pioB 15 GPIO_ACTIVE_LOW>;
                         status = "okay";
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index c60206efb583..2e0556af6e5e 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -239,22 +239,6 @@
                                 status = "okay";
                         };
 
-                        mdio@72004 {
-                                pinctrl-0 = <&mdio_pins>;
-                                pinctrl-names = "default";
-
-                                phy_dedicated: ethernet-phy@0 {
-                                        /*
-                                         * Annoyingly, the marvell phy driver
-                                         * configures the LED register, rather
-                                         * than preserving reset-loaded setting.
-                                         * We undo that rubbish here.
-                                         */
-                                        marvell,reg-init = <3 16 0 0x101e>;
-                                        reg = <0>;
-                                };
-                        };
-
                         pinctrl@18000 {
                                 clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
                                         marvell,pins = "mpp46";
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index e9ced30159a7..4da011a7a698 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -34,15 +34,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -178,7 +169,7 @@
 
         };
 
-        onewire@0 {
+        onewire {
                 compatible = "w1-gpio";
                 gpios = <&pioA 21 GPIO_ACTIVE_LOW>;
                 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
index b6ea3f4a7206..02d8ef43de3a 100644
--- a/arch/arm/boot/dts/at91-cosino.dtsi
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -26,15 +26,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
index 6bf873e7d96c..50d5e719b451 100644
--- a/arch/arm/boot/dts/at91-foxg20.dts
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -23,15 +23,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <18432000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -128,13 +119,13 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_i2c0>;
                 i2c-gpio,delay-us = <5>;        /* ~85 kHz */
diff --git a/arch/arm/boot/dts/at91-kizbox.dts b/arch/arm/boot/dts/at91-kizbox.dts
index 229e989eb60d..b4f147c193fd 100644
--- a/arch/arm/boot/dts/at91-kizbox.dts
+++ b/arch/arm/boot/dts/at91-kizbox.dts
@@ -54,7 +54,7 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <1>;
                         status = "okay";
                 };
@@ -96,7 +96,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
 
                 rtc: pcf8563@51 {
diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts
index 4f2eebf4a560..8f019184fccf 100644
--- a/arch/arm/boot/dts/at91-qil_a9260.dts
+++ b/arch/arm/boot/dts/at91-qil_a9260.dts
@@ -20,15 +20,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -111,7 +102,7 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
@@ -187,7 +178,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/at91-sam9_l9260.dts b/arch/arm/boot/dts/at91-sam9_l9260.dts
new file mode 100644
index 000000000000..171243ca4f2f
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sam9_l9260.dts
@@ -0,0 +1,121 @@
+/*
+ * at91-sam9_l9260.dts - Device Tree file for Olimex SAM9-L9260 board
+ *
+ *  Copyright (C) 2016 Raashid Muhammed <raashidmuhammed@zilogic.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+/dts-v1/;
+#include "at91sam9260.dtsi"
+
+/ {
+        model = "Olimex sam9-l9260";
+        compatible = "olimex,sam9-l9260", "atmel,at91sam9260", "atmel,at91sam9";
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                slow_xtal {
+                        clock-frequency = <32768>;
+                };
+
+                main_xtal {
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot1_cmd_dat0
+                                        &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioC 8 GPIO_ACTIVE_HIGH>;
+                                        wp-gpios = <&pioC 4 GPIO_ACTIVE_HIGH>;
+                                };
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                pinctrl-0 = <&pinctrl_macb_rmii &pinctrl_macb_rmii_mii_alt>;
+                                phy-mode = "mii";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "okay";
+
+                                ethernet-phy@1 {
+                                        reg = <0x1>;
+                                };
+                        };
+
+                        spi0: spi@fffc8000 {
+                                cs-gpios = <&pioC 11 0>, <0>, <0>, <0>;
+                                status = "okay";
+
+                                flash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <15000000>;
+                                        reg = <0>;
+                                };
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                mmc0 {
+                                        pinctrl_board_mmc0: mmc0-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH     /* CD pin */
+                                                         AT91_PIOC 4 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;    /* WP pin */
+                                        };
+                                };
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt = <1>;
+                        status = "okay";
+                };
+
+                usb0: ohci@500000 {
+                        status = "okay";
+                };
+
+        };
+
+        i2c-gpio-0 {
+                status = "okay";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                pwr_led {
+                        label = "sam9-l9260:yellow:pwr";
+                        gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "cpu0";
+                };
+
+                status_led {
+                        label = "sam9-l9260:green:status";
+                        gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
+                        linux,default-trigger = "timer";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index eb4f1ac96271..0b9a59d5fdac 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -158,56 +158,64 @@
                                 i2c-sda-hold-time-ns = <350>;
                                 status = "okay";
 
-                                pmic: act8865@5b {
-                                        compatible = "active-semi,act8865";
+                                pmic@5b {
+                                        compatible = "active-semi,act8945a";
                                         reg = <0x5b>;
                                         active-semi,vsel-high;
+                                        active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>;
+                                        active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>;
+                                        active-semi,irq_gpios = <&pioA 45 GPIO_ACTIVE_LOW>;
+                                        active-semi,input-voltage-threshold-microvolt = <6600>;
+                                        active-semi,precondition-timeout = <40>;
+                                        active-semi,total-timeout = <3>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>;
                                         status = "okay";
 
                                         regulators {
-                                                vdd_1v35_reg: DCDC_REG1 {
+                                                vdd_1v35_reg: REG_DCDC1 {
                                                         regulator-name = "VDD_1V35";
                                                         regulator-min-microvolt = <1350000>;
                                                         regulator-max-microvolt = <1350000>;
                                                         regulator-always-on;
                                                 };
 
-                                                vdd_1v2_reg: DCDC_REG2 {
+                                                vdd_1v2_reg: REG_DCDC2 {
                                                         regulator-name = "VDD_1V2";
                                                         regulator-min-microvolt = <1100000>;
                                                         regulator-max-microvolt = <1300000>;
                                                         regulator-always-on;
                                                 };
 
-                                                vdd_3v3_reg: DCDC_REG3 {
+                                                vdd_3v3_reg: REG_DCDC3 {
                                                         regulator-name = "VDD_3V3";
                                                         regulator-min-microvolt = <3300000>;
                                                         regulator-max-microvolt = <3300000>;
                                                         regulator-always-on;
                                                 };
 
-                                                vdd_fuse_reg: LDO_REG1 {
+                                                vdd_fuse_reg: REG_LDO1 {
                                                         regulator-name = "VDD_FUSE";
                                                         regulator-min-microvolt = <2500000>;
                                                         regulator-max-microvolt = <2500000>;
                                                         regulator-always-on;
                                                 };
 
-                                                vdd_3v3_lp_reg: LDO_REG2 {
+                                                vdd_3v3_lp_reg: REG_LDO2 {
                                                         regulator-name = "VDD_3V3_LP";
                                                         regulator-min-microvolt = <3300000>;
                                                         regulator-max-microvolt = <3300000>;
                                                         regulator-always-on;
                                                 };
 
-                                                vdd_led_reg: LDO_REG3 {
+                                                vdd_led_reg: REG_LDO3 {
                                                         regulator-name = "VDD_LED";
                                                         regulator-min-microvolt = <3300000>;
                                                         regulator-max-microvolt = <3300000>;
                                                         regulator-always-on;
                                                 };
 
-                                                vdd_sdhc_1v8_reg: LDO_REG4 {
+                                                vdd_sdhc_1v8_reg: REG_LDO4 {
                                                         regulator-name = "VDD_SDHC_1V8";
                                                         regulator-min-microvolt = <1800000>;
                                                         regulator-max-microvolt = <1800000>;
@@ -309,6 +317,21 @@
                                         bias-disable;
                                 };
 
+                                pinctrl_charger_chglev: charger_chglev {
+                                        pinmux = <PIN_PA12__GPIO>;
+                                        bias-disable;
+                                };
+
+                                pinctrl_charger_irq: charger_irq {
+                                        pinmux = <PIN_PB13__GPIO>;
+                                        bias-disable;
+                                };
+
+                                pinctrl_charger_lbo: charger_lbo {
+                                        pinmux = <PIN_PC8__GPIO>;
+                                        bias-pull-up;
+                                };
+
                                 pinctrl_flx0_default: flx0_default {
                                         pinmux = <PIN_PB28__FLEXCOM0_IO0>,
                                                  <PIN_PB29__FLEXCOM0_IO1>;
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index f3e2b96c06a3..c51fc652f6c7 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -297,7 +297,7 @@
                 };
         };
 
-        vcc_mmc0_reg: fixedregulator@0 {
+        vcc_mmc0_reg: fixedregulator_mmc0 {
                 compatible = "regulator-fixed";
                 gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
                 regulator-name = "mmc0-card-supply";
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
index e7b2109fc85a..a92c6e0ca854 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi
@@ -20,8 +20,11 @@
         };
 
         clocks {
-                main_clock: main_clock {
-                        compatible = "atmel,osc", "fixed-clock";
+                slow_xtal {
+                        clock-frequency = <32768>;
+                };
+
+                main_xtal {
                         clock-frequency = <12000000>;
                 };
 
@@ -106,7 +109,7 @@
                 };
         };
 
-        vcc_3v3_reg: fixedregulator@0 {
+        vcc_3v3_reg: fixedregulator_3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "VCC 3V3";
                 regulator-min-microvolt = <3300000>;
@@ -115,7 +118,7 @@
                 regulator-always-on;
         };
 
-        vcc_mmc0_reg: fixedregulator@1 {
+        vcc_mmc0_reg: fixedregulator_mmc0 {
                 compatible = "regulator-fixed";
                 gpio = <&pioE 15 GPIO_ACTIVE_HIGH>;
                 regulator-name = "RST_n MCI0";
diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
index abaaba58fbec..eac4ea2744cc 100644
--- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts
@@ -159,7 +159,7 @@
                 };
         };
 
-        vcc_mmc1_reg: fixedregulator@2 {
+        vcc_mmc1_reg: fixedregulator_mmc1 {
                 compatible = "regulator-fixed";
                 gpio = <&pioE 17 GPIO_ACTIVE_LOW>;
                 regulator-name = "VDD MCI1";
diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
index da84e65b56ef..ed7fce297738 100644
--- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts
@@ -252,7 +252,7 @@
                 };
         };
 
-        vcc_3v3_reg: fixedregulator@0 {
+        vcc_3v3_reg: fixedregulator_3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "VCC 3V3";
                 regulator-min-microvolt = <3300000>;
@@ -261,7 +261,7 @@
                 regulator-always-on;
         };
 
-        vcc_mmc1_reg: fixedregulator@1 {
+        vcc_mmc1_reg: fixedregulator_mmc1 {
                 compatible = "regulator-fixed";
                 gpio = <&pioE 4 GPIO_ACTIVE_LOW>;
                 regulator-name = "VDD MCI1";
diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts
index 4e98cda97403..f8b96cef5e1a 100644
--- a/arch/arm/boot/dts/at91-sama5d4ek.dts
+++ b/arch/arm/boot/dts/at91-sama5d4ek.dts
@@ -69,26 +69,6 @@
 
         ahb {
                 apb {
-                        lcd_bus@f0000000 {
-                                status = "okay";
-
-                                lcd@f0000000 {
-                                        status = "okay";
-                                };
-
-                                lcdovl1@f0000140 {
-                                        status = "okay";
-                                };
-
-                                lcdovl2@f0000240 {
-                                        status = "okay";
-                                };
-
-                                lcdheo1@f0000340 {
-                                        status = "okay";
-                                };
-                        };
-
                         adc0: adc@fc034000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <
diff --git a/arch/arm/boot/dts/at91-vinco.dts b/arch/arm/boot/dts/at91-vinco.dts
index 6a366ee952a8..e0c0b2897a49 100644
--- a/arch/arm/boot/dts/at91-vinco.dts
+++ b/arch/arm/boot/dts/at91-vinco.dts
@@ -245,7 +245,7 @@
 
         };
 
-        vcc_3v3_reg: fixedregulator@0 {
+        vcc_3v3_reg: fixedregulator_3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "VCC 3V3";
                 regulator-min-microvolt = <3300000>;
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index f6cb7a80a2f5..4e913c2ccb79 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -948,7 +948,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */
                          &pioA 26 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index d4884dd1c243..a3e363d79122 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -938,25 +938,21 @@
                                 atmel,adc-res-names = "lowres", "highres";
                                 atmel,adc-use-res = "highres";
 
-                                trigger@0 {
-                                        reg = <0>;
+                                trigger0 {
                                         trigger-name = "timer-counter-0";
                                         trigger-value = <0x1>;
                                 };
-                                trigger@1 {
-                                        reg = <1>;
+                                trigger1 {
                                         trigger-name = "timer-counter-1";
                                         trigger-value = <0x3>;
                                 };
 
-                                trigger@2 {
-                                        reg = <2>;
+                                trigger2 {
                                         trigger-name = "timer-counter-2";
                                         trigger-value = <0x5>;
                                 };
 
-                                trigger@3 {
-                                        reg = <3>;
+                                trigger3 {
                                         trigger-name = "external";
                                         trigger-value = <0xd>;
                                         trigger-external;
@@ -1007,7 +1003,7 @@
                         status = "disabled";
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x100000>;
                         interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
@@ -1017,7 +1013,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioA 23 GPIO_ACTIVE_HIGH /* sda */
                          &pioA 24 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9260ek.dts b/arch/arm/boot/dts/at91sam9260ek.dts
new file mode 100644
index 000000000000..2c87f58448e7
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9260ek.dts
@@ -0,0 +1,211 @@
+/*
+ * Device Tree file for Atmel at91sam9260 Evaluation Kit
+ *
+ *  Copyright (C) 2016 Atmel,
+ *                2016 Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+/dts-v1/;
+#include "at91sam9260.dtsi"
+
+/ {
+        model = "Atmel at91sam9260ek";
+        compatible = "atmel,at91sam9260ek", "atmel,at91sam9260", "atmel,at91sam9";
+
+        chosen {
+                stdout-path = &dbgu;
+        };
+
+        memory {
+                reg = <0x20000000 0x4000000>;
+        };
+
+        clocks {
+                slow_xtal {
+                        clock-frequency = <32768>;
+                };
+
+                main_xtal {
+                        clock-frequency = <18432000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+
+                        mmc0: mmc@fffa8000 {
+                                pinctrl-0 = <
+                                        &pinctrl_board_mmc0_slot1
+                                        &pinctrl_mmc0_clk
+                                        &pinctrl_mmc0_slot1_cmd_dat0
+                                        &pinctrl_mmc0_slot1_dat1_3>;
+                                status = "okay";
+                                slot@1 {
+                                        reg = <1>;
+                                        bus-width = <4>;
+                                        cd-gpios = <&pioC 9 GPIO_ACTIVE_HIGH>;
+                                };
+                        };
+
+                        usart0: serial@fffb0000 {
+                                pinctrl-0 =
+                                        <&pinctrl_usart0
+                                         &pinctrl_usart0_rts
+                                         &pinctrl_usart0_cts
+                                         &pinctrl_usart0_dtr_dsr
+                                         &pinctrl_usart0_dcd
+                                         &pinctrl_usart0_ri>;
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                        };
+
+                        ssc0: ssc@fffbc000 {
+                                status = "okay";
+                                pinctrl-0 = <&pinctrl_ssc0_tx>;
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        spi0: spi@fffc8000 {
+                                cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <50000000>;
+                                        reg = <1>;
+                                };
+                        };
+
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+
+                        pinctrl@fffff400 {
+                                board {
+                                        pinctrl_board_mmc0_slot1: mmc0_slot1-board {
+                                                atmel,pins =
+                                                        <AT91_PIOC 9 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
+                                        };
+                                };
+                        };
+
+                        shdwc@fffffd10 {
+                                atmel,wakeup-counter = <10>;
+                                atmel,wakeup-rtt-timer;
+                        };
+
+                        rtc@fffffd20 {
+                                atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
+                                status = "okay";
+                        };
+
+                        watchdog@fffffd40 {
+                                status = "okay";
+                        };
+
+                        gpbr: syscon@fffffd50 {
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+
+                btn3 {
+                        label = "Button 3";
+                        gpios = <&pioA 30 GPIO_ACTIVE_LOW>;
+                        linux,code = <0x103>;
+                        gpio-key,wakeup;
+                };
+
+                btn4 {
+                        label = "Button 4";
+                        gpios = <&pioA 31 GPIO_ACTIVE_LOW>;
+                        linux,code = <0x104>;
+                        gpio-key,wakeup;
+                };
+        };
+
+        i2c-gpio-0 {
+                status = "okay";
+
+                24c512@50 {
+                        compatible = "24c512";
+                        reg = <0x50>;
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                ds1 {
+                        label = "ds1";
+                        gpios = <&pioA 9 GPIO_ACTIVE_HIGH>;
+                        linux,default-trigger = "heartbeat";
+                };
+
+                ds5 {
+                        label = "ds5";
+                        gpios = <&pioA 6 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 5e09de4eb9cd..32752d7883f1 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -860,7 +860,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_i2c_bitbang>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 93446420af25..aeb1a36373f4 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -1019,7 +1019,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
                          &pioB 5 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 59df9d73d276..127cc42e9e29 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -215,7 +215,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
 
                 24c512@50 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index e9cc99b6353a..27847a47c108 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -170,13 +170,13 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
 
                 24c512@50 {
diff --git a/arch/arm/boot/dts/at91sam9g25ek.dts b/arch/arm/boot/dts/at91sam9g25ek.dts
index 707fd4ea58f5..91a71774472e 100644
--- a/arch/arm/boot/dts/at91sam9g25ek.dts
+++ b/arch/arm/boot/dts/at91sam9g25ek.dts
@@ -26,7 +26,24 @@
 
                         i2c0: i2c@f8010000 {
                                 ov2640: camera@0x30 {
+                                        compatible = "ovti,ov2640";
+                                        reg = <0x30>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
+                                        resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
+                                        pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
+                                        clocks = <&pck0>;
+                                        clock-names = "xvclk";
+                                        assigned-clocks = <&pck0>;
+                                        assigned-clock-rates = <25000000>;
                                         status = "okay";
+
+                                        port {
+                                                ov2640_0: endpoint {
+                                                        remote-endpoint = <&isi_0>;
+                                                        bus-width = <8>;
+                                                };
+                                        };
                                 };
                         };
 
@@ -37,6 +54,15 @@
 
                         isi: isi@f8048000 {
                                 status = "okay";
+                                port {
+                                        isi_0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&ov2640_0>;
+                                                bus-width = <8>;
+                                                vsync-active = <1>;
+                                                hsync-active = <1>;
+                                        };
+                                };
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 8837b7e4292c..b3501ae2a3bd 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -1044,28 +1044,24 @@
                                 atmel,adc-res-names = "lowres", "highres";
                                 atmel,adc-use-res = "highres";
 
-                                trigger@0 {
-                                        reg = <0>;
+                                trigger0 {
                                         trigger-name = "external-rising";
                                         trigger-value = <0x1>;
                                         trigger-external;
                                 };
-                                trigger@1 {
-                                        reg = <1>;
+                                trigger1 {
                                         trigger-name = "external-falling";
                                         trigger-value = <0x2>;
                                         trigger-external;
                                 };
 
-                                trigger@2 {
-                                        reg = <2>;
+                                trigger2 {
                                         trigger-name = "external-any";
                                         trigger-value = <0x3>;
                                         trigger-external;
                                 };
 
-                                trigger@3 {
-                                        reg = <3>;
+                                trigger3 {
                                         trigger-name = "continuous";
                                         trigger-value = <0x6>;
                                 };
@@ -1169,13 +1165,13 @@
                                 clock-names = "pclk", "hclk";
                                 status = "disabled";
 
-                                ep0 {
+                                ep@0 {
                                         reg = <0>;
                                         atmel,fifo-size = <64>;
                                         atmel,nb-banks = <1>;
                                 };
 
-                                ep1 {
+                                ep@1 {
                                         reg = <1>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <2>;
@@ -1183,7 +1179,7 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep2 {
+                                ep@2 {
                                         reg = <2>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <2>;
@@ -1191,21 +1187,21 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep3 {
+                                ep@3 {
                                         reg = <3>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
                                         atmel,can-dma;
                                 };
 
-                                ep4 {
+                                ep@4 {
                                         reg = <4>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
                                         atmel,can-dma;
                                 };
 
-                                ep5 {
+                                ep@5 {
                                         reg = <5>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
@@ -1213,7 +1209,7 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep6 {
+                                ep@6 {
                                         reg = <6>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
@@ -1320,7 +1316,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
                          &pioA 21 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 95569a87b6c9..3b3eb3edcb47 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -1030,7 +1030,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
                          &pioA 31 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 6d829db4e887..70adf940d98c 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -265,25 +265,21 @@
                                 atmel,adc-res-names = "lowres", "highres";
                                 atmel,adc-use-res = "highres";
 
-                                trigger@0 {
-                                        reg = <0>;
+                                trigger0 {
                                         trigger-name = "timer-counter-0";
                                         trigger-value = <0x1>;
                                 };
-                                trigger@1 {
-                                        reg = <1>;
+                                trigger1 {
                                         trigger-name = "timer-counter-1";
                                         trigger-value = <0x3>;
                                 };
 
-                                trigger@2 {
-                                        reg = <2>;
+                                trigger2 {
                                         trigger-name = "timer-counter-2";
                                         trigger-value = <0x5>;
                                 };
 
-                                trigger@3 {
-                                        reg = <3>;
+                                trigger3 {
                                         trigger-name = "external";
                                         trigger-value = <0x13>;
                                         trigger-external;
@@ -301,13 +297,13 @@
                                 clock-names = "pclk", "hclk";
                                 status = "disabled";
 
-                                ep0 {
+                                ep@0 {
                                         reg = <0>;
                                         atmel,fifo-size = <64>;
                                         atmel,nb-banks = <1>;
                                 };
 
-                                ep1 {
+                                ep@1 {
                                         reg = <1>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <2>;
@@ -315,7 +311,7 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep2 {
+                                ep@2 {
                                         reg = <2>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <2>;
@@ -323,21 +319,21 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep3 {
+                                ep@3 {
                                         reg = <3>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
                                         atmel,can-dma;
                                 };
 
-                                ep4 {
+                                ep@4 {
                                         reg = <4>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
                                         atmel,can-dma;
                                 };
 
-                                ep5 {
+                                ep@5 {
                                         reg = <5>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
@@ -345,7 +341,7 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep6 {
+                                ep@6 {
                                         reg = <6>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
@@ -1093,7 +1089,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioA 23 GPIO_ACTIVE_HIGH>, /* sda */
                         <&pioA 24 GPIO_ACTIVE_HIGH>; /* scl */
@@ -1107,7 +1103,7 @@
                 status = "disabled";
         };
 
-        i2c@1 {
+        i2c-gpio-1 {
                 compatible = "i2c-gpio";
                 gpios = <&pioD 10 GPIO_ACTIVE_HIGH>, /* sda */
                         <&pioD 11 GPIO_ACTIVE_HIGH>; /* scl */
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index f10566f759cd..2e567d90fba8 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -227,11 +227,11 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 
-        i2c@1 {
+        i2c-gpio-1 {
                 status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index cd0cd5fd09a3..ed4e4bd8a8f1 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -1048,29 +1048,25 @@
                                 atmel,adc-res-names = "lowres", "highres";
                                 atmel,adc-use-res = "highres";
 
-                                trigger@0 {
-                                        reg = <0>;
+                                trigger0 {
                                         trigger-name = "external-rising";
                                         trigger-value = <0x1>;
                                         trigger-external;
                                 };
 
-                                trigger@1 {
-                                        reg = <1>;
+                                trigger1 {
                                         trigger-name = "external-falling";
                                         trigger-value = <0x2>;
                                         trigger-external;
                                 };
 
-                                trigger@2 {
-                                        reg = <2>;
+                                trigger2 {
                                         trigger-name = "external-any";
                                         trigger-value = <0x3>;
                                         trigger-external;
                                 };
 
-                                trigger@3 {
-                                        reg = <3>;
+                                trigger3 {
                                         trigger-name = "continuous";
                                         trigger-value = <0x6>;
                                 };
@@ -1119,13 +1115,13 @@
                                 clock-names = "hclk", "pclk";
                                 status = "disabled";
 
-                                ep0 {
+                                ep@0 {
                                         reg = <0>;
                                         atmel,fifo-size = <64>;
                                         atmel,nb-banks = <1>;
                                 };
 
-                                ep1 {
+                                ep@1 {
                                         reg = <1>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <2>;
@@ -1133,7 +1129,7 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep2 {
+                                ep@2 {
                                         reg = <2>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <2>;
@@ -1141,21 +1137,21 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep3 {
+                                ep@3 {
                                         reg = <3>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
                                         atmel,can-dma;
                                 };
 
-                                ep4 {
+                                ep@4 {
                                         reg = <4>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
                                         atmel,can-dma;
                                 };
 
-                                ep5 {
+                                ep@5 {
                                         reg = <5>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
@@ -1163,7 +1159,7 @@
                                         atmel,can-isoc;
                                 };
 
-                                ep6 {
+                                ep@6 {
                                         reg = <6>;
                                         atmel,fifo-size = <1024>;
                                         atmel,nb-banks = <3>;
@@ -1242,7 +1238,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 compatible = "i2c-gpio";
                 gpios = <&pioA 30 GPIO_ACTIVE_HIGH /* sda */
                          &pioA 31 GPIO_ACTIVE_HIGH /* scl */
@@ -1257,7 +1253,7 @@
                 status = "disabled";
         };
 
-        i2c@1 {
+        i2c-gpio-1 {
                 compatible = "i2c-gpio";
                 gpios = <&pioC 0 GPIO_ACTIVE_HIGH /* sda */
                          &pioC 1 GPIO_ACTIVE_HIGH /* scl */
@@ -1272,7 +1268,7 @@
                 status = "disabled";
         };
 
-        i2c@2 {
+        i2c-gpio-2 {
                 compatible = "i2c-gpio";
                 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
                          &pioB 5 GPIO_ACTIVE_HIGH /* scl */
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 52425a4ca97e..696b8ba064a6 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -60,18 +60,6 @@
                                 status = "okay";
                         };
 
-                        isi: isi@f8048000 {
-                                status = "disabled";
-                                port {
-                                        isi_0: endpoint@0 {
-                                                remote-endpoint = <&ov2640_0>;
-                                                bus-width = <8>;
-                                                vsync-active = <1>;
-                                                hsync-active = <1>;
-                                        };
-                                };
-                        };
-
                         i2c0: i2c@f8010000 {
                                 status = "okay";
 
@@ -79,27 +67,6 @@
                                         compatible = "wm8731";
                                         reg = <0x1a>;
                                 };
-
-                                ov2640: camera@0x30 {
-                                        compatible = "ovti,ov2640";
-                                        reg = <0x30>;
-                                        pinctrl-names = "default";
-                                        pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
-                                        resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
-                                        pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
-                                        clocks = <&pck0>;
-                                        clock-names = "xvclk";
-                                        assigned-clocks = <&pck0>;
-                                        assigned-clock-rates = <25000000>;
-                                        status = "disabled";
-
-                                        port {
-                                                ov2640_0: endpoint {
-                                                        remote-endpoint = <&isi_0>;
-                                                        bus-width = <8>;
-                                                };
-                                        };
-                                };
                         };
 
                         adc0: adc@f804c000 {
diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
index 051ab3ba9a65..afbe89c01df5 100644
--- a/arch/arm/boot/dts/axp209.dtsi
+++ b/arch/arm/boot/dts/axp209.dtsi
@@ -87,6 +87,7 @@
 
                 reg_ldo5: ldo5 {
                         regulator-name = "ldo5";
+                        status = "disabled";
                 };
         };
 
diff --git a/arch/arm/boot/dts/axp22x.dtsi b/arch/arm/boot/dts/axp22x.dtsi
index 76302f58c478..458b6681e3ec 100644
--- a/arch/arm/boot/dts/axp22x.dtsi
+++ b/arch/arm/boot/dts/axp22x.dtsi
@@ -126,10 +126,12 @@
 
                 reg_ldo_io0: ldo_io0 {
                         regulator-name = "ldo_io0";
+                        status = "disabled";
                 };
 
                 reg_ldo_io1: ldo_io1 {
                         regulator-name = "ldo_io1";
+                        status = "disabled";
                 };
 
                 reg_rtc_ldo: rtc_ldo {
@@ -139,5 +141,15 @@
                         regulator-max-microvolt = <3000000>;
                         regulator-name = "rtc_ldo";
                 };
+
+                reg_drivevbus: drivevbus {
+                        regulator-name = "drivevbus";
+                        status = "disabled";
+                };
+        };
+
+        usb_power_supply: usb_power_supply {
+                compatible = "x-powers,axp221-usb-power-supply";
+                status = "disabled";
         };
 };
diff --git a/arch/arm/boot/dts/axp809.dtsi b/arch/arm/boot/dts/axp809.dtsi
new file mode 100644
index 000000000000..ab8e5f2d9246
--- /dev/null
+++ b/arch/arm/boot/dts/axp809.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2015 Chen-Yu Tsai
+ *
+ * Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * AXP809 Integrated Power Management Chip
+ */
+
+&axp809 {
+        compatible = "x-powers,axp809";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+};
diff --git a/arch/arm/boot/dts/bcm-cygnus.dtsi b/arch/arm/boot/dts/bcm-cygnus.dtsi
index b42fe5596b94..fabc9f36c408 100644
--- a/arch/arm/boot/dts/bcm-cygnus.dtsi
+++ b/arch/arm/boot/dts/bcm-cygnus.dtsi
@@ -366,5 +366,16 @@
                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
                         status = "disabled";
                 };
+
+                adc: adc@180a6000 {
+                        compatible = "brcm,iproc-static-adc";
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        adc-syscon = <&ts_adc_syscon>;
+                        clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
+                        clock-names = "tsc_clk";
+                        interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 6a40ed7d0502..c3bf7d23f136 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -57,7 +57,7 @@
                         compatible = "arm,cortex-a9";
                         next-level-cache = <&L2>;
                         enable-method = "brcm,bcm-nsp-smp";
-                        secondary-boot-reg = <0xffff042c>;
+                        secondary-boot-reg = <0xffff0fec>;
                         reg = <0x1>;
                 };
         };
@@ -192,6 +192,23 @@
                         status = "disabled";
                 };
 
+                dma@20000 {
+                        compatible = "arm,pl330", "arm,primecell";
+                        reg = <0x20000 0x1000>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&iprocslow>;
+                        clock-names = "apb_pclk";
+                        #dma-cells = <1>;
+                };
+
                 nand: nand@26000 {
                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
                         reg = <0x026000 0x600>,
@@ -337,6 +354,18 @@
                 ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
 
                 status = "disabled";
+
+                msi-parent = <&msi0>;
+                msi0: msi@18012000 {
+                        compatible = "brcm,iproc-msi";
+                        msi-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 128 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 129 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 130 IRQ_TYPE_NONE>;
+                        brcm,pcie-msi-inten;
+                };
         };
 
         pcie1: pcie@18013000 {
@@ -361,6 +390,18 @@
                 ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
 
                 status = "disabled";
+
+                msi-parent = <&msi1>;
+                msi1: msi@18013000 {
+                        compatible = "brcm,iproc-msi";
+                        msi-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <GIC_SPI 133 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 134 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 135 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 136 IRQ_TYPE_NONE>;
+                        brcm,pcie-msi-inten;
+                };
         };
 
         pcie2: pcie@18014000 {
@@ -385,5 +426,17 @@
                 ranges = <0x82000000 0 0x48000000 0x48000000 0 0x8000000>;
 
                 status = "disabled";
+
+                msi-parent = <&msi2>;
+                msi2: msi@18014000 {
+                        compatible = "brcm,iproc-msi";
+                        msi-controller;
+                        interrupt-parent = <&gic>;
+                        interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 140 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 141 IRQ_TYPE_NONE>,
+                                     <GIC_SPI 142 IRQ_TYPE_NONE>;
+                        brcm,pcie-msi-inten;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 3dc7a8cc5812..18045c38bcf1 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -30,7 +30,6 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                enable-method = "brcm,bcm11351-cpu-method";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -41,6 +40,7 @@
                 cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
+                        enable-method = "brcm,bcm11351-cpu-method";
                         secondary-boot-reg = <0x3500417c>;
                         reg = <1>;
                 };
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 3f525be28fd0..6dde95f21cef 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -30,7 +30,6 @@
        cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
-                enable-method = "brcm,bcm11351-cpu-method";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -41,6 +40,7 @@
                 cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a9";
+                        enable-method = "brcm,bcm11351-cpu-method";
                         secondary-boot-reg = <0x35004178>;
                         reg = <1>;
                 };
diff --git a/arch/arm/boot/dts/bcm23550-sparrow.dts b/arch/arm/boot/dts/bcm23550-sparrow.dts
new file mode 100644
index 000000000000..4d525ccb48c8
--- /dev/null
+++ b/arch/arm/boot/dts/bcm23550-sparrow.dts
@@ -0,0 +1,80 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2016 Broadcom.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+#include "bcm23550.dtsi"
+
+/ {
+        model = "BCM23550 Sparrow board";
+        compatible = "brcm,bcm23550-sparrow", "brcm,bcm23550";
+
+        chosen {
+                stdout-path = "/slaves@3e000000/serial@0:115200n8";
+                bootargs = "console=ttyS0,115200n8";
+        };
+
+        memory {
+                reg = <0x80000000 0x20000000>; /* 512 MB */
+        };
+};
+
+&uartb {
+        status = "okay";
+};
+
+&usbotg {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+};
+
+&sdio1 {
+        max-frequency = <48000000>;
+        status = "okay";
+};
+
+&sdio2 {
+        non-removable;
+        max-frequency = <48000000>;
+        status = "okay";
+};
+
+&sdio4 {
+        max-frequency = <48000000>;
+        cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm23550.dtsi b/arch/arm/boot/dts/bcm23550.dtsi
new file mode 100644
index 000000000000..a7a643f38385
--- /dev/null
+++ b/arch/arm/boot/dts/bcm23550.dtsi
@@ -0,0 +1,415 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2016 Broadcom.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* BCM23550 and BCM21664 have almost identical clocks */
+#include "dt-bindings/clock/bcm21664.h"
+
+#include "skeleton.dtsi"
+
+/ {
+        model = "BCM23550 SoC";
+        compatible = "brcm,bcm23550";
+        interrupt-parent = <&gic>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        enable-method = "brcm,bcm23550";
+                        secondary-boot-reg = <0x35004178>;
+                        reg = <1>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        enable-method = "brcm,bcm23550";
+                        secondary-boot-reg = <0x35004178>;
+                        reg = <2>;
+                        clock-frequency = <1000000000>;
+                };
+
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        enable-method = "brcm,bcm23550";
+                        secondary-boot-reg = <0x35004178>;
+                        reg = <3>;
+                        clock-frequency = <1000000000>;
+                };
+        };
+
+        /* Hub bus */
+        hub@34000000 {
+                compatible = "simple-bus";
+                ranges = <0 0x34000000 0x102f83ac>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                smc@4e000 {
+                        compatible = "brcm,bcm23550-smc", "brcm,kona-smc";
+                        reg = <0x0004e000 0x400>; /* 1 KiB in SRAM */
+                };
+
+                resetmgr: reset-controller@1001f00 {
+                        compatible = "brcm,bcm21664-resetmgr";
+                        reg = <0x01001f00 0x24>;
+                };
+
+                gpio: gpio@1003000 {
+                        compatible = "brcm,bcm23550-gpio", "brcm,kona-gpio";
+                        reg = <0x01003000 0x524>;
+                        interrupts =
+                               <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
+                                GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        #gpio-cells = <2>;
+                        #interrupt-cells = <2>;
+                        gpio-controller;
+                        interrupt-controller;
+                };
+
+                timer@1006000 {
+                        compatible = "brcm,kona-timer";
+                        reg = <0x01006000 0x1c>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
+                };
+        };
+
+        /* Slaves bus */
+        slaves@3e000000 {
+                compatible = "simple-bus";
+                ranges = <0 0x3e000000 0x0001c070>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                uartb: serial@0 {
+                        compatible = "snps,dw-apb-uart";
+                        status = "disabled";
+                        reg = <0x00000000 0x118>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
+                        interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uartb2: serial@1000 {
+                        compatible = "snps,dw-apb-uart";
+                        status = "disabled";
+                        reg = <0x00001000 0x118>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                uartb3: serial@2000 {
+                        compatible = "snps,dw-apb-uart";
+                        status = "disabled";
+                        reg = <0x00002000 0x118>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
+                        interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        reg-shift = <2>;
+                        reg-io-width = <4>;
+                };
+
+                bsc1: i2c@16000 {
+                        compatible = "brcm,kona-i2c";
+                        reg = <0x00016000 0x70>;
+                        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
+                        status = "disabled";
+                };
+
+                bsc2: i2c@17000 {
+                        compatible = "brcm,kona-i2c";
+                        reg = <0x00017000 0x70>;
+                        interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
+                        status = "disabled";
+                };
+
+                bsc3: i2c@18000 {
+                        compatible = "brcm,kona-i2c";
+                        reg = <0x00018000 0x70>;
+                        interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
+                        status = "disabled";
+                };
+
+                bsc4: i2c@1c000 {
+                        compatible = "brcm,kona-i2c";
+                        reg = <0x0001c000 0x70>;
+                        interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
+                        status = "disabled";
+                };
+        };
+
+        /* Apps bus */
+        apps@3e300000 {
+                compatible = "simple-bus";
+                ranges = <0 0x3e300000 0x01b77000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                usbotg: usb@e20000 {
+                        compatible = "snps,dwc2";
+                        reg = <0x00e20000 0x10000>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&usb_otg_ahb_clk>;
+                        clock-names = "otg";
+                        phys = <&usbphy>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+
+                usbphy: usb-phy@e30000 {
+                        compatible = "brcm,kona-usb2-phy";
+                        reg = <0x00e30000 0x28>;
+                        #phy-cells = <0>;
+                        status = "disabled";
+                };
+
+                sdio1: sdio@e80000 {
+                        compatible = "brcm,kona-sdhci";
+                        reg = <0x00e80000 0x801c>;
+                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
+                        status = "disabled";
+                };
+
+                sdio2: sdio@e90000 {
+                        compatible = "brcm,kona-sdhci";
+                        reg = <0x00e90000 0x801c>;
+                        interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
+                        status = "disabled";
+                };
+
+                sdio3: sdio@ea0000 {
+                        compatible = "brcm,kona-sdhci";
+                        reg = <0x00ea0000 0x801c>;
+                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
+                        status = "disabled";
+                };
+
+                sdio4: sdio@eb0000 {
+                        compatible = "brcm,kona-sdhci";
+                        reg = <0x00eb0000 0x801c>;
+                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
+                        status = "disabled";
+                };
+
+                cdc: cdc@1b0e000 {
+                        compatible = "brcm,bcm23550-cdc";
+                        reg = <0x01b0e000 0x78>;
+                };
+
+                gic: interrupt-controller@1b21000 {
+                        compatible = "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x01b21000 0x1000>,
+                              <0x01b22000 0x1000>;
+                };
+        };
+
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                /*
+                 * Fixed clocks are defined before CCUs whose
+                 * clocks may depend on them.
+                 */
+
+                ref_32k_clk: ref_32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                bbl_32k_clk: bbl_32k {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
+                };
+
+                ref_13m_clk: ref_13m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                };
+
+                var_13m_clk: var_13m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <13000000>;
+                };
+
+                dft_19_5m_clk: dft_19_5m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <19500000>;
+                };
+
+                ref_crystal_clk: ref_crystal {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <26000000>;
+                };
+
+                ref_52m_clk: ref_52m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
+                };
+
+                var_52m_clk: var_52m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
+                };
+
+                usb_otg_ahb_clk: usb_otg_ahb {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
+                };
+
+                ref_96m_clk: ref_96m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <96000000>;
+                };
+
+                var_96m_clk: var_96m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <96000000>;
+                };
+
+                ref_104m_clk: ref_104m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <104000000>;
+                };
+
+                var_104m_clk: var_104m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <104000000>;
+                };
+
+                ref_156m_clk: ref_156m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <156000000>;
+                };
+
+                var_156m_clk: var_156m {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <156000000>;
+                };
+
+                root_ccu: root_ccu {
+                        compatible = BCM21664_DT_ROOT_CCU_COMPAT;
+                        reg = <0x35001000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "frac_1m";
+                };
+
+                aon_ccu: aon_ccu {
+                        compatible = BCM21664_DT_AON_CCU_COMPAT;
+                        reg = <0x35002000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "hub_timer";
+                };
+
+                slave_ccu: slave_ccu {
+                        compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
+                        reg = <0x3e011000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "uartb",
+                                             "uartb2",
+                                             "uartb3",
+                                             "bsc1",
+                                             "bsc2",
+                                             "bsc3",
+                                             "bsc4";
+                };
+
+                master_ccu: master_ccu {
+                        compatible = BCM21664_DT_MASTER_CCU_COMPAT;
+                        reg = <0x3f001000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "sdio1",
+                                             "sdio2",
+                                             "sdio3",
+                                             "sdio4",
+                                             "sdio1_sleep",
+                                             "sdio2_sleep",
+                                             "sdio3_sleep",
+                                             "sdio4_sleep";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
index 57d313b6afaf..d5fdb8e761a3 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-plus.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 #include "bcm2835.dtsi"
 #include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9514.dtsi"
 
 / {
         compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
index cf2774ec0834..bfc4bd9b7733 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b-rev2.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 #include "bcm2835.dtsi"
 #include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9512.dtsi"
 
 / {
         compatible = "raspberrypi,model-b-rev2", "brcm,bcm2835";
diff --git a/arch/arm/boot/dts/bcm2835-rpi-b.dts b/arch/arm/boot/dts/bcm2835-rpi-b.dts
index 8b15f9c35643..0371bb7374b8 100644
--- a/arch/arm/boot/dts/bcm2835-rpi-b.dts
+++ b/arch/arm/boot/dts/bcm2835-rpi-b.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 #include "bcm2835.dtsi"
 #include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9512.dtsi"
 
 / {
         compatible = "raspberrypi,model-b", "brcm,bcm2835";
diff --git a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
index c4743f42237b..29e1cfe8eb14 100644
--- a/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
+++ b/arch/arm/boot/dts/bcm2836-rpi-2-b.dts
@@ -1,6 +1,7 @@
 /dts-v1/;
 #include "bcm2836.dtsi"
 #include "bcm2835-rpi.dtsi"
+#include "bcm283x-rpi-smsc9514.dtsi"
 
 / {
         compatible = "raspberrypi,2-model-b", "brcm,bcm2836";
diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
new file mode 100644
index 000000000000..12c981e51134
--- /dev/null
+++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9512.dtsi
@@ -0,0 +1,19 @@
+/ {
+        aliases {
+                ethernet = &ethernet;
+        };
+};
+
+&usb {
+        usb1@1 {
+                compatible = "usb424,9512";
+                reg = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethernet: usbether@1 {
+                        compatible = "usb424,ec00";
+                        reg = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
new file mode 100644
index 000000000000..3f0a56ebcf1f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm283x-rpi-smsc9514.dtsi
@@ -0,0 +1,19 @@
+/ {
+        aliases {
+                ethernet = &ethernet;
+        };
+};
+
+&usb {
+        usb1@1 {
+                compatible = "usb424,9514";
+                reg = <1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                ethernet: usbether@1 {
+                        compatible = "usb424,ec00";
+                        reg = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 10b27b912bac..b98252232d20 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -287,6 +287,8 @@
                         compatible = "brcm,bcm2835-usb";
                         reg = <0x7e980000 0x10000>;
                         interrupts = <1 9>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                 };
 
                 v3d: v3d@7ec00000 {
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index 5087aa81efb1..9cb186ea2e97 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -147,3 +147,7 @@
 &usb3 {
         vcc-gpio = <&chipcommon 10 GPIO_ACTIVE_LOW>;
 };
+
+&spi_nor {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
index 1049ab108b32..8ce39d58eeb8 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
@@ -90,3 +90,7 @@
 &usb3 {
         vcc-gpio = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
 };
+
+&spi_nor {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
index 3a94606d042b..6229ef283c41 100644
--- a/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
+++ b/arch/arm/boot/dts/bcm4708-netgear-r6300-v2.dts
@@ -82,3 +82,7 @@
                 };
         };
 };
+
+&spi_nor {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
index 8b0c440b2e71..70f4bb9d864a 100644
--- a/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
+++ b/arch/arm/boot/dts/bcm4708-smartrg-sr400ac.dts
@@ -126,3 +126,43 @@
 &spi_nor {
         status = "okay";
 };
+
+&srab {
+        status = "okay";
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        label = "lan4";
+                };
+
+                port@1 {
+                        reg = <1>;
+                        label = "lan3";
+                };
+
+                port@2 {
+                        reg = <2>;
+                        label = "lan2";
+                };
+
+                port@3 {
+                        reg = <3>;
+                        label = "lan1";
+                };
+
+                port@4 {
+                        reg = <4>;
+                        label = "wan";
+                };
+
+                port@5 {
+                        reg = <5>;
+                        label = "cpu";
+                        ethernet = <&gmac0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index 791d7225c733..0653e7ef248c 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -131,3 +131,7 @@
 &usb2 {
         vcc-gpio = <&chipcommon 13 GPIO_ACTIVE_HIGH>;
 };
+
+&spi_nor {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
index ace38efd2db3..c8c0b3616935 100644
--- a/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
+++ b/arch/arm/boot/dts/bcm47094-dlink-dir-885l.dts
@@ -10,7 +10,7 @@
 /dts-v1/;
 
 #include "bcm4708.dtsi"
-#include "bcm5301x-nand-cs0-bch8.dtsi"
+#include "bcm5301x-nand-cs0-bch1.dtsi"
 
 / {
         compatible = "dlink,dir-885l", "brcm,bcm47094", "brcm,bcm4708";
@@ -113,3 +113,7 @@
 &usb3 {
         vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
 };
+
+&spi_nor {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi
new file mode 100644
index 000000000000..24b099c00f13
--- /dev/null
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch1.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Broadcom Northstar NAND.
+ *
+ * Copyright (C) 2016 Rafał Miłecki <rafal.milecki@gmail.com>
+ *
+ * Licensed under the ISC license.
+ */
+
+#include "bcm5301x-nand-cs0.dtsi"
+
+&nandcs {
+        nand-ecc-algo = "bch";
+        nand-ecc-strength = <1>;
+        nand-ecc-step-size = <512>;
+};
diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi
index d10781e36f54..9a9630ded306 100644
--- a/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0-bch8.dtsi
@@ -9,16 +9,10 @@
  * Licensed under the GNU/GPL. See COPYING for details.
  */
 
-/ {
-        nand@18028000 {
-                nandcs@0 {
-                        compatible = "brcm,nandcs";
-                        reg = <0>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
+#include "bcm5301x-nand-cs0.dtsi"
 
-                        nand-ecc-strength = <8>;
-                        nand-ecc-step-size = <512>;
-                };
-        };
+&nandcs {
+        nand-ecc-algo = "bch";
+        nand-ecc-strength = <8>;
+        nand-ecc-step-size = <512>;
 };
diff --git a/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
new file mode 100644
index 000000000000..168495106b82
--- /dev/null
+++ b/arch/arm/boot/dts/bcm5301x-nand-cs0.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Broadcom Northstar NAND.
+ *
+ * Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+/ {
+        nand@18028000 {
+                nandcs: nandcs@0 {
+                        compatible = "brcm,nandcs";
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
index 7d4d29bf0ed3..8af47913b3b4 100644
--- a/arch/arm/boot/dts/bcm5301x.dtsi
+++ b/arch/arm/boot/dts/bcm5301x.dtsi
@@ -153,6 +153,21 @@
                         /* ChipCommon */
                         <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
 
+                        /* Switch Register Access Block */
+                        <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+
                         /* PCIe Controller 0 */
                         <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
                         <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
@@ -239,6 +254,22 @@
                                 status = "disabled";
                         };
                 };
+
+                gmac0: ethernet@24000 {
+                        reg = <0x24000 0x800>;
+                };
+
+                gmac1: ethernet@25000 {
+                        reg = <0x25000 0x800>;
+                };
+
+                gmac2: ethernet@26000 {
+                        reg = <0x26000 0x800>;
+                };
+
+                gmac3: ethernet@27000 {
+                        reg = <0x27000 0x800>;
+                };
         };
 
         lcpll0: lcpll0@1800c100 {
@@ -260,6 +291,22 @@
                                      "sata2";
         };
 
+        srab: srab@18007000 {
+                compatible = "brcm,bcm5301x-srab";
+                reg = <0x18007000 0x1000>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                status = "disabled";
+
+                /* ports are defined in board DTS */
+        };
+
+        rng: rng@18004000 {
+                compatible = "brcm,bcm5301x-rng";
+                reg = <0x18004000 0x14>;
+        };
+
         nand: nand@18028000 {
                 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
                 reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
diff --git a/arch/arm/boot/dts/bcm953012er.dts b/arch/arm/boot/dts/bcm953012er.dts
new file mode 100644
index 000000000000..0a9abecf9423
--- /dev/null
+++ b/arch/arm/boot/dts/bcm953012er.dts
@@ -0,0 +1,104 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2016 Broadcom. All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm4708.dtsi"
+#include "bcm5301x-nand-cs0-bch8.dtsi"
+
+/ {
+        model = "NorthStar Enterprise Router (BCM953012ER)";
+        compatible = "brcm,bcm953012er", "brcm,brcm53012", "brcm,bcm4708";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                reg = <0x00000000 0x8000000>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                wps {
+                        label = "WPS";
+                        linux,code = <KEY_WPS_BUTTON>;
+                        gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
+                };
+
+                restart {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&spi_nor {
+        status = "okay";
+};
+
+&srab {
+        status = "okay";
+
+        ports {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        label = "port0";
+                };
+
+                port@1 {
+                        reg = <1>;
+                        label = "port1";
+                };
+
+                port@5 {
+                        reg = <5>;
+                        label = "cpu";
+                        ethernet = <&gmac0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
new file mode 100644
index 000000000000..d257e83dedfc
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -0,0 +1,109 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright(c) 2016 Broadcom.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-nsp.dtsi"
+
+/ {
+        model = "NorthStar Plus XMC (BCM958525xmc)";
+        compatible = "brcm,bcm58525", "brcm,nsp";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&nand {
+        nandcs@0 {
+                compatible = "brcm,nandcs";
+                reg = <0>;
+                nand-on-flash-bbt;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                nand-ecc-strength = <24>;
+                nand-ecc-step-size = <1024>;
+
+                brcm,nand-oob-sector-size = <27>;
+
+                partition@0 {
+                        label = "nboot";
+                        reg = <0x00000000 0x00200000>;
+                        read-only;
+                };
+                partition@200000 {
+                        label = "nenv";
+                        reg = <0x00200000 0x00400000>;
+                };
+                partition@600000 {
+                        label = "nsystem";
+                        reg = <0x00600000 0x00a00000>;
+                };
+                partition@1000000 {
+                        label = "nrootfs";
+                        reg = <0x01000000 0x03000000>;
+                };
+                partition@4000000 {
+                        label = "ncustfs";
+                        reg = <0x04000000 0x3c000000>;
+                };
+        };
+};
+
+/* XHCI, SATA, MMC, and Ethernet support needed to be complete */
+
+&uart0 {
+        status = "okay";
+};
+
+&pcie0 {
+        status = "okay";
+};
+
+&pcie1 {
+        status = "okay";
+};
+
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_sel>;
+        nand_sel: nand_sel {
+                function = "nand";
+                groups = "nand_grp";
+        };
+};
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
new file mode 100644
index 000000000000..03b8bbeb694f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -0,0 +1,111 @@
+/*
+ *  BSD LICENSE
+ *
+ *  Copyright (c) 2016 Broadcom.  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    * Redistributions of source code must retain the above copyright
+ *      notice, this list of conditions and the following disclaimer.
+ *    * Redistributions in binary form must reproduce the above copyright
+ *      notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the
+ *      distribution.
+ *    * Neither the name of Broadcom Corporation nor the names of its
+ *      contributors may be used to endorse or promote products derived
+ *      from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/dts-v1/;
+
+#include "bcm-nsp.dtsi"
+
+/ {
+        model = "NorthStar Plus SVK (BCM958625HR)";
+        compatible = "brcm,bcm58625", "brcm,nsp";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory {
+                reg = <0x60000000 0x20000000>;
+        };
+};
+
+&nand {
+        nandcs@0 {
+                compatible = "brcm,nandcs";
+                reg = <0>;
+                nand-on-flash-bbt;
+
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                nand-ecc-strength = <24>;
+                nand-ecc-step-size = <1024>;
+
+                brcm,nand-oob-sector-size = <27>;
+
+                partition@0 {
+                        label = "nboot";
+                        reg = <0x00000000 0x00200000>;
+                        read-only;
+                };
+                partition@200000 {
+                        label = "nenv";
+                        reg = <0x00200000 0x00400000>;
+                };
+                partition@600000 {
+                        label = "nsystem";
+                        reg = <0x00600000 0x00a00000>;
+                };
+                partition@1000000 {
+                        label = "nrootfs";
+                        reg = <0x01000000 0x03000000>;
+                };
+                partition@4000000 {
+                        label = "ncustfs";
+                        reg = <0x04000000 0x3c000000>;
+                };
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&pcie0 {
+        status = "okay";
+};
+
+&pcie1 {
+        status = "okay";
+};
+
+&pinctrl {
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_sel>;
+        nand_sel: nand_sel {
+                function = "nand";
+                groups = "nand_grp";
+        };
+};
diff --git a/arch/arm/boot/dts/compulab-sb-som.dtsi b/arch/arm/boot/dts/compulab-sb-som.dtsi
index 93d7e235bc80..4af1adfee788 100644
--- a/arch/arm/boot/dts/compulab-sb-som.dtsi
+++ b/arch/arm/boot/dts/compulab-sb-som.dtsi
@@ -40,7 +40,7 @@
                 };
         };
 
-        hdmi_conn: connector@0 {
+        hdmi_conn: connector {
                 compatible = "hdmi-connector";
                 label = "hdmi";
 
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index f23cae0c2179..68e412c9863c 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -448,7 +448,7 @@
                         reg =   <0x49000000 0x10000>;
                         reg-names = "edma3_cc";
                         interrupts = <12 13 14>;
-                        interrupt-names = "edma3_ccint", "emda3_mperr",
+                        interrupt-names = "edma3_ccint", "edma3_mperr",
                                           "edma3_ccerrint";
                         dma-requests = <64>;
                         #dma-cells = <2>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index de559f6e4fee..d9bfb94a2992 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -73,6 +73,49 @@
                 interrupt-parent = <&gic>;
         };
 
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+
+                        operating-points-v2 = <&cpu0_opp_table>;
+                        ti,syscon-efuse = <&scm_wkup 0x20c 0xf80000 19>;
+                        ti,syscon-rev = <&scm_wkup 0x204>;
+
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
+
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
+
+                        /* cooling options */
+                        cooling-min-level = <0>;
+                        cooling-max-level = <2>;
+                        #cooling-cells = <2>; /* min followed by max */
+                };
+        };
+
+        cpu0_opp_table: opp_table0 {
+                compatible = "operating-points-v2";
+                opp-shared;
+
+                opp_nom@1000000000 {
+                        opp-hz = /bits/ 64 <1000000000>;
+                        opp-microvolt = <1060000 850000 1150000>;
+                        opp-supported-hw = <0xFF 0x01>;
+                        opp-suspend;
+                };
+
+                opp_od@1176000000 {
+                        opp-hz = /bits/ 64 <1176000000>;
+                        opp-microvolt = <1160000 885000 1160000>;
+                        opp-supported-hw = <0xFF 0x02>;
+                };
+        };
+
         /*
          * The soc node represents the soc top level view. It is used for IPs
          * that are not memory mapped in the MPU view or for the MPU itself.
@@ -233,6 +276,11 @@
                                 prm_clockdomains: clockdomains {
                                 };
                         };
+
+                        scm_wkup: scm_conf@c000 {
+                                compatible = "syscon";
+                                reg = <0xc000 0x1000>;
+                        };
                 };
 
                 axi@0 {
@@ -276,7 +324,7 @@
                         ranges = <0x51800000 0x51800000 0x3000
                                   0x0        0x30000000 0x10000000>;
                         status = "disabled";
-                        pcie@51000000 {
+                        pcie@51800000 {
                                 compatible = "ti,dra7-pcie";
                                 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
                                 reg-names = "rc_dbics", "ti_conf", "config";
@@ -304,6 +352,53 @@
                         };
                 };
 
+                ocmcram1: ocmcram@40300000 {
+                        compatible = "mmio-sram";
+                        reg = <0x40300000 0x80000>;
+                        ranges = <0x0 0x40300000 0x80000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        /*
+                         * This is a placeholder for an optional reserved
+                         * region for use by secure software. The size
+                         * of this region is not known until runtime so it
+                         * is set as zero to either be updated to reserve
+                         * space or left unchanged to leave all SRAM for use.
+                         * On HS parts that that require the reserved region
+                         * either the bootloader can update the size to
+                         * the required amount or the node can be overridden
+                         * from the board dts file for the secure platform.
+                         */
+                        sram-hs@0 {
+                                compatible = "ti,secure-ram";
+                                reg = <0x0 0x0>;
+                        };
+                };
+
+                /*
+                 * NOTE: ocmcram2 and ocmcram3 are not available on all
+                 * DRA7xx and AM57xx variants. Confirm availability in
+                 * the data manual for the exact part number in use
+                 * before enabling these nodes in the board dts file.
+                 */
+                ocmcram2: ocmcram@40400000 {
+                        status = "disabled";
+                        compatible = "mmio-sram";
+                        reg = <0x40400000 0x100000>;
+                        ranges = <0x0 0x40400000 0x100000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                };
+
+                ocmcram3: ocmcram@40500000 {
+                        status = "disabled";
+                        compatible = "mmio-sram";
+                        reg = <0x40500000 0x100000>;
+                        ranges = <0x0 0x40500000 0x100000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                };
+
                 bandgap: bandgap@4a0021e0 {
                         reg = <0x4a0021e0 0xc
                                 0x4a00232c 0xc
@@ -341,7 +436,7 @@
                         interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
                                      <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupt-names = "edma3_ccint", "emda3_mperr",
+                        interrupt-names = "edma3_ccint", "edma3_mperr",
                                           "edma3_ccerrint";
                         dma-requests = <64>;
                         #dma-cells = <2>;
@@ -1744,6 +1839,149 @@
                                 clock-names = "fck", "sys_clk";
                         };
                 };
+
+                epwmss0: epwmss@4843e000 {
+                        compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+                        reg = <0x4843e000 0x30>;
+                        ti,hwmods = "epwmss0";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges;
+
+                        ehrpwm0: pwm@4843e200 {
+                                compatible = "ti,dra746-ehrpwm",
+                                             "ti,am3352-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x4843e200 0x80>;
+                                clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
+                                clock-names = "tbclk", "fck";
+                                status = "disabled";
+                        };
+
+                        ecap0: ecap@4843e100 {
+                                compatible = "ti,dra746-ecap",
+                                             "ti,am3352-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x4843e100 0x80>;
+                                clocks = <&l4_root_clk_div>;
+                                clock-names = "fck";
+                                status = "disabled";
+                        };
+                };
+
+                epwmss1: epwmss@48440000 {
+                        compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+                        reg = <0x48440000 0x30>;
+                        ti,hwmods = "epwmss1";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges;
+
+                        ehrpwm1: pwm@48440200 {
+                                compatible = "ti,dra746-ehrpwm",
+                                             "ti,am3352-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48440200 0x80>;
+                                clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
+                                clock-names = "tbclk", "fck";
+                                status = "disabled";
+                        };
+
+                        ecap1: ecap@48440100 {
+                                compatible = "ti,dra746-ecap",
+                                             "ti,am3352-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48440100 0x80>;
+                                clocks = <&l4_root_clk_div>;
+                                clock-names = "fck";
+                                status = "disabled";
+                        };
+                };
+
+                epwmss2: epwmss@48442000 {
+                        compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
+                        reg = <0x48442000 0x30>;
+                        ti,hwmods = "epwmss2";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                        ranges;
+
+                        ehrpwm2: pwm@48442200 {
+                                compatible = "ti,dra746-ehrpwm",
+                                             "ti,am3352-ehrpwm";
+                                #pwm-cells = <3>;
+                                reg = <0x48442200 0x80>;
+                                clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
+                                clock-names = "tbclk", "fck";
+                                status = "disabled";
+                        };
+
+                        ecap2: ecap@48442100 {
+                                compatible = "ti,dra746-ecap",
+                                             "ti,am3352-ecap";
+                                #pwm-cells = <3>;
+                                reg = <0x48442100 0x80>;
+                                clocks = <&l4_root_clk_div>;
+                                clock-names = "fck";
+                                status = "disabled";
+                        };
+                };
+
+                aes1: aes@4b500000 {
+                        compatible = "ti,omap4-aes";
+                        ti,hwmods = "aes1";
+                        reg = <0x4b500000 0xa0>;
+                        interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+                        dma-names = "tx", "rx";
+                        clocks = <&l3_iclk_div>;
+                        clock-names = "fck";
+                };
+
+                aes2: aes@4b700000 {
+                        compatible = "ti,omap4-aes";
+                        ti,hwmods = "aes2";
+                        reg = <0x4b700000 0xa0>;
+                        interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+                        dma-names = "tx", "rx";
+                        clocks = <&l3_iclk_div>;
+                        clock-names = "fck";
+                };
+
+                des: des@480a5000 {
+                        compatible = "ti,omap4-des";
+                        ti,hwmods = "des";
+                        reg = <0x480a5000 0xa0>;
+                        interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
+                        dma-names = "tx", "rx";
+                        clocks = <&l3_iclk_div>;
+                        clock-names = "fck";
+                };
+
+                sham: sham@53100000 {
+                        compatible = "ti,omap5-sham";
+                        ti,hwmods = "sham";
+                        reg = <0x4b101000 0x300>;
+                        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+                        dmas = <&edma_xbar 119 0>;
+                        dma-names = "rx";
+                        clocks = <&l3_iclk_div>;
+                        clock-names = "fck";
+                };
+
+                rng: rng@48090000 {
+                        compatible = "ti,omap4-rng";
+                        ti,hwmods = "rng";
+                        reg = <0x48090000 0x2000>;
+                        interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&l3_iclk_div>;
+                        clock-names = "fck";
+                };
         };
 
         thermal_zones: thermal-zones {
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 093538ea5b5f..9d3cf50ca37e 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -18,7 +18,7 @@
                 display0 = &hdmi0;
         };
 
-        evm_3v3: fixedregulator-evm_3v3 {
+        evm_3v3_sw: fixedregulator-evm_3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "evm_3v3";
                 regulator-min-microvolt = <3300000>;
@@ -29,7 +29,7 @@
                 /* TPS77018DBVT */
                 compatible = "regulator-fixed";
                 regulator-name = "aic_dvdd";
-                vin-supply = <&evm_3v3>;
+                vin-supply = <&evm_3v3_sw>;
                 regulator-min-microvolt = <1800000>;
                 regulator-max-microvolt = <1800000>;
         };
@@ -414,9 +414,9 @@
                 status = "okay";
 
                 /* Regulators */
-                AVDD-supply = <&evm_3v3>;
-                IOVDD-supply = <&evm_3v3>;
-                DRVDD-supply = <&evm_3v3>;
+                AVDD-supply = <&evm_3v3_sw>;
+                IOVDD-supply = <&evm_3v3_sw>;
+                DRVDD-supply = <&evm_3v3_sw>;
                 DVDD-supply = <&aic_dvdd>;
         };
 };
@@ -597,7 +597,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mmc2_pins_default>;
 
-        vmmc-supply = <&evm_3v3>;
+        vmmc-supply = <&evm_3v3_sw>;
         bus-width = <8>;
         ti,non-removable;
         max-frequency = <192000000>;
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index 70a217050a4c..67107605fb4c 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -12,22 +12,6 @@
 / {
         compatible = "ti,dra722", "ti,dra72", "ti,dra7";
 
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu0: cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a15";
-                        reg = <0>;
-
-                        /* cooling options */
-                        cooling-min-level = <0>;
-                        cooling-max-level = <2>;
-                        #cooling-cells = <2>; /* min followed by max */
-                };
-        };
-
         pmu {
                 compatible = "arm,cortex-a15-pmu";
                 interrupt-parent = <&wakeupgen>;
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 5e06020f450b..8987b3e180a1 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -13,34 +13,11 @@
         compatible = "ti,dra742", "ti,dra74", "ti,dra7";
 
         cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu0: cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a15";
-                        reg = <0>;
-
-                        operating-points = <
-                                /* kHz    uV */
-                                1000000 1060000
-                                1176000 1160000
-                                >;
-
-                        clocks = <&dpll_mpu_ck>;
-                        clock-names = "cpu";
-
-                        clock-latency = <300000>; /* From omap-cpufreq driver */
-
-                        /* cooling options */
-                        cooling-min-level = <0>;
-                        cooling-max-level = <2>;
-                        #cooling-cells = <2>; /* min followed by max */
-                };
                 cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <1>;
+                        operating-points-v2 = <&cpu0_opp_table>;
                 };
         };
 
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index a35b851e1cd7..60d0a732833a 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -18,14 +18,18 @@
         model = "EMEV2 KZM9D Board";
         compatible = "renesas,kzm9d", "renesas,emev2";
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0x8000000>;
         };
 
+        aliases {
+                serial1 = &uart1;
+        };
+
         chosen {
-                bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";
-                stdout-path = &uart1;
+                bootargs = "ignore_loglevel root=/dev/nfs ip=dhcp";
+                stdout-path = "serial1:115200n8";
         };
 
         gpio_keys {
@@ -33,28 +37,28 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                button@1 {
+                one {
                         debounce_interval = <50>;
                         wakeup-source;
                         label = "DSW2-1";
                         linux,code = <KEY_1>;
                         gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
                 };
-                button@2 {
+                two {
                         debounce_interval = <50>;
                         wakeup-source;
                         label = "DSW2-2";
                         linux,code = <KEY_2>;
                         gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
                 };
-                button@3 {
+                three {
                         debounce_interval = <50>;
                         wakeup-source;
                         label = "DSW2-3";
                         linux,code = <KEY_3>;
                         gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
                 };
-                button@4 {
+                four {
                         debounce_interval = <50>;
                         wakeup-source;
                         label = "DSW2-4";
@@ -63,7 +67,7 @@
                 };
         };
 
-        reg_1p8v: regulator@0 {
+        reg_1p8v: regulator-1p8v {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-1.8V";
                 regulator-min-microvolt = <1800000>;
@@ -72,7 +76,7 @@
                 regulator-boot-on;
         };
 
-        reg_3p3v: regulator@1 {
+        reg_3p3v: regulator-3p3v {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -104,7 +108,7 @@
 };
 
 &pfc {
-        uart1_pins: serial@e1030000 {
+        uart1_pins: uart1 {
                 groups = "uart1_ctrl", "uart1_data";
                 function = "uart1";
         };
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index bcce6f50c93d..cd119400f440 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -69,25 +69,25 @@
                         clock-frequency = <32768>;
                         #clock-cells = <0>;
                 };
-                iic0_sclkdiv: iic0_sclkdiv {
+                iic0_sclkdiv: iic0_sclkdiv@624,0 {
                         compatible = "renesas,emev2-smu-clkdiv";
                         reg = <0x624 0>;
                         clocks = <&pll3_fo>;
                         #clock-cells = <0>;
                 };
-                iic0_sclk: iic0_sclk {
+                iic0_sclk: iic0_sclk@48c,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x48c 1>;
                         clocks = <&iic0_sclkdiv>;
                         #clock-cells = <0>;
                 };
-                iic1_sclkdiv: iic1_sclkdiv {
+                iic1_sclkdiv: iic1_sclkdiv@624,16 {
                         compatible = "renesas,emev2-smu-clkdiv";
                         reg = <0x624 16>;
                         clocks = <&pll3_fo>;
                         #clock-cells = <0>;
                 };
-                iic1_sclk: iic1_sclk {
+                iic1_sclk: iic1_sclk@490,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x490 1>;
                         clocks = <&iic1_sclkdiv>;
@@ -100,55 +100,55 @@
                         clock-mult = <7000>;
                         #clock-cells = <0>;
                 };
-                usia_u0_sclkdiv: usia_u0_sclkdiv {
+                usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
                         compatible = "renesas,emev2-smu-clkdiv";
                         reg = <0x610 0>;
                         clocks = <&pll3_fo>;
                         #clock-cells = <0>;
                 };
-                usib_u1_sclkdiv: usib_u1_sclkdiv {
+                usib_u1_sclkdiv: usib_u1_sclkdiv@65c,0 {
                         compatible = "renesas,emev2-smu-clkdiv";
                         reg = <0x65c 0>;
                         clocks = <&pll3_fo>;
                         #clock-cells = <0>;
                 };
-                usib_u2_sclkdiv: usib_u2_sclkdiv {
+                usib_u2_sclkdiv: usib_u2_sclkdiv@65c,16 {
                         compatible = "renesas,emev2-smu-clkdiv";
                         reg = <0x65c 16>;
                         clocks = <&pll3_fo>;
                         #clock-cells = <0>;
                 };
-                usib_u3_sclkdiv: usib_u3_sclkdiv {
+                usib_u3_sclkdiv: usib_u3_sclkdiv@660,0 {
                         compatible = "renesas,emev2-smu-clkdiv";
                         reg = <0x660 0>;
                         clocks = <&pll3_fo>;
                         #clock-cells = <0>;
                 };
-                usia_u0_sclk: usia_u0_sclk {
+                usia_u0_sclk: usia_u0_sclk@4a0,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x4a0 1>;
                         clocks = <&usia_u0_sclkdiv>;
                         #clock-cells = <0>;
                 };
-                usib_u1_sclk: usib_u1_sclk {
+                usib_u1_sclk: usib_u1_sclk@4b8,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x4b8 1>;
                         clocks = <&usib_u1_sclkdiv>;
                         #clock-cells = <0>;
                 };
-                usib_u2_sclk: usib_u2_sclk {
+                usib_u2_sclk: usib_u2_sclk@4bc,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x4bc 1>;
                         clocks = <&usib_u2_sclkdiv>;
                         #clock-cells = <0>;
                 };
-                usib_u3_sclk: usib_u3_sclk {
+                usib_u3_sclk: usib_u3_sclk@4c0,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x4c0 1>;
                         clocks = <&usib_u3_sclkdiv>;
                         #clock-cells = <0>;
                 };
-                sti_sclk: sti_sclk {
+                sti_sclk: sti_sclk@528,1 {
                         compatible = "renesas,emev2-smu-gclk";
                         reg = <0x528 1>;
                         clocks = <&c32ki>;
diff --git a/arch/arm/boot/dts/ep7209.dtsi b/arch/arm/boot/dts/ep7209.dtsi
new file mode 100644
index 000000000000..aaf1261d2ee4
--- /dev/null
+++ b/arch/arm/boot/dts/ep7209.dtsi
@@ -0,0 +1,191 @@
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ */
+
+/dts-v1/;
+
+#include "skeleton.dtsi"
+
+#include <dt-bindings/clock/clps711x-clock.h>
+
+/ {
+        model = "Cirrus Logic EP7209";
+        compatible = "cirrus,ep7209";
+
+        aliases {
+                gpio0 = &porta;
+                gpio1 = &portb;
+                gpio3 = &portd;
+                gpio4 = &porte;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                spi0 = &spi;
+                timer0 = &timer1;
+                timer1 = &timer2;
+        };
+
+        cpus {
+                #address-cells = <0>;
+                #size-cells = <0>;
+
+                cpu {
+                        device_type = "cpu";
+                        compatible = "arm,arm720t";
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                clks: clks@80000000 {
+                        #clock-cells = <1>;
+                        compatible = "cirrus,ep7209-clk";
+                        reg = <0x80000000 0xc000>;
+                        startup-frequency = <73728000>;
+                };
+
+                intc: intc@80000000 {
+                        compatible = "cirrus,ep7209-intc";
+                        reg = <0x80000000 0x4000>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                porta: gpio@80000000 {
+                        compatible = "cirrus,ep7209-gpio";
+                        reg = <0x80000000 0x1 0x80000040 0x1>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                portb: gpio@80000001 {
+                        compatible = "cirrus,ep7209-gpio";
+                        reg = <0x80000001 0x1 0x80000041 0x1>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                portd: gpio@80000003 {
+                        compatible = "cirrus,ep7209-gpio";
+                        reg = <0x80000003 0x1 0x80000043 0x1>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                porte: gpio@80000083 {
+                        compatible = "cirrus,ep7209-gpio";
+                        reg = <0x80000083 0x1 0x800000c3 0x1>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+
+                syscon1: syscon@80000100 {
+                        compatible = "cirrus,ep7209-syscon1", "syscon";
+                        reg = <0x80000100 0x80>;
+                };
+
+                bus: bus@80000180 {
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        compatible = "cirrus,ep7209-bus", "simple-bus";
+                        clocks = <&clks CLPS711X_CLK_BUS>;
+                        reg = <0x80000180 0x80>;
+                        ranges = <
+                                0 0 0x00000000 0x10000000
+                                1 0 0x10000000 0x10000000
+                                2 0 0x20000000 0x10000000
+                                3 0 0x30000000 0x10000000
+                                4 0 0x40000000 0x10000000
+                                5 0 0x50000000 0x10000000
+                                6 0 0x60000000 0x0000c000
+                                7 0 0x70000000 0x00000080
+                        >;
+                };
+
+                fb: fb@800002c0 {
+                        compatible = "cirrus,ep7209-fb";
+                        reg = <0x800002c0 0xd44>, <0x60000000 0xc000>;
+                        clocks = <&clks CLPS711X_CLK_BUS>;
+                        status = "disabled";
+                };
+
+                timer1: timer@80000300 {
+                        compatible = "cirrus,ep7209-timer";
+                        reg = <0x80000300 0x4>;
+                        clocks = <&clks CLPS711X_CLK_TIMER1>;
+                        interrupts = <8>;
+                };
+
+                timer2: timer@80000340 {
+                        compatible = "cirrus,ep7209-timer";
+                        reg = <0x80000340 0x4>;
+                        clocks = <&clks CLPS711X_CLK_TIMER2>;
+                        interrupts = <9>;
+                };
+
+                pwm: pwm@80000400 {
+                        compatible = "cirrus,ep7209-pwm";
+                        reg = <0x80000400 0x4>;
+                        clocks = <&clks CLPS711X_CLK_PWM>;
+                        #pwm-cells = <1>;
+                };
+
+                uart1: uart@80000480 {
+                        compatible = "cirrus,ep7209-uart";
+                        reg = <0x80000480 0x80>;
+                        interrupts = <12 13>;
+                        clocks = <&clks CLPS711X_CLK_UART>;
+                        syscon = <&syscon1>;
+                };
+
+                spi: spi@80000500 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "cirrus,ep7209-spi";
+                        reg = <0x80000500 0x4>;
+                        interrupts = <15>;
+                        clocks = <&clks CLPS711X_CLK_SPI>;
+                        status = "disabled";
+                };
+
+                syscon2: syscon@80001100 {
+                        compatible = "cirrus,ep7209-syscon2", "syscon";
+                        reg = <0x80001100 0x80>;
+                };
+
+                uart2: uart@80001480 {
+                        compatible = "cirrus,ep7209-uart";
+                        reg = <0x80001480 0x80>;
+                        interrupts = <28 29>;
+                        clocks = <&clks CLPS711X_CLK_UART>;
+                        syscon = <&syscon2>;
+                };
+
+                dai: dai@80002000 {
+                        #sound-dai-cells = <0>;
+                        compatible = "cirrus,ep7209-dai";
+                        reg = <0x80002000 0x604>;
+                        clocks = <&clks CLPS711X_CLK_PLL>;
+                        clock-names = "pll";
+                        interrupts = <32>;
+                        status = "disabled";
+                };
+
+                syscon3: syscon@80002200 {
+                        compatible = "cirrus,ep7209-syscon3", "syscon";
+                        reg = <0x80002200 0x40>;
+                };
+        };
+
+        mctrl: mctrl {
+                compatible = "cirrus,ep7209-mctrl-gpio";
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/ep7211-edb7211.dts b/arch/arm/boot/dts/ep7211-edb7211.dts
new file mode 100644
index 000000000000..9a134ed271eb
--- /dev/null
+++ b/arch/arm/boot/dts/ep7211-edb7211.dts
@@ -0,0 +1,100 @@
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ */
+
+#include "ep7211.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        model = "Cirrus Logic EP7211 Development Board";
+        compatible = "cirrus,edb7211", "cirrus,ep7211", "cirrus,ep7209";
+
+        memory {
+                reg = <0xc0000000 0x02000000>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0>;
+                brightness-levels = <
+                        0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
+                        0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf
+                >;
+                default-brightness-level = <0x0>;
+                power-supply = <&blen>;
+        };
+
+        display: display {
+                model = "320x240x4";
+                native-mode = <&timing0>;
+                bits-per-pixel = <4>;
+                ac-prescale = <17>;
+
+                display-timings {
+                        timing0: 320x240 {
+                                hactive = <320>;
+                                hback-porch = <0>;
+                                hfront-porch = <0>;
+                                hsync-len = <0>;
+                                vactive = <240>;
+                                vback-porch = <0>;
+                                vfront-porch = <0>;
+                                vsync-len = <0>;
+                                clock-frequency = <6500000>;
+                        };
+                };
+        };
+
+        i2c: i2c {
+                compatible = "i2c-gpio";
+                gpios = <&portd 4 GPIO_ACTIVE_HIGH>,
+                        <&portd 5 GPIO_ACTIVE_HIGH>;
+                i2c-gpio,delay-us = <2>;
+                i2c-gpio,scl-output-only;
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        lcddc: lcddc {
+                compatible = "regulator-fixed";
+                regulator-name = "BACKLIGHT ENABLE";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&portd 1 GPIO_ACTIVE_HIGH>;
+        };
+
+        blen: blen {
+                compatible = "regulator-fixed";
+                regulator-name = "BACKLIGHT ENABLE";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&portd 3 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&bus {
+        flash: nor@00000000 {
+                compatible = "cfi-flash";
+                reg = <0 0x00000000 0x02000000>;
+                bank-width = <2>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+
+&fb {
+        display = <&display>;
+        lcd-supply = <&lcddc>;
+        status = "okay";
+};
+
+&portd {
+        lcden {
+                gpio-hog;
+                gpios = <2 GPIO_ACTIVE_HIGH>;
+                output-high;
+                line-name = "LCD ENABLE";
+        };
+};
diff --git a/arch/arm/boot/dts/ep7211.dtsi b/arch/arm/boot/dts/ep7211.dtsi
new file mode 100644
index 000000000000..e438f6db0673
--- /dev/null
+++ b/arch/arm/boot/dts/ep7211.dtsi
@@ -0,0 +1,12 @@
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ */
+
+#include "ep7209.dtsi"
+
+/ {
+        model = "Cirrus Logic EP7211";
+        compatible = "cirrus,ep7211", "cirrus,ep7209";
+};
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 243044343ee8..4687229a3ab9 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -77,13 +77,13 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
 
                 pcf8563@50 {
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index f72969efe6d7..20a4481b6e12 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -46,13 +46,13 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 
diff --git a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
index c4d063ae6b74..f78c14c82e17 100644
--- a/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
+++ b/arch/arm/boot/dts/exynos-mfc-reserved-memory.dtsi
@@ -14,16 +14,22 @@
                 #size-cells = <1>;
                 ranges;
 
-                mfc_left: region@51000000 {
+                mfc_left: region_mfc_left {
                         compatible = "shared-dma-pool";
                         no-map;
-                        reg = <0x51000000 0x800000>;
+                        size = <0x1000000>;
+                        alignment = <0x100000>;
                 };
 
-                mfc_right: region@43000000 {
+                mfc_right: region_mfc_right {
                         compatible = "shared-dma-pool";
                         no-map;
-                        reg = <0x43000000 0x800000>;
+                        size = <0x800000>;
+                        alignment = <0x100000>;
                 };
         };
 };
+
+&mfc {
+        memory-region = <&mfc_left>, <&mfc_right>;
+};
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts
index e422819591dc..a92181368e5b 100644
--- a/arch/arm/boot/dts/exynos3250-rinato.dts
+++ b/arch/arm/boot/dts/exynos3250-rinato.dts
@@ -632,10 +632,6 @@
         status = "okay";
 };
 
-&mfc {
-        status = "okay";
-};
-
 &jpeg {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 62f3dcd9e046..70e3aceab3a9 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -431,7 +431,6 @@
                         clocks = <&cmu CLK_MFC>, <&cmu CLK_SCLK_MFC>;
                         power-domains = <&pd_mfc>;
                         iommus = <&sysmmu_mfc>;
-                        status = "disabled";
                 };
 
                 sysmmu_mfc: sysmmu@13620000 {
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index ca8f3e3cf2f3..32f22e12c70b 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -428,7 +428,6 @@
                 clock-names = "mfc", "sclk_mfc";
                 iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
                 iommu-names = "left", "right";
-                status = "disabled";
         };
 
         serial_0: serial@13800000 {
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index f5e4eb23aa21..be2751eebaf8 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -288,11 +288,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-        status = "okay";
-};
-
 &sdhci_0 {
         bus-width = <4>;
         pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_cd>;
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index de917f0d907d..847fae3dd1f1 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -133,11 +133,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-        status = "okay";
-};
-
 &pinctrl_1 {
         keypad_rows: keypad-rows {
                 samsung,pins = "gpx2-0", "gpx2-1";
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
index 276ac9a7bb82..58ad48e7b8f7 100644
--- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -298,7 +298,6 @@
                                 regulator-name = "VDDQ_MMC2_2.8V";
                                 regulator-min-microvolt = <2800000>;
                                 regulator-max-microvolt = <2800000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                         };
 
@@ -391,10 +390,18 @@
                         };
 
                         ldo21_reg: LDO21 {
-                                regulator-name = "LDO21_3.3V";
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
+                                regulator-name = "TFLASH_2.8V";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                                regulator-boot-on;
+                        };
+
+                        ldo22_reg: LDO22 {
+                                /*
+                                 * Only U3 uses it, so let it define the
+                                 * constraints
+                                 */
+                                regulator-name = "LDO22";
                                 regulator-boot-on;
                         };
 
@@ -461,9 +468,11 @@
                         };
 
                         buck8_reg: BUCK8 {
+                                /*
+                                 * Constraints set by specific board: X,
+                                 * X2 and U3.
+                                 */
                                 regulator-name = "BUCK8_2.8V";
-                                regulator-min-microvolt = <2800000>;
-                                regulator-max-microvolt = <2800000>;
                         };
                 };
         };
@@ -500,11 +509,6 @@
         clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-        status = "okay";
-};
-
 &mixer {
         status = "okay";
 };
@@ -512,7 +516,7 @@
 &mshc_0 {
         pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
         pinctrl-names = "default";
-        vmmc-supply = <&ldo20_reg &buck8_reg>;
+        vmmc-supply = <&ldo20_reg>;
         mmc-pwrseq = <&emmc_pwrseq>;
         status = "okay";
 
@@ -536,7 +540,8 @@
         bus-width = <4>;
         pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
         pinctrl-names = "default";
-        vmmc-supply = <&ldo4_reg &ldo21_reg>;
+        vmmc-supply = <&ldo21_reg>;
+        vqmmc-supply = <&ldo4_reg>;
         cd-gpios = <&gpk2 2 GPIO_ACTIVE_HIGH>;
         cd-inverted;
         status = "okay";
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
index dd89f7b37c9f..d73aa6c58fe3 100644
--- a/arch/arm/boot/dts/exynos4412-odroidu3.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -69,6 +69,24 @@
         };
 };
 
+/* Supply for LAN9730/SMSC95xx */
+&buck8_reg {
+        regulator-name = "BUCK8_P3V3";
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+};
+
+/* VDDQ for MSHC (eMMC card) */
+&ldo22_reg {
+        regulator-name = "LDO22_VDDQ_MMC4_2.8V";
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+&mshc_0 {
+        vqmmc-supply = <&ldo22_reg>;
+};
+
 &pwm {
         pinctrl-0 = <&pwm0_out>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index bf7b21b817e4..2af235151301 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -63,12 +63,23 @@
         };
 };
 
+/* VDDQ for MSHC (eMMC card) */
+&buck8_reg {
+        regulator-name = "BUCK8_VDDQ_MMC4_2.8V";
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
 &ehci {
         port@1 {
                 status = "okay";
         };
 };
 
+&mshc_0 {
+        vqmmc-supply = <&buck8_reg>;
+};
+
 &pinctrl_1 {
         gpio_home_key: home_key {
                 samsung,pins = "gpx2-2";
diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts
index 6e33678562ae..3e3584270e00 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx2.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts
@@ -22,6 +22,17 @@
         };
 };
 
+/* VDDQ for MSHC (eMMC card) */
+&buck8_reg {
+        regulator-name = "BUCK8_VDDQ_MMC4_2.8V";
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
+
+&mshc_0 {
+        vqmmc-supply = <&buck8_reg>;
+};
+
 &sound {
         simple-audio-card,name = "Odroid-X2";
         simple-audio-card,widgets =
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index cd363d7e4e34..26a36fed9652 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -84,6 +84,22 @@
         cpu0-supply = <&buck2_reg>;
 };
 
+&exynos_usbphy {
+        status = "okay";
+};
+
+&ehci {
+        samsung,vbus-gpio = <&gpx3 5 1>;
+        status = "okay";
+
+        port@1{
+                status = "okay";
+        };
+        port@2 {
+                status = "okay";
+        };
+};
+
 &fimd {
         pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
         pinctrl-names = "default";
@@ -466,11 +482,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-        status = "okay";
-};
-
 &mshc_0 {
         pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
         pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/exynos4412-smdk4412.dts b/arch/arm/boot/dts/exynos4412-smdk4412.dts
index 9b6d561dbdac..231ffbdbf9d0 100644
--- a/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -112,11 +112,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-        status = "okay";
-};
-
 &pinctrl_1 {
         keypad_rows: keypad-rows {
                 samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 9336fd4824d9..129e973a06a6 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -253,7 +253,7 @@
         };
 
         thermistor-ap {
-                compatible = "ntc,ncp15wb473";
+                compatible = "murata,ncp15wb473";
                 pullup-uv = <1800000>;   /* VCC_1.8V_AP */
                 pullup-ohm = <100000>;   /* 100K */
                 pulldown-ohm = <100000>; /* 100K */
@@ -261,7 +261,7 @@
         };
 
         thermistor-battery {
-                compatible = "ntc,ncp15wb473";
+                compatible = "murata,ncp15wb473";
                 pullup-uv = <1800000>;   /* VCC_1.8V_AP */
                 pullup-ohm = <100000>;   /* 100K */
                 pulldown-ohm = <100000>; /* 100K */
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index d5c0f18a4223..cab91782e20c 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -20,97 +20,160 @@
         interrupt-parent = <&gic>;
 
         aliases {
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+                i2c2 = &i2c_2;
+                i2c3 = &i2c_3;
                 serial0 = &serial_0;
                 serial1 = &serial_1;
                 serial2 = &serial_2;
                 serial3 = &serial_3;
         };
 
-        chipid@10000000 {
-                compatible = "samsung,exynos4210-chipid";
-                reg = <0x10000000 0x100>;
-        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
 
-        memory-controller@12250000 {
-                compatible = "samsung,exynos4210-srom";
-                reg = <0x12250000 0x14>;
-        };
+                chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
 
-        combiner: interrupt-controller@10440000 {
-                compatible = "samsung,exynos4210-combiner";
-                #interrupt-cells = <2>;
-                interrupt-controller;
-                samsung,combiner-nr = <32>;
-                reg = <0x10440000 0x1000>;
-                interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                                <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                                <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                                <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                                <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                                <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                                <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
-        };
+                sromc: memory-controller@12250000 {
+                        compatible = "samsung,exynos4210-srom";
+                        reg = <0x12250000 0x14>;
+                };
 
-        gic: interrupt-controller@10481000 {
-                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
-                reg =   <0x10481000 0x1000>,
-                        <0x10482000 0x1000>,
-                        <0x10484000 0x2000>,
-                        <0x10486000 0x2000>;
-                interrupts = <1 9 0xf04>;
-        };
+                combiner: interrupt-controller@10440000 {
+                        compatible = "samsung,exynos4210-combiner";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        samsung,combiner-nr = <32>;
+                        reg = <0x10440000 0x1000>;
+                        interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                                        <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                                        <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                                        <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                                        <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                        <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                                        <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                        <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                };
 
-        serial_0: serial@12C00000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C00000 0x100>;
-                interrupts = <0 51 0>;
-        };
+                gic: interrupt-controller@10481000 {
+                        compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg =   <0x10481000 0x1000>,
+                                <0x10482000 0x1000>,
+                                <0x10484000 0x2000>,
+                                <0x10486000 0x2000>;
+                        interrupts = <1 9 0xf04>;
+                };
 
-        serial_1: serial@12C10000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C10000 0x100>;
-                interrupts = <0 52 0>;
-        };
+                sysreg_system_controller: syscon@10050000 {
+                        compatible = "samsung,exynos5-sysreg", "syscon";
+                        reg = <0x10050000 0x5000>;
+                };
 
-        serial_2: serial@12C20000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C20000 0x100>;
-                interrupts = <0 53 0>;
-        };
+                serial_0: serial@12C00000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C00000 0x100>;
+                        interrupts = <0 51 0>;
+                };
 
-        serial_3: serial@12C30000 {
-                compatible = "samsung,exynos4210-uart";
-                reg = <0x12C30000 0x100>;
-                interrupts = <0 54 0>;
-        };
+                serial_1: serial@12C10000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C10000 0x100>;
+                        interrupts = <0 52 0>;
+                };
 
-        rtc: rtc@101E0000 {
-                compatible = "samsung,s3c6410-rtc";
-                reg = <0x101E0000 0x100>;
-                interrupts = <0 43 0>, <0 44 0>;
-                status = "disabled";
-        };
+                serial_2: serial@12C20000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C20000 0x100>;
+                        interrupts = <0 53 0>;
+                };
 
-        fimd: fimd@14400000 {
-                compatible = "samsung,exynos5250-fimd";
-                interrupt-parent = <&combiner>;
-                reg = <0x14400000 0x40000>;
-                interrupt-names = "fifo", "vsync", "lcd_sys";
-                interrupts = <18 4>, <18 5>, <18 6>;
-                samsung,sysreg = <&sysreg_system_controller>;
-                status = "disabled";
-        };
+                serial_3: serial@12C30000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C30000 0x100>;
+                        interrupts = <0 54 0>;
+                };
 
-        dp: dp-controller@145B0000 {
-                compatible = "samsung,exynos5-dp";
-                reg = <0x145B0000 0x1000>;
-                interrupts = <10 3>;
-                interrupt-parent = <&combiner>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
+                i2c_0: i2c@12C60000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12C60000 0x100>;
+                        interrupts = <0 56 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        status = "disabled";
+                };
+
+                i2c_1: i2c@12C70000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12C70000 0x100>;
+                        interrupts = <0 57 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        status = "disabled";
+                };
+
+                i2c_2: i2c@12C80000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12C80000 0x100>;
+                        interrupts = <0 58 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        status = "disabled";
+                };
+
+                i2c_3: i2c@12C90000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12C90000 0x100>;
+                        interrupts = <0 59 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        status = "disabled";
+                };
+
+                pwm: pwm@12DD0000 {
+                        compatible = "samsung,exynos4210-pwm";
+                        reg = <0x12DD0000 0x100>;
+                        samsung,pwm-outputs = <0>, <1>, <2>, <3>;
+                        #pwm-cells = <3>;
+                };
+
+                rtc: rtc@101E0000 {
+                        compatible = "samsung,s3c6410-rtc";
+                        reg = <0x101E0000 0x100>;
+                        interrupts = <0 43 0>, <0 44 0>;
+                        status = "disabled";
+                };
+
+                fimd: fimd@14400000 {
+                        compatible = "samsung,exynos5250-fimd";
+                        interrupt-parent = <&combiner>;
+                        reg = <0x14400000 0x40000>;
+                        interrupt-names = "fifo", "vsync", "lcd_sys";
+                        interrupts = <18 4>, <18 5>, <18 6>;
+                        samsung,sysreg = <&sysreg_system_controller>;
+                        status = "disabled";
+                };
+
+                dp: dp-controller@145B0000 {
+                        compatible = "samsung,exynos5-dp";
+                        reg = <0x145B0000 0x1000>;
+                        interrupts = <10 3>;
+                        interrupt-parent = <&combiner>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 39940f4bd556..ea70603f660d 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -516,10 +516,6 @@
         status = "okay";
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 9fac874af5eb..381af134c4c8 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -344,10 +344,6 @@
         status = "okay";
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index fa14f77df563..fadbea744e1a 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -61,7 +61,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                i2c-parent = <&{/i2c@12CA0000}>;
+                i2c-parent = <&i2c_4>;
 
                 our-claim-gpio = <&gpf0 3 GPIO_ACTIVE_LOW>;
                 their-claim-gpios = <&gpe0 4 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index 784130bdb6a3..44f4292bfef6 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -425,10 +425,6 @@
         status = "okay";
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index c7158b2fb213..f7357d99b47c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -37,10 +37,6 @@
                 mshc1 = &mmc_1;
                 mshc2 = &mmc_2;
                 mshc3 = &mmc_3;
-                i2c0 = &i2c_0;
-                i2c1 = &i2c_1;
-                i2c2 = &i2c_2;
-                i2c3 = &i2c_3;
                 i2c4 = &i2c_4;
                 i2c5 = &i2c_5;
                 i2c6 = &i2c_6;
@@ -96,962 +92,896 @@
                 };
         };
 
-        sysram@02020000 {
-                compatible = "mmio-sram";
-                reg = <0x02020000 0x30000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0x02020000 0x30000>;
+        soc: soc {
+                sysram@02020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x30000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x30000>;
 
-                smp-sysram@0 {
-                        compatible = "samsung,exynos4210-sysram";
-                        reg = <0x0 0x1000>;
-                };
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
 
-                smp-sysram@2f000 {
-                        compatible = "samsung,exynos4210-sysram-ns";
-                        reg = <0x2f000 0x1000>;
+                        smp-sysram@2f000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x2f000 0x1000>;
+                        };
                 };
-        };
 
-        pd_gsc: gsc-power-domain@10044000 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044000 0x20>;
-                #power-domain-cells = <0>;
-        };
+                pd_gsc: gsc-power-domain@10044000 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10044000 0x20>;
+                        #power-domain-cells = <0>;
+                };
 
-        pd_mfc: mfc-power-domain@10044040 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044040 0x20>;
-                #power-domain-cells = <0>;
-        };
+                pd_mfc: mfc-power-domain@10044040 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10044040 0x20>;
+                        #power-domain-cells = <0>;
+                };
 
-        pd_disp1: disp1-power-domain@100440A0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x100440A0 0x20>;
-                #power-domain-cells = <0>;
-                clocks = <&clock CLK_FIN_PLL>,
-                         <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
-                         <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
-                clock-names = "oscclk", "clk0", "clk1";
-        };
+                pd_disp1: disp1-power-domain@100440A0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x100440A0 0x20>;
+                        #power-domain-cells = <0>;
+                        clocks = <&clock CLK_FIN_PLL>,
+                                 <&clock CLK_MOUT_ACLK200_DISP1_SUB>,
+                                 <&clock CLK_MOUT_ACLK300_DISP1_SUB>;
+                        clock-names = "oscclk", "clk0", "clk1";
+                };
 
-        clock: clock-controller@10010000 {
-                compatible = "samsung,exynos5250-clock";
-                reg = <0x10010000 0x30000>;
-                #clock-cells = <1>;
-        };
+                clock: clock-controller@10010000 {
+                        compatible = "samsung,exynos5250-clock";
+                        reg = <0x10010000 0x30000>;
+                        #clock-cells = <1>;
+                };
 
-        clock_audss: audss-clock-controller@3810000 {
-                compatible = "samsung,exynos5250-audss-clock";
-                reg = <0x03810000 0x0C>;
-                #clock-cells = <1>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
-                         <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
-                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
-        };
+                clock_audss: audss-clock-controller@3810000 {
+                        compatible = "samsung,exynos5250-audss-clock";
+                        reg = <0x03810000 0x0C>;
+                        #clock-cells = <1>;
+                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
+                                 <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
+                        clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
+                };
 
-        timer {
-                compatible = "arm,armv7-timer";
-                interrupts = <1 13 0xf08>,
-                             <1 14 0xf08>,
-                             <1 11 0xf08>,
-                             <1 10 0xf08>;
-                /* Unfortunately we need this since some versions of U-Boot
-                 * on Exynos don't set the CNTFRQ register, so we need the
-                 * value from DT.
-                 */
-                clock-frequency = <24000000>;
-        };
+                timer {
+                        compatible = "arm,armv7-timer";
+                        interrupts = <1 13 0xf08>,
+                                     <1 14 0xf08>,
+                                     <1 11 0xf08>,
+                                     <1 10 0xf08>;
+                        /*
+                         * Unfortunately we need this since some versions
+                         * of U-Boot on Exynos don't set the CNTFRQ register,
+                         * so we need the value from DT.
+                         */
+                        clock-frequency = <24000000>;
+                };
 
-        mct@101C0000 {
-                compatible = "samsung,exynos4210-mct";
-                reg = <0x101C0000 0x800>;
-                interrupt-controller;
-                #interrupt-cells = <2>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
-                             <4 0>, <5 0>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
-                clock-names = "fin_pll", "mct";
-
-                mct_map: mct-map {
+                mct@101C0000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x101C0000 0x800>;
+                        interrupt-controller;
                         #interrupt-cells = <2>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0x0 0 &combiner 23 3>,
-                                        <0x1 0 &combiner 23 4>,
-                                        <0x2 0 &combiner 25 2>,
-                                        <0x3 0 &combiner 25 3>,
-                                        <0x4 0 &gic 0 120 0>,
-                                        <0x5 0 &gic 0 121 0>;
+                        interrupt-parent = <&mct_map>;
+                        interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
+                                     <4 0>, <5 0>;
+                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+
+                        mct_map: mct-map {
+                                #interrupt-cells = <2>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = <0x0 0 &combiner 23 3>,
+                                                <0x1 0 &combiner 23 4>,
+                                                <0x2 0 &combiner 25 2>,
+                                                <0x3 0 &combiner 25 3>,
+                                                <0x4 0 &gic 0 120 0>,
+                                                <0x5 0 &gic 0 121 0>;
+                        };
                 };
-        };
-
-        pmu {
-                compatible = "arm,cortex-a15-pmu";
-                interrupt-parent = <&combiner>;
-                interrupts = <1 2>, <22 4>;
-        };
-
-        pinctrl_0: pinctrl@11400000 {
-                compatible = "samsung,exynos5250-pinctrl";
-                reg = <0x11400000 0x1000>;
-                interrupts = <0 46 0>;
 
-                wakup_eint: wakeup-interrupt-controller {
-                        compatible = "samsung,exynos4210-wakeup-eint";
-                        interrupt-parent = <&gic>;
-                        interrupts = <0 32 0>;
+                pmu {
+                        compatible = "arm,cortex-a15-pmu";
+                        interrupt-parent = <&combiner>;
+                        interrupts = <1 2>, <22 4>;
                 };
-        };
-
-        pinctrl_1: pinctrl@13400000 {
-                compatible = "samsung,exynos5250-pinctrl";
-                reg = <0x13400000 0x1000>;
-                interrupts = <0 45 0>;
-        };
 
-        pinctrl_2: pinctrl@10d10000 {
-                compatible = "samsung,exynos5250-pinctrl";
-                reg = <0x10d10000 0x1000>;
-                interrupts = <0 50 0>;
-        };
-
-        pinctrl_3: pinctrl@03860000 {
-                compatible = "samsung,exynos5250-pinctrl";
-                reg = <0x03860000 0x1000>;
-                interrupts = <0 47 0>;
-        };
-
-        pmu_system_controller: system-controller@10040000 {
-                compatible = "samsung,exynos5250-pmu", "syscon";
-                reg = <0x10040000 0x5000>;
-                clock-names = "clkout16";
-                clocks = <&clock CLK_FIN_PLL>;
-                #clock-cells = <1>;
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                interrupt-parent = <&gic>;
-        };
+                pinctrl_0: pinctrl@11400000 {
+                        compatible = "samsung,exynos5250-pinctrl";
+                        reg = <0x11400000 0x1000>;
+                        interrupts = <0 46 0>;
 
-        sysreg_system_controller: syscon@10050000 {
-                compatible = "samsung,exynos5-sysreg", "syscon";
-                reg = <0x10050000 0x5000>;
-        };
+                        wakup_eint: wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 32 0>;
+                        };
+                };
 
-        watchdog@101D0000 {
-                compatible = "samsung,exynos5250-wdt";
-                reg = <0x101D0000 0x100>;
-                interrupts = <0 42 0>;
-                clocks = <&clock CLK_WDT>;
-                clock-names = "watchdog";
-                samsung,syscon-phandle = <&pmu_system_controller>;
-        };
+                pinctrl_1: pinctrl@13400000 {
+                        compatible = "samsung,exynos5250-pinctrl";
+                        reg = <0x13400000 0x1000>;
+                        interrupts = <0 45 0>;
+                };
 
-        g2d@10850000 {
-                compatible = "samsung,exynos5250-g2d";
-                reg = <0x10850000 0x1000>;
-                interrupts = <0 91 0>;
-                clocks = <&clock CLK_G2D>;
-                clock-names = "fimg2d";
-                iommus = <&sysmmu_g2d>;
-        };
+                pinctrl_2: pinctrl@10d10000 {
+                        compatible = "samsung,exynos5250-pinctrl";
+                        reg = <0x10d10000 0x1000>;
+                        interrupts = <0 50 0>;
+                };
 
-        mfc: codec@11000000 {
-                compatible = "samsung,mfc-v6";
-                reg = <0x11000000 0x10000>;
-                interrupts = <0 96 0>;
-                power-domains = <&pd_mfc>;
-                clocks = <&clock CLK_MFC>;
-                clock-names = "mfc";
-                iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
-                iommu-names = "left", "right";
-        };
+                pinctrl_3: pinctrl@03860000 {
+                        compatible = "samsung,exynos5250-pinctrl";
+                        reg = <0x03860000 0x1000>;
+                        interrupts = <0 47 0>;
+                };
 
-        rotator: rotator@11C00000 {
-                compatible = "samsung,exynos5250-rotator";
-                reg = <0x11C00000 0x64>;
-                interrupts = <0 84 0>;
-                clocks = <&clock CLK_ROTATOR>;
-                clock-names = "rotator";
-                iommus = <&sysmmu_rotator>;
-        };
+                pmu_system_controller: system-controller@10040000 {
+                        compatible = "samsung,exynos5250-pmu", "syscon";
+                        reg = <0x10040000 0x5000>;
+                        clock-names = "clkout16";
+                        clocks = <&clock CLK_FIN_PLL>;
+                        #clock-cells = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupt-parent = <&gic>;
+                };
 
-        tmu: tmu@10060000 {
-                compatible = "samsung,exynos5250-tmu";
-                reg = <0x10060000 0x100>;
-                interrupts = <0 65 0>;
-                clocks = <&clock CLK_TMU>;
-                clock-names = "tmu_apbif";
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
+                watchdog@101D0000 {
+                        compatible = "samsung,exynos5250-wdt";
+                        reg = <0x101D0000 0x100>;
+                        interrupts = <0 42 0>;
+                        clocks = <&clock CLK_WDT>;
+                        clock-names = "watchdog";
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                };
 
-        thermal-zones {
-                cpu_thermal: cpu-thermal {
-                        polling-delay-passive = <0>;
-                        polling-delay = <0>;
-                        thermal-sensors = <&tmu 0>;
+                g2d@10850000 {
+                        compatible = "samsung,exynos5250-g2d";
+                        reg = <0x10850000 0x1000>;
+                        interrupts = <0 91 0>;
+                        clocks = <&clock CLK_G2D>;
+                        clock-names = "fimg2d";
+                        iommus = <&sysmmu_g2d>;
+                };
 
-                        cooling-maps {
-                                map0 {
-                                     /* Corresponds to 800MHz at freq_table */
-                                     cooling-device = <&cpu0 9 9>;
-                                };
-                                map1 {
-                                     /* Corresponds to 200MHz at freq_table */
-                                     cooling-device = <&cpu0 15 15>;
-                               };
-                       };
+                mfc: codec@11000000 {
+                        compatible = "samsung,mfc-v6";
+                        reg = <0x11000000 0x10000>;
+                        interrupts = <0 96 0>;
+                        power-domains = <&pd_mfc>;
+                        clocks = <&clock CLK_MFC>;
+                        clock-names = "mfc";
+                        iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+                        iommu-names = "left", "right";
                 };
-        };
 
-        sata: sata@122F0000 {
-                compatible = "snps,dwc-ahci";
-                samsung,sata-freq = <66>;
-                reg = <0x122F0000 0x1ff>;
-                interrupts = <0 115 0>;
-                clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
-                clock-names = "sata", "sclk_sata";
-                phys = <&sata_phy>;
-                phy-names = "sata-phy";
-                status = "disabled";
-        };
+                rotator: rotator@11C00000 {
+                        compatible = "samsung,exynos5250-rotator";
+                        reg = <0x11C00000 0x64>;
+                        interrupts = <0 84 0>;
+                        clocks = <&clock CLK_ROTATOR>;
+                        clock-names = "rotator";
+                        iommus = <&sysmmu_rotator>;
+                };
 
-        sata_phy: sata-phy@12170000 {
-                compatible = "samsung,exynos5250-sata-phy";
-                reg = <0x12170000 0x1ff>;
-                clocks = <&clock CLK_SATA_PHYCTRL>;
-                clock-names = "sata_phyctrl";
-                #phy-cells = <0>;
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                status = "disabled";
-        };
+                tmu: tmu@10060000 {
+                        compatible = "samsung,exynos5250-tmu";
+                        reg = <0x10060000 0x100>;
+                        interrupts = <0 65 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
 
-        i2c_0: i2c@12C60000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C60000 0x100>;
-                interrupts = <0 56 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C0>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c0_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
+                sata: sata@122F0000 {
+                        compatible = "snps,dwc-ahci";
+                        samsung,sata-freq = <66>;
+                        reg = <0x122F0000 0x1ff>;
+                        interrupts = <0 115 0>;
+                        clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>;
+                        clock-names = "sata", "sclk_sata";
+                        phys = <&sata_phy>;
+                        phy-names = "sata-phy";
+                        status = "disabled";
+                };
 
-        i2c_1: i2c@12C70000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C70000 0x100>;
-                interrupts = <0 57 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C1>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c1_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
+                sata_phy: sata-phy@12170000 {
+                        compatible = "samsung,exynos5250-sata-phy";
+                        reg = <0x12170000 0x1ff>;
+                        clocks = <&clock CLK_SATA_PHYCTRL>;
+                        clock-names = "sata_phyctrl";
+                        #phy-cells = <0>;
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        status = "disabled";
+                };
 
-        i2c_2: i2c@12C80000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C80000 0x100>;
-                interrupts = <0 58 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C2>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c2_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
+                /* i2c_0-3 are defined in exynos5.dtsi */
+                i2c_4: i2c@12CA0000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12CA0000 0x100>;
+                        interrupts = <0 60 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_I2C4>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c4_bus>;
+                        status = "disabled";
+                };
 
-        i2c_3: i2c@12C90000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C90000 0x100>;
-                interrupts = <0 59 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C3>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c3_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
+                i2c_5: i2c@12CB0000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12CB0000 0x100>;
+                        interrupts = <0 61 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_I2C5>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c5_bus>;
+                        status = "disabled";
+                };
 
-        i2c_4: i2c@12CA0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12CA0000 0x100>;
-                interrupts = <0 60 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C4>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c4_bus>;
-                status = "disabled";
-        };
+                i2c_6: i2c@12CC0000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12CC0000 0x100>;
+                        interrupts = <0 62 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_I2C6>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c6_bus>;
+                        status = "disabled";
+                };
 
-        i2c_5: i2c@12CB0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12CB0000 0x100>;
-                interrupts = <0 61 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C5>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c5_bus>;
-                status = "disabled";
-        };
+                i2c_7: i2c@12CD0000 {
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x12CD0000 0x100>;
+                        interrupts = <0 63 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_I2C7>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c7_bus>;
+                        status = "disabled";
+                };
 
-        i2c_6: i2c@12CC0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12CC0000 0x100>;
-                interrupts = <0 62 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C6>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c6_bus>;
-                status = "disabled";
-        };
+                i2c_8: i2c@12CE0000 {
+                        compatible = "samsung,s3c2440-hdmiphy-i2c";
+                        reg = <0x12CE0000 0x1000>;
+                        interrupts = <0 64 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_I2C_HDMI>;
+                        clock-names = "i2c";
+                        status = "disabled";
+                };
 
-        i2c_7: i2c@12CD0000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12CD0000 0x100>;
-                interrupts = <0 63 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C7>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c7_bus>;
-                status = "disabled";
-        };
+                i2c_9: i2c@121D0000 {
+                        compatible = "samsung,exynos5-sata-phy-i2c";
+                        reg = <0x121D0000 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SATA_PHYI2C>;
+                        clock-names = "i2c";
+                        status = "disabled";
+                };
 
-        i2c_8: i2c@12CE0000 {
-                compatible = "samsung,s3c2440-hdmiphy-i2c";
-                reg = <0x12CE0000 0x1000>;
-                interrupts = <0 64 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C_HDMI>;
-                clock-names = "i2c";
-                status = "disabled";
-        };
+                spi_0: spi@12d20000 {
+                        compatible = "samsung,exynos4210-spi";
+                        status = "disabled";
+                        reg = <0x12d20000 0x100>;
+                        interrupts = <0 66 0>;
+                        dmas = <&pdma0 5
+                                &pdma0 4>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                };
 
-        i2c_9: i2c@121D0000 {
-                compatible = "samsung,exynos5-sata-phy-i2c";
-                reg = <0x121D0000 0x100>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SATA_PHYI2C>;
-                clock-names = "i2c";
-                status = "disabled";
-        };
+                spi_1: spi@12d30000 {
+                        compatible = "samsung,exynos4210-spi";
+                        status = "disabled";
+                        reg = <0x12d30000 0x100>;
+                        interrupts = <0 67 0>;
+                        dmas = <&pdma1 5
+                                &pdma1 4>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                };
 
-        spi_0: spi@12d20000 {
-                compatible = "samsung,exynos4210-spi";
-                status = "disabled";
-                reg = <0x12d20000 0x100>;
-                interrupts = <0 66 0>;
-                dmas = <&pdma0 5
-                        &pdma0 4>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
-                clock-names = "spi", "spi_busclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi0_bus>;
-        };
+                spi_2: spi@12d40000 {
+                        compatible = "samsung,exynos4210-spi";
+                        status = "disabled";
+                        reg = <0x12d40000 0x100>;
+                        interrupts = <0 68 0>;
+                        dmas = <&pdma0 7
+                                &pdma0 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
+                        clock-names = "spi", "spi_busclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_bus>;
+                };
 
-        spi_1: spi@12d30000 {
-                compatible = "samsung,exynos4210-spi";
-                status = "disabled";
-                reg = <0x12d30000 0x100>;
-                interrupts = <0 67 0>;
-                dmas = <&pdma1 5
-                        &pdma1 4>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
-                clock-names = "spi", "spi_busclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi1_bus>;
-        };
+                mmc_0: mmc@12200000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        interrupts = <0 75 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x12200000 0x1000>;
+                        clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
 
-        spi_2: spi@12d40000 {
-                compatible = "samsung,exynos4210-spi";
-                status = "disabled";
-                reg = <0x12d40000 0x100>;
-                interrupts = <0 68 0>;
-                dmas = <&pdma0 7
-                        &pdma0 6>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
-                clock-names = "spi", "spi_busclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi2_bus>;
-        };
+                mmc_1: mmc@12210000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        interrupts = <0 76 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x12210000 0x1000>;
+                        clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
 
-        mmc_0: mmc@12200000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x12200000 0x1000>;
-                clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x80>;
-                status = "disabled";
-        };
+                mmc_2: mmc@12220000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        interrupts = <0 77 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x12220000 0x1000>;
+                        clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
 
-        mmc_1: mmc@12210000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 76 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x12210000 0x1000>;
-                clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x80>;
-                status = "disabled";
-        };
+                mmc_3: mmc@12230000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12230000 0x1000>;
+                        interrupts = <0 78 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
 
-        mmc_2: mmc@12220000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x12220000 0x1000>;
-                clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x80>;
-                status = "disabled";
-        };
+                i2s0: i2s@03830000 {
+                        compatible = "samsung,s5pv210-i2s";
+                        status = "disabled";
+                        reg = <0x03830000 0x100>;
+                        dmas = <&pdma0 10
+                                &pdma0 9
+                                &pdma0 8>;
+                        dma-names = "tx", "rx", "tx-sec";
+                        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                                <&clock_audss EXYNOS_I2S_BUS>,
+                                <&clock_audss EXYNOS_SCLK_I2S>;
+                        clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+                        samsung,idma-addr = <0x03000000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s0_bus>;
+                };
 
-        mmc_3: mmc@12230000 {
-                compatible = "samsung,exynos5250-dw-mshc";
-                reg = <0x12230000 0x1000>;
-                interrupts = <0 78 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x80>;
-                status = "disabled";
-        };
+                i2s1: i2s@12D60000 {
+                        compatible = "samsung,s3c6410-i2s";
+                        status = "disabled";
+                        reg = <0x12D60000 0x100>;
+                        dmas = <&pdma1 12
+                                &pdma1 11>;
+                        dma-names = "tx", "rx";
+                        clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
+                        clock-names = "iis", "i2s_opclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s1_bus>;
+                };
 
-        i2s0: i2s@03830000 {
-                compatible = "samsung,s5pv210-i2s";
-                status = "disabled";
-                reg = <0x03830000 0x100>;
-                dmas = <&pdma0 10
-                        &pdma0 9
-                        &pdma0 8>;
-                dma-names = "tx", "rx", "tx-sec";
-                clocks = <&clock_audss EXYNOS_I2S_BUS>,
-                        <&clock_audss EXYNOS_I2S_BUS>,
-                        <&clock_audss EXYNOS_SCLK_I2S>;
-                clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
-                samsung,idma-addr = <0x03000000>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2s0_bus>;
-        };
+                i2s2: i2s@12D70000 {
+                        compatible = "samsung,s3c6410-i2s";
+                        status = "disabled";
+                        reg = <0x12D70000 0x100>;
+                        dmas = <&pdma0 12
+                                &pdma0 11>;
+                        dma-names = "tx", "rx";
+                        clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
+                        clock-names = "iis", "i2s_opclk0";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s2_bus>;
+                };
 
-        i2s1: i2s@12D60000 {
-                compatible = "samsung,s3c6410-i2s";
-                status = "disabled";
-                reg = <0x12D60000 0x100>;
-                dmas = <&pdma1 12
-                        &pdma1 11>;
-                dma-names = "tx", "rx";
-                clocks = <&clock CLK_I2S1>, <&clock CLK_DIV_I2S1>;
-                clock-names = "iis", "i2s_opclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2s1_bus>;
-        };
+                usb_dwc3 {
+                        compatible = "samsung,exynos5250-dwusb3";
+                        clocks = <&clock CLK_USB3>;
+                        clock-names = "usbdrd30";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbdrd_dwc3: dwc3@12000000 {
+                                compatible = "synopsys,dwc3";
+                                reg = <0x12000000 0x10000>;
+                                interrupts = <0 72 0>;
+                                phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                        };
+                };
 
-        i2s2: i2s@12D70000 {
-                compatible = "samsung,s3c6410-i2s";
-                status = "disabled";
-                reg = <0x12D70000 0x100>;
-                dmas = <&pdma0 12
-                        &pdma0 11>;
-                dma-names = "tx", "rx";
-                clocks = <&clock CLK_I2S2>, <&clock CLK_DIV_I2S2>;
-                clock-names = "iis", "i2s_opclk0";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2s2_bus>;
-        };
+                usbdrd_phy: phy@12100000 {
+                        compatible = "samsung,exynos5250-usbdrd-phy";
+                        reg = <0x12100000 0x100>;
+                        clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
+                        clock-names = "phy", "ref";
+                        samsung,pmu-syscon = <&pmu_system_controller>;
+                        #phy-cells = <1>;
+                };
 
-        usb_dwc3 {
-                compatible = "samsung,exynos5250-dwusb3";
-                clocks = <&clock CLK_USB3>;
-                clock-names = "usbdrd30";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
+                ehci: usb@12110000 {
+                        compatible = "samsung,exynos4210-ehci";
+                        reg = <0x12110000 0x100>;
+                        interrupts = <0 71 0>;
 
-                usbdrd_dwc3: dwc3@12000000 {
-                        compatible = "synopsys,dwc3";
-                        reg = <0x12000000 0x10000>;
-                        interrupts = <0 72 0>;
-                        phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
-                        phy-names = "usb2-phy", "usb3-phy";
+                        clocks = <&clock CLK_USB2>;
+                        clock-names = "usbhost";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&usb2_phy_gen 1>;
+                        };
                 };
-        };
-
-        usbdrd_phy: phy@12100000 {
-                compatible = "samsung,exynos5250-usbdrd-phy";
-                reg = <0x12100000 0x100>;
-                clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
-                clock-names = "phy", "ref";
-                samsung,pmu-syscon = <&pmu_system_controller>;
-                #phy-cells = <1>;
-        };
 
-        ehci: usb@12110000 {
-                compatible = "samsung,exynos4210-ehci";
-                reg = <0x12110000 0x100>;
-                interrupts = <0 71 0>;
+                ohci: usb@12120000 {
+                        compatible = "samsung,exynos4210-ohci";
+                        reg = <0x12120000 0x100>;
+                        interrupts = <0 71 0>;
 
-                clocks = <&clock CLK_USB2>;
-                clock-names = "usbhost";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        phys = <&usb2_phy_gen 1>;
+                        clocks = <&clock CLK_USB2>;
+                        clock-names = "usbhost";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&usb2_phy_gen 1>;
+                        };
                 };
-        };
 
-        ohci: usb@12120000 {
-                compatible = "samsung,exynos4210-ohci";
-                reg = <0x12120000 0x100>;
-                interrupts = <0 71 0>;
-
-                clocks = <&clock CLK_USB2>;
-                clock-names = "usbhost";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        phys = <&usb2_phy_gen 1>;
+                usb2_phy_gen: phy@12130000 {
+                        compatible = "samsung,exynos5250-usb2-phy";
+                        reg = <0x12130000 0x100>;
+                        clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
+                        clock-names = "phy", "ref";
+                        #phy-cells = <1>;
+                        samsung,sysreg-phandle = <&sysreg_system_controller>;
+                        samsung,pmureg-phandle = <&pmu_system_controller>;
                 };
-        };
 
-        usb2_phy_gen: phy@12130000 {
-                compatible = "samsung,exynos5250-usb2-phy";
-                reg = <0x12130000 0x100>;
-                clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
-                clock-names = "phy", "ref";
-                #phy-cells = <1>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                samsung,pmureg-phandle = <&pmu_system_controller>;
-        };
+                amba {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
+                        interrupt-parent = <&gic>;
+                        ranges;
+
+                        pdma0: pdma@121A0000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x121A0000 0x1000>;
+                                interrupts = <0 34 0>;
+                                clocks = <&clock CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        pdma1: pdma@121B0000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x121B0000 0x1000>;
+                                interrupts = <0 35 0>;
+                                clocks = <&clock CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        mdma0: mdma@10800000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x10800000 0x1000>;
+                                interrupts = <0 33 0>;
+                                clocks = <&clock CLK_MDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <1>;
+                        };
+
+                        mdma1: mdma@11C10000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x11C10000 0x1000>;
+                                interrupts = <0 124 0>;
+                                clocks = <&clock CLK_MDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <1>;
+                        };
+                };
 
-        pwm: pwm@12dd0000 {
-                compatible = "samsung,exynos4210-pwm";
-                reg = <0x12dd0000 0x100>;
-                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
-                #pwm-cells = <3>;
-                clocks = <&clock CLK_PWM>;
-                clock-names = "timers";
-        };
+                gsc_0:  gsc@13e00000 {
+                        compatible = "samsung,exynos5-gsc";
+                        reg = <0x13e00000 0x1000>;
+                        interrupts = <0 85 0>;
+                        power-domains = <&pd_gsc>;
+                        clocks = <&clock CLK_GSCL0>;
+                        clock-names = "gscl";
+                        iommu = <&sysmmu_gsc0>;
+                };
 
-        amba {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&gic>;
-                ranges;
-
-                pdma0: pdma@121A0000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121A0000 0x1000>;
-                        interrupts = <0 34 0>;
-                        clocks = <&clock CLK_PDMA0>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                pdma1: pdma@121B0000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121B0000 0x1000>;
-                        interrupts = <0 35 0>;
-                        clocks = <&clock CLK_PDMA1>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                mdma0: mdma@10800000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x10800000 0x1000>;
-                        interrupts = <0 33 0>;
-                        clocks = <&clock CLK_MDMA0>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <1>;
-                };
-
-                mdma1: mdma@11C10000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x11C10000 0x1000>;
-                        interrupts = <0 124 0>;
-                        clocks = <&clock CLK_MDMA1>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <1>;
+                gsc_1:  gsc@13e10000 {
+                        compatible = "samsung,exynos5-gsc";
+                        reg = <0x13e10000 0x1000>;
+                        interrupts = <0 86 0>;
+                        power-domains = <&pd_gsc>;
+                        clocks = <&clock CLK_GSCL1>;
+                        clock-names = "gscl";
+                        iommu = <&sysmmu_gsc1>;
                 };
-        };
 
-        gsc_0:  gsc@13e00000 {
-                compatible = "samsung,exynos5-gsc";
-                reg = <0x13e00000 0x1000>;
-                interrupts = <0 85 0>;
-                power-domains = <&pd_gsc>;
-                clocks = <&clock CLK_GSCL0>;
-                clock-names = "gscl";
-                iommu = <&sysmmu_gsc0>;
-        };
+                gsc_2:  gsc@13e20000 {
+                        compatible = "samsung,exynos5-gsc";
+                        reg = <0x13e20000 0x1000>;
+                        interrupts = <0 87 0>;
+                        power-domains = <&pd_gsc>;
+                        clocks = <&clock CLK_GSCL2>;
+                        clock-names = "gscl";
+                        iommu = <&sysmmu_gsc2>;
+                };
 
-        gsc_1:  gsc@13e10000 {
-                compatible = "samsung,exynos5-gsc";
-                reg = <0x13e10000 0x1000>;
-                interrupts = <0 86 0>;
-                power-domains = <&pd_gsc>;
-                clocks = <&clock CLK_GSCL1>;
-                clock-names = "gscl";
-                iommu = <&sysmmu_gsc1>;
-        };
+                gsc_3:  gsc@13e30000 {
+                        compatible = "samsung,exynos5-gsc";
+                        reg = <0x13e30000 0x1000>;
+                        interrupts = <0 88 0>;
+                        power-domains = <&pd_gsc>;
+                        clocks = <&clock CLK_GSCL3>;
+                        clock-names = "gscl";
+                        iommu = <&sysmmu_gsc3>;
+                };
 
-        gsc_2:  gsc@13e20000 {
-                compatible = "samsung,exynos5-gsc";
-                reg = <0x13e20000 0x1000>;
-                interrupts = <0 87 0>;
-                power-domains = <&pd_gsc>;
-                clocks = <&clock CLK_GSCL2>;
-                clock-names = "gscl";
-                iommu = <&sysmmu_gsc2>;
-        };
+                hdmi: hdmi@14530000 {
+                        compatible = "samsung,exynos4212-hdmi";
+                        reg = <0x14530000 0x70000>;
+                        power-domains = <&pd_disp1>;
+                        interrupts = <0 95 0>;
+                        clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
+                                 <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
+                                 <&clock CLK_MOUT_HDMI>;
+                        clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                        "sclk_hdmiphy", "mout_hdmi";
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                };
 
-        gsc_3:  gsc@13e30000 {
-                compatible = "samsung,exynos5-gsc";
-                reg = <0x13e30000 0x1000>;
-                interrupts = <0 88 0>;
-                power-domains = <&pd_gsc>;
-                clocks = <&clock CLK_GSCL3>;
-                clock-names = "gscl";
-                iommu = <&sysmmu_gsc3>;
-        };
+                mixer@14450000 {
+                        compatible = "samsung,exynos5250-mixer";
+                        reg = <0x14450000 0x10000>;
+                        power-domains = <&pd_disp1>;
+                        interrupts = <0 94 0>;
+                        clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
+                                 <&clock CLK_SCLK_HDMI>;
+                        clock-names = "mixer", "hdmi", "sclk_hdmi";
+                        iommus = <&sysmmu_tv>;
+                };
 
-        hdmi: hdmi@14530000 {
-                compatible = "samsung,exynos4212-hdmi";
-                reg = <0x14530000 0x70000>;
-                power-domains = <&pd_disp1>;
-                interrupts = <0 95 0>;
-                clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
-                         <&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
-                         <&clock CLK_MOUT_HDMI>;
-                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
-                                "sclk_hdmiphy", "mout_hdmi";
-                samsung,syscon-phandle = <&pmu_system_controller>;
-        };
+                dp_phy: video-phy {
+                        compatible = "samsung,exynos5250-dp-video-phy";
+                        samsung,pmu-syscon = <&pmu_system_controller>;
+                        #phy-cells = <0>;
+                };
 
-        mixer@14450000 {
-                compatible = "samsung,exynos5250-mixer";
-                reg = <0x14450000 0x10000>;
-                power-domains = <&pd_disp1>;
-                interrupts = <0 94 0>;
-                clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
-                         <&clock CLK_SCLK_HDMI>;
-                clock-names = "mixer", "hdmi", "sclk_hdmi";
-                iommus = <&sysmmu_tv>;
-        };
+                adc: adc@12D10000 {
+                        compatible = "samsung,exynos-adc-v1";
+                        reg = <0x12D10000 0x100>;
+                        interrupts = <0 106 0>;
+                        clocks = <&clock CLK_ADC>;
+                        clock-names = "adc";
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        status = "disabled";
+                };
 
-        dp_phy: video-phy {
-                compatible = "samsung,exynos5250-dp-video-phy";
-                samsung,pmu-syscon = <&pmu_system_controller>;
-                #phy-cells = <0>;
-        };
+                sss@10830000 {
+                        compatible = "samsung,exynos4210-secss";
+                        reg = <0x10830000 0x300>;
+                        interrupts = <0 112 0>;
+                        clocks = <&clock CLK_SSS>;
+                        clock-names = "secss";
+                };
 
-        adc: adc@12D10000 {
-                compatible = "samsung,exynos-adc-v1";
-                reg = <0x12D10000 0x100>;
-                interrupts = <0 106 0>;
-                clocks = <&clock CLK_ADC>;
-                clock-names = "adc";
-                #io-channel-cells = <1>;
-                io-channel-ranges;
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                status = "disabled";
-        };
+                sysmmu_g2d: sysmmu@10A60000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x10A60000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <24 5>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
+                        #iommu-cells = <0>;
+                };
 
-        sss@10830000 {
-                compatible = "samsung,exynos4210-secss";
-                reg = <0x10830000 0x300>;
-                interrupts = <0 112 0>;
-                clocks = <&clock CLK_SSS>;
-                clock-names = "secss";
-        };
+                sysmmu_mfc_r: sysmmu@11200000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11200000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <6 2>;
+                        power-domains = <&pd_mfc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_g2d: sysmmu@10A60000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x10A60000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <24 5>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_2D>, <&clock CLK_G2D>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_mfc_l: sysmmu@11210000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11210000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <8 5>;
+                        power-domains = <&pd_mfc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_mfc_r: sysmmu@11200000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11200000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <6 2>;
-                power-domains = <&pd_mfc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_rotator: sysmmu@11D40000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11D40000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_mfc_l: sysmmu@11210000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11210000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <8 5>;
-                power-domains = <&pd_mfc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_jpeg: sysmmu@11F20000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11F20000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 2>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_rotator: sysmmu@11D40000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11D40000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_isp: sysmmu@13260000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13260000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <10 6>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_ISP>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_jpeg: sysmmu@11F20000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11F20000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 2>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_drc: sysmmu@13270000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13270000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <11 6>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_DRC>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_isp: sysmmu@13260000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13260000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <10 6>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_ISP>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_fd: sysmmu@132A0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x132A0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 0>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_FD>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_drc: sysmmu@13270000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13270000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <11 6>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_DRC>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_scc: sysmmu@13280000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13280000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 2>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_SCC>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_fd: sysmmu@132A0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x132A0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 0>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_FD>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_scp: sysmmu@13290000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13290000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <3 6>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_SCP>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_scc: sysmmu@13280000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13280000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 2>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_SCC>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_mcuctl: sysmmu@132B0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x132B0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 4>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_MCU>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_scp: sysmmu@13290000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13290000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <3 6>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_SCP>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_odc: sysmmu@132C0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x132C0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <11 0>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_ODC>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_mcuctl: sysmmu@132B0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x132B0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 4>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_MCU>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_dis0: sysmmu@132D0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x132D0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <10 4>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_DIS0>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_odc: sysmmu@132C0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x132C0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <11 0>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_ODC>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_dis1: sysmmu@132E0000{
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x132E0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <9 4>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_DIS1>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_dis0: sysmmu@132D0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x132D0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <10 4>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_DIS0>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_3dnr: sysmmu@132F0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x132F0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <5 6>;
+                        clock-names = "sysmmu";
+                        clocks = <&clock CLK_SMMU_FIMC_3DNR>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_dis1: sysmmu@132E0000{
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x132E0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <9 4>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_DIS1>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_lite0: sysmmu@13C40000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13C40000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <3 4>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_3dnr: sysmmu@132F0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x132F0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <5 6>;
-                clock-names = "sysmmu";
-                clocks = <&clock CLK_SMMU_FIMC_3DNR>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimc_lite1: sysmmu@13C50000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13C50000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <24 1>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_lite0: sysmmu@13C40000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13C40000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <3 4>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMC_LITE0>, <&clock CLK_CAMIF_TOP>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_gsc0: sysmmu@13E80000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13E80000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 0>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_fimc_lite1: sysmmu@13C50000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13C50000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <24 1>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMC_LITE1>, <&clock CLK_CAMIF_TOP>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_gsc1: sysmmu@13E90000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13E90000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 2>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_gsc0: sysmmu@13E80000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13E80000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <2 0>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_gsc2: sysmmu@13EA0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13EA0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 4>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_gsc1: sysmmu@13E90000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13E90000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <2 2>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_gsc3: sysmmu@13EB0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13EB0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 6>;
+                        power-domains = <&pd_gsc>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_gsc2: sysmmu@13EA0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13EA0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <2 4>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_GSCL2>, <&clock CLK_GSCL2>;
-                #iommu-cells = <0>;
-        };
+                sysmmu_fimd1: sysmmu@14640000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x14640000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <3 2>;
+                        power-domains = <&pd_disp1>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
+                        #iommu-cells = <0>;
+                };
 
-        sysmmu_gsc3: sysmmu@13EB0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13EB0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <2 6>;
-                power-domains = <&pd_gsc>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_GSCL3>, <&clock CLK_GSCL3>;
-                #iommu-cells = <0>;
+                sysmmu_tv: sysmmu@14650000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x14650000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <7 4>;
+                        power-domains = <&pd_disp1>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
+                        #iommu-cells = <0>;
+                };
         };
 
-        sysmmu_fimd1: sysmmu@14640000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x14640000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <3 2>;
-                power-domains = <&pd_disp1>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMD1>, <&clock CLK_FIMD1>;
-                #iommu-cells = <0>;
-        };
+        thermal-zones {
+                cpu_thermal: cpu-thermal {
+                        polling-delay-passive = <0>;
+                        polling-delay = <0>;
+                        thermal-sensors = <&tmu 0>;
 
-        sysmmu_tv: sysmmu@14650000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x14650000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <7 4>;
-                power-domains = <&pd_disp1>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
-                #iommu-cells = <0>;
+                        cooling-maps {
+                                map0 {
+                                     /* Corresponds to 800MHz at freq_table */
+                                     cooling-device = <&cpu0 9 9>;
+                                };
+                                map1 {
+                                     /* Corresponds to 200MHz at freq_table */
+                                     cooling-device = <&cpu0 15 15>;
+                               };
+                       };
+                };
         };
 };
 
@@ -1070,6 +1000,39 @@
         iommus = <&sysmmu_fimd1>;
 };
 
+&i2c_0 {
+        clocks = <&clock CLK_I2C0>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_bus>;
+};
+
+&i2c_1 {
+        clocks = <&clock CLK_I2C1>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_bus>;
+};
+
+&i2c_2 {
+        clocks = <&clock CLK_I2C2>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_bus>;
+};
+
+&i2c_3 {
+        clocks = <&clock CLK_I2C3>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_bus>;
+};
+
+&pwm {
+        clocks = <&clock CLK_PWM>;
+        clock-names = "timers";
+};
+
 &rtc {
         clocks = <&clock CLK_RTC>;
         clock-names = "rtc";
diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts
new file mode 100644
index 000000000000..d9499310a301
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts
@@ -0,0 +1,580 @@
+/*
+ * Hardkernel Odroid XU board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+#include "exynos5410.dtsi"
+#include <dt-bindings/clock/maxim,max77802.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "exynos54xx-odroidxu-leds.dtsi"
+
+/ {
+        model = "Hardkernel Odroid XU";
+        compatible = "hardkernel,odroid-xu", "samsung,exynos5410", "samsung,exynos5";
+
+        memory {
+                reg = <0x40000000 0x7ea00000>;
+        };
+
+        chosen {
+                linux,stdout-path = &serial_2;
+        };
+
+        emmc_pwrseq: pwrseq {
+                pinctrl-0 = <&emmc_nrst_pin>;
+                pinctrl-names = "default";
+                compatible = "mmc-pwrseq-emmc";
+                reset-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>;
+        };
+
+        fan0: pwm-fan {
+                compatible = "pwm-fan";
+                pwms = <&pwm 0 20972 0>;
+                cooling-min-state = <0>;
+                cooling-max-state = <3>;
+                #cooling-cells = <2>;
+                cooling-levels = <0 130 170 230>;
+        };
+
+        fin_pll: xxti {
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "fin_pll";
+                #clock-cells = <0>;
+        };
+
+        firmware@02073000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x02073000 0x1000>;
+        };
+};
+
+&cpu0_thermal {
+        thermal-sensors = <&tmu_cpu0 0>;
+        polling-delay-passive = <0>;
+        polling-delay = <0>;
+
+        trips {
+                cpu_alert0: cpu-alert-0 {
+                        temperature = <50000>; /* millicelsius */
+                        hysteresis = <5000>; /* millicelsius */
+                        type = "active";
+                };
+                cpu_alert1: cpu-alert-1 {
+                        temperature = <60000>; /* millicelsius */
+                        hysteresis = <5000>; /* millicelsius */
+                        type = "active";
+                };
+                cpu_alert2: cpu-alert-2 {
+                        temperature = <70000>; /* millicelsius */
+                        hysteresis = <5000>; /* millicelsius */
+                        type = "active";
+                };
+                cpu_crit0: cpu-crit-0 {
+                        temperature = <120000>; /* millicelsius */
+                        hysteresis = <0>; /* millicelsius */
+                        type = "critical";
+                };
+        };
+
+        cooling-maps {
+                map0 {
+                        trip = <&cpu_alert0>;
+                        cooling-device = <&fan0 0 1>;
+                };
+                map1 {
+                        trip = <&cpu_alert1>;
+                        cooling-device = <&fan0 1 2>;
+                };
+                map2 {
+                        trip = <&cpu_alert2>;
+                        cooling-device = <&fan0 2 3>;
+                };
+        };
+};
+
+&hsi2c_4 {
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <400000>;
+        status = "okay";
+
+        usb3503: usb-hub@08 {
+                compatible = "smsc,usb3503";
+                reg = <0x08>;
+
+                intn-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+                connect-gpios = <&gpx0 6 GPIO_ACTIVE_HIGH>;
+                reset-gpios = <&gpx1 4 GPIO_ACTIVE_HIGH>;
+                initial-mode = <1>;
+
+                clock-names = "refclk";
+                clocks = <&pmu_system_controller 0>;
+                refclk-frequency = <24000000>;
+        };
+
+        max77802: pmic@09 {
+                compatible = "maxim,max77802";
+                reg = <0x9>;
+                interrupt-parent = <&gpx0>;
+                interrupts = <4 IRQ_TYPE_NONE>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&max77802_irq>, <&pmic_dvs_1>, <&pmic_dvs_2>,
+                            <&pmic_dvs_3>;
+                #clock-cells = <1>;
+
+                inl1-supply = <&buck5_reg>;
+                inl2-supply = <&buck7_reg>;
+                inl3-supply = <&buck9_reg>;
+                inl4-supply = <&buck9_reg>;
+                inl5-supply = <&buck9_reg>;
+                inl6-supply = <&buck10_reg>;
+                inl7-supply = <&buck9_reg>;
+                /* inl9 supply is BOOST, not configured here */
+                inl10-supply = <&buck7_reg>;
+
+                regulators {
+                        buck1_reg: BUCK1 {
+                                regulator-name = "vdd_mif";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck2_reg: BUCK2 {
+                                regulator-name = "vdd_arm";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck3_reg: BUCK3 {
+                                regulator-name = "vdd_int";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck4_reg: BUCK4 {
+                                regulator-name = "vdd_g3d";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1400000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck5_reg: BUCK5 {
+                                regulator-name = "vdd_mem";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck6_reg: BUCK6 {
+                                regulator-name = "vdd_kfc";
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck7_reg: BUCK7 {
+                                regulator-name = "buck7";
+                                regulator-min-microvolt = <1300000>;
+                                regulator-max-microvolt = <1300000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck8_reg: BUCK8 {
+                                /* vdd_mmc0 */
+                                regulator-name = "vddf_2v85";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck9_reg: BUCK9 {
+                                regulator-name = "buck9";
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        buck10_reg: BUCK10 {
+                                regulator-name = "buck10";
+                                regulator-min-microvolt = <2950000>;
+                                regulator-max-microvolt = <2950000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+
+                        ldo1_reg: LDO1 {
+                                regulator-name = "vdd_alive";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo2_reg: LDO2 {
+                                regulator-name = "vddq_m1_m2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        ldo3_reg: LDO3 {
+                                regulator-name = "vddq_gpio";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo4_reg: LDO4 {
+                                regulator-name = "vddq_mmc2";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3000000>;
+                                /* Having it off prevents reboot */
+                                regulator-always-on;
+                        };
+
+                        ldo5_reg: LDO5 {
+                                regulator-name = "vdd18_hsic";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo6_reg: LDO6 {
+                                regulator-name = "vdd18_bpll";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo7_reg: LDO7 {
+                                regulator-name = "vddq_lcd";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo8_reg: LDO8 {
+                                regulator-name = "vdd10_hdmi";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo9_reg: LDO9 {
+                                regulator-name = "ldo9";
+                        };
+
+                        ldo10_reg: LDO10 {
+                                regulator-name = "vdd18_mipi";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo11_reg: LDO11 {
+                                regulator-name = "vddq_mmc01";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                /*
+                                 * Having it off prevents accessing MMC after
+                                 * reboot with error:
+                                 * MMC Device 1: Clock OFF has been failed.
+                                 */
+                                regulator-always-on;
+                        };
+
+                        ldo12_reg: LDO12 {
+                                regulator-name = "vdd33_usb3";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        ldo13_reg: LDO13 {
+                                regulator-name = "vddq_abbg0";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo14_reg: LDO14 {
+                                regulator-name = "vddq_abbg1";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+
+                        ldo15_reg: LDO15 {
+                                regulator-name = "vdd10_usb3";
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1000000>;
+                                regulator-always-on;
+                        };
+
+                        ldo16_reg: LDO16 {
+                                regulator-name = "ldo16";
+                        };
+
+                        ldo17_reg: LDO17 {
+                                regulator-name = "cam_sensor_core";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                        };
+
+                        ldo18_reg: LDO18 {
+                                regulator-name = "ldo18";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo19_reg: LDO19 {
+                                regulator-name = "ldo19";
+                        };
+
+                        ldo20_reg: LDO20 {
+                                regulator-name = "vdd_mmc0";
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                        };
+
+                        ldo21_reg: LDO21 {
+                                /* vdd_mmc2 */
+                                regulator-name = "vddf_2v8";
+                                regulator-min-microvolt = <2850000>;
+                                regulator-max-microvolt = <2850000>;
+                        };
+
+                        ldo22_reg: LDO22 {
+                                regulator-name = "ldo22";
+                        };
+
+                        ldo23_reg: LDO23 {
+                                regulator-name = "dp_p3v3";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        ldo24_reg: LDO24 {
+                                regulator-name = "cam_af";
+                                regulator-min-microvolt = <2800000>;
+                                regulator-max-microvolt = <2800000>;
+                        };
+
+                        ldo25_reg: LDO25 {
+                                regulator-name = "eth_p3v3";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        ldo26_reg: LDO26 {
+                                regulator-name = "usb30_extclk";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        ldo27_reg: LDO27 {
+                                regulator-name = "ldo27";
+                        };
+
+                        ldo28_reg: LDO28 {
+                                regulator-name = "ldo28";
+                        };
+
+                        ldo29_reg: LDO29 {
+                                regulator-name = "ldo29";
+                        };
+
+                        ldo30_reg: LDO30 {
+                                regulator-name = "vddq_e1_e2";
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+
+                        ldo31_reg: LDO31 {
+                                regulator-name = "ldo31";
+                        };
+
+                        /* On revisions with ti,ina231 this is sensor VS */
+                        ldo32_reg: LDO32 {
+                                regulator-name = "vs_power_meter";
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+
+                        ldo33_reg: LDO33 {
+                                regulator-name = "ldo33";
+                        };
+
+                        ldo34_reg: LDO34 {
+                                regulator-name = "ldo34";
+                        };
+
+                        ldo35_reg: LDO35 {
+                                regulator-name = "ldo35";
+                        };
+                };
+        };
+};
+
+&mmc_0 {
+        status = "okay";
+        mmc-pwrseq = <&emmc_pwrseq>;
+        cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        samsung,dw-mshc-hs400-timing = <0 2>;
+        samsung,read-strobe-delay = <90>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_cd>;
+        bus-width = <8>;
+        cap-mmc-highspeed;
+        mmc-hs200-1_8v;
+        mmc-hs400-1_8v;
+        vmmc-supply = <&ldo20_reg>;
+        vqmmc-supply = <&ldo11_reg>;
+};
+
+&mmc_2 {
+        status = "okay";
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+        bus-width = <4>;
+        cap-sd-highspeed;
+        vmmc-supply = <&ldo21_reg>;
+        vqmmc-supply = <&ldo4_reg>;
+};
+
+&pinctrl_0 {
+        emmc_nrst_pin: emmc-nrst {
+                samsung,pins = "gpd1-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pmic_dvs_3: pmic-dvs-3 {
+                samsung,pins = "gpx0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pmic_dvs_2: pmic-dvs-2 {
+                samsung,pins = "gpx0-1";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pmic_dvs_1: pmic-dvs-1 {
+                samsung,pins = "gpx0-2";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+                samsung,pin-val = <1>;
+        };
+
+        max77802_irq: max77802-irq {
+                samsung,pins = "gpx0-4";
+                samsung,pin-function = <0xf>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+
+&pwm {
+        /*
+         * PWM 0 -- fan
+         * PWM 1 -- Green LED
+         * PWM 2 -- Blue LED
+         * PWM 3 -- on MIPI connector for backlight
+         */
+        pinctrl-0 = <&pwm0_out &pwm1_out &pwm2_out &pwm3_out>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+
+&rtc {
+        status = "okay";
+        clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>;
+        clock-names = "rtc", "rtc_src";
+};
+
+&serial_0 {
+        status = "okay";
+};
+
+&serial_1 {
+        status = "okay";
+};
+
+&serial_2 {
+        status = "okay";
+};
+
+&serial_3 {
+        status = "okay";
+};
+
+&tmu_cpu0 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu1 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu2 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu3 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&usbdrd_dwc3_0 {
+        dr_mode = "host";
+};
+
+&usbdrd_dwc3_1 {
+        dr_mode = "peripheral";
+};
+
+&usbdrd3_0 {
+        vdd33-supply = <&ldo12_reg>;
+        vdd10-supply = <&ldo15_reg>;
+};
+
+&usbdrd3_1 {
+        vdd33-supply = <&ldo12_reg>;
+        vdd10-supply = <&ldo15_reg>;
+};
diff --git a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
index f9aa6bb55464..b58a0f29f42c 100644
--- a/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5410-pinctrl.dtsi
@@ -277,6 +277,216 @@
                 interrupt-controller;
                 #interrupt-cells = <2>;
         };
+
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart2_fctl: uart2-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c3_bus: i2c3-bus {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        uart3_data: uart3-data {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c4_hs_bus: i2c4-hs-bus {
+                samsung,pins = "gpa2-0", "gpa2-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c5_hs_bus: i2c5-hs-bus {
+                samsung,pins = "gpa2-2", "gpa2-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c6_hs_bus: i2c6-hs-bus {
+                samsung,pins = "gpb1-3", "gpb1-4";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpb2-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpb2-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpb2-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpb2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c7_hs_bus: i2c7-hs-bus {
+                samsung,pins = "gpb2-2", "gpb2-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpb3-0", "gpb3-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpb3-2", "gpb3-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpc0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpc0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpc0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpc0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpc0-4", "gpc0-5", "gpc0-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpc2-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpc2-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpc2-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpc2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
 };
 
 &pinctrl_1 {
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
index 0f6429e1b75c..777fcf2edd79 100644
--- a/arch/arm/boot/dts/exynos5410-smdk5410.dts
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -102,14 +102,14 @@
         };
 };
 
-&uart0 {
+&serial_0 {
         status = "okay";
 };
 
-&uart1 {
+&serial_1 {
         status = "okay";
 };
 
-&uart2 {
+&serial_2 {
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 7a56aec2c5ba..137f48464f8b 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -13,9 +13,10 @@
  * published by the Free Software Foundation.
  */
 
-#include "skeleton.dtsi"
+#include "exynos54xx.dtsi"
 #include "exynos-syscon-restart.dtsi"
 #include <dt-bindings/clock/exynos5410.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
         compatible = "samsung,exynos5410", "samsung,exynos5";
@@ -26,37 +27,34 @@
                 pinctrl1 = &pinctrl_1;
                 pinctrl2 = &pinctrl_2;
                 pinctrl3 = &pinctrl_3;
-                serial0 = &uart0;
-                serial1 = &uart1;
-                serial2 = &uart2;
         };
 
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                CPU0: cpu@0 {
+                cpu0: cpu@0 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0x0>;
                         clock-frequency = <1600000000>;
                 };
 
-                CPU1: cpu@1 {
+                cpu1: cpu@1 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0x1>;
                         clock-frequency = <1600000000>;
                 };
 
-                CPU2: cpu@2 {
+                cpu2: cpu@2 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0x2>;
                         clock-frequency = <1600000000>;
                 };
 
-                CPU3: cpu@3 {
+                cpu3: cpu@3 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a15";
                         reg = <0x3>;
@@ -70,105 +68,54 @@
                 #size-cells = <1>;
                 ranges;
 
-                combiner: interrupt-controller@10440000 {
-                        compatible = "samsung,exynos4210-combiner";
-                        #interrupt-cells = <2>;
-                        interrupt-controller;
-                        samsung,combiner-nr = <32>;
-                        reg = <0x10440000 0x1000>;
-                        interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
-                                        <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
-                                        <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
-                                        <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
-                                        <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
-                                        <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
-                                        <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
-                                        <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
-                };
-
-                gic: interrupt-controller@10481000 {
-                        compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
-                        #interrupt-cells = <3>;
-                        interrupt-controller;
-                        reg =   <0x10481000 0x1000>,
-                                <0x10482000 0x1000>,
-                                <0x10484000 0x2000>,
-                                <0x10486000 0x2000>;
-                        interrupts = <1 9 0xf04>;
-                };
-
-                chipid@10000000 {
-                        compatible = "samsung,exynos4210-chipid";
-                        reg = <0x10000000 0x100>;
-                };
-
-                sromc: memory-controller@12250000 {
-                        compatible = "samsung,exynos4210-srom";
-                        reg = <0x12250000 0x14>;
-                        #address-cells = <2>;
-                        #size-cells = <1>;
-                        ranges = <0 0 0x04000000 0x20000
-                                  1 0 0x05000000 0x20000
-                                  2 0 0x06000000 0x20000
-                                  3 0 0x07000000 0x20000>;
-                };
-
                 pmu_system_controller: system-controller@10040000 {
                         compatible = "samsung,exynos5410-pmu", "syscon";
                         reg = <0x10040000 0x5000>;
+                        clock-names = "clkout16";
+                        clocks = <&fin_pll>;
+                        #clock-cells = <1>;
                 };
 
-                mct: mct@101C0000 {
-                        compatible = "samsung,exynos4210-mct";
-                        reg = <0x101C0000 0xB00>;
-                        interrupt-parent = <&interrupt_map>;
-                        interrupts = <0>, <1>, <2>, <3>,
-                                <4>, <5>, <6>, <7>,
-                                <8>, <9>, <10>, <11>;
-                        clocks = <&fin_pll>, <&clock CLK_MCT>;
-                        clock-names = "fin_pll", "mct";
-
-                        interrupt_map: interrupt-map {
-                                #interrupt-cells = <1>;
-                                #address-cells = <0>;
-                                #size-cells = <0>;
-                                interrupt-map = <0 &combiner 23 3>,
-                                                <1 &combiner 23 4>,
-                                                <2 &combiner 25 2>,
-                                                <3 &combiner 25 3>,
-                                                <4 &gic 0 120 0>,
-                                                <5 &gic 0 121 0>,
-                                                <6 &gic 0 122 0>,
-                                                <7 &gic 0 123 0>,
-                                                <8 &gic 0 128 0>,
-                                                <9 &gic 0 129 0>,
-                                                <10 &gic 0 130 0>,
-                                                <11 &gic 0 131 0>;
-                        };
+                clock: clock-controller@10010000 {
+                        compatible = "samsung,exynos5410-clock";
+                        reg = <0x10010000 0x30000>;
+                        #clock-cells = <1>;
                 };
 
-                sysram@02020000 {
-                        compatible = "mmio-sram";
-                        reg = <0x02020000 0x54000>;
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        ranges = <0 0x02020000 0x54000>;
+                tmu_cpu0: tmu@10060000 {
+                        compatible = "samsung,exynos5420-tmu";
+                        reg = <0x10060000 0x100>;
+                        interrupts = <GIC_SPI 65 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
 
-                        smp-sysram@0 {
-                                compatible = "samsung,exynos4210-sysram";
-                                reg = <0x0 0x1000>;
-                        };
+                tmu_cpu1: tmu@10064000 {
+                        compatible = "samsung,exynos5420-tmu";
+                        reg = <0x10064000 0x100>;
+                        interrupts = <GIC_SPI 183 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
 
-                        smp-sysram@53000 {
-                                compatible = "samsung,exynos4210-sysram-ns";
-                                reg = <0x53000 0x1000>;
-                        };
+                tmu_cpu2: tmu@10068000 {
+                        compatible = "samsung,exynos5420-tmu";
+                        reg = <0x10068000 0x100>;
+                        interrupts = <GIC_SPI 184 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
                 };
 
-                clock: clock-controller@10010000 {
-                        compatible = "samsung,exynos5410-clock";
-                        reg = <0x10010000 0x30000>;
-                        #clock-cells = <1>;
+                tmu_cpu3: tmu@1006c000 {
+                        compatible = "samsung,exynos5420-tmu";
+                        reg = <0x1006c000 0x100>;
+                        interrupts = <GIC_SPI 185 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
                 };
 
                 mmc_0: mmc@12200000 {
@@ -236,34 +183,182 @@
                         reg = <0x03860000 0x1000>;
                         interrupts = <0 47 0>;
                 };
+        };
 
-                uart0: serial@12C00000 {
-                        compatible = "samsung,exynos4210-uart";
-                        reg = <0x12C00000 0x100>;
-                        interrupts = <0 51 0>;
-                        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
-                        clock-names = "uart", "clk_uart_baud0";
-                        status = "disabled";
+        thermal-zones {
+                cpu0_thermal: cpu0-thermal {
+                        thermal-sensors = <&tmu_cpu0>;
+                        #include "exynos5420-trip-points.dtsi"
                 };
-
-                uart1: serial@12C10000 {
-                        compatible = "samsung,exynos4210-uart";
-                        reg = <0x12C10000 0x100>;
-                        interrupts = <0 52 0>;
-                        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
-                        clock-names = "uart", "clk_uart_baud0";
-                        status = "disabled";
+                cpu1_thermal: cpu1-thermal {
+                       thermal-sensors = <&tmu_cpu1>;
+                       #include "exynos5420-trip-points.dtsi"
                 };
-
-                uart2: serial@12C20000 {
-                        compatible = "samsung,exynos4210-uart";
-                        reg = <0x12C20000 0x100>;
-                        interrupts = <0 53 0>;
-                        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
-                        clock-names = "uart", "clk_uart_baud0";
-                        status = "disabled";
+                cpu2_thermal: cpu2-thermal {
+                       thermal-sensors = <&tmu_cpu2>;
+                       #include "exynos5420-trip-points.dtsi"
+                };
+                cpu3_thermal: cpu3-thermal {
+                       thermal-sensors = <&tmu_cpu3>;
+                       #include "exynos5420-trip-points.dtsi"
                 };
         };
 };
 
+&i2c_0 {
+        clocks = <&clock CLK_I2C0>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_bus>;
+};
+
+&i2c_1 {
+        clocks = <&clock CLK_I2C1>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_bus>;
+};
+
+&i2c_2 {
+        clocks = <&clock CLK_I2C2>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_bus>;
+};
+
+&i2c_3 {
+        clocks = <&clock CLK_I2C3>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_bus>;
+};
+
+&hsi2c_4 {
+        clocks = <&clock CLK_USI0>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c4_hs_bus>;
+};
+
+&hsi2c_5 {
+        clocks = <&clock CLK_USI1>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c5_hs_bus>;
+};
+
+&hsi2c_6 {
+        clocks = <&clock CLK_USI2>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c6_hs_bus>;
+};
+
+&hsi2c_7 {
+        clocks = <&clock CLK_USI3>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c7_hs_bus>;
+};
+
+&mct {
+        clocks = <&fin_pll>, <&clock CLK_MCT>;
+        clock-names = "fin_pll", "mct";
+};
+
+&pwm {
+        clocks = <&clock CLK_PWM>;
+        clock-names = "timers";
+};
+
+&rtc {
+        clocks = <&clock CLK_RTC>;
+        clock-names = "rtc";
+        interrupt-parent = <&pmu_system_controller>;
+        status = "disabled";
+};
+
+&serial_0 {
+        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+        clock-names = "uart", "clk_uart_baud0";
+};
+
+&serial_1 {
+        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+        clock-names = "uart", "clk_uart_baud0";
+};
+
+&serial_2 {
+        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+        clock-names = "uart", "clk_uart_baud0";
+};
+
+&serial_3 {
+        clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
+        clock-names = "uart", "clk_uart_baud0";
+};
+
+&sss {
+        clocks = <&clock CLK_SSS>;
+        clock-names = "secss";
+};
+
+&sromc {
+        #address-cells = <2>;
+        #size-cells = <1>;
+        ranges = <0 0 0x04000000 0x20000
+                  1 0 0x05000000 0x20000
+                  2 0 0x06000000 0x20000
+                  3 0 0x07000000 0x20000>;
+};
+
+&usbdrd3_0 {
+        clocks = <&clock CLK_USBD300>;
+        clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+        clock-names = "phy", "ref";
+        samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+        clocks = <&clock CLK_USBD301>;
+        clock-names = "usbdrd30";
+};
+
+&usbdrd_dwc3_1 {
+        interrupts = <GIC_SPI 200 0>;
+};
+
+&usbdrd_phy1 {
+        clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+        clock-names = "phy", "ref";
+        samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+        clocks = <&clock CLK_USBH20>;
+        clock-names = "usbhost";
+};
+
+&usbhost2 {
+        clocks = <&clock CLK_USBH20>;
+        clock-names = "usbhost";
+};
+
+&usb2_phy {
+        clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+        clock-names = "phy", "ref";
+        samsung,sysreg-phandle = <&sysreg_system_controller>;
+        samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
+&watchdog {
+        clocks = <&clock CLK_WDT>;
+        clock-names = "watchdog";
+        samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5410-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index b8b5f3ae2942..39a3b81478fd 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -347,10 +347,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         broken-cd;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 6b6766e3d90a..fe4e0915c0c6 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -279,7 +279,6 @@
                                 regulator-name = "vdd_1v2";
                                 regulator-min-microvolt = <1200000>;
                                 regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-off-in-suspend;
@@ -302,7 +301,6 @@
                                 regulator-name = "vdd_1v35";
                                 regulator-min-microvolt = <1350000>;
                                 regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -324,7 +322,6 @@
                                 regulator-name = "vdd_2v";
                                 regulator-min-microvolt = <2000000>;
                                 regulator-max-microvolt = <2000000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -335,7 +332,6 @@
                                 regulator-name = "vdd_1v8";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -420,7 +416,6 @@
                                 regulator-name = "vdd_ldo9";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
                                         regulator-mode = <MAX77802_OPMODE_LP>;
@@ -431,7 +426,6 @@
                                 regulator-name = "vdd_ldo10";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
                                 regulator-state-mem {
                                         regulator-off-in-suspend;
                                 };
@@ -702,10 +696,6 @@
         status = "okay";
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
@@ -1053,6 +1043,26 @@
         status = "okay";
 };
 
+&tmu_cpu0 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu1 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu2 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu3 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_gpu {
+        vtmu-supply = <&ldo10_reg>;
+};
+
 &usbdrd_dwc3_0 {
         dr_mode = "host";
 };
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index 130563b2ca95..14beb7e07323 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -193,17 +193,17 @@
                 samsung,pin-drv = <3>;
         };
 
-        sd1_clk: sd1-clk {
-                samsung,pins = "gpc1-0";
+        sd0_rclk: sd0-rclk {
+                samsung,pins = "gpc0-7";
                 samsung,pin-function = <2>;
-                samsung,pin-pud = <0>;
+                samsung,pin-pud = <1>;
                 samsung,pin-drv = <3>;
         };
 
-        sd0_rclk: sd0-rclk {
-                samsung,pins = "gpc0-7";
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpc1-0";
                 samsung,pin-function = <2>;
-                samsung,pin-pud = <1>;
+                samsung,pin-pud = <0>;
                 samsung,pin-drv = <3>;
         };
 
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 5206f41e548d..ed8f3426911b 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -355,10 +355,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         broken-cd;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c6e05eb88937..00c4cfa54839 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -13,10 +13,10 @@
  * published by the Free Software Foundation.
  */
 
+#include "exynos54xx.dtsi"
 #include <dt-bindings/clock/exynos5420.h>
-#include "exynos5.dtsi"
-
 #include <dt-bindings/clock/exynos-audss-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
         compatible = "samsung,exynos5420", "samsung,exynos5";
@@ -30,14 +30,6 @@
                 pinctrl2 = &pinctrl_2;
                 pinctrl3 = &pinctrl_3;
                 pinctrl4 = &pinctrl_4;
-                i2c0 = &i2c_0;
-                i2c1 = &i2c_1;
-                i2c2 = &i2c_2;
-                i2c3 = &i2c_3;
-                i2c4 = &hsi2c_4;
-                i2c5 = &hsi2c_5;
-                i2c6 = &hsi2c_6;
-                i2c7 = &hsi2c_7;
                 i2c8 = &hsi2c_8;
                 i2c9 = &hsi2c_9;
                 i2c10 = &hsi2c_10;
@@ -46,118 +38,6 @@
                 spi0 = &spi_0;
                 spi1 = &spi_1;
                 spi2 = &spi_2;
-                usbdrdphy0 = &usbdrd_phy0;
-                usbdrdphy1 = &usbdrd_phy1;
-        };
-
-        cluster_a15_opp_table: opp_table0 {
-                compatible = "operating-points-v2";
-                opp-shared;
-                opp@1800000000 {
-                        opp-hz = /bits/ 64 <1800000000>;
-                        opp-microvolt = <1250000>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1700000000 {
-                        opp-hz = /bits/ 64 <1700000000>;
-                        opp-microvolt = <1212500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1600000000 {
-                        opp-hz = /bits/ 64 <1600000000>;
-                        opp-microvolt = <1175000>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1500000000 {
-                        opp-hz = /bits/ 64 <1500000000>;
-                        opp-microvolt = <1137500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1400000000 {
-                        opp-hz = /bits/ 64 <1400000000>;
-                        opp-microvolt = <1112500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1300000000 {
-                        opp-hz = /bits/ 64 <1300000000>;
-                        opp-microvolt = <1062500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1200000000 {
-                        opp-hz = /bits/ 64 <1200000000>;
-                        opp-microvolt = <1037500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1100000000 {
-                        opp-hz = /bits/ 64 <1100000000>;
-                        opp-microvolt = <1012500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1000000000 {
-                        opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = < 987500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@900000000 {
-                        opp-hz = /bits/ 64 <900000000>;
-                        opp-microvolt = < 962500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@800000000 {
-                        opp-hz = /bits/ 64 <800000000>;
-                        opp-microvolt = < 937500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@700000000 {
-                        opp-hz = /bits/ 64 <700000000>;
-                        opp-microvolt = < 912500>;
-                        clock-latency-ns = <140000>;
-                };
-        };
-
-        cluster_a7_opp_table: opp_table1 {
-                compatible = "operating-points-v2";
-                opp-shared;
-                opp@1300000000 {
-                        opp-hz = /bits/ 64 <1300000000>;
-                        opp-microvolt = <1275000>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1200000000 {
-                        opp-hz = /bits/ 64 <1200000000>;
-                        opp-microvolt = <1212500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1100000000 {
-                        opp-hz = /bits/ 64 <1100000000>;
-                        opp-microvolt = <1162500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@1000000000 {
-                        opp-hz = /bits/ 64 <1000000000>;
-                        opp-microvolt = <1112500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@900000000 {
-                        opp-hz = /bits/ 64 <900000000>;
-                        opp-microvolt = <1062500>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@800000000 {
-                        opp-hz = /bits/ 64 <800000000>;
-                        opp-microvolt = <1025000>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@700000000 {
-                        opp-hz = /bits/ 64 <700000000>;
-                        opp-microvolt = <975000>;
-                        clock-latency-ns = <140000>;
-                };
-                opp@600000000 {
-                        opp-hz = /bits/ 64 <600000000>;
-                        opp-microvolt = <937500>;
-                        clock-latency-ns = <140000>;
-                };
         };
 
         /*
@@ -165,1434 +45,1270 @@
          * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi.
          */
 
-        cci: cci@10d20000 {
-                compatible = "arm,cci-400";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                reg = <0x10d20000 0x1000>;
-                ranges = <0x0 0x10d20000 0x6000>;
-
-                cci_control0: slave-if@4000 {
-                        compatible = "arm,cci-400-ctrl-if";
-                        interface-type = "ace";
-                        reg = <0x4000 0x1000>;
-                };
-                cci_control1: slave-if@5000 {
-                        compatible = "arm,cci-400-ctrl-if";
-                        interface-type = "ace";
-                        reg = <0x5000 0x1000>;
+        soc: soc {
+                cluster_a15_opp_table: opp_table0 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+                        opp@1800000000 {
+                                opp-hz = /bits/ 64 <1800000000>;
+                                opp-microvolt = <1250000>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1700000000 {
+                                opp-hz = /bits/ 64 <1700000000>;
+                                opp-microvolt = <1212500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1600000000 {
+                                opp-hz = /bits/ 64 <1600000000>;
+                                opp-microvolt = <1175000>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1500000000 {
+                                opp-hz = /bits/ 64 <1500000000>;
+                                opp-microvolt = <1137500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1400000000 {
+                                opp-hz = /bits/ 64 <1400000000>;
+                                opp-microvolt = <1112500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1300000000 {
+                                opp-hz = /bits/ 64 <1300000000>;
+                                opp-microvolt = <1062500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1200000000 {
+                                opp-hz = /bits/ 64 <1200000000>;
+                                opp-microvolt = <1037500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1100000000 {
+                                opp-hz = /bits/ 64 <1100000000>;
+                                opp-microvolt = <1012500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1000000000 {
+                                opp-hz = /bits/ 64 <1000000000>;
+                                opp-microvolt = < 987500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@900000000 {
+                                opp-hz = /bits/ 64 <900000000>;
+                                opp-microvolt = < 962500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@800000000 {
+                                opp-hz = /bits/ 64 <800000000>;
+                                opp-microvolt = < 937500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@700000000 {
+                                opp-hz = /bits/ 64 <700000000>;
+                                opp-microvolt = < 912500>;
+                                clock-latency-ns = <140000>;
+                        };
+                };
+
+                cluster_a7_opp_table: opp_table1 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+                        opp@1300000000 {
+                                opp-hz = /bits/ 64 <1300000000>;
+                                opp-microvolt = <1275000>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1200000000 {
+                                opp-hz = /bits/ 64 <1200000000>;
+                                opp-microvolt = <1212500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1100000000 {
+                                opp-hz = /bits/ 64 <1100000000>;
+                                opp-microvolt = <1162500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@1000000000 {
+                                opp-hz = /bits/ 64 <1000000000>;
+                                opp-microvolt = <1112500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@900000000 {
+                                opp-hz = /bits/ 64 <900000000>;
+                                opp-microvolt = <1062500>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@800000000 {
+                                opp-hz = /bits/ 64 <800000000>;
+                                opp-microvolt = <1025000>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@700000000 {
+                                opp-hz = /bits/ 64 <700000000>;
+                                opp-microvolt = <975000>;
+                                clock-latency-ns = <140000>;
+                        };
+                        opp@600000000 {
+                                opp-hz = /bits/ 64 <600000000>;
+                                opp-microvolt = <937500>;
+                                clock-latency-ns = <140000>;
+                        };
+                };
+
+                cci: cci@10d20000 {
+                        compatible = "arm,cci-400";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x10d20000 0x1000>;
+                        ranges = <0x0 0x10d20000 0x6000>;
+
+                        cci_control0: slave-if@4000 {
+                                compatible = "arm,cci-400-ctrl-if";
+                                interface-type = "ace";
+                                reg = <0x4000 0x1000>;
+                        };
+                        cci_control1: slave-if@5000 {
+                                compatible = "arm,cci-400-ctrl-if";
+                                interface-type = "ace";
+                                reg = <0x5000 0x1000>;
+                        };
+                };
+
+                clock: clock-controller@10010000 {
+                        compatible = "samsung,exynos5420-clock";
+                        reg = <0x10010000 0x30000>;
+                        #clock-cells = <1>;
+                };
+
+                clock_audss: audss-clock-controller@3810000 {
+                        compatible = "samsung,exynos5420-audss-clock";
+                        reg = <0x03810000 0x0C>;
+                        #clock-cells = <1>;
+                        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
+                                 <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
+                        clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
+                };
+
+                mfc: codec@11000000 {
+                        compatible = "samsung,mfc-v7";
+                        reg = <0x11000000 0x10000>;
+                        interrupts = <0 96 0>;
+                        clocks = <&clock CLK_MFC>;
+                        clock-names = "mfc";
+                        power-domains = <&mfc_pd>;
+                        iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
+                        iommu-names = "left", "right";
+                };
+
+                mmc_0: mmc@12200000 {
+                        compatible = "samsung,exynos5420-dw-mshc-smu";
+                        interrupts = <0 75 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x12200000 0x2000>;
+                        clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x40>;
+                        status = "disabled";
                 };
-        };
-
-        sysram@02020000 {
-                compatible = "mmio-sram";
-                reg = <0x02020000 0x54000>;
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges = <0 0x02020000 0x54000>;
 
-                smp-sysram@0 {
-                        compatible = "samsung,exynos4210-sysram";
-                        reg = <0x0 0x1000>;
+                mmc_1: mmc@12210000 {
+                        compatible = "samsung,exynos5420-dw-mshc-smu";
+                        interrupts = <0 76 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x12210000 0x2000>;
+                        clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x40>;
+                        status = "disabled";
                 };
 
-                smp-sysram@53000 {
-                        compatible = "samsung,exynos4210-sysram-ns";
-                        reg = <0x53000 0x1000>;
+                mmc_2: mmc@12220000 {
+                        compatible = "samsung,exynos5420-dw-mshc";
+                        interrupts = <0 77 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        reg = <0x12220000 0x1000>;
+                        clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x40>;
+                        status = "disabled";
                 };
-        };
-
-        clock: clock-controller@10010000 {
-                compatible = "samsung,exynos5420-clock";
-                reg = <0x10010000 0x30000>;
-                #clock-cells = <1>;
-        };
 
-        clock_audss: audss-clock-controller@3810000 {
-                compatible = "samsung,exynos5420-audss-clock";
-                reg = <0x03810000 0x0C>;
-                #clock-cells = <1>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
-                         <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
-                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
-        };
-
-        mfc: codec@11000000 {
-                compatible = "samsung,mfc-v7";
-                reg = <0x11000000 0x10000>;
-                interrupts = <0 96 0>;
-                clocks = <&clock CLK_MFC>;
-                clock-names = "mfc";
-                power-domains = <&mfc_pd>;
-                iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
-                iommu-names = "left", "right";
-        };
+                nocp_mem0_0: nocp@10CA1000 {
+                        compatible = "samsung,exynos5420-nocp";
+                        reg = <0x10CA1000 0x200>;
+                        status = "disabled";
+                };
 
-        mmc_0: mmc@12200000 {
-                compatible = "samsung,exynos5420-dw-mshc-smu";
-                interrupts = <0 75 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x12200000 0x2000>;
-                clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x40>;
-                status = "disabled";
-        };
+                nocp_mem0_1: nocp@10CA1400 {
+                        compatible = "samsung,exynos5420-nocp";
+                        reg = <0x10CA1400 0x200>;
+                        status = "disabled";
+                };
 
-        mmc_1: mmc@12210000 {
-                compatible = "samsung,exynos5420-dw-mshc-smu";
-                interrupts = <0 76 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x12210000 0x2000>;
-                clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x40>;
-                status = "disabled";
-        };
+                nocp_mem1_0: nocp@10CA1800 {
+                        compatible = "samsung,exynos5420-nocp";
+                        reg = <0x10CA1800 0x200>;
+                        status = "disabled";
+                };
 
-        mmc_2: mmc@12220000 {
-                compatible = "samsung,exynos5420-dw-mshc";
-                interrupts = <0 77 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg = <0x12220000 0x1000>;
-                clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
-                clock-names = "biu", "ciu";
-                fifo-depth = <0x40>;
-                status = "disabled";
-        };
+                nocp_mem1_1: nocp@10CA1C00 {
+                        compatible = "samsung,exynos5420-nocp";
+                        reg = <0x10CA1C00 0x200>;
+                        status = "disabled";
+                };
 
-        mct: mct@101C0000 {
-                compatible = "samsung,exynos4210-mct";
-                reg = <0x101C0000 0x800>;
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                interrupt-parent = <&mct_map>;
-                interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
-                                <8>, <9>, <10>, <11>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
-                clock-names = "fin_pll", "mct";
-
-                mct_map: mct-map {
-                        #interrupt-cells = <1>;
-                        #address-cells = <0>;
-                        #size-cells = <0>;
-                        interrupt-map = <0 &combiner 23 3>,
-                                        <1 &combiner 23 4>,
-                                        <2 &combiner 25 2>,
-                                        <3 &combiner 25 3>,
-                                        <4 &gic 0 120 0>,
-                                        <5 &gic 0 121 0>,
-                                        <6 &gic 0 122 0>,
-                                        <7 &gic 0 123 0>,
-                                        <8 &gic 0 128 0>,
-                                        <9 &gic 0 129 0>,
-                                        <10 &gic 0 130 0>,
-                                        <11 &gic 0 131 0>;
+                nocp_g3d_0: nocp@11A51000 {
+                        compatible = "samsung,exynos5420-nocp";
+                        reg = <0x11A51000 0x200>;
+                        status = "disabled";
                 };
-        };
 
-        nocp_mem0_0: nocp@10CA1000 {
-                compatible = "samsung,exynos5420-nocp";
-                reg = <0x10CA1000 0x200>;
-                status = "disabled";
-        };
+                nocp_g3d_1: nocp@11A51400 {
+                        compatible = "samsung,exynos5420-nocp";
+                        reg = <0x11A51400 0x200>;
+                        status = "disabled";
+                };
 
-        nocp_mem0_1: nocp@10CA1400 {
-                compatible = "samsung,exynos5420-nocp";
-                reg = <0x10CA1400 0x200>;
-                status = "disabled";
-        };
+                gsc_pd: power-domain@10044000 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10044000 0x20>;
+                        #power-domain-cells = <0>;
+                        clocks = <&clock CLK_FIN_PLL>,
+                                 <&clock CLK_MOUT_USER_ACLK300_GSCL>,
+                                 <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
+                        clock-names = "oscclk", "clk0", "asb0", "asb1";
+                };
 
-        nocp_mem1_0: nocp@10CA1800 {
-                compatible = "samsung,exynos5420-nocp";
-                reg = <0x10CA1800 0x200>;
-                status = "disabled";
-        };
+                isp_pd: power-domain@10044020 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10044020 0x20>;
+                        #power-domain-cells = <0>;
+                };
 
-        nocp_mem1_1: nocp@10CA1C00 {
-                compatible = "samsung,exynos5420-nocp";
-                reg = <0x10CA1C00 0x200>;
-                status = "disabled";
-        };
+                mfc_pd: power-domain@10044060 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10044060 0x20>;
+                        clocks = <&clock CLK_FIN_PLL>,
+                                 <&clock CLK_MOUT_USER_ACLK333>,
+                                 <&clock CLK_ACLK333>;
+                        clock-names = "oscclk", "clk0","asb0";
+                        #power-domain-cells = <0>;
+                };
 
-        nocp_g3d_0: nocp@11A51000 {
-                compatible = "samsung,exynos5420-nocp";
-                reg = <0x11A51000 0x200>;
-                status = "disabled";
-        };
+                msc_pd: power-domain@10044120 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10044120 0x20>;
+                        #power-domain-cells = <0>;
+                };
 
-        nocp_g3d_1: nocp@11A51400 {
-                compatible = "samsung,exynos5420-nocp";
-                reg = <0x11A51400 0x200>;
-                status = "disabled";
-        };
+                disp_pd: power-domain@100440C0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x100440C0 0x20>;
+                        #power-domain-cells = <0>;
+                        clocks = <&clock CLK_FIN_PLL>,
+                                 <&clock CLK_MOUT_USER_ACLK200_DISP1>,
+                                 <&clock CLK_MOUT_USER_ACLK300_DISP1>,
+                                 <&clock CLK_MOUT_USER_ACLK400_DISP1>,
+                                 <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
+                        clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
+                };
 
-        gsc_pd: power-domain@10044000 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044000 0x20>;
-                #power-domain-cells = <0>;
-                clocks = <&clock CLK_FIN_PLL>,
-                         <&clock CLK_MOUT_USER_ACLK300_GSCL>,
-                         <&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
-                clock-names = "oscclk", "clk0", "asb0", "asb1";
-        };
+                pinctrl_0: pinctrl@13400000 {
+                        compatible = "samsung,exynos5420-pinctrl";
+                        reg = <0x13400000 0x1000>;
+                        interrupts = <0 45 0>;
 
-        isp_pd: power-domain@10044020 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044020 0x20>;
-                #power-domain-cells = <0>;
-        };
+                        wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 32 0>;
+                        };
+                };
 
-        mfc_pd: power-domain@10044060 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044060 0x20>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_USER_ACLK333>;
-                clock-names = "oscclk", "clk0";
-                #power-domain-cells = <0>;
-        };
+                pinctrl_1: pinctrl@13410000 {
+                        compatible = "samsung,exynos5420-pinctrl";
+                        reg = <0x13410000 0x1000>;
+                        interrupts = <0 78 0>;
+                };
 
-        msc_pd: power-domain@10044120 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044120 0x20>;
-                #power-domain-cells = <0>;
-        };
+                pinctrl_2: pinctrl@14000000 {
+                        compatible = "samsung,exynos5420-pinctrl";
+                        reg = <0x14000000 0x1000>;
+                        interrupts = <0 46 0>;
+                };
 
-        disp_pd: power-domain@100440C0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x100440C0 0x20>;
-                #power-domain-cells = <0>;
-                clocks = <&clock CLK_FIN_PLL>,
-                         <&clock CLK_MOUT_USER_ACLK200_DISP1>,
-                         <&clock CLK_MOUT_USER_ACLK300_DISP1>,
-                         <&clock CLK_MOUT_USER_ACLK400_DISP1>,
-                         <&clock CLK_FIMD1>, <&clock CLK_MIXER>;
-                clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
-        };
+                pinctrl_3: pinctrl@14010000 {
+                        compatible = "samsung,exynos5420-pinctrl";
+                        reg = <0x14010000 0x1000>;
+                        interrupts = <0 50 0>;
+                };
 
-        pinctrl_0: pinctrl@13400000 {
-                compatible = "samsung,exynos5420-pinctrl";
-                reg = <0x13400000 0x1000>;
-                interrupts = <0 45 0>;
+                pinctrl_4: pinctrl@03860000 {
+                        compatible = "samsung,exynos5420-pinctrl";
+                        reg = <0x03860000 0x1000>;
+                        interrupts = <0 47 0>;
+                };
 
-                wakeup-interrupt-controller {
-                        compatible = "samsung,exynos4210-wakeup-eint";
+                amba {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "simple-bus";
                         interrupt-parent = <&gic>;
-                        interrupts = <0 32 0>;
+                        ranges;
+
+                        adma: adma@03880000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x03880000 0x1000>;
+                                interrupts = <0 110 0>;
+                                clocks = <&clock_audss EXYNOS_ADMA>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <6>;
+                                #dma-requests = <16>;
+                        };
+
+                        pdma0: pdma@121A0000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x121A0000 0x1000>;
+                                interrupts = <0 34 0>;
+                                clocks = <&clock CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        pdma1: pdma@121B0000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x121B0000 0x1000>;
+                                interrupts = <0 35 0>;
+                                clocks = <&clock CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+
+                        mdma0: mdma@10800000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x10800000 0x1000>;
+                                interrupts = <0 33 0>;
+                                clocks = <&clock CLK_MDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <1>;
+                        };
+
+                        mdma1: mdma@11C10000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x11C10000 0x1000>;
+                                interrupts = <0 124 0>;
+                                clocks = <&clock CLK_MDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <1>;
+                                /*
+                                 * MDMA1 can support both secure and non-secure
+                                 * AXI transactions. When this is enabled in
+                                 * the kernel for boards that run in secure
+                                 * mode, we are getting imprecise external
+                                 * aborts causing the kernel to oops.
+                                 */
+                                status = "disabled";
+                        };
+                };
+
+                i2s0: i2s@03830000 {
+                        compatible = "samsung,exynos5420-i2s";
+                        reg = <0x03830000 0x100>;
+                        dmas = <&adma 0
+                                &adma 2
+                                &adma 1>;
+                        dma-names = "tx", "rx", "tx-sec";
+                        clocks = <&clock_audss EXYNOS_I2S_BUS>,
+                                <&clock_audss EXYNOS_I2S_BUS>,
+                                <&clock_audss EXYNOS_SCLK_I2S>;
+                        clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
+                        #clock-cells = <1>;
+                        clock-output-names = "i2s_cdclk0";
+                        #sound-dai-cells = <1>;
+                        samsung,idma-addr = <0x03000000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s0_bus>;
+                        status = "disabled";
                 };
-        };
-
-        pinctrl_1: pinctrl@13410000 {
-                compatible = "samsung,exynos5420-pinctrl";
-                reg = <0x13410000 0x1000>;
-                interrupts = <0 78 0>;
-        };
 
-        pinctrl_2: pinctrl@14000000 {
-                compatible = "samsung,exynos5420-pinctrl";
-                reg = <0x14000000 0x1000>;
-                interrupts = <0 46 0>;
-        };
-
-        pinctrl_3: pinctrl@14010000 {
-                compatible = "samsung,exynos5420-pinctrl";
-                reg = <0x14010000 0x1000>;
-                interrupts = <0 50 0>;
-        };
-
-        pinctrl_4: pinctrl@03860000 {
-                compatible = "samsung,exynos5420-pinctrl";
-                reg = <0x03860000 0x1000>;
-                interrupts = <0 47 0>;
-        };
-
-        amba {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&gic>;
-                ranges;
-
-                adma: adma@03880000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x03880000 0x1000>;
-                        interrupts = <0 110 0>;
-                        clocks = <&clock_audss EXYNOS_ADMA>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <6>;
-                        #dma-requests = <16>;
-                };
-
-                pdma0: pdma@121A0000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121A0000 0x1000>;
-                        interrupts = <0 34 0>;
-                        clocks = <&clock CLK_PDMA0>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                pdma1: pdma@121B0000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x121B0000 0x1000>;
-                        interrupts = <0 35 0>;
-                        clocks = <&clock CLK_PDMA1>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <32>;
-                };
-
-                mdma0: mdma@10800000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x10800000 0x1000>;
-                        interrupts = <0 33 0>;
-                        clocks = <&clock CLK_MDMA0>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <1>;
-                };
-
-                mdma1: mdma@11C10000 {
-                        compatible = "arm,pl330", "arm,primecell";
-                        reg = <0x11C10000 0x1000>;
-                        interrupts = <0 124 0>;
-                        clocks = <&clock CLK_MDMA1>;
-                        clock-names = "apb_pclk";
-                        #dma-cells = <1>;
-                        #dma-channels = <8>;
-                        #dma-requests = <1>;
-                        /*
-                         * MDMA1 can support both secure and non-secure
-                         * AXI transactions. When this is enabled in the kernel
-                         * for boards that run in secure mode, we are getting
-                         * imprecise external aborts causing the kernel to oops.
-                         */
+                i2s1: i2s@12D60000 {
+                        compatible = "samsung,exynos5420-i2s";
+                        reg = <0x12D60000 0x100>;
+                        dmas = <&pdma1 12
+                                &pdma1 11>;
+                        dma-names = "tx", "rx";
+                        clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
+                        clock-names = "iis", "i2s_opclk0";
+                        #clock-cells = <1>;
+                        clock-output-names = "i2s_cdclk1";
+                        #sound-dai-cells = <1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s1_bus>;
                         status = "disabled";
                 };
-        };
-
-        i2s0: i2s@03830000 {
-                compatible = "samsung,exynos5420-i2s";
-                reg = <0x03830000 0x100>;
-                dmas = <&adma 0
-                        &adma 2
-                        &adma 1>;
-                dma-names = "tx", "rx", "tx-sec";
-                clocks = <&clock_audss EXYNOS_I2S_BUS>,
-                        <&clock_audss EXYNOS_I2S_BUS>,
-                        <&clock_audss EXYNOS_SCLK_I2S>;
-                clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
-                #clock-cells = <1>;
-                clock-output-names = "i2s_cdclk0";
-                #sound-dai-cells = <1>;
-                samsung,idma-addr = <0x03000000>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2s0_bus>;
-                status = "disabled";
-        };
-
-        i2s1: i2s@12D60000 {
-                compatible = "samsung,exynos5420-i2s";
-                reg = <0x12D60000 0x100>;
-                dmas = <&pdma1 12
-                        &pdma1 11>;
-                dma-names = "tx", "rx";
-                clocks = <&clock CLK_I2S1>, <&clock CLK_SCLK_I2S1>;
-                clock-names = "iis", "i2s_opclk0";
-                #clock-cells = <1>;
-                clock-output-names = "i2s_cdclk1";
-                #sound-dai-cells = <1>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2s1_bus>;
-                status = "disabled";
-        };
-
-        i2s2: i2s@12D70000 {
-                compatible = "samsung,exynos5420-i2s";
-                reg = <0x12D70000 0x100>;
-                dmas = <&pdma0 12
-                        &pdma0 11>;
-                dma-names = "tx", "rx";
-                clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
-                clock-names = "iis", "i2s_opclk0";
-                #clock-cells = <1>;
-                clock-output-names = "i2s_cdclk2";
-                #sound-dai-cells = <1>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2s2_bus>;
-                status = "disabled";
-        };
-
-        spi_0: spi@12d20000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x12d20000 0x100>;
-                interrupts = <0 68 0>;
-                dmas = <&pdma0 5
-                        &pdma0 4>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi0_bus>;
-                clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
-                clock-names = "spi", "spi_busclk0";
-                status = "disabled";
-        };
-
-        spi_1: spi@12d30000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x12d30000 0x100>;
-                interrupts = <0 69 0>;
-                dmas = <&pdma1 5
-                        &pdma1 4>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi1_bus>;
-                clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
-                clock-names = "spi", "spi_busclk0";
-                status = "disabled";
-        };
-
-        spi_2: spi@12d40000 {
-                compatible = "samsung,exynos4210-spi";
-                reg = <0x12d40000 0x100>;
-                interrupts = <0 70 0>;
-                dmas = <&pdma0 7
-                        &pdma0 6>;
-                dma-names = "tx", "rx";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&spi2_bus>;
-                clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
-                clock-names = "spi", "spi_busclk0";
-                status = "disabled";
-        };
-
-        pwm: pwm@12dd0000 {
-                compatible = "samsung,exynos4210-pwm";
-                reg = <0x12dd0000 0x100>;
-                samsung,pwm-outputs = <0>, <1>, <2>, <3>;
-                #pwm-cells = <3>;
-                clocks = <&clock CLK_PWM>;
-                clock-names = "timers";
-        };
-
-        dp_phy: dp-video-phy {
-                compatible = "samsung,exynos5420-dp-video-phy";
-                samsung,pmu-syscon = <&pmu_system_controller>;
-                #phy-cells = <0>;
-        };
-
-        mipi_phy: mipi-video-phy {
-                compatible = "samsung,s5pv210-mipi-video-phy";
-                syscon = <&pmu_system_controller>;
-                #phy-cells = <1>;
-        };
-
-        dsi@14500000 {
-                compatible = "samsung,exynos5410-mipi-dsi";
-                reg = <0x14500000 0x10000>;
-                interrupts = <0 82 0>;
-                phys = <&mipi_phy 1>;
-                phy-names = "dsim";
-                clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
-                clock-names = "bus_clk", "pll_clk";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                status = "disabled";
-        };
-
-        adc: adc@12D10000 {
-                compatible = "samsung,exynos-adc-v2";
-                reg = <0x12D10000 0x100>;
-                interrupts = <0 106 0>;
-                clocks = <&clock CLK_TSADC>;
-                clock-names = "adc";
-                #io-channel-cells = <1>;
-                io-channel-ranges;
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                status = "disabled";
-        };
-
-        i2c_0: i2c@12C60000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C60000 0x100>;
-                interrupts = <0 56 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C0>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c0_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
-
-        i2c_1: i2c@12C70000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C70000 0x100>;
-                interrupts = <0 57 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C1>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c1_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
-
-        i2c_2: i2c@12C80000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C80000 0x100>;
-                interrupts = <0 58 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C2>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c2_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
-
-        i2c_3: i2c@12C90000 {
-                compatible = "samsung,s3c2440-i2c";
-                reg = <0x12C90000 0x100>;
-                interrupts = <0 59 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                clocks = <&clock CLK_I2C3>;
-                clock-names = "i2c";
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c3_bus>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                status = "disabled";
-        };
 
-        hsi2c_4: i2c@12CA0000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12CA0000 0x1000>;
-                interrupts = <0 60 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c4_hs_bus>;
-                clocks = <&clock CLK_USI0>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hsi2c_5: i2c@12CB0000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12CB0000 0x1000>;
-                interrupts = <0 61 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c5_hs_bus>;
-                clocks = <&clock CLK_USI1>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hsi2c_6: i2c@12CC0000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12CC0000 0x1000>;
-                interrupts = <0 62 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c6_hs_bus>;
-                clocks = <&clock CLK_USI2>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hsi2c_7: i2c@12CD0000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12CD0000 0x1000>;
-                interrupts = <0 63 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c7_hs_bus>;
-                clocks = <&clock CLK_USI3>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hsi2c_8: i2c@12E00000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12E00000 0x1000>;
-                interrupts = <0 87 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c8_hs_bus>;
-                clocks = <&clock CLK_USI4>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hsi2c_9: i2c@12E10000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12E10000 0x1000>;
-                interrupts = <0 88 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c9_hs_bus>;
-                clocks = <&clock CLK_USI5>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hsi2c_10: i2c@12E20000 {
-                compatible = "samsung,exynos5-hsi2c";
-                reg = <0x12E20000 0x1000>;
-                interrupts = <0 203 0>;
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-names = "default";
-                pinctrl-0 = <&i2c10_hs_bus>;
-                clocks = <&clock CLK_USI6>;
-                clock-names = "hsi2c";
-                status = "disabled";
-        };
-
-        hdmi: hdmi@14530000 {
-                compatible = "samsung,exynos5420-hdmi";
-                reg = <0x14530000 0x70000>;
-                interrupts = <0 95 0>;
-                clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
-                         <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
-                         <&clock CLK_MOUT_HDMI>;
-                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
-                        "sclk_hdmiphy", "mout_hdmi";
-                phy = <&hdmiphy>;
-                samsung,syscon-phandle = <&pmu_system_controller>;
-                status = "disabled";
-                power-domains = <&disp_pd>;
-        };
-
-        hdmiphy: hdmiphy@145D0000 {
-                reg = <0x145D0000 0x20>;
-        };
-
-        mixer: mixer@14450000 {
-                compatible = "samsung,exynos5420-mixer";
-                reg = <0x14450000 0x10000>;
-                interrupts = <0 94 0>;
-                clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
-                         <&clock CLK_SCLK_HDMI>;
-                clock-names = "mixer", "hdmi", "sclk_hdmi";
-                power-domains = <&disp_pd>;
-                iommus = <&sysmmu_tv>;
-        };
-
-        rotator: rotator@11C00000 {
-                compatible = "samsung,exynos5250-rotator";
-                reg = <0x11C00000 0x64>;
-                interrupts = <0 84 0>;
-                clocks = <&clock CLK_ROTATOR>;
-                clock-names = "rotator";
-                iommus = <&sysmmu_rotator>;
-        };
-
-        gsc_0: video-scaler@13e00000 {
-                compatible = "samsung,exynos5-gsc";
-                reg = <0x13e00000 0x1000>;
-                interrupts = <0 85 0>;
-                clocks = <&clock CLK_GSCL0>;
-                clock-names = "gscl";
-                power-domains = <&gsc_pd>;
-                iommus = <&sysmmu_gscl0>;
-        };
-
-        gsc_1: video-scaler@13e10000 {
-                compatible = "samsung,exynos5-gsc";
-                reg = <0x13e10000 0x1000>;
-                interrupts = <0 86 0>;
-                clocks = <&clock CLK_GSCL1>;
-                clock-names = "gscl";
-                power-domains = <&gsc_pd>;
-                iommus = <&sysmmu_gscl1>;
-        };
-
-        jpeg_0: jpeg@11F50000 {
-                compatible = "samsung,exynos5420-jpeg";
-                reg = <0x11F50000 0x1000>;
-                interrupts = <0 89 0>;
-                clock-names = "jpeg";
-                clocks = <&clock CLK_JPEG>;
-                iommus = <&sysmmu_jpeg0>;
-        };
-
-        jpeg_1: jpeg@11F60000 {
-                compatible = "samsung,exynos5420-jpeg";
-                reg = <0x11F60000 0x1000>;
-                interrupts = <0 168 0>;
-                clock-names = "jpeg";
-                clocks = <&clock CLK_JPEG2>;
-                iommus = <&sysmmu_jpeg1>;
-        };
-
-        pmu_system_controller: system-controller@10040000 {
-                compatible = "samsung,exynos5420-pmu", "syscon";
-                reg = <0x10040000 0x5000>;
-                clock-names = "clkout16";
-                clocks = <&clock CLK_FIN_PLL>;
-                #clock-cells = <1>;
-                interrupt-controller;
-                #interrupt-cells = <3>;
-                interrupt-parent = <&gic>;
-        };
-
-        sysreg_system_controller: syscon@10050000 {
-                compatible = "samsung,exynos5-sysreg", "syscon";
-                reg = <0x10050000 0x5000>;
-        };
-
-        tmu_cpu0: tmu@10060000 {
-                compatible = "samsung,exynos5420-tmu";
-                reg = <0x10060000 0x100>;
-                interrupts = <0 65 0>;
-                clocks = <&clock CLK_TMU>;
-                clock-names = "tmu_apbif";
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
-
-        tmu_cpu1: tmu@10064000 {
-                compatible = "samsung,exynos5420-tmu";
-                reg = <0x10064000 0x100>;
-                interrupts = <0 183 0>;
-                clocks = <&clock CLK_TMU>;
-                clock-names = "tmu_apbif";
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
-
-        tmu_cpu2: tmu@10068000 {
-                compatible = "samsung,exynos5420-tmu-ext-triminfo";
-                reg = <0x10068000 0x100>, <0x1006c000 0x4>;
-                interrupts = <0 184 0>;
-                clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
-                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
-
-        tmu_cpu3: tmu@1006c000 {
-                compatible = "samsung,exynos5420-tmu-ext-triminfo";
-                reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
-                interrupts = <0 185 0>;
-                clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
-                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
-
-        tmu_gpu: tmu@100a0000 {
-                compatible = "samsung,exynos5420-tmu-ext-triminfo";
-                reg = <0x100a0000 0x100>, <0x10068000 0x4>;
-                interrupts = <0 215 0>;
-                clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
-                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
-                #include "exynos4412-tmu-sensor-conf.dtsi"
-        };
-
-        thermal-zones {
-                cpu0_thermal: cpu0-thermal {
-                        thermal-sensors = <&tmu_cpu0>;
-                        #include "exynos5420-trip-points.dtsi"
-                };
-                cpu1_thermal: cpu1-thermal {
-                       thermal-sensors = <&tmu_cpu1>;
-                       #include "exynos5420-trip-points.dtsi"
-                };
-                cpu2_thermal: cpu2-thermal {
-                       thermal-sensors = <&tmu_cpu2>;
-                       #include "exynos5420-trip-points.dtsi"
-                };
-                cpu3_thermal: cpu3-thermal {
-                       thermal-sensors = <&tmu_cpu3>;
-                       #include "exynos5420-trip-points.dtsi"
-                };
-                gpu_thermal: gpu-thermal {
-                       thermal-sensors = <&tmu_gpu>;
-                       #include "exynos5420-trip-points.dtsi"
+                i2s2: i2s@12D70000 {
+                        compatible = "samsung,exynos5420-i2s";
+                        reg = <0x12D70000 0x100>;
+                        dmas = <&pdma0 12
+                                &pdma0 11>;
+                        dma-names = "tx", "rx";
+                        clocks = <&clock CLK_I2S2>, <&clock CLK_SCLK_I2S2>;
+                        clock-names = "iis", "i2s_opclk0";
+                        #clock-cells = <1>;
+                        clock-output-names = "i2s_cdclk2";
+                        #sound-dai-cells = <1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2s2_bus>;
+                        status = "disabled";
                 };
-        };
 
-        watchdog: watchdog@101D0000 {
-                compatible = "samsung,exynos5420-wdt";
-                reg = <0x101D0000 0x100>;
-                interrupts = <0 42 0>;
-                clocks = <&clock CLK_WDT>;
-                clock-names = "watchdog";
-                samsung,syscon-phandle = <&pmu_system_controller>;
-        };
-
-        sss: sss@10830000 {
-                compatible = "samsung,exynos4210-secss";
-                reg = <0x10830000 0x300>;
-                interrupts = <0 112 0>;
-                clocks = <&clock CLK_SSS>;
-                clock-names = "secss";
-        };
-
-        usbdrd3_0: usb3-0 {
-                compatible = "samsung,exynos5250-dwusb3";
-                clocks = <&clock CLK_USBD300>;
-                clock-names = "usbdrd30";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                usbdrd_dwc3_0: dwc3@12000000 {
-                        compatible = "snps,dwc3";
-                        reg = <0x12000000 0x10000>;
-                        interrupts = <0 72 0>;
-                        phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
-                        phy-names = "usb2-phy", "usb3-phy";
+                spi_0: spi@12d20000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x12d20000 0x100>;
+                        interrupts = <0 68 0>;
+                        dmas = <&pdma0 5
+                                &pdma0 4>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                        clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        status = "disabled";
                 };
-        };
-
-        usbdrd_phy0: phy@12100000 {
-                compatible = "samsung,exynos5420-usbdrd-phy";
-                reg = <0x12100000 0x100>;
-                clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
-                clock-names = "phy", "ref";
-                samsung,pmu-syscon = <&pmu_system_controller>;
-                #phy-cells = <1>;
-        };
 
-        usbdrd3_1: usb3-1 {
-                compatible = "samsung,exynos5250-dwusb3";
-                clocks = <&clock CLK_USBD301>;
-                clock-names = "usbdrd30";
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                usbdrd_dwc3_1: dwc3@12400000 {
-                        compatible = "snps,dwc3";
-                        reg = <0x12400000 0x10000>;
-                        interrupts = <0 73 0>;
-                        phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
-                        phy-names = "usb2-phy", "usb3-phy";
+                spi_1: spi@12d30000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x12d30000 0x100>;
+                        interrupts = <0 69 0>;
+                        dmas = <&pdma1 5
+                                &pdma1 4>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                        clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        status = "disabled";
                 };
-        };
-
-        usbdrd_phy1: phy@12500000 {
-                compatible = "samsung,exynos5420-usbdrd-phy";
-                reg = <0x12500000 0x100>;
-                clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
-                clock-names = "phy", "ref";
-                samsung,pmu-syscon = <&pmu_system_controller>;
-                #phy-cells = <1>;
-        };
-
-        usbhost2: usb@12110000 {
-                compatible = "samsung,exynos4210-ehci";
-                reg = <0x12110000 0x100>;
-                interrupts = <0 71 0>;
 
-                clocks = <&clock CLK_USBH20>;
-                clock-names = "usbhost";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        phys = <&usb2_phy 1>;
+                spi_2: spi@12d40000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x12d40000 0x100>;
+                        interrupts = <0 70 0>;
+                        dmas = <&pdma0 7
+                                &pdma0 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi2_bus>;
+                        clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
+                        clock-names = "spi", "spi_busclk0";
+                        status = "disabled";
                 };
-        };
 
-        usbhost1: usb@12120000 {
-                compatible = "samsung,exynos4210-ohci";
-                reg = <0x12120000 0x100>;
-                interrupts = <0 71 0>;
-
-                clocks = <&clock CLK_USBH20>;
-                clock-names = "usbhost";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                port@0 {
-                        reg = <0>;
-                        phys = <&usb2_phy 1>;
+                dp_phy: dp-video-phy {
+                        compatible = "samsung,exynos5420-dp-video-phy";
+                        samsung,pmu-syscon = <&pmu_system_controller>;
+                        #phy-cells = <0>;
                 };
-        };
-
-        usb2_phy: phy@12130000 {
-                compatible = "samsung,exynos5250-usb2-phy";
-                reg = <0x12130000 0x100>;
-                clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
-                clock-names = "phy", "ref";
-                #phy-cells = <1>;
-                samsung,sysreg-phandle = <&sysreg_system_controller>;
-                samsung,pmureg-phandle = <&pmu_system_controller>;
-        };
-
-        sysmmu_g2dr: sysmmu@0x10A60000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x10A60000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <24 5>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_g2dw: sysmmu@0x10A70000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x10A70000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <22 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_tv: sysmmu@0x14650000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x14650000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <7 4>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
-                power-domains = <&disp_pd>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_gscl0: sysmmu@0x13E80000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13E80000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <2 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
-                power-domains = <&gsc_pd>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_gscl1: sysmmu@0x13E90000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x13E90000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <2 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
-                power-domains = <&gsc_pd>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_scaler0r: sysmmu@0x12880000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12880000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <22 4>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_scaler1r: sysmmu@0x12890000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x12890000 0x1000>;
-                interrupts = <0 186 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
-                #iommu-cells = <0>;
-        };
 
-        sysmmu_scaler2r: sysmmu@0x128A0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x128A0000 0x1000>;
-                interrupts = <0 188 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_scaler0w: sysmmu@0x128C0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x128C0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <27 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_scaler1w: sysmmu@0x128D0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x128D0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <22 6>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_scaler2w: sysmmu@0x128E0000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x128E0000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <19 6>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_rotator: sysmmu@0x11D40000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11D40000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_jpeg0: sysmmu@0x11F10000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11F10000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <4 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_jpeg1: sysmmu@0x11F20000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11F20000 0x1000>;
-                interrupts = <0 169 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_mfc_l: sysmmu@0x11200000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11200000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <6 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
-                power-domains = <&mfc_pd>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_mfc_r: sysmmu@0x11210000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x11210000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <8 5>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
-                power-domains = <&mfc_pd>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_fimd1_0: sysmmu@0x14640000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x14640000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <3 2>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
-                power-domains = <&disp_pd>;
-                #iommu-cells = <0>;
-        };
-
-        sysmmu_fimd1_1: sysmmu@0x14680000 {
-                compatible = "samsung,exynos-sysmmu";
-                reg = <0x14680000 0x1000>;
-                interrupt-parent = <&combiner>;
-                interrupts = <3 0>;
-                clock-names = "sysmmu", "master";
-                clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
-                power-domains = <&disp_pd>;
-                #iommu-cells = <0>;
-        };
-
-        bus_wcore: bus_wcore {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_wcore_opp_table>;
-                status = "disabled";
-        };
-
-        bus_noc: bus_noc {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK100_NOC>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_noc_opp_table>;
-                status = "disabled";
-        };
-
-        bus_fsys_apb: bus_fsys_apb {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_fsys_apb_opp_table>;
-                status = "disabled";
-        };
-
-        bus_fsys: bus_fsys {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_fsys_apb_opp_table>;
-                status = "disabled";
-        };
-
-        bus_fsys2: bus_fsys2 {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_fsys2_opp_table>;
-                status = "disabled";
-        };
-
-        bus_mfc: bus_mfc {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK333>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_mfc_opp_table>;
-                status = "disabled";
-        };
-
-        bus_gen: bus_gen {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK266>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_gen_opp_table>;
-                status = "disabled";
-        };
-
-        bus_peri: bus_peri {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK66>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_peri_opp_table>;
-                status = "disabled";
-        };
-
-        bus_g2d: bus_g2d {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK333_G2D>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_g2d_opp_table>;
-                status = "disabled";
-        };
-
-        bus_g2d_acp: bus_g2d_acp {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK266_G2D>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_g2d_acp_opp_table>;
-                status = "disabled";
-        };
-
-        bus_jpeg: bus_jpeg {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_jpeg_opp_table>;
-                status = "disabled";
-        };
-
-        bus_jpeg_apb: bus_jpeg_apb {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK166>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_jpeg_apb_opp_table>;
-                status = "disabled";
-        };
-
-        bus_disp1_fimd: bus_disp1_fimd {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_disp1_fimd_opp_table>;
-                status = "disabled";
-        };
-
-        bus_disp1: bus_disp1 {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_disp1_opp_table>;
-                status = "disabled";
-        };
-
-        bus_gscl_scaler: bus_gscl_scaler {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_gscl_opp_table>;
-                status = "disabled";
-        };
-
-        bus_mscl: bus_mscl {
-                compatible = "samsung,exynos-bus";
-                clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
-                clock-names = "bus";
-                operating-points-v2 = <&bus_mscl_opp_table>;
-                status = "disabled";
-        };
-
-        bus_wcore_opp_table: opp_table2 {
-                compatible = "operating-points-v2";
-
-                opp00 {
-                        opp-hz = /bits/ 64 <84000000>;
-                        opp-microvolt = <925000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <111000000>;
-                        opp-microvolt = <950000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <222000000>;
-                        opp-microvolt = <950000>;
+                mipi_phy: mipi-video-phy {
+                        compatible = "samsung,s5pv210-mipi-video-phy";
+                        syscon = <&pmu_system_controller>;
+                        #phy-cells = <1>;
                 };
-                opp03 {
-                        opp-hz = /bits/ 64 <333000000>;
-                        opp-microvolt = <950000>;
-                };
-                opp04 {
-                        opp-hz = /bits/ 64 <400000000>;
-                        opp-microvolt = <987500>;
-                };
-        };
 
-        bus_noc_opp_table: opp_table3 {
-                compatible = "operating-points-v2";
-
-                opp00 {
-                        opp-hz = /bits/ 64 <67000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <75000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <86000000>;
-                };
-                opp03 {
-                        opp-hz = /bits/ 64 <100000000>;
+                dsi@14500000 {
+                        compatible = "samsung,exynos5410-mipi-dsi";
+                        reg = <0x14500000 0x10000>;
+                        interrupts = <0 82 0>;
+                        phys = <&mipi_phy 1>;
+                        phy-names = "dsim";
+                        clocks = <&clock CLK_DSIM1>, <&clock CLK_SCLK_MIPI1>;
+                        clock-names = "bus_clk", "pll_clk";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
                 };
-        };
-
-        bus_fsys_apb_opp_table: opp_table4 {
-                compatible = "operating-points-v2";
-                opp-shared;
 
-                opp00 {
-                        opp-hz = /bits/ 64 <100000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <200000000>;
+                adc: adc@12D10000 {
+                        compatible = "samsung,exynos-adc-v2";
+                        reg = <0x12D10000 0x100>;
+                        interrupts = <0 106 0>;
+                        clocks = <&clock CLK_TSADC>;
+                        clock-names = "adc";
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        status = "disabled";
                 };
-        };
-
-        bus_fsys2_opp_table: opp_table5 {
-                compatible = "operating-points-v2";
 
-                opp00 {
-                        opp-hz = /bits/ 64 <75000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <100000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <150000000>;
+                hsi2c_8: i2c@12E00000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12E00000 0x1000>;
+                        interrupts = <0 87 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c8_hs_bus>;
+                        clocks = <&clock CLK_USI4>;
+                        clock-names = "hsi2c";
+                        status = "disabled";
                 };
-        };
 
-        bus_mfc_opp_table: opp_table6 {
-                compatible = "operating-points-v2";
-
-                opp00 {
-                        opp-hz = /bits/ 64 <96000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <111000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <167000000>;
-                };
-                opp03 {
-                        opp-hz = /bits/ 64 <222000000>;
-                };
-                opp04 {
-                        opp-hz = /bits/ 64 <333000000>;
+                hsi2c_9: i2c@12E10000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12E10000 0x1000>;
+                        interrupts = <0 88 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c9_hs_bus>;
+                        clocks = <&clock CLK_USI5>;
+                        clock-names = "hsi2c";
+                        status = "disabled";
                 };
-        };
 
-        bus_gen_opp_table: opp_table7 {
-                compatible = "operating-points-v2";
-
-                opp00 {
-                        opp-hz = /bits/ 64 <89000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <133000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <178000000>;
-                };
-                opp03 {
-                        opp-hz = /bits/ 64 <267000000>;
+                hsi2c_10: i2c@12E20000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12E20000 0x1000>;
+                        interrupts = <0 203 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c10_hs_bus>;
+                        clocks = <&clock CLK_USI6>;
+                        clock-names = "hsi2c";
+                        status = "disabled";
                 };
-        };
-
-        bus_peri_opp_table: opp_table8 {
-                compatible = "operating-points-v2";
 
-                opp00 {
-                        opp-hz = /bits/ 64 <67000000>;
+                hdmi: hdmi@14530000 {
+                        compatible = "samsung,exynos5420-hdmi";
+                        reg = <0x14530000 0x70000>;
+                        interrupts = <0 95 0>;
+                        clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
+                                 <&clock CLK_DOUT_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
+                                 <&clock CLK_MOUT_HDMI>;
+                        clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
+                                "sclk_hdmiphy", "mout_hdmi";
+                        phy = <&hdmiphy>;
+                        samsung,syscon-phandle = <&pmu_system_controller>;
+                        status = "disabled";
+                        power-domains = <&disp_pd>;
+                };
+
+                hdmiphy: hdmiphy@145D0000 {
+                        reg = <0x145D0000 0x20>;
+                };
+
+                mixer: mixer@14450000 {
+                        compatible = "samsung,exynos5420-mixer";
+                        reg = <0x14450000 0x10000>;
+                        interrupts = <0 94 0>;
+                        clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>,
+                                 <&clock CLK_SCLK_HDMI>;
+                        clock-names = "mixer", "hdmi", "sclk_hdmi";
+                        power-domains = <&disp_pd>;
+                        iommus = <&sysmmu_tv>;
+                };
+
+                rotator: rotator@11C00000 {
+                        compatible = "samsung,exynos5250-rotator";
+                        reg = <0x11C00000 0x64>;
+                        interrupts = <0 84 0>;
+                        clocks = <&clock CLK_ROTATOR>;
+                        clock-names = "rotator";
+                        iommus = <&sysmmu_rotator>;
+                };
+
+                gsc_0: video-scaler@13e00000 {
+                        compatible = "samsung,exynos5-gsc";
+                        reg = <0x13e00000 0x1000>;
+                        interrupts = <0 85 0>;
+                        clocks = <&clock CLK_GSCL0>;
+                        clock-names = "gscl";
+                        power-domains = <&gsc_pd>;
+                        iommus = <&sysmmu_gscl0>;
+                };
+
+                gsc_1: video-scaler@13e10000 {
+                        compatible = "samsung,exynos5-gsc";
+                        reg = <0x13e10000 0x1000>;
+                        interrupts = <0 86 0>;
+                        clocks = <&clock CLK_GSCL1>;
+                        clock-names = "gscl";
+                        power-domains = <&gsc_pd>;
+                        iommus = <&sysmmu_gscl1>;
+                };
+
+                jpeg_0: jpeg@11F50000 {
+                        compatible = "samsung,exynos5420-jpeg";
+                        reg = <0x11F50000 0x1000>;
+                        interrupts = <0 89 0>;
+                        clock-names = "jpeg";
+                        clocks = <&clock CLK_JPEG>;
+                        iommus = <&sysmmu_jpeg0>;
+                };
+
+                jpeg_1: jpeg@11F60000 {
+                        compatible = "samsung,exynos5420-jpeg";
+                        reg = <0x11F60000 0x1000>;
+                        interrupts = <0 168 0>;
+                        clock-names = "jpeg";
+                        clocks = <&clock CLK_JPEG2>;
+                        iommus = <&sysmmu_jpeg1>;
+                };
+
+                pmu_system_controller: system-controller@10040000 {
+                        compatible = "samsung,exynos5420-pmu", "syscon";
+                        reg = <0x10040000 0x5000>;
+                        clock-names = "clkout16";
+                        clocks = <&clock CLK_FIN_PLL>;
+                        #clock-cells = <1>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        interrupt-parent = <&gic>;
                 };
-        };
-
-        bus_g2d_opp_table: opp_table9 {
-                compatible = "operating-points-v2";
 
-                opp00 {
-                        opp-hz = /bits/ 64 <84000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <167000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <222000000>;
-                };
-                opp03 {
-                        opp-hz = /bits/ 64 <300000000>;
-                };
-                opp04 {
-                        opp-hz = /bits/ 64 <333000000>;
+                tmu_cpu0: tmu@10060000 {
+                        compatible = "samsung,exynos5420-tmu";
+                        reg = <0x10060000 0x100>;
+                        interrupts = <0 65 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
+
+                tmu_cpu1: tmu@10064000 {
+                        compatible = "samsung,exynos5420-tmu";
+                        reg = <0x10064000 0x100>;
+                        interrupts = <0 183 0>;
+                        clocks = <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
+
+                tmu_cpu2: tmu@10068000 {
+                        compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                        reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+                        interrupts = <0 184 0>;
+                        clocks = <&clock CLK_TMU>, <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
+
+                tmu_cpu3: tmu@1006c000 {
+                        compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                        reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+                        interrupts = <0 185 0>;
+                        clocks = <&clock CLK_TMU>, <&clock CLK_TMU_GPU>;
+                        clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
+
+                tmu_gpu: tmu@100a0000 {
+                        compatible = "samsung,exynos5420-tmu-ext-triminfo";
+                        reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+                        interrupts = <0 215 0>;
+                        clocks = <&clock CLK_TMU_GPU>, <&clock CLK_TMU>;
+                        clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+                        #include "exynos4412-tmu-sensor-conf.dtsi"
+                };
+
+                sysmmu_g2dr: sysmmu@0x10A60000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x10A60000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <24 5>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_g2dw: sysmmu@0x10A70000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x10A70000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <22 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_tv: sysmmu@0x14650000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x14650000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <7 4>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MIXER>, <&clock CLK_MIXER>;
+                        power-domains = <&disp_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_gscl0: sysmmu@0x13E80000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13E80000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_GSCL0>, <&clock CLK_GSCL0>;
+                        power-domains = <&gsc_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_gscl1: sysmmu@0x13E90000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x13E90000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <2 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_GSCL1>, <&clock CLK_GSCL1>;
+                        power-domains = <&gsc_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_scaler0r: sysmmu@0x12880000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12880000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <22 4>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_scaler1r: sysmmu@0x12890000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x12890000 0x1000>;
+                        interrupts = <0 186 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_scaler2r: sysmmu@0x128A0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x128A0000 0x1000>;
+                        interrupts = <0 188 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_scaler0w: sysmmu@0x128C0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x128C0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <27 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MSCL0>, <&clock CLK_MSCL0>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_scaler1w: sysmmu@0x128D0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x128D0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <22 6>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MSCL1>, <&clock CLK_MSCL1>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_scaler2w: sysmmu@0x128E0000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x128E0000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <19 6>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_rotator: sysmmu@0x11D40000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11D40000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_jpeg0: sysmmu@0x11F10000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11F10000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <4 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_jpeg1: sysmmu@0x11F20000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11F20000 0x1000>;
+                        interrupts = <0 169 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_mfc_l: sysmmu@0x11200000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11200000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <6 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
+                        power-domains = <&mfc_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_mfc_r: sysmmu@0x11210000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x11210000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <8 5>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
+                        power-domains = <&mfc_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_fimd1_0: sysmmu@0x14640000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x14640000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <3 2>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMD1M0>, <&clock CLK_FIMD1>;
+                        power-domains = <&disp_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                sysmmu_fimd1_1: sysmmu@0x14680000 {
+                        compatible = "samsung,exynos-sysmmu";
+                        reg = <0x14680000 0x1000>;
+                        interrupt-parent = <&combiner>;
+                        interrupts = <3 0>;
+                        clock-names = "sysmmu", "master";
+                        clocks = <&clock CLK_SMMU_FIMD1M1>, <&clock CLK_FIMD1>;
+                        power-domains = <&disp_pd>;
+                        #iommu-cells = <0>;
+                };
+
+                bus_wcore: bus_wcore {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK400_WCORE>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_wcore_opp_table>;
+                        status = "disabled";
                 };
-        };
-
-        bus_g2d_acp_opp_table: opp_table10 {
-                compatible = "operating-points-v2";
 
-                opp00 {
-                        opp-hz = /bits/ 64 <67000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <133000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <178000000>;
-                };
-                opp03 {
-                        opp-hz = /bits/ 64 <267000000>;
+                bus_noc: bus_noc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK100_NOC>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_noc_opp_table>;
+                        status = "disabled";
                 };
-        };
-
-        bus_jpeg_opp_table: opp_table11 {
-                compatible = "operating-points-v2";
 
-                opp00 {
-                        opp-hz = /bits/ 64 <75000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <150000000>;
-                };
-                opp02 {
-                        opp-hz = /bits/ 64 <200000000>;
-                };
-                opp03 {
-                        opp-hz = /bits/ 64 <300000000>;
+                bus_fsys_apb: bus_fsys_apb {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_PCLK200_FSYS>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_fsys_apb_opp_table>;
+                        status = "disabled";
                 };
-        };
-
-        bus_jpeg_apb_opp_table: opp_table12 {
-                compatible = "operating-points-v2";
 
-                opp00 {
-                        opp-hz = /bits/ 64 <84000000>;
-                };
-                opp01 {
-                        opp-hz = /bits/ 64 <111000000>;
+                bus_fsys: bus_fsys {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK200_FSYS>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_fsys_apb_opp_table>;
+                        status = "disabled";
                 };
-                opp02 {
-                        opp-hz = /bits/ 64 <134000000>;
+
+                bus_fsys2: bus_fsys2 {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK200_FSYS2>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_fsys2_opp_table>;
+                        status = "disabled";
                 };
-                opp03 {
-                        opp-hz = /bits/ 64 <167000000>;
+
+                bus_mfc: bus_mfc {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK333>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_mfc_opp_table>;
+                        status = "disabled";
                 };
-        };
 
-        bus_disp1_fimd_opp_table: opp_table13 {
-                compatible = "operating-points-v2";
+                bus_gen: bus_gen {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK266>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_gen_opp_table>;
+                        status = "disabled";
+                };
 
-                opp00 {
-                        opp-hz = /bits/ 64 <120000000>;
+                bus_peri: bus_peri {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK66>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_peri_opp_table>;
+                        status = "disabled";
                 };
-                opp01 {
-                        opp-hz = /bits/ 64 <200000000>;
+
+                bus_g2d: bus_g2d {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK333_G2D>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_g2d_opp_table>;
+                        status = "disabled";
                 };
-        };
 
-        bus_disp1_opp_table: opp_table14 {
-                compatible = "operating-points-v2";
+                bus_g2d_acp: bus_g2d_acp {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK266_G2D>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_g2d_acp_opp_table>;
+                        status = "disabled";
+                };
 
-                opp00 {
-                        opp-hz = /bits/ 64 <120000000>;
+                bus_jpeg: bus_jpeg {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK300_JPEG>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_jpeg_opp_table>;
+                        status = "disabled";
                 };
-                opp01 {
-                        opp-hz = /bits/ 64 <200000000>;
+
+                bus_jpeg_apb: bus_jpeg_apb {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK166>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_jpeg_apb_opp_table>;
+                        status = "disabled";
                 };
-                opp02 {
-                        opp-hz = /bits/ 64 <300000000>;
+
+                bus_disp1_fimd: bus_disp1_fimd {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK300_DISP1>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_disp1_fimd_opp_table>;
+                        status = "disabled";
                 };
-        };
 
-        bus_gscl_opp_table: opp_table15 {
-                compatible = "operating-points-v2";
+                bus_disp1: bus_disp1 {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK400_DISP1>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_disp1_opp_table>;
+                        status = "disabled";
+                };
 
-                opp00 {
-                        opp-hz = /bits/ 64 <150000000>;
+                bus_gscl_scaler: bus_gscl_scaler {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK300_GSCL>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_gscl_opp_table>;
+                        status = "disabled";
                 };
-                opp01 {
-                        opp-hz = /bits/ 64 <200000000>;
+
+                bus_mscl: bus_mscl {
+                        compatible = "samsung,exynos-bus";
+                        clocks = <&clock CLK_DOUT_ACLK400_MSCL>;
+                        clock-names = "bus";
+                        operating-points-v2 = <&bus_mscl_opp_table>;
+                        status = "disabled";
                 };
-                opp02 {
-                        opp-hz = /bits/ 64 <300000000>;
+
+                bus_wcore_opp_table: opp_table2 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <84000000>;
+                                opp-microvolt = <925000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <111000000>;
+                                opp-microvolt = <950000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <222000000>;
+                                opp-microvolt = <950000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <333000000>;
+                                opp-microvolt = <950000>;
+                        };
+                        opp04 {
+                                opp-hz = /bits/ 64 <400000000>;
+                                opp-microvolt = <987500>;
+                        };
+                };
+
+                bus_noc_opp_table: opp_table3 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <67000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <75000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <86000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                };
+
+                bus_fsys_apb_opp_table: opp_table4 {
+                        compatible = "operating-points-v2";
+                        opp-shared;
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                };
+
+                bus_fsys2_opp_table: opp_table5 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <75000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <100000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <150000000>;
+                        };
+                };
+
+                bus_mfc_opp_table: opp_table6 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <96000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <111000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <167000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <222000000>;
+                        };
+                        opp04 {
+                                opp-hz = /bits/ 64 <333000000>;
+                        };
+                };
+
+                bus_gen_opp_table: opp_table7 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <89000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <133000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <178000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <267000000>;
+                        };
+                };
+
+                bus_peri_opp_table: opp_table8 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <67000000>;
+                        };
+                };
+
+                bus_g2d_opp_table: opp_table9 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <84000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <167000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <222000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <300000000>;
+                        };
+                        opp04 {
+                                opp-hz = /bits/ 64 <333000000>;
+                        };
+                };
+
+                bus_g2d_acp_opp_table: opp_table10 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <67000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <133000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <178000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <267000000>;
+                        };
+                };
+
+                bus_jpeg_opp_table: opp_table11 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <75000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <150000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <300000000>;
+                        };
+                };
+
+                bus_jpeg_apb_opp_table: opp_table12 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <84000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <111000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <134000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <167000000>;
+                        };
+                };
+
+                bus_disp1_fimd_opp_table: opp_table13 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <120000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                };
+
+                bus_disp1_opp_table: opp_table14 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <120000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <300000000>;
+                        };
+                };
+
+                bus_gscl_opp_table: opp_table15 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <150000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <200000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <300000000>;
+                        };
+                };
+
+                bus_mscl_opp_table: opp_table16 {
+                        compatible = "operating-points-v2";
+
+                        opp00 {
+                                opp-hz = /bits/ 64 <84000000>;
+                        };
+                        opp01 {
+                                opp-hz = /bits/ 64 <167000000>;
+                        };
+                        opp02 {
+                                opp-hz = /bits/ 64 <222000000>;
+                        };
+                        opp03 {
+                                opp-hz = /bits/ 64 <333000000>;
+                        };
+                        opp04 {
+                                opp-hz = /bits/ 64 <400000000>;
+                        };
                 };
         };
 
-        bus_mscl_opp_table: opp_table16 {
-                compatible = "operating-points-v2";
-
-                opp00 {
-                        opp-hz = /bits/ 64 <84000000>;
+        thermal-zones {
+                cpu0_thermal: cpu0-thermal {
+                        thermal-sensors = <&tmu_cpu0>;
+                        #include "exynos5420-trip-points.dtsi"
                 };
-                opp01 {
-                        opp-hz = /bits/ 64 <167000000>;
+                cpu1_thermal: cpu1-thermal {
+                       thermal-sensors = <&tmu_cpu1>;
+                       #include "exynos5420-trip-points.dtsi"
                 };
-                opp02 {
-                        opp-hz = /bits/ 64 <222000000>;
+                cpu2_thermal: cpu2-thermal {
+                       thermal-sensors = <&tmu_cpu2>;
+                       #include "exynos5420-trip-points.dtsi"
                 };
-                opp03 {
-                        opp-hz = /bits/ 64 <333000000>;
+                cpu3_thermal: cpu3-thermal {
+                       thermal-sensors = <&tmu_cpu3>;
+                       #include "exynos5420-trip-points.dtsi"
                 };
-                opp04 {
-                        opp-hz = /bits/ 64 <400000000>;
+                gpu_thermal: gpu-thermal {
+                       thermal-sensors = <&tmu_gpu>;
+                       #include "exynos5420-trip-points.dtsi"
                 };
         };
 };
@@ -1614,6 +1330,72 @@
         iommu-names = "m0", "m1";
 };
 
+&i2c_0 {
+        clocks = <&clock CLK_I2C0>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_bus>;
+};
+
+&i2c_1 {
+        clocks = <&clock CLK_I2C1>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_bus>;
+};
+
+&i2c_2 {
+        clocks = <&clock CLK_I2C2>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c2_bus>;
+};
+
+&i2c_3 {
+        clocks = <&clock CLK_I2C3>;
+        clock-names = "i2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_bus>;
+};
+
+&hsi2c_4 {
+        clocks = <&clock CLK_USI0>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c4_hs_bus>;
+};
+
+&hsi2c_5 {
+        clocks = <&clock CLK_USI1>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c5_hs_bus>;
+};
+
+&hsi2c_6 {
+        clocks = <&clock CLK_USI2>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c6_hs_bus>;
+};
+
+&hsi2c_7 {
+        clocks = <&clock CLK_USI3>;
+        clock-names = "hsi2c";
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c7_hs_bus>;
+};
+
+&mct {
+        clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
+        clock-names = "fin_pll", "mct";
+};
+
+&pwm {
+        clocks = <&clock CLK_PWM>;
+        clock-names = "timers";
+};
+
 &rtc {
         clocks = <&clock CLK_RTC>;
         clock-names = "rtc";
@@ -1641,4 +1423,58 @@
         clock-names = "uart", "clk_uart_baud0";
 };
 
+&sss {
+        clocks = <&clock CLK_SSS>;
+        clock-names = "secss";
+};
+
+&usbdrd3_0 {
+        clocks = <&clock CLK_USBD300>;
+        clock-names = "usbdrd30";
+};
+
+&usbdrd_phy0 {
+        clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+        clock-names = "phy", "ref";
+        samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbdrd3_1 {
+        clocks = <&clock CLK_USBD301>;
+        clock-names = "usbdrd30";
+};
+
+&usbdrd_dwc3_1 {
+        interrupts = <GIC_SPI 73 0>;
+};
+
+&usbdrd_phy1 {
+        clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+        clock-names = "phy", "ref";
+        samsung,pmu-syscon = <&pmu_system_controller>;
+};
+
+&usbhost1 {
+        clocks = <&clock CLK_USBH20>;
+        clock-names = "usbhost";
+};
+
+&usbhost2 {
+        clocks = <&clock CLK_USBH20>;
+        clock-names = "usbhost";
+};
+
+&usb2_phy {
+        clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+        clock-names = "phy", "ref";
+        samsung,sysreg-phandle = <&sysreg_system_controller>;
+        samsung,pmureg-phandle = <&pmu_system_controller>;
+};
+
+&watchdog {
+        clocks = <&clock CLK_WDT>;
+        clock-names = "watchdog";
+        samsung,syscon-phandle = <&pmu_system_controller>;
+};
+
 #include "exynos5420-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi b/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi
deleted file mode 100644
index 3e4c4ad96d63..000000000000
--- a/arch/arm/boot/dts/exynos5422-cpu-thermal.dtsi
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Device tree sources for Exynos5422 thermal zone
- *
- * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
- *                      Anand Moon <linux.amoon@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
-        thermal-zones {
-                cpu0_thermal: cpu0-thermal {
-                        thermal-sensors = <&tmu_cpu0 0>;
-                        polling-delay-passive = <250>;
-                        polling-delay = <0>;
-                        trips {
-                                cpu_alert0: cpu-alert-0 {
-                                        temperature = <50000>; /* millicelsius */
-                                        hysteresis = <5000>; /* millicelsius */
-                                        type = "active";
-                                };
-                                cpu_alert1: cpu-alert-1 {
-                                        temperature = <60000>; /* millicelsius */
-                                        hysteresis = <5000>; /* millicelsius */
-                                        type = "active";
-                                };
-                                cpu_alert2: cpu-alert-2 {
-                                        temperature = <70000>; /* millicelsius */
-                                        hysteresis = <5000>; /* millicelsius */
-                                        type = "active";
-                                };
-                                cpu_crit0: cpu-crit-0 {
-                                        temperature = <120000>; /* millicelsius */
-                                        hysteresis = <0>; /* millicelsius */
-                                        type = "critical";
-                                };
-                                /*
-                                 * Exyunos542x support only 4 trip-points
-                                 * so for these polling mode is required.
-                                 * Start polling at temperature level of last
-                                 * interrupt-driven trip: cpu_alert2
-                                 */
-                                cpu_alert3: cpu-alert-3 {
-                                        temperature = <70000>; /* millicelsius */
-                                        hysteresis = <10000>; /* millicelsius */
-                                        type = "passive";
-                                };
-                                cpu_alert4: cpu-alert-4 {
-                                        temperature = <85000>; /* millicelsius */
-                                        hysteresis = <10000>; /* millicelsius */
-                                        type = "passive";
-                                };
-
-                        };
-                        cooling-maps {
-                                map0 {
-                                     trip = <&cpu_alert0>;
-                                     cooling-device = <&fan0 0 1>;
-                                };
-                                map1 {
-                                     trip = <&cpu_alert1>;
-                                     cooling-device = <&fan0 1 2>;
-                                };
-                                map2 {
-                                     trip = <&cpu_alert2>;
-                                     cooling-device = <&fan0 2 3>;
-                                };
-                                /*
-                                 * When reaching cpu_alert3, reduce CPU
-                                 * by 2 steps. On Exynos5422/5800 that would
-                                 * be: 1500 MHz and 1100 MHz.
-                                 */
-                                map3 {
-                                     trip = <&cpu_alert3>;
-                                     cooling-device = <&cpu0 0 2>;
-                                };
-                                map4 {
-                                     trip = <&cpu_alert3>;
-                                     cooling-device = <&cpu4 0 2>;
-                                };
-
-                                /*
-                                 * When reaching cpu_alert4, reduce CPU
-                                 * further, down to 600 MHz (11 steps for big,
-                                 * 7 steps for LITTLE).
-                                 */
-                                map5 {
-                                     trip = <&cpu_alert4>;
-                                     cooling-device = <&cpu0 3 7>;
-                                };
-                                map6 {
-                                     trip = <&cpu_alert4>;
-                                     cooling-device = <&cpu4 3 11>;
-                                };
-                        };
-                };
-        };
-};
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
index 7c2335f18bfc..d56253049ccb 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
@@ -1,9 +1,11 @@
 /*
  * Hardkernel Odroid XU3 board device tree source
  *
- * Copyright (c) 2014 Collabora Ltd.
  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
+ * Copyright (c) 2014 Collabora Ltd.
+ * Copyright (c) 2015 Lukasz Majewski <l.majewski@samsung.com>
+ *                    Anand Moon <linux.amoon@gmail.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -16,7 +18,6 @@
 #include <dt-bindings/sound/samsung-i2s.h>
 #include "exynos5800.dtsi"
 #include "exynos5422-cpus.dtsi"
-#include "exynos5422-cpu-thermal.dtsi"
 #include "exynos-mfc-reserved-memory.dtsi"
 
 / {
@@ -55,6 +56,94 @@
                 #cooling-cells = <2>;
                 cooling-levels = <0 130 170 230>;
         };
+
+        thermal-zones {
+                cpu0_thermal: cpu0-thermal {
+                        thermal-sensors = <&tmu_cpu0 0>;
+                        polling-delay-passive = <250>;
+                        polling-delay = <0>;
+                        trips {
+                                cpu_alert0: cpu-alert-0 {
+                                        temperature = <50000>; /* millicelsius */
+                                        hysteresis = <5000>; /* millicelsius */
+                                        type = "active";
+                                };
+                                cpu_alert1: cpu-alert-1 {
+                                        temperature = <60000>; /* millicelsius */
+                                        hysteresis = <5000>; /* millicelsius */
+                                        type = "active";
+                                };
+                                cpu_alert2: cpu-alert-2 {
+                                        temperature = <70000>; /* millicelsius */
+                                        hysteresis = <5000>; /* millicelsius */
+                                        type = "active";
+                                };
+                                cpu_crit0: cpu-crit-0 {
+                                        temperature = <120000>; /* millicelsius */
+                                        hysteresis = <0>; /* millicelsius */
+                                        type = "critical";
+                                };
+                                /*
+                                 * Exynos542x supports only 4 trip-points
+                                 * so for these polling mode is required.
+                                 * Start polling at temperature level of last
+                                 * interrupt-driven trip: cpu_alert2
+                                 */
+                                cpu_alert3: cpu-alert-3 {
+                                        temperature = <70000>; /* millicelsius */
+                                        hysteresis = <10000>; /* millicelsius */
+                                        type = "passive";
+                                };
+                                cpu_alert4: cpu-alert-4 {
+                                        temperature = <85000>; /* millicelsius */
+                                        hysteresis = <10000>; /* millicelsius */
+                                        type = "passive";
+                                };
+
+                        };
+                        cooling-maps {
+                                map0 {
+                                        trip = <&cpu_alert0>;
+                                        cooling-device = <&fan0 0 1>;
+                                };
+                                map1 {
+                                        trip = <&cpu_alert1>;
+                                        cooling-device = <&fan0 1 2>;
+                                };
+                                map2 {
+                                        trip = <&cpu_alert2>;
+                                        cooling-device = <&fan0 2 3>;
+                                };
+                                /*
+                                 * When reaching cpu_alert3, reduce CPU
+                                 * by 2 steps. On Exynos5422/5800 that would
+                                 * be: 1600 MHz and 1100 MHz.
+                                 */
+                                map3 {
+                                        trip = <&cpu_alert3>;
+                                        cooling-device = <&cpu0 0 2>;
+                                };
+                                map4 {
+                                        trip = <&cpu_alert3>;
+                                        cooling-device = <&cpu4 0 2>;
+                                };
+
+                                /*
+                                 * When reaching cpu_alert4, reduce CPU
+                                 * further, down to 600 MHz (11 steps for big,
+                                 * 7 steps for LITTLE).
+                                 */
+                                map5 {
+                                        trip = <&cpu_alert4>;
+                                        cooling-device = <&cpu0 3 7>;
+                                };
+                                map6 {
+                                        trip = <&cpu_alert4>;
+                                        cooling-device = <&cpu4 3 11>;
+                                };
+                        };
+                };
+        };
 };
 
 &bus_wcore {
@@ -406,10 +495,6 @@
         };
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         mmc-pwrseq = <&emmc_pwrseq>;
@@ -487,27 +572,22 @@
 
 &tmu_cpu0 {
         vtmu-supply = <&ldo7_reg>;
-        status = "okay";
 };
 
 &tmu_cpu1 {
         vtmu-supply = <&ldo7_reg>;
-        status = "okay";
 };
 
 &tmu_cpu2 {
         vtmu-supply = <&ldo7_reg>;
-        status = "okay";
 };
 
 &tmu_cpu3 {
         vtmu-supply = <&ldo7_reg>;
-        status = "okay";
 };
 
 &tmu_gpu {
         vtmu-supply = <&ldo7_reg>;
-        status = "okay";
 };
 
 &rtc {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
index 2ae1cf41dcb6..03fa88c45426 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts
@@ -14,44 +14,11 @@
 /dts-v1/;
 #include "exynos5422-odroidxu3-common.dtsi"
 #include "exynos5422-odroidxu3-audio.dtsi"
+#include "exynos54xx-odroidxu-leds.dtsi"
 
 / {
         model = "Hardkernel Odroid XU3 Lite";
         compatible = "hardkernel,odroid-xu3-lite", "samsung,exynos5800", "samsung,exynos5";
-
-        pwmleds {
-                compatible = "pwm-leds";
-
-                greenled {
-                        label = "green:mmc0";
-                        pwms = <&pwm 1 2000000 0>;
-                        pwm-names = "pwm1";
-                        /*
-                         * Green LED is much brighter than the others
-                         * so limit its max brightness
-                         */
-                        max_brightness = <127>;
-                        linux,default-trigger = "mmc0";
-                };
-
-                blueled {
-                        label = "blue:heartbeat";
-                        pwms = <&pwm 2 2000000 0>;
-                        pwm-names = "pwm2";
-                        max_brightness = <255>;
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-
-        gpioleds {
-                compatible = "gpio-leds";
-                redled {
-                        label = "red:microSD";
-                        gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
-                        default-state = "off";
-                        linux,default-trigger = "mmc1";
-                };
-        };
 };
 
 &pwm {
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
index 432406db85de..9ed6564acfb0 100644
--- a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
+++ b/arch/arm/boot/dts/exynos5422-odroidxu3.dts
@@ -13,44 +13,11 @@
 /dts-v1/;
 #include "exynos5422-odroidxu3-common.dtsi"
 #include "exynos5422-odroidxu3-audio.dtsi"
+#include "exynos54xx-odroidxu-leds.dtsi"
 
 / {
         model = "Hardkernel Odroid XU3";
         compatible = "hardkernel,odroid-xu3", "samsung,exynos5800", "samsung,exynos5";
-
-        pwmleds {
-                compatible = "pwm-leds";
-
-                greenled {
-                        label = "green:mmc0";
-                        pwms = <&pwm 1 2000000 0>;
-                        pwm-names = "pwm1";
-                        /*
-                         * Green LED is much brighter than the others
-                         * so limit its max brightness
-                         */
-                        max_brightness = <127>;
-                        linux,default-trigger = "mmc0";
-                };
-
-                blueled {
-                        label = "blue:heartbeat";
-                        pwms = <&pwm 2 2000000 0>;
-                        pwm-names = "pwm2";
-                        max_brightness = <255>;
-                        linux,default-trigger = "heartbeat";
-                };
-        };
-
-        gpioleds {
-                compatible = "gpio-leds";
-                redled {
-                        label = "red:microSD";
-                        gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
-                        default-state = "off";
-                        linux,default-trigger = "mmc1";
-                };
-        };
 };
 
 &i2c_0 {
diff --git a/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
new file mode 100644
index 000000000000..0ed30206625c
--- /dev/null
+++ b/arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Hardkernel Odroid XU/XU3 LED device tree source
+ *
+ * Copyright (c) 2015,2016 Krzysztof Kozlowski
+ * Copyright (c) 2014 Collabora Ltd.
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+        pwmleds {
+                compatible = "pwm-leds";
+
+                greenled {
+                        label = "green:mmc0";
+                        pwms = <&pwm 1 2000000 0>;
+                        pwm-names = "pwm1";
+                        /*
+                         * Green LED is much brighter than the others
+                         * so limit its max brightness
+                         */
+                        max_brightness = <127>;
+                        linux,default-trigger = "mmc0";
+                };
+
+                blueled {
+                        label = "blue:heartbeat";
+                        pwms = <&pwm 2 2000000 0>;
+                        pwm-names = "pwm2";
+                        max_brightness = <255>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        gpioleds {
+                compatible = "gpio-leds";
+                redled {
+                        label = "red:microSD";
+                        gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
+                        default-state = "off";
+                        linux,default-trigger = "mmc1";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi
new file mode 100644
index 000000000000..06a604911e87
--- /dev/null
+++ b/arch/arm/boot/dts/exynos54xx.dtsi
@@ -0,0 +1,199 @@
+/*
+ * Samsung's Exynos54xx SoC series common device tree source
+ *
+ * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ * Copyright (c) 2016 Krzysztof Kozlowski
+ *
+ * Device nodes common for Samsung Exynos5410/5420/5422/5800. Specific
+ * Exynos 54xx SoCs should include this file and customize it further
+ * (e.g. with clocks).
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "skeleton.dtsi"
+#include "exynos5.dtsi"
+
+/ {
+        compatible = "samsung,exynos5";
+
+        aliases {
+                i2c4 = &hsi2c_4;
+                i2c5 = &hsi2c_5;
+                i2c6 = &hsi2c_6;
+                i2c7 = &hsi2c_7;
+                usbdrdphy0 = &usbdrd_phy0;
+                usbdrdphy1 = &usbdrd_phy1;
+        };
+
+        soc: soc {
+                sysram@02020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x54000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x54000>;
+
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
+
+                        smp-sysram@53000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x53000 0x1000>;
+                        };
+                };
+
+                mct: mct@101c0000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x101c0000 0xb00>;
+                        interrupt-parent = <&mct_map>;
+                        interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>,
+                                        <8>, <9>, <10>, <11>;
+
+                        mct_map: mct-map {
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = <0 &combiner 23 3>,
+                                                <1 &combiner 23 4>,
+                                                <2 &combiner 25 2>,
+                                                <3 &combiner 25 3>,
+                                                <4 &gic 0 120 0>,
+                                                <5 &gic 0 121 0>,
+                                                <6 &gic 0 122 0>,
+                                                <7 &gic 0 123 0>,
+                                                <8 &gic 0 128 0>,
+                                                <9 &gic 0 129 0>,
+                                                <10 &gic 0 130 0>,
+                                                <11 &gic 0 131 0>;
+                        };
+                };
+
+                watchdog: watchdog@101d0000 {
+                        compatible = "samsung,exynos5420-wdt";
+                        reg = <0x101d0000 0x100>;
+                        interrupts = <0 42 0>;
+                };
+
+                sss: sss@10830000 {
+                        compatible = "samsung,exynos4210-secss";
+                        reg = <0x10830000 0x300>;
+                        interrupts = <0 112 0>;
+                };
+
+                /* i2c_0-3 are defined in exynos5.dtsi */
+                hsi2c_4: i2c@12ca0000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12ca0000 0x1000>;
+                        interrupts = <0 60 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                hsi2c_5: i2c@12cb0000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12cb0000 0x1000>;
+                        interrupts = <0 61 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                hsi2c_6: i2c@12cc0000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12cc0000 0x1000>;
+                        interrupts = <0 62 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                hsi2c_7: i2c@12cd0000 {
+                        compatible = "samsung,exynos5250-hsi2c";
+                        reg = <0x12cd0000 0x1000>;
+                        interrupts = <0 63 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+
+                usbdrd3_0: usb3-0 {
+                        compatible = "samsung,exynos5250-dwusb3";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbdrd_dwc3_0: dwc3@12000000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x12000000 0x10000>;
+                                interrupts = <0 72 0>;
+                                phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                        };
+                };
+
+                usbdrd_phy0: phy@12100000 {
+                        compatible = "samsung,exynos5420-usbdrd-phy";
+                        reg = <0x12100000 0x100>;
+                        #phy-cells = <1>;
+                };
+
+                usbdrd3_1: usb3-1 {
+                        compatible = "samsung,exynos5250-dwusb3";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+
+                        usbdrd_dwc3_1: dwc3@12400000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x12400000 0x10000>;
+                                phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                        };
+                };
+
+                usbdrd_phy1: phy@12500000 {
+                        compatible = "samsung,exynos5420-usbdrd-phy";
+                        reg = <0x12500000 0x100>;
+                        #phy-cells = <1>;
+                };
+
+                usbhost2: usb@12110000 {
+                        compatible = "samsung,exynos4210-ehci";
+                        reg = <0x12110000 0x100>;
+                        interrupts = <0 71 0>;
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&usb2_phy 1>;
+                        };
+                };
+
+                usbhost1: usb@12120000 {
+                        compatible = "samsung,exynos4210-ohci";
+                        reg = <0x12120000 0x100>;
+                        interrupts = <0 71 0>;
+
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        port@0 {
+                                reg = <0>;
+                                phys = <&usb2_phy 1>;
+                        };
+                };
+
+                usb2_phy: phy@12130000 {
+                        compatible = "samsung,exynos5250-usb2-phy";
+                        reg = <0x12130000 0x100>;
+                        #phy-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 1f735963ca98..5ec71e2400fd 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -279,7 +279,6 @@
                                 regulator-name = "vdd_1v2";
                                 regulator-min-microvolt = <1200000>;
                                 regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-off-in-suspend;
@@ -302,7 +301,6 @@
                                 regulator-name = "vdd_1v35";
                                 regulator-min-microvolt = <1350000>;
                                 regulator-max-microvolt = <1350000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -324,7 +322,6 @@
                                 regulator-name = "vdd_2v";
                                 regulator-min-microvolt = <2000000>;
                                 regulator-max-microvolt = <2000000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -335,7 +332,6 @@
                                 regulator-name = "vdd_1v8";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
                                 regulator-boot-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
@@ -420,7 +416,6 @@
                                 regulator-name = "vdd_ldo9";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
                                 regulator-state-mem {
                                         regulator-on-in-suspend;
                                         regulator-mode = <MAX77802_OPMODE_LP>;
@@ -431,7 +426,6 @@
                                 regulator-name = "vdd_ldo10";
                                 regulator-min-microvolt = <1800000>;
                                 regulator-max-microvolt = <1800000>;
-                                regulator-always-on;
                                 regulator-state-mem {
                                         regulator-off-in-suspend;
                                 };
@@ -670,10 +664,6 @@
         status = "okay";
 };
 
-&mfc {
-        memory-region = <&mfc_left>, <&mfc_right>;
-};
-
 &mmc_0 {
         status = "okay";
         num-slots = <1>;
@@ -1022,6 +1012,26 @@
         status = "okay";
 };
 
+&tmu_cpu0 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu1 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu2 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_cpu3 {
+        vtmu-supply = <&ldo10_reg>;
+};
+
+&tmu_gpu {
+        vtmu-supply = <&ldo10_reg>;
+};
+
 &usbdrd_dwc3_0 {
         dr_mode = "host";
 };
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 0d0e62489d93..4aee5cc75fa4 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -11,15 +11,6 @@
 
 / {
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <6000000>;
-                };
-
                 main_xtal {
                         clock-frequency = <6000000>;
                 };
diff --git a/arch/arm/boot/dts/hi3519-demb.dts b/arch/arm/boot/dts/hi3519-demb.dts
new file mode 100644
index 000000000000..6991ab694c9c
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519-demb.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+/dts-v1/;
+#include "hi3519.dtsi"
+
+/ {
+        model = "HiSilicon HI3519 DEMO Board";
+        compatible = "hisilicon,hi3519";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>;
+        };
+};
+
+&uart0 {
+        status = "okay";
+};
+
+&dual_timer0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/hi3519.dtsi b/arch/arm/boot/dts/hi3519.dtsi
new file mode 100644
index 000000000000..5729ecfcdc8b
--- /dev/null
+++ b/arch/arm/boot/dts/hi3519.dtsi
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2015 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <dt-bindings/clock/hi3519-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        chosen { };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0>;
+                };
+        };
+
+        gic: interrupt-controller@10300000 {
+                compatible = "arm,cortex-a7-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x10301000 0x1000>, <0x10302000 0x1000>;
+        };
+
+        clk_3m: clk_3m {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <3000000>;
+        };
+
+        crg: clock-reset-controller@12010000 {
+                compatible = "hisilicon,hi3519-crg";
+                #clock-cells = <1>;
+                #reset-cells = <2>;
+                reg = <0x12010000 0x10000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+                ranges;
+
+                uart0: serial@12100000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x12100000 0x1000>;
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_UART0_CLK>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                uart1: serial@12101000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x12101000 0x1000>;
+                        interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_UART1_CLK>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                uart2: serial@12102000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x12102000 0x1000>;
+                        interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_UART2_CLK>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                uart3: serial@12103000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x12103000 0x1000>;
+                        interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_UART3_CLK>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                uart4: serial@12104000 {
+                        compatible = "arm,pl011", "arm,primecell";
+                        reg = <0x12104000 0x1000>;
+                        interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_UART4_CLK>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                dual_timer0: timer@12000000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x12000000 0x1000>;
+                        clocks = <&clk_3m>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                dual_timer1: timer@12001000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x12001000 0x1000>;
+                        clocks = <&clk_3m>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                dual_timer2: timer@12002000 {
+                        compatible = "arm,sp804", "arm,primecell";
+                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x12002000 0x1000>;
+                        clocks = <&clk_3m>;
+                        clock-names = "apb_pclk";
+                        status = "disable";
+                };
+
+                spi_bus0: spi@12120000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x12120000 0x1000>;
+                        interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_SPI0_CLK>;
+                        clock-names = "apb_pclk";
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disable";
+                };
+
+                spi_bus1: spi@12121000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x12121000 0x1000>;
+                        interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_SPI1_CLK>;
+                        clock-names = "apb_pclk";
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disable";
+                };
+
+                spi_bus2: spi@12122000 {
+                        compatible = "arm,pl022", "arm,primecell";
+                        reg = <0x12122000 0x1000>;
+                        interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&crg HI3519_SPI2_CLK>;
+                        clock-names = "apb_pclk";
+                        num-cs = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disable";
+                };
+
+                sysctrl: system-controller@12020000 {
+                        compatible = "hisilicon,hi3519-sysctrl", "syscon";
+                        reg = <0x12020000 0x1000>;
+                };
+
+                reboot {
+                        compatible = "syscon-reboot";
+                        regmap = <&sysctrl>;
+                        offset = <0x4>;
+                        mask = <0xdeadbeef>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
index af4eee5794aa..f50498659cc3 100644
--- a/arch/arm/boot/dts/imx1-ads.dts
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -66,14 +66,14 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
index 07d92fb40e6f..e8b4b52c2418 100644
--- a/arch/arm/boot/dts/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -34,14 +34,14 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx23-sansa.dts b/arch/arm/boot/dts/imx23-sansa.dts
new file mode 100644
index 000000000000..4ec32f4c7885
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-sansa.dts
@@ -0,0 +1,207 @@
+/*
+ * Copyright (C) 2013-2016 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/dts-v1/;
+#include "imx23.dtsi"
+
+/ {
+        model = "SanDisk Sansa Fuze+";
+        compatible = "sandisk,sansa_fuze_plus", "fsl,imx23";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
+                                vmmc-supply = <&reg_vddio_sd0>;
+                                cd-inverted;
+                                status = "okay";
+                        };
+
+                        ssp1: ssp@80034000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc1_8bit_pins_a>;
+                                bus-width = <8>;
+                                vmmc-supply = <&reg_vddio_sd1>;
+                                non-removable;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX23_PAD_GPMI_D08__GPIO_0_8
+                                                MX23_PAD_PWM3__GPIO_1_29
+                                                MX23_PAD_AUART1_RTS__GPIO_0_27
+                                                MX23_PAD_AUART1_CTS__GPIO_0_26
+                                                MX23_PAD_I2C_SCL__I2C_SCL
+                                                MX23_PAD_I2C_SDA__I2C_SDA
+                                                MX23_PAD_LCD_DOTCK__GPIO_1_22
+                                                MX23_PAD_LCD_HSYNC__GPIO_1_24
+                                                MX23_PAD_PWM3__GPIO_1_29
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm2_pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        dr_mode = "peripheral";
+                        status = "okay";
+                };
+        };
+
+        reg_vddio_sd0: regulator-vddio-sd0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vddio-sd0";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio0 8 0>;
+        };
+
+        reg_vddio_sd1: regulator-vddio-sd1 {
+                compatible = "regulator-fixed";
+                regulator-name = "vddio-sd1";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio1 29 0>;
+        };
+
+        reg_vdd_touchpad: regulator-vdd-touchpad0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd-touchpad0";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio0 26 0>;
+                regulator-always-on;
+                enable-active-low;
+        };
+
+        reg_vdd_tuner: regulator-vdd-tuner0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd-tuner0";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio0 29 0>;
+                regulator-always-on;
+                enable-active-low;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        i2c-0 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                gpios = <
+                        &gpio1 24 0             /* SDA */
+                        &gpio1 22 0             /* SCL */
+                >;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+        };
+
+        i2c-1 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                gpios = <
+                        &gpio0 31 0             /* SDA */
+                        &gpio0 30 0             /* SCL */
+                >;
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+
+                touch: touch@20 {
+                        compatible = "synaptics,synaptics_i2c";
+                        reg = <0x20>;
+                };
+
+                eeprom: eeprom@50 {
+                        compatible = "atmel,24c64";
+                        reg = <0x50>;
+                        pagesize = <32>;
+                };
+        };
+
+};
diff --git a/arch/arm/boot/dts/imx23-xfi3.dts b/arch/arm/boot/dts/imx23-xfi3.dts
new file mode 100644
index 000000000000..025cf949662d
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-xfi3.dts
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2013-2016 Marek Vasut <marek.vasut@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of
+ *     the License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/dts-v1/;
+#include "imx23.dtsi"
+
+/ {
+        model = "Creative ZEN X-Fi3";
+        compatible = "creative,x-fi3", "fsl,imx23";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
+                                vmmc-supply = <&reg_vddio_sd0>;
+                                cd-inverted;
+                                status = "okay";
+                        };
+
+                        ssp1: ssp@80034000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc1_4bit_pins_a>;
+                                bus-width = <4>;
+                                non-removable;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX23_PAD_GPMI_D07__GPIO_0_7
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                key_pins_a: keys@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX23_PAD_ROTARYA__GPIO_2_7
+                                                MX23_PAD_ROTARYB__GPIO_2_8
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        i2c: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c_pins_a>;
+                                status = "okay";
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm2_pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006e000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_2pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+
+                        lradc@80050000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                usb0: usb@80080000 {
+                        dr_mode = "peripheral";
+                        status = "okay";
+                };
+        };
+
+        reg_vddio_sd0: regulator-vddio-sd0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vddio-sd0";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio0 7 0>;
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&key_pins_a>;
+
+                voldown {
+                        label = "volume-down";
+                        linux,code = <114>;
+                        gpios = <&gpio2 7 0>;
+                        debounce-interval = <20>;
+                };
+
+                volup {
+                        label = "volume-up";
+                        linux,code = <115>;
+                        gpios = <&gpio2 8 0>;
+                        debounce-interval = <20>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 302d1168f424..440ee9a4a158 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -111,6 +111,7 @@
 
                                 gpio0: gpio@0 {
                                         compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+                                        reg = <0>;
                                         interrupts = <16>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -120,6 +121,7 @@
 
                                 gpio1: gpio@1 {
                                         compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+                                        reg = <1>;
                                         interrupts = <17>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -129,6 +131,7 @@
 
                                 gpio2: gpio@2 {
                                         compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+                                        reg = <2>;
                                         interrupts = <18>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -171,6 +174,17 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
+                                auart1_2pins_a: auart1-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX23_PAD_GPMI_D14__AUART2_RX
+                                                MX23_PAD_GPMI_D15__AUART2_TX
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_DISABLE>;
+                                };
+
                                 gpmi_pins_a: gpmi-nand@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
@@ -249,6 +263,40 @@
                                         fsl,pull-up = <MXS_PULL_DISABLE>;
                                 };
 
+                                mmc1_4bit_pins_a: mmc1-4bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX23_PAD_GPMI_D00__SSP2_DATA0
+                                                MX23_PAD_GPMI_D01__SSP2_DATA1
+                                                MX23_PAD_GPMI_D02__SSP2_DATA2
+                                                MX23_PAD_GPMI_D03__SSP2_DATA3
+                                                MX23_PAD_GPMI_RDY1__SSP2_CMD
+                                                MX23_PAD_GPMI_WRN__SSP2_SCK
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
+
+                                mmc1_8bit_pins_a: mmc1-8bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                MX23_PAD_GPMI_D00__SSP2_DATA0
+                                                MX23_PAD_GPMI_D01__SSP2_DATA1
+                                                MX23_PAD_GPMI_D02__SSP2_DATA2
+                                                MX23_PAD_GPMI_D03__SSP2_DATA3
+                                                MX23_PAD_GPMI_D04__SSP2_DATA4
+                                                MX23_PAD_GPMI_D05__SSP2_DATA5
+                                                MX23_PAD_GPMI_D06__SSP2_DATA6
+                                                MX23_PAD_GPMI_D07__SSP2_DATA7
+                                                MX23_PAD_GPMI_RDY1__SSP2_CMD
+                                                MX23_PAD_GPMI_WRN__SSP2_SCK
+                                        >;
+                                        fsl,drive-strength = <MXS_DRIVE_8mA>;
+                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
+                                        fsl,pull-up = <MXS_PULL_ENABLE>;
+                                };
+
                                 pwm2_pins_a: pwm2@0 {
                                         reg = <0>;
                                         fsl,pinmux-ids = <
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index cda6907a27b9..9300711f1ea3 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -161,14 +161,14 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9351296356dc..70292101ba03 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -298,7 +298,7 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx25-pinfunc.h b/arch/arm/boot/dts/imx25-pinfunc.h
index f96fa2df8f11..f840f03ad171 100644
--- a/arch/arm/boot/dts/imx25-pinfunc.h
+++ b/arch/arm/boot/dts/imx25-pinfunc.h
@@ -26,77 +26,77 @@
 #define MX25_PAD_A13__GPIO_4_1                  0x00c 0x22C 0x000 0x05 0x000
 #define MX25_PAD_A13__LCDC_CLS                  0x00c 0x22C 0x000 0x07 0x000
 
-#define MX25_PAD_A14__A14                       0x010 0x230 0x000 0x10 0x000
-#define MX25_PAD_A14__GPIO_2_0                  0x010 0x230 0x000 0x15 0x000
-#define MX25_PAD_A14__SIM1_CLK1                 0x010 0x230 0x000 0x16 0x000
-#define MX25_PAD_A14__LCDC_SPL                  0x010 0x230 0x000 0x17 0x000
-
-#define MX25_PAD_A15__A15                       0x014 0x234 0x000 0x10 0x000
-#define MX25_PAD_A15__GPIO_2_1                  0x014 0x234 0x000 0x15 0x000
-#define MX25_PAD_A15__SIM1_RST1                 0x014 0x234 0x000 0x16 0x000
-#define MX25_PAD_A15__LCDC_PS                   0x014 0x234 0x000 0x17 0x000
-
-#define MX25_PAD_A16__A16                       0x018 0x000 0x000 0x10 0x000
-#define MX25_PAD_A16__GPIO_2_2                  0x018 0x000 0x000 0x15 0x000
-#define MX25_PAD_A16__SIM1_VEN1                 0x018 0x000 0x000 0x16 0x000
-#define MX25_PAD_A16__LCDC_REV                  0x018 0x000 0x000 0x17 0x000
-
-#define MX25_PAD_A17__A17                       0x01c 0x238 0x000 0x10 0x000
-#define MX25_PAD_A17__GPIO_2_3                  0x01c 0x238 0x000 0x15 0x000
-#define MX25_PAD_A17__SIM1_TX                   0x01c 0x238 0x554 0x16 0x000
-#define MX25_PAD_A17__FEC_TX_ERR                0x01c 0x238 0x000 0x17 0x000
-
-#define MX25_PAD_A18__A18                       0x020 0x23c 0x000 0x10 0x000
-#define MX25_PAD_A18__GPIO_2_4                  0x020 0x23c 0x000 0x15 0x000
-#define MX25_PAD_A18__SIM1_PD1                  0x020 0x23c 0x550 0x16 0x000
-#define MX25_PAD_A18__FEC_COL                   0x020 0x23c 0x504 0x17 0x000
-
-#define MX25_PAD_A19__A19                       0x024 0x240 0x000 0x10 0x000
-#define MX25_PAD_A19__GPIO_2_5                  0x024 0x240 0x000 0x15 0x000
-#define MX25_PAD_A19__SIM1_RX1                  0x024 0x240 0x54c 0x16 0x000
-#define MX25_PAD_A19__FEC_RX_ERR                0x024 0x240 0x518 0x17 0x000
-
-#define MX25_PAD_A20__A20                       0x028 0x244 0x000 0x10 0x000
-#define MX25_PAD_A20__GPIO_2_6                  0x028 0x244 0x000 0x15 0x000
-#define MX25_PAD_A20__SIM2_CLK1                 0x028 0x244 0x000 0x16 0x000
-#define MX25_PAD_A20__FEC_RDATA2                0x028 0x244 0x50c 0x17 0x000
-
-#define MX25_PAD_A21__A21                       0x02c 0x248 0x000 0x10 0x000
-#define MX25_PAD_A21__GPIO_2_7                  0x02c 0x248 0x000 0x15 0x000
-#define MX25_PAD_A21__SIM2_RST1                 0x02c 0x248 0x000 0x16 0x000
-#define MX25_PAD_A21__FEC_RDATA3                0x02c 0x248 0x510 0x17 0x000
-
-#define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x10 0x000
-#define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x15 0x000
-#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
-#define MX25_PAD_A22__SIM2_VEN1                 0x030 0x000 0x000 0x16 0x000
-#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x17 0x000
-
-#define MX25_PAD_A23__A23                       0x034 0x24c 0x000 0x10 0x000
-#define MX25_PAD_A23__GPIO_2_9                  0x034 0x24c 0x000 0x15 0x000
-#define MX25_PAD_A23__SIM2_TX1                  0x034 0x24c 0x560 0x16 0x000
-#define MX25_PAD_A23__FEC_TDATA3                0x034 0x24c 0x000 0x17 0x000
-
-#define MX25_PAD_A24__A24                       0x038 0x250 0x000 0x10 0x000
-#define MX25_PAD_A24__GPIO_2_10                 0x038 0x250 0x000 0x15 0x000
-#define MX25_PAD_A24__SIM2_PD1                  0x038 0x250 0x55c 0x16 0x000
-#define MX25_PAD_A24__FEC_RX_CLK                0x038 0x250 0x514 0x17 0x000
-
-#define MX25_PAD_A25__A25                       0x03c 0x254 0x000 0x10 0x000
-#define MX25_PAD_A25__GPIO_2_11                 0x03c 0x254 0x000 0x15 0x000
-#define MX25_PAD_A25__FEC_CRS                   0x03c 0x254 0x508 0x17 0x000
-
-#define MX25_PAD_EB0__EB0                       0x040 0x258 0x000 0x10 0x000
-#define MX25_PAD_EB0__AUD4_TXD                  0x040 0x258 0x464 0x14 0x000
-#define MX25_PAD_EB0__GPIO_2_12                 0x040 0x258 0x000 0x15 0x000
-
-#define MX25_PAD_EB1__EB1                       0x044 0x25c 0x000 0x10 0x000
-#define MX25_PAD_EB1__AUD4_RXD                  0x044 0x25c 0x460 0x14 0x000
-#define MX25_PAD_EB1__GPIO_2_13                 0x044 0x25c 0x000 0x15 0x000
-
-#define MX25_PAD_OE__OE                         0x048 0x260 0x000 0x10 0x000
-#define MX25_PAD_OE__AUD4_TXC                   0x048 0x260 0x000 0x14 0x000
-#define MX25_PAD_OE__GPIO_2_14                  0x048 0x260 0x000 0x15 0x000
+#define MX25_PAD_A14__A14                       0x010 0x230 0x000 0x00 0x000
+#define MX25_PAD_A14__GPIO_2_0                  0x010 0x230 0x000 0x05 0x000
+#define MX25_PAD_A14__SIM1_CLK1                 0x010 0x230 0x000 0x06 0x000
+#define MX25_PAD_A14__LCDC_SPL                  0x010 0x230 0x000 0x07 0x000
+
+#define MX25_PAD_A15__A15                       0x014 0x234 0x000 0x00 0x000
+#define MX25_PAD_A15__GPIO_2_1                  0x014 0x234 0x000 0x05 0x000
+#define MX25_PAD_A15__SIM1_RST1                 0x014 0x234 0x000 0x06 0x000
+#define MX25_PAD_A15__LCDC_PS                   0x014 0x234 0x000 0x07 0x000
+
+#define MX25_PAD_A16__A16                       0x018 0x000 0x000 0x00 0x000
+#define MX25_PAD_A16__GPIO_2_2                  0x018 0x000 0x000 0x05 0x000
+#define MX25_PAD_A16__SIM1_VEN1                 0x018 0x000 0x000 0x06 0x000
+#define MX25_PAD_A16__LCDC_REV                  0x018 0x000 0x000 0x07 0x000
+
+#define MX25_PAD_A17__A17                       0x01c 0x238 0x000 0x00 0x000
+#define MX25_PAD_A17__GPIO_2_3                  0x01c 0x238 0x000 0x05 0x000
+#define MX25_PAD_A17__SIM1_TX                   0x01c 0x238 0x554 0x06 0x000
+#define MX25_PAD_A17__FEC_TX_ERR                0x01c 0x238 0x000 0x07 0x000
+
+#define MX25_PAD_A18__A18                       0x020 0x23c 0x000 0x00 0x000
+#define MX25_PAD_A18__GPIO_2_4                  0x020 0x23c 0x000 0x05 0x000
+#define MX25_PAD_A18__SIM1_PD1                  0x020 0x23c 0x550 0x06 0x000
+#define MX25_PAD_A18__FEC_COL                   0x020 0x23c 0x504 0x07 0x000
+
+#define MX25_PAD_A19__A19                       0x024 0x240 0x000 0x00 0x000
+#define MX25_PAD_A19__GPIO_2_5                  0x024 0x240 0x000 0x05 0x000
+#define MX25_PAD_A19__SIM1_RX1                  0x024 0x240 0x54c 0x06 0x000
+#define MX25_PAD_A19__FEC_RX_ERR                0x024 0x240 0x518 0x07 0x000
+
+#define MX25_PAD_A20__A20                       0x028 0x244 0x000 0x00 0x000
+#define MX25_PAD_A20__GPIO_2_6                  0x028 0x244 0x000 0x05 0x000
+#define MX25_PAD_A20__SIM2_CLK1                 0x028 0x244 0x000 0x06 0x000
+#define MX25_PAD_A20__FEC_RDATA2                0x028 0x244 0x50c 0x07 0x000
+
+#define MX25_PAD_A21__A21                       0x02c 0x248 0x000 0x00 0x000
+#define MX25_PAD_A21__GPIO_2_7                  0x02c 0x248 0x000 0x05 0x000
+#define MX25_PAD_A21__SIM2_RST1                 0x02c 0x248 0x000 0x06 0x000
+#define MX25_PAD_A21__FEC_RDATA3                0x02c 0x248 0x510 0x07 0x000
+
+#define MX25_PAD_A22__A22                       0x030 0x000 0x000 0x00 0x000
+#define MX25_PAD_A22__GPIO_2_8                  0x030 0x000 0x000 0x05 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x07 0x000
+#define MX25_PAD_A22__SIM2_VEN1                 0x030 0x000 0x000 0x06 0x000
+#define MX25_PAD_A22__FEC_TDATA2                0x030 0x000 0x000 0x07 0x000
+
+#define MX25_PAD_A23__A23                       0x034 0x24c 0x000 0x00 0x000
+#define MX25_PAD_A23__GPIO_2_9                  0x034 0x24c 0x000 0x05 0x000
+#define MX25_PAD_A23__SIM2_TX1                  0x034 0x24c 0x560 0x06 0x000
+#define MX25_PAD_A23__FEC_TDATA3                0x034 0x24c 0x000 0x07 0x000
+
+#define MX25_PAD_A24__A24                       0x038 0x250 0x000 0x00 0x000
+#define MX25_PAD_A24__GPIO_2_10                 0x038 0x250 0x000 0x05 0x000
+#define MX25_PAD_A24__SIM2_PD1                  0x038 0x250 0x55c 0x06 0x000
+#define MX25_PAD_A24__FEC_RX_CLK                0x038 0x250 0x514 0x07 0x000
+
+#define MX25_PAD_A25__A25                       0x03c 0x254 0x000 0x00 0x000
+#define MX25_PAD_A25__GPIO_2_11                 0x03c 0x254 0x000 0x05 0x000
+#define MX25_PAD_A25__FEC_CRS                   0x03c 0x254 0x508 0x07 0x000
+
+#define MX25_PAD_EB0__EB0                       0x040 0x258 0x000 0x00 0x000
+#define MX25_PAD_EB0__AUD4_TXD                  0x040 0x258 0x464 0x04 0x000
+#define MX25_PAD_EB0__GPIO_2_12                 0x040 0x258 0x000 0x05 0x000
+
+#define MX25_PAD_EB1__EB1                       0x044 0x25c 0x000 0x00 0x000
+#define MX25_PAD_EB1__AUD4_RXD                  0x044 0x25c 0x460 0x04 0x000
+#define MX25_PAD_EB1__GPIO_2_13                 0x044 0x25c 0x000 0x05 0x000
+
+#define MX25_PAD_OE__OE                         0x048 0x260 0x000 0x00 0x000
+#define MX25_PAD_OE__AUD4_TXC                   0x048 0x260 0x000 0x04 0x000
+#define MX25_PAD_OE__GPIO_2_14                  0x048 0x260 0x000 0x05 0x000
 
 #define MX25_PAD_CS0__CS0                       0x04c 0x000 0x000 0x00 0x000
 #define MX25_PAD_CS0__GPIO_4_2                  0x04c 0x000 0x000 0x05 0x000
@@ -105,51 +105,51 @@
 #define MX25_PAD_CS1__NF_CE3                    0x050 0x000 0x000 0x01 0x000
 #define MX25_PAD_CS1__GPIO_4_3                  0x050 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_CS4__CS4                       0x054 0x264 0x000 0x10 0x000
+#define MX25_PAD_CS4__CS4                       0x054 0x264 0x000 0x00 0x000
 #define MX25_PAD_CS4__NF_CE1                    0x054 0x264 0x000 0x01 0x000
-#define MX25_PAD_CS4__UART5_CTS                 0x054 0x264 0x000 0x13 0x000
-#define MX25_PAD_CS4__GPIO_3_20                 0x054 0x264 0x000 0x15 0x000
+#define MX25_PAD_CS4__UART5_CTS                 0x054 0x264 0x000 0x03 0x000
+#define MX25_PAD_CS4__GPIO_3_20                 0x054 0x264 0x000 0x05 0x000
 
 #define MX25_PAD_CS5__CS5                       0x058 0x268 0x000 0x00 0x000
 #define MX25_PAD_CS5__NF_CE2                    0x058 0x268 0x000 0x01 0x000
 #define MX25_PAD_CS5__UART5_RTS                 0x058 0x268 0x574 0x03 0x000
 #define MX25_PAD_CS5__GPIO_3_21                 0x058 0x268 0x000 0x05 0x000
 
-#define MX25_PAD_NF_CE0__NF_CE0                 0x05c 0x26c 0x000 0x10 0x000
-#define MX25_PAD_NF_CE0__GPIO_3_22              0x05c 0x26c 0x000 0x15 0x000
+#define MX25_PAD_NF_CE0__NF_CE0                 0x05c 0x26c 0x000 0x00 0x000
+#define MX25_PAD_NF_CE0__GPIO_3_22              0x05c 0x26c 0x000 0x05 0x000
 
-#define MX25_PAD_ECB__ECB                       0x060 0x270 0x000 0x10 0x000
-#define MX25_PAD_ECB__UART5_TXD                 0x060 0x270 0x000 0x13 0x000
-#define MX25_PAD_ECB__GPIO_3_23                 0x060 0x270 0x000 0x15 0x000
+#define MX25_PAD_ECB__ECB                       0x060 0x270 0x000 0x00 0x000
+#define MX25_PAD_ECB__UART5_TXD                 0x060 0x270 0x000 0x03 0x000
+#define MX25_PAD_ECB__GPIO_3_23                 0x060 0x270 0x000 0x05 0x000
 
-#define MX25_PAD_LBA__LBA                       0x064 0x274 0x000 0x10 0x000
-#define MX25_PAD_LBA__UART5_RXD                 0x064 0x274 0x578 0x13 0x000
-#define MX25_PAD_LBA__GPIO_3_24                 0x064 0x274 0x000 0x15 0x000
+#define MX25_PAD_LBA__LBA                       0x064 0x274 0x000 0x00 0x000
+#define MX25_PAD_LBA__UART5_RXD                 0x064 0x274 0x578 0x03 0x000
+#define MX25_PAD_LBA__GPIO_3_24                 0x064 0x274 0x000 0x05 0x000
 
 #define MX25_PAD_BCLK__BCLK                     0x068 0x000 0x000 0x00 0x000
 #define MX25_PAD_BCLK__GPIO_4_4                 0x068 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_RW__RW                         0x06c 0x278 0x000 0x10 0x000
-#define MX25_PAD_RW__AUD4_TXFS                  0x06c 0x278 0x474 0x14 0x000
-#define MX25_PAD_RW__GPIO_3_25                  0x06c 0x278 0x000 0x15 0x000
+#define MX25_PAD_RW__RW                         0x06c 0x278 0x000 0x00 0x000
+#define MX25_PAD_RW__AUD4_TXFS                  0x06c 0x278 0x474 0x04 0x000
+#define MX25_PAD_RW__GPIO_3_25                  0x06c 0x278 0x000 0x05 0x000
 
-#define MX25_PAD_NFWE_B__NFWE_B                 0x070 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFWE_B__GPIO_3_26              0x070 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFWE_B__NFWE_B                 0x070 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFWE_B__GPIO_3_26              0x070 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_NFRE_B__NFRE_B                 0x074 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFRE_B__GPIO_3_27              0x074 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFRE_B__NFRE_B                 0x074 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFRE_B__GPIO_3_27              0x074 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_NFALE__NFALE                   0x078 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFALE__GPIO_3_28               0x078 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFALE__NFALE                   0x078 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFALE__GPIO_3_28               0x078 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_NFCLE__NFCLE                   0x07c 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFCLE__GPIO_3_29               0x07c 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFCLE__NFCLE                   0x07c 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFCLE__GPIO_3_29               0x07c 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_NFWP_B__NFWP_B                 0x080 0x000 0x000 0x10 0x000
-#define MX25_PAD_NFWP_B__GPIO_3_30              0x080 0x000 0x000 0x15 0x000
+#define MX25_PAD_NFWP_B__NFWP_B                 0x080 0x000 0x000 0x00 0x000
+#define MX25_PAD_NFWP_B__GPIO_3_30              0x080 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_NFRB__NFRB                     0x084 0x27c 0x000 0x10 0x000
-#define MX25_PAD_NFRB__GPIO_3_31                0x084 0x27c 0x000 0x15 0x000
+#define MX25_PAD_NFRB__NFRB                     0x084 0x27c 0x000 0x00 0x000
+#define MX25_PAD_NFRB__GPIO_3_31                0x084 0x27c 0x000 0x05 0x000
 
 #define MX25_PAD_D15__D15                       0x088 0x280 0x000 0x00 0x000
 #define MX25_PAD_D15__LD16                      0x088 0x280 0x000 0x01 0x000
@@ -210,101 +210,101 @@
 #define MX25_PAD_D0__D0                         0x0c4 0x2bc 0x000 0x00 0x000
 #define MX25_PAD_D0__GPIO_4_20                  0x0c4 0x2bc 0x000 0x05 0x000
 
-#define MX25_PAD_LD0__LD0                       0x0c8 0x2c0 0x000 0x10 0x000
-#define MX25_PAD_LD0__CSI_D0                    0x0c8 0x2c0 0x488 0x12 0x000
-#define MX25_PAD_LD0__GPIO_2_15                 0x0c8 0x2c0 0x000 0x15 0x000
+#define MX25_PAD_LD0__LD0                       0x0c8 0x2c0 0x000 0x00 0x000
+#define MX25_PAD_LD0__CSI_D0                    0x0c8 0x2c0 0x488 0x02 0x000
+#define MX25_PAD_LD0__GPIO_2_15                 0x0c8 0x2c0 0x000 0x05 0x000
 
-#define MX25_PAD_LD1__LD1                       0x0cc 0x2c4 0x000 0x10 0x000
-#define MX25_PAD_LD1__CSI_D1                    0x0cc 0x2c4 0x48c 0x12 0x000
-#define MX25_PAD_LD1__GPIO_2_16                 0x0cc 0x2c4 0x000 0x15 0x000
+#define MX25_PAD_LD1__LD1                       0x0cc 0x2c4 0x000 0x00 0x000
+#define MX25_PAD_LD1__CSI_D1                    0x0cc 0x2c4 0x48c 0x02 0x000
+#define MX25_PAD_LD1__GPIO_2_16                 0x0cc 0x2c4 0x000 0x05 0x000
 
-#define MX25_PAD_LD2__LD2                       0x0d0 0x2c8 0x000 0x10 0x000
-#define MX25_PAD_LD2__GPIO_2_17                 0x0d0 0x2c8 0x000 0x15 0x000
+#define MX25_PAD_LD2__LD2                       0x0d0 0x2c8 0x000 0x00 0x000
+#define MX25_PAD_LD2__GPIO_2_17                 0x0d0 0x2c8 0x000 0x05 0x000
 
-#define MX25_PAD_LD3__LD3                       0x0d4 0x2cc 0x000 0x10 0x000
-#define MX25_PAD_LD3__GPIO_2_18                 0x0d4 0x2cc 0x000 0x15 0x000
+#define MX25_PAD_LD3__LD3                       0x0d4 0x2cc 0x000 0x00 0x000
+#define MX25_PAD_LD3__GPIO_2_18                 0x0d4 0x2cc 0x000 0x05 0x000
 
-#define MX25_PAD_LD4__LD4                       0x0d8 0x2d0 0x000 0x10 0x000
-#define MX25_PAD_LD4__GPIO_2_19                 0x0d8 0x2d0 0x000 0x15 0x000
+#define MX25_PAD_LD4__LD4                       0x0d8 0x2d0 0x000 0x00 0x000
+#define MX25_PAD_LD4__GPIO_2_19                 0x0d8 0x2d0 0x000 0x05 0x000
 
-#define MX25_PAD_LD5__LD5                       0x0dc 0x2d4 0x000 0x10 0x000
-#define MX25_PAD_LD5__GPIO_1_19                 0x0dc 0x2d4 0x000 0x15 0x000
+#define MX25_PAD_LD5__LD5                       0x0dc 0x2d4 0x000 0x00 0x000
+#define MX25_PAD_LD5__GPIO_1_19                 0x0dc 0x2d4 0x000 0x05 0x000
 
-#define MX25_PAD_LD6__LD6                       0x0e0 0x2d8 0x000 0x10 0x000
-#define MX25_PAD_LD6__GPIO_1_20                 0x0e0 0x2d8 0x000 0x15 0x000
+#define MX25_PAD_LD6__LD6                       0x0e0 0x2d8 0x000 0x00 0x000
+#define MX25_PAD_LD6__GPIO_1_20                 0x0e0 0x2d8 0x000 0x05 0x000
 
-#define MX25_PAD_LD7__LD7                       0x0e4 0x2dc 0x000 0x10 0x000
-#define MX25_PAD_LD7__GPIO_1_21                 0x0e4 0x2dc 0x000 0x15 0x000
+#define MX25_PAD_LD7__LD7                       0x0e4 0x2dc 0x000 0x00 0x000
+#define MX25_PAD_LD7__GPIO_1_21                 0x0e4 0x2dc 0x000 0x05 0x000
 
-#define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x10 0x000
-#define MX25_PAD_LD8__UART4_RXD                 0x0e8 0x2e0 0x570 0x12 0x000
-#define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x15 0x000
+#define MX25_PAD_LD8__LD8                       0x0e8 0x2e0 0x000 0x00 0x000
+#define MX25_PAD_LD8__UART4_RXD                 0x0e8 0x2e0 0x570 0x02 0x000
+#define MX25_PAD_LD8__FEC_TX_ERR                0x0e8 0x2e0 0x000 0x05 0x000
 #define MX25_PAD_LD8__SDHC2_CMD                 0x0e8 0x2e0 0x4e0 0x06 0x000
 
-#define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x10 0x000
-#define MX25_PAD_LD9__UART4_TXD                 0x0ec 0x2e4 0x000 0x12 0x000
-#define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x15 0x001
+#define MX25_PAD_LD9__LD9                       0x0ec 0x2e4 0x000 0x00 0x000
+#define MX25_PAD_LD9__UART4_TXD                 0x0ec 0x2e4 0x000 0x02 0x000
+#define MX25_PAD_LD9__FEC_COL                   0x0ec 0x2e4 0x504 0x05 0x001
 #define MX25_PAD_LD9__SDHC2_CLK                 0x0ec 0x2e4 0x4dc 0x06 0x000
 
 #define MX25_PAD_LD10__LD10                     0x0f0 0x2e8 0x000 0x00 0x000
 #define MX25_PAD_LD10__UART4_RTS                0x0f0 0x2e8 0x56c 0x02 0x000
 #define MX25_PAD_LD10__FEC_RX_ERR               0x0f0 0x2e8 0x518 0x05 0x001
 
-#define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x10 0x000
-#define MX25_PAD_LD11__UART4_CTS                0x0f4 0x2ec 0x000 0x12 0x000
-#define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x15 0x001
+#define MX25_PAD_LD11__LD11                     0x0f4 0x2ec 0x000 0x00 0x000
+#define MX25_PAD_LD11__UART4_CTS                0x0f4 0x2ec 0x000 0x02 0x000
+#define MX25_PAD_LD11__FEC_RDATA2               0x0f4 0x2ec 0x50c 0x05 0x001
 #define MX25_PAD_LD11__SDHC2_DAT1               0x0f4 0x2ec 0x4e8 0x06 0x000
 
-#define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x10 0x000
+#define MX25_PAD_LD12__LD12                     0x0f8 0x2f0 0x000 0x00 0x000
 #define MX25_PAD_LD12__CSPI2_MOSI               0x0f8 0x2f0 0x4a0 0x02 0x000
-#define MX25_PAD_LD12__FEC_RDATA3               0x0f8 0x2f0 0x510 0x15 0x001
+#define MX25_PAD_LD12__FEC_RDATA3               0x0f8 0x2f0 0x510 0x05 0x001
 
-#define MX25_PAD_LD13__LD13                     0x0fc 0x2f4 0x000 0x10 0x000
+#define MX25_PAD_LD13__LD13                     0x0fc 0x2f4 0x000 0x00 0x000
 #define MX25_PAD_LD13__CSPI2_MISO               0x0fc 0x2f4 0x49c 0x02 0x000
-#define MX25_PAD_LD13__FEC_TDATA2               0x0fc 0x2f4 0x000 0x15 0x000
+#define MX25_PAD_LD13__FEC_TDATA2               0x0fc 0x2f4 0x000 0x05 0x000
 
-#define MX25_PAD_LD14__LD14                     0x100 0x2f8 0x000 0x10 0x000
+#define MX25_PAD_LD14__LD14                     0x100 0x2f8 0x000 0x00 0x000
 #define MX25_PAD_LD14__CSPI2_SCLK               0x100 0x2f8 0x494 0x02 0x000
-#define MX25_PAD_LD14__FEC_TDATA3               0x100 0x2f8 0x000 0x15 0x000
+#define MX25_PAD_LD14__FEC_TDATA3               0x100 0x2f8 0x000 0x05 0x000
 
-#define MX25_PAD_LD15__LD15                     0x104 0x2fc 0x000 0x10 0x000
+#define MX25_PAD_LD15__LD15                     0x104 0x2fc 0x000 0x00 0x000
 #define MX25_PAD_LD15__CSPI2_RDY                0x104 0x2fc 0x498 0x02 0x000
-#define MX25_PAD_LD15__FEC_RX_CLK               0x104 0x2fc 0x514 0x15 0x001
+#define MX25_PAD_LD15__FEC_RX_CLK               0x104 0x2fc 0x514 0x05 0x001
 
-#define MX25_PAD_HSYNC__HSYNC                   0x108 0x300 0x000 0x10 0x000
-#define MX25_PAD_HSYNC__GPIO_1_22               0x108 0x300 0x000 0x15 0x000
+#define MX25_PAD_HSYNC__HSYNC                   0x108 0x300 0x000 0x00 0x000
+#define MX25_PAD_HSYNC__GPIO_1_22               0x108 0x300 0x000 0x05 0x000
 
-#define MX25_PAD_VSYNC__VSYNC                   0x10c 0x304 0x000 0x10 0x000
-#define MX25_PAD_VSYNC__GPIO_1_23               0x10c 0x304 0x000 0x15 0x000
+#define MX25_PAD_VSYNC__VSYNC                   0x10c 0x304 0x000 0x00 0x000
+#define MX25_PAD_VSYNC__GPIO_1_23               0x10c 0x304 0x000 0x05 0x000
 
-#define MX25_PAD_LSCLK__LSCLK                   0x110 0x308 0x000 0x10 0x000
-#define MX25_PAD_LSCLK__GPIO_1_24               0x110 0x308 0x000 0x15 0x000
+#define MX25_PAD_LSCLK__LSCLK                   0x110 0x308 0x000 0x00 0x000
+#define MX25_PAD_LSCLK__GPIO_1_24               0x110 0x308 0x000 0x05 0x000
 
-#define MX25_PAD_OE_ACD__OE_ACD                 0x114 0x30c 0x000 0x10 0x000
+#define MX25_PAD_OE_ACD__OE_ACD                 0x114 0x30c 0x000 0x00 0x000
 #define MX25_PAD_OE_ACD__CSPI2_SS0              0x114 0x30c 0x4a4 0x02 0x000
-#define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x15 0x000
+#define MX25_PAD_OE_ACD__GPIO_1_25              0x114 0x30c 0x000 0x05 0x000
 
-#define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x10 0x000
-#define MX25_PAD_CONTRAST__CC4                  0x118 0x310 0x000 0x11 0x000
-#define MX25_PAD_CONTRAST__PWM4_PWMO            0x118 0x310 0x000 0x14 0x000
-#define MX25_PAD_CONTRAST__FEC_CRS              0x118 0x310 0x508 0x15 0x001
-#define MX25_PAD_CONTRAST__USBH2_PWR            0x118 0x310 0x000 0x16 0x000
+#define MX25_PAD_CONTRAST__CONTRAST             0x118 0x310 0x000 0x00 0x000
+#define MX25_PAD_CONTRAST__CC4                  0x118 0x310 0x000 0x01 0x000
+#define MX25_PAD_CONTRAST__PWM4_PWMO            0x118 0x310 0x000 0x04 0x000
+#define MX25_PAD_CONTRAST__FEC_CRS              0x118 0x310 0x508 0x05 0x001
+#define MX25_PAD_CONTRAST__USBH2_PWR            0x118 0x310 0x000 0x06 0x000
 
-#define MX25_PAD_PWM__PWM                       0x11c 0x314 0x000 0x10 0x000
-#define MX25_PAD_PWM__GPIO_1_26                 0x11c 0x314 0x000 0x15 0x000
-#define MX25_PAD_PWM__USBH2_OC                  0x11c 0x314 0x580 0x16 0x001
+#define MX25_PAD_PWM__PWM                       0x11c 0x314 0x000 0x00 0x000
+#define MX25_PAD_PWM__GPIO_1_26                 0x11c 0x314 0x000 0x05 0x000
+#define MX25_PAD_PWM__USBH2_OC                  0x11c 0x314 0x580 0x06 0x001
 
-#define MX25_PAD_CSI_D2__CSI_D2                 0x120 0x318 0x000 0x10 0x000
-#define MX25_PAD_CSI_D2__UART5_RXD              0x120 0x318 0x578 0x11 0x001
+#define MX25_PAD_CSI_D2__CSI_D2                 0x120 0x318 0x000 0x00 0x000
+#define MX25_PAD_CSI_D2__UART5_RXD              0x120 0x318 0x578 0x01 0x001
 #define MX25_PAD_CSI_D2__SIM1_CLK0              0x120 0x318 0x000 0x04 0x000
-#define MX25_PAD_CSI_D2__GPIO_1_27              0x120 0x318 0x000 0x15 0x000
-#define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x17 0x000
+#define MX25_PAD_CSI_D2__GPIO_1_27              0x120 0x318 0x000 0x05 0x000
+#define MX25_PAD_CSI_D2__CSPI3_MOSI             0x120 0x318 0x000 0x07 0x000
 
-#define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x10 0x000
-#define MX25_PAD_CSI_D3__UART5_TXD              0x124 0x31c 0x000 0x11 0x000
+#define MX25_PAD_CSI_D3__CSI_D3                 0x124 0x31c 0x000 0x00 0x000
+#define MX25_PAD_CSI_D3__UART5_TXD              0x124 0x31c 0x000 0x01 0x000
 #define MX25_PAD_CSI_D3__SIM1_RST0              0x124 0x31c 0x000 0x04 0x000
-#define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x15 0x000
-#define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x17 0x001
+#define MX25_PAD_CSI_D3__GPIO_1_28              0x124 0x31c 0x000 0x05 0x000
+#define MX25_PAD_CSI_D3__CSPI3_MISO             0x124 0x31c 0x4b4 0x07 0x001
 
 #define MX25_PAD_CSI_D4__CSI_D4                 0x128 0x320 0x000 0x00 0x000
 #define MX25_PAD_CSI_D4__UART5_RTS              0x128 0x320 0x574 0x01 0x001
@@ -312,80 +312,80 @@
 #define MX25_PAD_CSI_D4__GPIO_1_29              0x128 0x320 0x000 0x05 0x000
 #define MX25_PAD_CSI_D4__CSPI3_SCLK             0x128 0x320 0x000 0x07 0x000
 
-#define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x10 0x000
-#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x11 0x000
+#define MX25_PAD_CSI_D5__CSI_D5                 0x12c 0x324 0x000 0x00 0x000
+#define MX25_PAD_CSI_D5__UART5_CTS              0x12c 0x324 0x000 0x01 0x000
 #define MX25_PAD_CSI_D5__SIM1_TX0               0x12c 0x324 0x000 0x04 0x000
-#define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x15 0x000
-#define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x17 0x000
+#define MX25_PAD_CSI_D5__GPIO_1_30              0x12c 0x324 0x000 0x05 0x000
+#define MX25_PAD_CSI_D5__CSPI3_RDY              0x12c 0x324 0x000 0x07 0x000
 
-#define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x10 0x000
-#define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x12 0x001
+#define MX25_PAD_CSI_D6__CSI_D6                 0x130 0x328 0x000 0x00 0x000
+#define MX25_PAD_CSI_D6__SDHC2_CMD              0x130 0x328 0x4e0 0x02 0x001
 #define MX25_PAD_CSI_D6__SIM1_PD0               0x130 0x328 0x000 0x04 0x000
-#define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x15 0x000
+#define MX25_PAD_CSI_D6__GPIO_1_31              0x130 0x328 0x000 0x05 0x000
 
-#define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x10 0x000
-#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          0x134 0x32C 0x4dc 0x12 0x001
-#define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x15 0x000
+#define MX25_PAD_CSI_D7__CSI_D7                 0x134 0x32c 0x000 0x00 0x000
+#define MX25_PAD_CSI_D7__SDHC2_DAT_CLK          0x134 0x32C 0x4dc 0x02 0x001
+#define MX25_PAD_CSI_D7__GPIO_1_6               0x134 0x32c 0x000 0x05 0x000
 
-#define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x10 0x000
-#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x12 0x000
-#define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x15 0x000
-#define MX25_PAD_CSI_D8__CSPI3_SS2              0x138 0x330 0x4c4 0x17 0x000
+#define MX25_PAD_CSI_D8__CSI_D8                 0x138 0x330 0x000 0x00 0x000
+#define MX25_PAD_CSI_D8__AUD6_RXC               0x138 0x330 0x000 0x02 0x000
+#define MX25_PAD_CSI_D8__GPIO_1_7               0x138 0x330 0x000 0x05 0x000
+#define MX25_PAD_CSI_D8__CSPI3_SS2              0x138 0x330 0x4c4 0x07 0x000
 
-#define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x10 0x000
-#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x12 0x000
-#define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x15 0x000
-#define MX25_PAD_CSI_D9__CSPI3_SS3              0x13c 0x334 0x4c8 0x17 0x000
+#define MX25_PAD_CSI_D9__CSI_D9                 0x13c 0x334 0x000 0x00 0x000
+#define MX25_PAD_CSI_D9__AUD6_RXFS              0x13c 0x334 0x000 0x02 0x000
+#define MX25_PAD_CSI_D9__GPIO_4_21              0x13c 0x334 0x000 0x05 0x000
+#define MX25_PAD_CSI_D9__CSPI3_SS3              0x13c 0x334 0x4c8 0x07 0x000
 
-#define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x10 0x000
-#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x11 0x000
-#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x12 0x001
-#define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x15 0x000
+#define MX25_PAD_CSI_MCLK__CSI_MCLK             0x140 0x338 0x000 0x00 0x000
+#define MX25_PAD_CSI_MCLK__AUD6_TXD             0x140 0x338 0x000 0x01 0x000
+#define MX25_PAD_CSI_MCLK__SDHC2_DAT0           0x140 0x338 0x4e4 0x02 0x001
+#define MX25_PAD_CSI_MCLK__GPIO_1_8             0x140 0x338 0x000 0x05 0x000
 
-#define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x10 0x000
-#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x11 0x000
-#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x12 0x001
-#define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x15 0x000
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC           0x144 0x33c 0x000 0x00 0x000
+#define MX25_PAD_CSI_VSYNC__AUD6_RXD            0x144 0x33c 0x000 0x01 0x000
+#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1          0x144 0x33c 0x4e8 0x02 0x001
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9            0x144 0x33c 0x000 0x05 0x000
 
-#define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x10 0x000
-#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x11 0x000
-#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x12 0x001
-#define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x15 0x000
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC           0x148 0x340 0x000 0x00 0x000
+#define MX25_PAD_CSI_HSYNC__AUD6_TXC            0x148 0x340 0x000 0x01 0x000
+#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2          0x148 0x340 0x4ec 0x02 0x001
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10           0x148 0x340 0x000 0x05 0x000
 
-#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x10 0x000
-#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x11 0x000
-#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x12 0x001
-#define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x15 0x000
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK         0x14c 0x344 0x000 0x00 0x000
+#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS          0x14c 0x344 0x000 0x01 0x000
+#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3         0x14c 0x344 0x4f0 0x02 0x001
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11          0x14c 0x344 0x000 0x05 0x000
 
-#define MX25_PAD_I2C1_CLK__I2C1_CLK             0x150 0x348 0x000 0x10 0x000
-#define MX25_PAD_I2C1_CLK__GPIO_1_12            0x150 0x348 0x000 0x15 0x000
+#define MX25_PAD_I2C1_CLK__I2C1_CLK             0x150 0x348 0x000 0x00 0x000
+#define MX25_PAD_I2C1_CLK__GPIO_1_12            0x150 0x348 0x000 0x05 0x000
 
-#define MX25_PAD_I2C1_DAT__I2C1_DAT             0x154 0x34c 0x000 0x10 0x000
-#define MX25_PAD_I2C1_DAT__GPIO_1_13            0x154 0x34c 0x000 0x15 0x000
+#define MX25_PAD_I2C1_DAT__I2C1_DAT             0x154 0x34c 0x000 0x00 0x000
+#define MX25_PAD_I2C1_DAT__GPIO_1_13            0x154 0x34c 0x000 0x05 0x000
 
-#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI         0x158 0x350 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_MOSI__UART3_RXD          0x158 0x350 0x568 0x12 0x000
-#define MX25_PAD_CSPI1_MOSI__GPIO_1_14          0x158 0x350 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI         0x158 0x350 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_MOSI__UART3_RXD          0x158 0x350 0x568 0x02 0x000
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14          0x158 0x350 0x000 0x05 0x000
 
-#define MX25_PAD_CSPI1_MISO__CSPI1_MISO         0x15c 0x354 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_MISO__UART3_TXD          0x15c 0x354 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_MISO__GPIO_1_15          0x15c 0x354 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO         0x15c 0x354 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_MISO__UART3_TXD          0x15c 0x354 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15          0x15c 0x354 0x000 0x05 0x000
 
-#define MX25_PAD_CSPI1_SS0__CSPI1_SS0           0x160 0x358 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_SS0__PWM2_PWMO           0x160 0x358 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_SS0__GPIO_1_16           0x160 0x358 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0           0x160 0x358 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_SS0__PWM2_PWMO           0x160 0x358 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16           0x160 0x358 0x000 0x05 0x000
 
 #define MX25_PAD_CSPI1_SS1__CSPI1_SS1           0x164 0x35c 0x000 0x00 0x000
 #define MX25_PAD_CSPI1_SS1__I2C3_DAT            0x164 0x35C 0x528 0x01 0x001
 #define MX25_PAD_CSPI1_SS1__UART3_RTS           0x164 0x35c 0x000 0x02 0x000
 #define MX25_PAD_CSPI1_SS1__GPIO_1_17           0x164 0x35c 0x000 0x05 0x000
 
-#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK         0x168 0x360 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_SCLK__UART3_CTS          0x168 0x360 0x000 0x12 0x000
-#define MX25_PAD_CSPI1_SCLK__GPIO_1_18          0x168 0x360 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK         0x168 0x360 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_SCLK__UART3_CTS          0x168 0x360 0x000 0x02 0x000
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18          0x168 0x360 0x000 0x05 0x000
 
-#define MX25_PAD_CSPI1_RDY__CSPI1_RDY           0x16c 0x364 0x000 0x10 0x000
-#define MX25_PAD_CSPI1_RDY__GPIO_2_22           0x16c 0x364 0x000 0x15 0x000
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY           0x16c 0x364 0x000 0x00 0x000
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22           0x16c 0x364 0x000 0x05 0x000
 
 #define MX25_PAD_UART1_RXD__UART1_RXD           0x170 0x368 0x000 0x00 0x000
 #define MX25_PAD_UART1_RXD__UART2_DTR           0x170 0x368 0x000 0x03 0x000
@@ -406,46 +406,55 @@
 #define MX25_PAD_UART1_CTS__UART2_RI            0x17c 0x374 0x000 0x03 0x001
 #define MX25_PAD_UART1_CTS__GPIO_4_25           0x17c 0x374 0x000 0x05 0x000
 
-#define MX25_PAD_UART2_RXD__UART2_RXD           0x180 0x378 0x000 0x10 0x000
-#define MX25_PAD_UART2_RXD__GPIO_4_26           0x180 0x378 0x000 0x15 0x000
+#define MX25_PAD_UART2_RXD__UART2_RXD           0x180 0x378 0x000 0x00 0x000
+#define MX25_PAD_UART2_RXD__GPIO_4_26           0x180 0x378 0x000 0x05 0x000
 
-#define MX25_PAD_UART2_TXD__UART2_TXD           0x184 0x37c 0x000 0x10 0x000
-#define MX25_PAD_UART2_TXD__GPIO_4_27           0x184 0x37c 0x000 0x15 0x000
+#define MX25_PAD_UART2_TXD__UART2_TXD           0x184 0x37c 0x000 0x00 0x000
+#define MX25_PAD_UART2_TXD__GPIO_4_27           0x184 0x37c 0x000 0x05 0x000
 
 #define MX25_PAD_UART2_RTS__UART2_RTS           0x188 0x380 0x000 0x00 0x000
 #define MX25_PAD_UART2_RTS__FEC_COL             0x188 0x380 0x504 0x02 0x002
 #define MX25_PAD_UART2_RTS__CC1                 0x188 0x380 0x000 0x03 0x000
 #define MX25_PAD_UART2_RTS__GPIO_4_28           0x188 0x380 0x000 0x05 0x000
 
-#define MX25_PAD_UART2_CTS__UART2_CTS           0x18c 0x384 0x000 0x10 0x000
-#define MX25_PAD_UART2_CTS__FEC_RX_ERR          0x18c 0x384 0x518 0x12 0x002
-#define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x15 0x000
+#define MX25_PAD_UART2_CTS__UART2_CTS           0x18c 0x384 0x000 0x00 0x000
+#define MX25_PAD_UART2_CTS__FEC_RX_ERR          0x18c 0x384 0x518 0x02 0x002
+#define MX25_PAD_UART2_CTS__GPIO_4_29           0x18c 0x384 0x000 0x05 0x000
 
+/*
+ * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
+ * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
+ * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
+ * bug that configuring the SD1_CMD function doesn't enable the input path for
+ * this pin.
+ * This might have side effects for other hardware units that are connected to
+ * that pin and use the respective function as input.
+ */
 #define MX25_PAD_SD1_CMD__SD1_CMD               0x190 0x388 0x000 0x10 0x000
-#define MX25_PAD_SD1_CMD__CSPI2_MOSI            0x190 0x388 0x4a0 0x11 0x001
-#define MX25_PAD_SD1_CMD__FEC_RDATA2            0x190 0x388 0x50c 0x12 0x002
-#define MX25_PAD_SD1_CMD__GPIO_2_23             0x190 0x388 0x000 0x15 0x000
+#define MX25_PAD_SD1_CMD__CSPI2_MOSI            0x190 0x388 0x4a0 0x01 0x001
+#define MX25_PAD_SD1_CMD__FEC_RDATA2            0x190 0x388 0x50c 0x02 0x002
+#define MX25_PAD_SD1_CMD__GPIO_2_23             0x190 0x388 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_CLK__SD1_CLK               0x194 0x38c 0x000 0x10 0x000
-#define MX25_PAD_SD1_CLK__CSPI2_MISO            0x194 0x38c 0x49c 0x11 0x001
-#define MX25_PAD_SD1_CLK__FEC_RDATA3            0x194 0x38c 0x510 0x12 0x002
-#define MX25_PAD_SD1_CLK__GPIO_2_24             0x194 0x38c 0x000 0x15 0x000
+#define MX25_PAD_SD1_CLK__SD1_CLK               0x194 0x38c 0x000 0x00 0x000
+#define MX25_PAD_SD1_CLK__CSPI2_MISO            0x194 0x38c 0x49c 0x01 0x001
+#define MX25_PAD_SD1_CLK__FEC_RDATA3            0x194 0x38c 0x510 0x02 0x002
+#define MX25_PAD_SD1_CLK__GPIO_2_24             0x194 0x38c 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA0__SD1_DATA0           0x198 0x390 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA0__CSPI2_SCLK          0x198 0x390 0x494 0x11 0x001
-#define MX25_PAD_SD1_DATA0__GPIO_2_25           0x198 0x390 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA0__SD1_DATA0           0x198 0x390 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA0__CSPI2_SCLK          0x198 0x390 0x494 0x01 0x001
+#define MX25_PAD_SD1_DATA0__GPIO_2_25           0x198 0x390 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA1__SD1_DATA1           0x19c 0x394 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA1__AUD7_RXD            0x19c 0x394 0x478 0x13 0x000
-#define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA1__SD1_DATA1           0x19c 0x394 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA1__AUD7_RXD            0x19c 0x394 0x478 0x03 0x000
+#define MX25_PAD_SD1_DATA1__GPIO_2_26           0x19c 0x394 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x12 0x002
-#define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA2__SD1_DATA2           0x1a0 0x398 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK          0x1a0 0x398 0x514 0x02 0x002
+#define MX25_PAD_SD1_DATA2__GPIO_2_27           0x1a0 0x398 0x000 0x05 0x000
 
-#define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x10 0x000
-#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x12 0x002
-#define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x15 0x000
+#define MX25_PAD_SD1_DATA3__SD1_DATA3           0x1a4 0x39c 0x000 0x00 0x000
+#define MX25_PAD_SD1_DATA3__FEC_CRS             0x1a4 0x39c 0x508 0x02 0x002
+#define MX25_PAD_SD1_DATA3__GPIO_2_28           0x1a4 0x39c 0x000 0x05 0x000
 
 #define MX25_PAD_KPP_ROW0__KPP_ROW0             0x1a8 0x3a0 0x000 0x00 0x000
 #define MX25_PAD_KPP_ROW0__UART3_RXD            0x1a8 0x3a0 0x568 0x01 0x001
@@ -469,123 +478,123 @@
 #define MX25_PAD_KPP_ROW3__UART1_RI             0x1b4 0x3ac 0x000 0x04 0x000
 #define MX25_PAD_KPP_ROW3__GPIO_3_0             0x1b4 0x3ac 0x000 0x05 0x000
 
-#define MX25_PAD_KPP_COL0__KPP_COL0             0x1b8 0x3b0 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL0__UART4_RXD            0x1b8 0x3b0 0x570 0x11 0x001
-#define MX25_PAD_KPP_COL0__AUD5_TXD             0x1b8 0x3b0 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL0__GPIO_3_1             0x1b8 0x3b0 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL0__KPP_COL0             0x1b8 0x3b0 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL0__UART4_RXD            0x1b8 0x3b0 0x570 0x01 0x001
+#define MX25_PAD_KPP_COL0__AUD5_TXD             0x1b8 0x3b0 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL0__GPIO_3_1             0x1b8 0x3b0 0x000 0x05 0x000
 
-#define MX25_PAD_KPP_COL1__KPP_COL1             0x1bc 0x3b4 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL1__UART4_TXD            0x1bc 0x3b4 0x000 0x11 0x000
-#define MX25_PAD_KPP_COL1__AUD5_RXD             0x1bc 0x3b4 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL1__GPIO_3_2             0x1bc 0x3b4 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL1__KPP_COL1             0x1bc 0x3b4 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL1__UART4_TXD            0x1bc 0x3b4 0x000 0x01 0x000
+#define MX25_PAD_KPP_COL1__AUD5_RXD             0x1bc 0x3b4 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL1__GPIO_3_2             0x1bc 0x3b4 0x000 0x05 0x000
 
 #define MX25_PAD_KPP_COL2__KPP_COL2             0x1c0 0x3b8 0x000 0x00 0x000
 #define MX25_PAD_KPP_COL2__UART4_RTS            0x1c0 0x3b8 0x56c 0x01 0x001
 #define MX25_PAD_KPP_COL2__AUD5_TXC             0x1c0 0x3b8 0x000 0x02 0x000
 #define MX25_PAD_KPP_COL2__GPIO_3_3             0x1c0 0x3b8 0x000 0x05 0x000
 
-#define MX25_PAD_KPP_COL3__KPP_COL3             0x1c4 0x3bc 0x000 0x10 0x000
-#define MX25_PAD_KPP_COL3__UART4_CTS            0x1c4 0x3bc 0x000 0x11 0x000
-#define MX25_PAD_KPP_COL3__AUD5_TXFS            0x1c4 0x3bc 0x000 0x12 0x000
-#define MX25_PAD_KPP_COL3__GPIO_3_4             0x1c4 0x3bc 0x000 0x15 0x000
+#define MX25_PAD_KPP_COL3__KPP_COL3             0x1c4 0x3bc 0x000 0x00 0x000
+#define MX25_PAD_KPP_COL3__UART4_CTS            0x1c4 0x3bc 0x000 0x01 0x000
+#define MX25_PAD_KPP_COL3__AUD5_TXFS            0x1c4 0x3bc 0x000 0x02 0x000
+#define MX25_PAD_KPP_COL3__GPIO_3_4             0x1c4 0x3bc 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_MDC__FEC_MDC               0x1c8 0x3c0 0x000 0x10 0x000
-#define MX25_PAD_FEC_MDC__AUD4_TXD              0x1c8 0x3c0 0x464 0x12 0x001
-#define MX25_PAD_FEC_MDC__GPIO_3_5              0x1c8 0x3c0 0x000 0x15 0x000
+#define MX25_PAD_FEC_MDC__FEC_MDC               0x1c8 0x3c0 0x000 0x00 0x000
+#define MX25_PAD_FEC_MDC__AUD4_TXD              0x1c8 0x3c0 0x464 0x02 0x001
+#define MX25_PAD_FEC_MDC__GPIO_3_5              0x1c8 0x3c0 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_MDIO__FEC_MDIO             0x1cc 0x3c4 0x000 0x10 0x000
-#define MX25_PAD_FEC_MDIO__AUD4_RXD             0x1cc 0x3c4 0x460 0x12 0x001
-#define MX25_PAD_FEC_MDIO__GPIO_3_6             0x1cc 0x3c4 0x000 0x15 0x000
+#define MX25_PAD_FEC_MDIO__FEC_MDIO             0x1cc 0x3c4 0x000 0x00 0x000
+#define MX25_PAD_FEC_MDIO__AUD4_RXD             0x1cc 0x3c4 0x460 0x02 0x001
+#define MX25_PAD_FEC_MDIO__GPIO_3_6             0x1cc 0x3c4 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x1d0 0x3c8 0x000 0x10 0x000
-#define MX25_PAD_FEC_TDATA0__GPIO_3_7           0x1d0 0x3c8 0x000 0x15 0x000
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x1d0 0x3c8 0x000 0x00 0x000
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7           0x1d0 0x3c8 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x1d4 0x3cc 0x000 0x10 0x000
-#define MX25_PAD_FEC_TDATA1__AUD4_TXFS          0x1d4 0x3cc 0x474 0x12 0x001
-#define MX25_PAD_FEC_TDATA1__GPIO_3_8           0x1d4 0x3cc 0x000 0x15 0x000
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x1d4 0x3cc 0x000 0x00 0x000
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS          0x1d4 0x3cc 0x474 0x02 0x001
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8           0x1d4 0x3cc 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x1d8 0x3d0 0x000 0x10 0x000
-#define MX25_PAD_FEC_TX_EN__GPIO_3_9            0x1d8 0x3d0 0x000 0x15 0x000
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x1d8 0x3d0 0x000 0x00 0x000
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9            0x1d8 0x3d0 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x1dc 0x3d4 0x000 0x10 0x000
-#define MX25_PAD_FEC_RDATA0__GPIO_3_10          0x1dc 0x3d4 0x000 0x15 0x000
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x1dc 0x3d4 0x000 0x00 0x000
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10          0x1dc 0x3d4 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x1e0 0x3d8 0x000 0x10 0x000
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x1e0 0x3d8 0x000 0x00 0x000
 /*
  * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
  * 01/2011) this is CAN1_TX but that's wrong.
  */
-#define MX25_PAD_FEC_RDATA1__CAN2_TX            0x1e0 0x3d8 0x000 0x14 0x000
-#define MX25_PAD_FEC_RDATA1__GPIO_3_11          0x1e0 0x3d8 0x000 0x15 0x000
+#define MX25_PAD_FEC_RDATA1__CAN2_TX            0x1e0 0x3d8 0x000 0x04 0x000
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11          0x1e0 0x3d8 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x1e4 0x3dc 0x000 0x10 0x000
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x1e4 0x3dc 0x000 0x00 0x000
 /*
  * According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
  * 01/2011) this is CAN1_RX but that's wrong.
  */
-#define MX25_PAD_FEC_RX_DV__CAN2_RX             0x1e4 0x3dc 0x484 0x14 0x000
-#define MX25_PAD_FEC_RX_DV__GPIO_3_12           0x1e4 0x3dc 0x000 0x15 0x000
+#define MX25_PAD_FEC_RX_DV__CAN2_RX             0x1e4 0x3dc 0x484 0x04 0x000
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12           0x1e4 0x3dc 0x000 0x05 0x000
 
-#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1e8 0x3e0 0x000 0x10 0x000
-#define MX25_PAD_FEC_TX_CLK__GPIO_3_13          0x1e8 0x3e0 0x000 0x15 0x000
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1e8 0x3e0 0x000 0x00 0x000
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13          0x1e8 0x3e0 0x000 0x05 0x000
 
-#define MX25_PAD_RTCK__RTCK                     0x1ec 0x3e4 0x000 0x10 0x000
-#define MX25_PAD_RTCK__OWIRE                    0x1ec 0x3e4 0x000 0x11 0x000
-#define MX25_PAD_RTCK__GPIO_3_14                0x1ec 0x3e4 0x000 0x15 0x000
+#define MX25_PAD_RTCK__RTCK                     0x1ec 0x3e4 0x000 0x00 0x000
+#define MX25_PAD_RTCK__OWIRE                    0x1ec 0x3e4 0x000 0x01 0x000
+#define MX25_PAD_RTCK__GPIO_3_14                0x1ec 0x3e4 0x000 0x05 0x000
 
-#define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x10 0x000
-#define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x15 0x000
+#define MX25_PAD_DE_B__DE_B                     0x1f0 0x3ec 0x000 0x00 0x000
+#define MX25_PAD_DE_B__GPIO_2_20                0x1f0 0x3ec 0x000 0x05 0x000
 
-#define MX25_PAD_GPIO_A__GPIO_A                 0x1f4 0x3f0 0x000 0x10 0x000
-#define MX25_PAD_GPIO_A__CAN1_TX                0x1f4 0x3f0 0x000 0x16 0x000
-#define MX25_PAD_GPIO_A__USBOTG_PWR             0x1f4 0x3f0 0x000 0x12 0x000
+#define MX25_PAD_GPIO_A__GPIO_A                 0x1f4 0x3f0 0x000 0x00 0x000
+#define MX25_PAD_GPIO_A__CAN1_TX                0x1f4 0x3f0 0x000 0x06 0x000
+#define MX25_PAD_GPIO_A__USBOTG_PWR             0x1f4 0x3f0 0x000 0x02 0x000
 
-#define MX25_PAD_GPIO_B__GPIO_B                 0x1f8 0x3f4 0x000 0x10 0x000
-#define MX25_PAD_GPIO_B__USBOTG_OC              0x1f8 0x3f4 0x57c 0x12 0x001
-#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x16 0x001
+#define MX25_PAD_GPIO_B__GPIO_B                 0x1f8 0x3f4 0x000 0x00 0x000
+#define MX25_PAD_GPIO_B__USBOTG_OC              0x1f8 0x3f4 0x57c 0x02 0x001
+#define MX25_PAD_GPIO_B__CAN1_RX                0x1f8 0x3f4 0x480 0x06 0x001
 
-#define MX25_PAD_GPIO_C__GPIO_C                 0x1fc 0x3f8 0x000 0x10 0x000
-#define MX25_PAD_GPIO_C__PWM4_PWMO              0x1fc 0x3f8 0x000 0x11 0x000
-#define MX25_PAD_GPIO_C__I2C2_SCL               0x1fc 0x3f8 0x51c 0x12 0x001
-#define MX25_PAD_GPIO_C__KPP_COL4               0x1fc 0x3f8 0x52c 0x13 0x001
-#define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x16 0x000
+#define MX25_PAD_GPIO_C__GPIO_C                 0x1fc 0x3f8 0x000 0x00 0x000
+#define MX25_PAD_GPIO_C__PWM4_PWMO              0x1fc 0x3f8 0x000 0x01 0x000
+#define MX25_PAD_GPIO_C__I2C2_SCL               0x1fc 0x3f8 0x51c 0x02 0x001
+#define MX25_PAD_GPIO_C__KPP_COL4               0x1fc 0x3f8 0x52c 0x03 0x001
+#define MX25_PAD_GPIO_C__CAN2_TX                0x1fc 0x3f8 0x000 0x06 0x000
 
-#define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x10 0x000
-#define MX25_PAD_GPIO_D__I2C2_SDA               0x200 0x3fc 0x520 0x12 0x001
-#define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x16 0x001
+#define MX25_PAD_GPIO_D__GPIO_D                 0x200 0x3fc 0x000 0x00 0x000
+#define MX25_PAD_GPIO_D__I2C2_SDA               0x200 0x3fc 0x520 0x02 0x001
+#define MX25_PAD_GPIO_D__CAN2_RX                0x200 0x3fc 0x484 0x06 0x001
 
-#define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x10 0x000
-#define MX25_PAD_GPIO_E__I2C3_CLK               0x204 0x400 0x524 0x11 0x002
-#define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x12 0x000
-#define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x14 0x000
-#define MX25_PAD_GPIO_E__UART4_RXD              0x204 0x400 0x570 0x16 0x002
+#define MX25_PAD_GPIO_E__GPIO_E                 0x204 0x400 0x000 0x00 0x000
+#define MX25_PAD_GPIO_E__I2C3_CLK               0x204 0x400 0x524 0x01 0x002
+#define MX25_PAD_GPIO_E__LD16                   0x204 0x400 0x000 0x02 0x000
+#define MX25_PAD_GPIO_E__AUD7_TXD               0x204 0x400 0x000 0x04 0x000
+#define MX25_PAD_GPIO_E__UART4_RXD              0x204 0x400 0x570 0x06 0x002
 
-#define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x10 0x000
-#define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x12 0x000
-#define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x14 0x000
-#define MX25_PAD_GPIO_F__UART4_TXD              0x208 0x404 0x000 0x16 0x000
+#define MX25_PAD_GPIO_F__GPIO_F                 0x208 0x404 0x000 0x00 0x000
+#define MX25_PAD_GPIO_F__LD17                   0x208 0x404 0x000 0x02 0x000
+#define MX25_PAD_GPIO_F__AUD7_TXC               0x208 0x404 0x000 0x04 0x000
+#define MX25_PAD_GPIO_F__UART4_TXD              0x208 0x404 0x000 0x06 0x000
 
-#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x10 0x000
-#define MX25_PAD_EXT_ARMCLK__GPIO_3_15          0x20c 0x000 0x000 0x15 0x000
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK         0x20c 0x000 0x000 0x00 0x000
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15          0x20c 0x000 0x000 0x05 0x000
 
-#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK       0x210 0x000 0x000 0x10 0x000
-#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16         0x210 0x000 0x000 0x15 0x000
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK       0x210 0x000 0x000 0x00 0x000
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16         0x210 0x000 0x000 0x05 0x000
 
 #define MX25_PAD_VSTBY_REQ__VSTBY_REQ           0x214 0x408 0x000 0x00 0x000
 #define MX25_PAD_VSTBY_REQ__AUD7_TXFS           0x214 0x408 0x000 0x04 0x000
 #define MX25_PAD_VSTBY_REQ__GPIO_3_17           0x214 0x408 0x000 0x05 0x000
 #define MX25_PAD_VSTBY_REQ__UART4_RTS           0x214 0x408 0x56c 0x06 0x002
 
-#define MX25_PAD_VSTBY_ACK__VSTBY_ACK           0x218 0x40c 0x000 0x10 0x000
-#define MX25_PAD_VSTBY_ACK__GPIO_3_18           0x218 0x40c 0x000 0x15 0x000
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK           0x218 0x40c 0x000 0x00 0x000
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18           0x218 0x40c 0x000 0x05 0x000
 
-#define MX25_PAD_POWER_FAIL__POWER_FAIL         0x21c 0x410 0x000 0x10 0x000
-#define MX25_PAD_POWER_FAIL__AUD7_RXD           0x21c 0x410 0x478 0x14 0x001
-#define MX25_PAD_POWER_FAIL__GPIO_3_19          0x21c 0x410 0x000 0x15 0x000
-#define MX25_PAD_POWER_FAIL__UART4_CTS          0x21c 0x410 0x000 0x16 0x000
+#define MX25_PAD_POWER_FAIL__POWER_FAIL         0x21c 0x410 0x000 0x00 0x000
+#define MX25_PAD_POWER_FAIL__AUD7_RXD           0x21c 0x410 0x478 0x04 0x001
+#define MX25_PAD_POWER_FAIL__GPIO_3_19          0x21c 0x410 0x000 0x05 0x000
+#define MX25_PAD_POWER_FAIL__UART4_CTS          0x21c 0x410 0x000 0x06 0x000
 
-#define MX25_PAD_CLKO__CLKO                     0x220 0x414 0x000 0x10 0x000
-#define MX25_PAD_CLKO__GPIO_2_21                0x220 0x414 0x000 0x15 0x000
+#define MX25_PAD_CLKO__CLKO                     0x220 0x414 0x000 0x00 0x000
+#define MX25_PAD_CLKO__GPIO_2_21                0x220 0x414 0x000 0x05 0x000
 
 #define MX25_PAD_BOOT_MODE0__BOOT_MODE0         0x224 0x000 0x000 0x00 0x000
 #define MX25_PAD_BOOT_MODE0__GPIO_4_30          0x224 0x000 0x000 0x05 0x000
diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
index e2242638ea0b..2cf896c505f9 100644
--- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
@@ -77,7 +77,7 @@
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
index 2ab65fc4c1e1..27846ff9bb0d 100644
--- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -140,21 +140,21 @@
 };
 
 &uart1 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
         status = "okay";
 };
 
 &uart2 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
         status = "okay";
 };
 
 &uart3 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 49450dbbcab8..d0ef496a1af8 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -106,7 +106,7 @@
 };
 
 &uart1 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 7c869fe3c30b..bfd4946cf9fe 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -147,21 +147,21 @@
 };
 
 &uart1 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
         status = "okay";
 };
 
 &uart2 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
         status = "okay";
 };
 
 &uart3 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 538568b0de26..cf09e72aeb06 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -283,14 +283,14 @@
 };
 
 &uart1 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
         status = "okay";
 };
 
 &uart2 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
         status = "okay";
diff --git a/arch/arm/boot/dts/imx28-apf28dev.dts b/arch/arm/boot/dts/imx28-apf28dev.dts
index 1eaa131e2d18..c4fadbc1b400 100644
--- a/arch/arm/boot/dts/imx28-apf28dev.dts
+++ b/arch/arm/boot/dts/imx28-apf28dev.dts
@@ -140,7 +140,7 @@
                         auart0: serial@8006a000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&auart0_pins_a>;
-                                fsl,uart-has-rtscts;
+                                uart-has-rtscts;
                                 status = "okay";
                         };
 
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index ef944b6d4f01..a9c347e48bcf 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -426,7 +426,7 @@
 
         };
 
-        onewire@0 {
+        onewire {
                 compatible = "w1-gpio";
                 pinctrl-names = "default";
                 pinctrl-0 = <&w1_gpio_pins>;
diff --git a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
index 88594747f454..581e85f4fd4c 100644
--- a/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
+++ b/arch/arm/boot/dts/imx28-eukrea-mbmx28lc.dtsi
@@ -84,6 +84,7 @@
 
                 reg_3p3v: regulator@0 {
                         compatible = "regulator-fixed";
+                        reg = <0>;
                         regulator-name = "3P3V";
                         regulator-min-microvolt = <3300000>;
                         regulator-max-microvolt = <3300000>;
@@ -92,6 +93,7 @@
 
                 reg_lcd_3v3: regulator@1 {
                         compatible = "regulator-fixed";
+                        reg = <1>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&reg_lcd_3v3_pins_mbmx28lc>;
                         regulator-name = "lcd-3v3";
@@ -103,6 +105,7 @@
 
                 reg_usb0_vbus: regulator@2 {
                         compatible = "regulator-fixed";
+                        reg = <2>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&reg_usb0_vbus_pins_mbmx28lc>;
                         regulator-name = "usb0_vbus";
@@ -114,6 +117,7 @@
 
                 reg_usb1_vbus: regulator@3 {
                         compatible = "regulator-fixed";
+                        reg = <3>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&reg_usb1_vbus_pins_mbmx28lc>;
                         regulator-name = "usb1_vbus";
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index e3ef94ac159f..a5ba669b4eaa 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -224,7 +224,7 @@
                         auart0: serial@8006a000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&auart0_pins_a>;
-                                fsl,uart-has-rtscts;
+                                uart-has-rtscts;
                                 status = "okay";
                         };
 
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index fd20e99c777e..0ebbc83852d0 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -173,7 +173,7 @@
                 default-brightness-level = <50>;
         };
 
-        matrix_keypad: matrix-keypad@0 {
+        matrix_keypad: matrix-keypad {
                 compatible = "gpio-matrix-keypad";
                 col-gpios = <
                         &gpio5 0 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 74aa151cdb45..0ad893bf5f43 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -165,6 +165,7 @@
 
                                 gpio0: gpio@0 {
                                         compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+                                        reg = <0>;
                                         interrupts = <127>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -174,6 +175,7 @@
 
                                 gpio1: gpio@1 {
                                         compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+                                        reg = <1>;
                                         interrupts = <126>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -183,6 +185,7 @@
 
                                 gpio2: gpio@2 {
                                         compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+                                        reg = <2>;
                                         interrupts = <125>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -192,6 +195,7 @@
 
                                 gpio3: gpio@3 {
                                         compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+                                        reg = <3>;
                                         interrupts = <124>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
@@ -201,6 +205,7 @@
 
                                 gpio4: gpio@4 {
                                         compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+                                        reg = <4>;
                                         interrupts = <123>;
                                         gpio-controller;
                                         #gpio-cells = <2>;
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
index 2424abfc9c7b..ae6cebbed84b 100644
--- a/arch/arm/boot/dts/imx31-bug.dts
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -22,6 +22,6 @@
 };
 
 &uart5 {
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index 4727bbb804e1..e9357131b026 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -139,14 +139,14 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts
index 8d715523708f..9bb628f22502 100644
--- a/arch/arm/boot/dts/imx35-pdk.dts
+++ b/arch/arm/boot/dts/imx35-pdk.dts
@@ -63,6 +63,6 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 018d24eb9965..f097b4f29ab4 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -388,7 +388,7 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
@@ -401,7 +401,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index d270df3e5891..728212861ece 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -261,14 +261,14 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx51-ts4800.dts b/arch/arm/boot/dts/imx51-ts4800.dts
index 30f44b5565b9..ca1cc5eca80f 100644
--- a/arch/arm/boot/dts/imx51-ts4800.dts
+++ b/arch/arm/boot/dts/imx51-ts4800.dts
@@ -165,6 +165,27 @@
                         reg = <0x12000 0x1000>;
                         syscon = <&syscon 0x10 6>;
                 };
+
+                fpga_irqc: fpga-irqc@15000 {
+                        compatible = "technologic,ts4800-irqc";
+                        reg = <0x15000 0x1000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_interrupt_fpga>;
+                        interrupt-parent = <&gpio2>;
+                        interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                can@1a000 {
+                        compatible = "technologic,sja1000";
+                        reg = <0x1a000 0x100>;
+                        interrupt-parent = <&fpga_irqc>;
+                        interrupts = <1>;
+                        reg-io-width = <2>;
+                        nxp,tx-output-config = <0x06>;
+                        nxp,external-clock-frequency = <24000000>;
+                };
         };
 };
 
@@ -228,6 +249,12 @@
                 >;
         };
 
+        pinctrl_interrupt_fpga: fpgaicgrp {
+                fsl,pins = <
+                        MX51_PAD_EIM_D27__GPIO2_9               0xe5
+                >;
+        };
+
         pinctrl_lcd: lcdgrp {
                 fsl,pins = <
                         MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 542ab9e697fb..9f5190040555 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -56,7 +56,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index e03373a58760..91a6a9ff50d7 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -218,7 +218,7 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index bd3dfefa5778..57e75f1639e0 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -513,21 +513,21 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index bfbed52ce1bd..2becd7cd6544 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -97,6 +97,7 @@
         phy-reset-gpios = <&gpio3 31 0>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 8e67ca27ad79..207b85b91ada 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -93,7 +93,7 @@
                         reg = <0>;
 
                         lcd_display_in: endpoint {
-                                remote-endpoint = <&ipu1_di0_disp1>;
+                                remote-endpoint = <&ipu1_di1_disp1>;
                         };
                 };
 
@@ -210,7 +210,7 @@
         };
 };
 
-&ipu1_di0_disp1 {
+&ipu1_di1_disp1 {
         remote-endpoint = <&lcd_display_in>;
 };
 
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d6515f7a56c4..d8acf15611e4 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -185,6 +185,7 @@
         phy-mode = "rgmii";
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
@@ -218,7 +219,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
         fsl,dte-mode;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index f7e17e2004ac..f2adc60723da 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -351,7 +351,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index bb66dfd5294c..cf3fd31e3406 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -52,6 +52,12 @@
                 };
         };
 
+        gpio-poweroff {
+                compatible = "gpio-poweroff";
+                gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+                status = "okay";
+        };
+
         reg_wl18xx_vmmc: regulator-wl18xx {
                 compatible = "regulator-fixed";
                 regulator-name = "vwl1807";
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index 99b46f8030ad..b5de7e620905 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -3,15 +3,46 @@
  *
  * Author: Valentin Raevsky <valentin@compulab.co.il>
  *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
  *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
 #include "imx6q.dtsi"
 
 / {
@@ -31,6 +62,71 @@
                         linux,default-trigger = "heartbeat";
                 };
         };
+
+        reg_pcie_power_on_gpio: regulator-pcie-power-on-gpio {
+                compatible = "regulator-fixed";
+                regulator-name = "regulator-pcie-power-on-gpio";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usb_h1_vbus: usb_h1_vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_h1_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+
+        reg_usb_otg_vbus: usb_otg_vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "usb_otg_vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+        };
+};
+
+&cpu0 {
+        /*
+         * Although the imx6q fuse indicates that 1.2GHz operation is possible,
+         * the module behaves unstable at this frequency. Hence, remove the
+         * 1.2GHz operation point here.
+         */
+        operating-points = <
+                /* kHz  uV */
+                996000  1250000
+                852000  1250000
+                792000  1175000
+                396000  975000
+        >;
+        fsl,soc-operating-points = <
+                /* ARM kHz      SOC-PU uV */
+                996000          1250000
+                852000          1250000
+                792000          1175000
+                396000          1175000
+        >;
+};
+
+&ecspi1 {
+        fsl,spi-num-chipselects = <2>;
+        cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        status = "okay";
+
+        m25p80@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "st,m25p", "jedec,spi-nor";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
 };
 
 &fec {
@@ -46,58 +142,122 @@
         status = "okay";
 };
 
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        status = "okay";
+        clock-frequency = <100000>;
+
+        eeprom@50 {
+                compatible = "at24,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+};
+
 &iomuxc {
-        imx6q-cm-fx6 {
-                pinctrl_enet: enetgrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
-                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
-                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
-                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
-                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
-                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
-                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
-                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
-                        >;
-                };
+        pinctrl_ecspi1: ecspi1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
+                        MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
+                        MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
+                        MX6QDL_PAD_EIM_EB2__GPIO2_IO30  0x100b1
+                        MX6QDL_PAD_EIM_D19__GPIO3_IO19  0x100b1
+                >;
+        };
 
-                pinctrl_gpmi_nand: gpminandgrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
-                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
-                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
-                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
-                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
-                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
-                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
-                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
-                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
-                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
-                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
-                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
-                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
-                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
-                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
-                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
-                        >;
-                };
+        pinctrl_enet: enetgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                        MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                        MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                        MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                        MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                        MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                        MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                        MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                        MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                        MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
+                >;
+        };
 
-                pinctrl_uart4: uart4grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
-                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
-                        >;
-                };
+        pinctrl_gpmi_nand: gpminandgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                        MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                        MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                        MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                        MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                        MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                        MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                        MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                        MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                        MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                        MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                        MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                        MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                        MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                        MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                        MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                        MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                >;
+        };
+
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_3__I2C3_SCL     0x4001b8b1
+                        MX6QDL_PAD_GPIO_6__I2C3_SDA     0x4001b8b1
+                >;
+        };
+
+        pinctrl_pcie: pciegrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
+                        MX6QDL_PAD_EIM_CS1__GPIO2_IO24  0x1b0b1
+                >;
+        };
+
+        pinctrl_uart4: uart4grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                        MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                >;
         };
+
+        pinctrl_usbh1: usbh1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x1b0b1
+                >;
+        };
+
+        pinctrl_usbotg: usbotggrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
+                        MX6QDL_PAD_EIM_D22__GPIO3_IO22  0x130b0
+                >;
+        };
+};
+
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
+        vdd-supply = <&reg_pcie_power_on_gpio>;
+        status = "okay";
+};
+
+&sata {
+        status = "okay";
+};
+
+&snvs_poweroff {
+        status = "okay";
 };
 
 &uart4 {
@@ -105,3 +265,18 @@
         pinctrl-0 = <&pinctrl_uart4>;
         status = "okay";
 };
+
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        status = "okay";
+};
+
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        dr_mode = "otg";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts
new file mode 100644
index 000000000000..65e66f994f88
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-h100.dts
@@ -0,0 +1,395 @@
+/*
+ * Copyright (C) 2015 Lucas Stach <kernel@pengutronix.de>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-microsom.dtsi"
+#include "imx6qdl-microsom-ar8035.dtsi"
+
+/ {
+        model = "Auvidea H100";
+        compatible = "auvidea,h100", "fsl,imx6q";
+
+        aliases {
+                rtc0 = &rtc;
+                rtc1 = &snvs_rtc;
+        };
+
+        chosen {
+                stdout-path = &uart2;
+        };
+
+        hdmi_osc: hdmi-osc {
+                compatible = "fixed-clock";
+                clock-output-names = "hdmi-osc";
+                clock-frequency = <27000000>;
+                #clock-cells = <0>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_leds>;
+
+                led0: power {
+                        label = "power";
+                        gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                };
+
+                led1: stream {
+                        label = "stream";
+                        gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+
+                led2: rec {
+                        label = "rec";
+                        gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+
+        reg_hdmi: regulator-hdmi {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_reg_hdmi>;
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+                regulator-name = "V_HDMI";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                regulator-always-on;
+        };
+
+        reg_nvcc_sd2: regulator-nvcc-sd2 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_reg_nvcc_sd2>;
+                compatible = "regulator-gpio";
+                regulator-name = "NVCC_SD2";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-type = "voltage";
+                regulator-boot-on;
+                regulator-always-on;
+                gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+                states = <1800000 0x1
+                          3300000 0x0>;
+        };
+
+        reg_usbh1_vbus: regulator-usb-h1-vbus {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_usbh1_vbus>;
+                regulator-name = "USB_H1_VBUS";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        reg_usbotg_vbus: regulator-usb-otg-vbus {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_usbotg_vbus>;
+                regulator-name = "USB_OTG_VBUS";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        sound-sgtl5000 {
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "H100 on-board codec";
+                audio-codec = <&sgtl5000>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-ext-port = <5>;
+                mux-int-port = <1>;
+                ssi-controller = <&ssi1>;
+        };
+};
+
+&audmux {
+        status = "okay";
+};
+
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_h100_hdmi>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_h100_i2c1>;
+        status = "okay";
+
+        eeprom: 24c02@51 {
+                compatible = "microchip,24c02", "at24";
+                reg = <0x51>;
+        };
+
+        rtc: pcf8523@68 {
+                compatible = "nxp,pcf8523";
+                reg = <0x68>;
+        };
+
+        sgtl5000: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_sgtl5000>;
+                clocks = <&clks IMX6QDL_CLK_CKO>;
+                VDDA-supply = <&reg_3p3v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+
+        tc358743: tc358743@0f {
+                compatible = "toshiba,tc358743";
+                reg = <0x0f>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_h100_tc358743>;
+                clocks = <&hdmi_osc>;
+                clock-names = "refclk";
+                reset-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
+                /* IRQ has a wrong pull resistor which renders it useless  */
+
+                port@0 {
+                        tc358743_out: endpoint {
+                                remote-endpoint = <&mipi_csi2_in>;
+                                data-lanes = <1 2 3 4>;
+                                clock-lanes = <0>;
+                                clock-noncontinuous;
+                                link-frequencies = /bits/ 64 <297000000>;
+                        };
+                };
+        };
+};
+
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_h100_i2c2>;
+        status = "okay";
+};
+
+&iomuxc {
+        h100 {
+                pinctrl_h100_hdmi: h100-hdmi {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE   0x1f8b0
+                        >;
+                };
+
+                pinctrl_h100_i2c1: h100-i2c1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+
+                pinctrl_h100_i2c2: h100-i2c2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+
+                pinctrl_h100_leds: pinctrl-h100-leds {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_DA0__GPIO3_IO00          0x1b0b0
+                                MX6QDL_PAD_EIM_EB1__GPIO2_IO29          0x1b0b0
+                                MX6QDL_PAD_EIM_EB0__GPIO2_IO28          0x1b0b0
+                        >;
+                };
+
+                pinctrl_h100_reg_hdmi: h100-reg-hdmi {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A18__GPIO2_IO20          0x1b0b0
+                        >;
+                };
+
+                pinctrl_h100_reg_nvcc_sd2: h100-reg-nvcc-sd2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x1b0b0
+                        >;
+                };
+
+                pinctrl_h100_sgtl5000: h100-sgtl5000 {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
+                                MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
+                                MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x110b0
+                                MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
+                                MX6QDL_PAD_GPIO_5__CCM_CLKO1            0x130b0
+                        >;
+                };
+
+                pinctrl_h100_tc358743: h100-tc358743 {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x1b0b0
+                        >;
+                };
+
+                pinctrl_h100_uart2: h100-uart2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
+                                MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
+                        >;
+                };
+
+                pinctrl_h100_usbh1_vbus: hummingboard-usbh1-vbus {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
+                        >;
+                };
+
+                pinctrl_h100_usbotg_id: hummingboard-usbotg-id {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x13059
+                        >;
+                };
+
+                pinctrl_h100_usbotg_vbus: hummingboard-usbotg-vbus {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
+                        >;
+                };
+
+                pinctrl_h100_usdhc2: h100-usdhc2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1f071
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x13059
+                        >;
+                };
+
+                pinctrl_h100_usdhc2_100mhz: h100-usdhc2-100mhz {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1f071
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170b9
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100b9
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170b9
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170b9
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170b9
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170b9
+                        >;
+                };
+
+                pinctrl_h100_usdhc2_200mhz: h100-usdhc2-200mhz {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x1f071
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x170f9
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x100f9
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x170f9
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x170f9
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x170f9
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x170f9
+                        >;
+                };
+        };
+};
+
+&mipi_csi {
+        status = "okay";
+
+        port@0 {
+                mipi_csi2_in: endpoint {
+                        remote-endpoint = <&tc358743_out>;
+                        data-lanes = <1 2 3 4>;
+                        clock-lanes = <0>;
+                        clock-noncontinuous;
+                        link-frequencies = /bits/ 64 <297000000>;
+                };
+        };
+};
+
+&ssi1 {
+        status = "okay";
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_h100_uart2>;
+        status = "okay";
+};
+
+&usbh1 {
+        disable-over-current;
+        vbus-supply = <&reg_usbh1_vbus>;
+        status = "okay";
+};
+
+&usbotg {
+        disable-over-current;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_h100_usbotg_id>;
+        vbus-supply = <&reg_usbotg_vbus>;
+        status = "okay";
+};
+
+&usdhc2 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_h100_usdhc2>;
+        pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>;
+        pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>;
+        vmmc-supply = <&reg_3p3v>;
+        vqmmc-supply = <&reg_nvcc_sd2>;
+        cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index 1926b1348a62..d7c8ccb2da95 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -191,7 +191,7 @@
 &pcie {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_pcie>;
-        reset-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+        reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
new file mode 100644
index 000000000000..61990630a748
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -0,0 +1,197 @@
+/*
+ * Copyright 2013 CompuLab Ltd.
+ * Copyright 2016 Christopher Spinrath
+ *
+ * Based on the devicetree distributed with the vendor kernel for the
+ * Utilite Pro:
+ *      Copyright 2013 CompuLab Ltd.
+ *      Author: Valentin Raevsky <valentin@compulab.co.il>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/input/input.h>
+#include "imx6q-cm-fx6.dts"
+
+/ {
+        model = "CompuLab Utilite Pro";
+        compatible = "compulab,utilite-pro", "compulab,cm-fx6", "fsl,imx6q";
+
+        aliases {
+                ethernet1 = &eth1;
+                rtc0 = &em3027;
+                rtc1 = &snvs_rtc;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
+
+                power {
+                        label = "Power Button";
+                        gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+        };
+};
+
+&hdmi {
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+
+        eeprom@50 {
+                compatible = "at24,24c02";
+                reg = <0x50>;
+                pagesize = <16>;
+        };
+
+        em3027: rtc@56 {
+                compatible = "emmicro,em3027";
+                reg = <0x56>;
+        };
+};
+
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+
+&iomuxc {
+        pinctrl_gpio_keys: gpio_keysgrp {
+                fsl,pins = <
+                        MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
+                >;
+        };
+
+        pinctrl_i2c1: i2c1grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
+                        MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
+                >;
+        };
+
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+                        MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+                >;
+        };
+
+        pinctrl_uart2: uart2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
+                        MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x1b0b1
+                        MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
+                        MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
+                >;
+        };
+
+        pinctrl_usdhc3: usdhc3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD     0x17059
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK     0x10059
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x17059
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x17059
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x17059
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x17059
+                >;
+        };
+
+        pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD     0x170B9
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK     0x100B9
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x170B9
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x170B9
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x170B9
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x170B9
+                >;
+        };
+
+        pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+                fsl,pins = <
+                        MX6QDL_PAD_SD3_CMD__SD3_CMD     0x170F9
+                        MX6QDL_PAD_SD3_CLK__SD3_CLK     0x100F9
+                        MX6QDL_PAD_SD3_DAT0__SD3_DATA0  0x170F9
+                        MX6QDL_PAD_SD3_DAT1__SD3_DATA1  0x170F9
+                        MX6QDL_PAD_SD3_DAT2__SD3_DATA2  0x170F9
+                        MX6QDL_PAD_SD3_DAT3__SD3_DATA3  0x170F9
+                >;
+        };
+};
+
+&pcie {
+        pcie@0,0 {
+                reg = <0x000000 0 0 0 0>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+
+                /* non-removable i211 ethernet card */
+                eth1: intel,i211@pcie0,0 {
+                        reg = <0x010000 0 0 0 0>;
+                };
+        };
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        uart-has-rtscts;
+        status = "okay";
+};
+
+&usdhc3 {
+        pinctrl-names = "default", "state_100mhz", "state_200mhz";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+        pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+        no-1-8-v;
+        broken-cd;
+        keep-power-in-suspend;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 922b1dd06fda..315e033ff1d8 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -423,7 +423,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
         fsl,dte-mode;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "disabled";
 };
 
@@ -431,7 +431,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2_dte>;
         fsl,dte-mode;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "disabled";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index 865c9a264a43..edbce222c782 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -254,7 +254,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3 &pinctrl_gsm>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index ecbc6eba6a2c..54f4f0193f2b 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -143,14 +143,14 @@
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart4>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart5 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart5>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
index 7d81100e7d47..7fff02c406f2 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
@@ -351,7 +351,7 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
@@ -364,7 +364,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 86460e46d055..3d62401dbd7f 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -143,7 +143,7 @@
 &uart4 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_microsom_brcm_bt &pinctrl_microsom_uart4>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index e456b5cc1b03..cfd50ea1ed48 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -250,6 +250,7 @@
         txd3-skew-ps = <0>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
@@ -591,7 +592,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index 657da6b6ccd2..9677bf323823 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -385,6 +385,7 @@
         txd3-skew-ps = <0>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 73915db704a0..97d9c333902b 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -287,6 +287,7 @@
         txd3-skew-ps = <0>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d354d406954d..6aa193fb283f 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -155,6 +155,7 @@
         phy-mode = "rgmii";
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index c47fe6c79b36..f65fdfc2536d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -273,6 +273,7 @@
         txd3-skew-ps = <0>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 5248e7bd2b06..d77ea9423bbc 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -501,6 +501,12 @@
                                 MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
                         >;
                 };
+
+                pinctrl_wdog: wdoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__WDOG2_B              0x1b0b0
+                        >;
+                };
         };
 
         gpio_leds {
@@ -533,7 +539,7 @@
 &pcie {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_pcie>;
-        reset-gpio = <&gpio7 12 0>;
+        reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
         status = "okay";
 };
 
@@ -596,3 +602,14 @@
         no-1-8-v;
         status = "okay";
 };
+
+&wdog1 {
+        status = "disabled";
+};
+
+&wdog2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 39b85aef93e1..ac9529f85593 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -689,21 +689,21 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 8e7c40e114dd..3ffe00c557f1 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -211,6 +211,7 @@
         phy-reset-gpios = <&gpio3 29 0>;
         interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
                               <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        fsl,err006687-workaround-present;
         status = "okay";
 };
 
@@ -233,7 +234,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ed613ebe0812..b620ac884cfd 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -185,6 +185,7 @@
                         cache-level = <2>;
                         arm,tag-latency = <4 2 3>;
                         arm,data-latency = <4 2 3>;
+                        arm,shared-override;
                 };
 
                 pcie: pcie@0x01000000 {
@@ -1100,6 +1101,7 @@
                         ocotp: ocotp@021bc000 {
                                 compatible = "fsl,imx6q-ocotp", "syscon";
                                 reg = <0x021bc000 0x4000>;
+                                clocks = <&clks IMX6QDL_CLK_IIM>;
                         };
 
                         tzasc@021d0000 { /* TZASC1 */
@@ -1255,7 +1257,7 @@
                                 #size-cells = <0>;
                                 reg = <3>;
 
-                                ipu1_di0_disp1: disp1-endpoint {
+                                ipu1_di1_disp1: disp1-endpoint {
                                 };
 
                                 ipu1_di1_hdmi: hdmi-endpoint {
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
index 058bcdceb81a..72c7745f51d3 100644
--- a/arch/arm/boot/dts/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -84,7 +84,7 @@
 &uart5 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart5>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index d12b250342a6..542515089b1e 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -461,7 +461,7 @@
                                              <0 54 IRQ_TYPE_LEVEL_HIGH>,
                                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 
-                                regulator-1p1@110 {
+                                regulator-1p1 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd1p1";
                                         regulator-min-microvolt = <800000>;
@@ -475,7 +475,7 @@
                                         anatop-max-voltage = <1375000>;
                                 };
 
-                                regulator-3p0@120 {
+                                regulator-3p0 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd3p0";
                                         regulator-min-microvolt = <2800000>;
@@ -489,7 +489,7 @@
                                         anatop-max-voltage = <3400000>;
                                 };
 
-                                regulator-2p5@130 {
+                                regulator-2p5 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd2p5";
                                         regulator-min-microvolt = <2100000>;
@@ -503,7 +503,7 @@
                                         anatop-max-voltage = <2850000>;
                                 };
 
-                                reg_arm: regulator-vddcore@140 {
+                                reg_arm: regulator-vddcore {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddarm";
                                         regulator-min-microvolt = <725000>;
@@ -520,7 +520,7 @@
                                         anatop-max-voltage = <1450000>;
                                 };
 
-                                reg_pu: regulator-vddpu@140 {
+                                reg_pu: regulator-vddpu {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddpu";
                                         regulator-min-microvolt = <725000>;
@@ -537,7 +537,7 @@
                                         anatop-max-voltage = <1450000>;
                                 };
 
-                                reg_soc: regulator-vddsoc@140 {
+                                reg_soc: regulator-vddsoc {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddsoc";
                                         regulator-min-microvolt = <725000>;
@@ -853,6 +853,7 @@
                         ocotp: ocotp@021bc000 {
                                 compatible = "fsl,imx6sl-ocotp", "syscon";
                                 reg = <0x021bc000 0x4000>;
+                                clocks = <&clks IMX6SL_CLK_OCOTP>;
                         };
 
                         audmux: audmux@021d8000 {
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index ba62348d8284..9b817f3501a6 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -326,7 +326,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index e5eafe4d9a70..9d70cfd40aff 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -273,7 +273,7 @@
 &uart5 { /* for bluetooth */
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart5>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
@@ -322,6 +322,12 @@
         status = "okay";
 };
 
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
 &iomuxc {
         imx6x-sdb {
                 pinctrl_audmux: audmuxgrp {
@@ -588,5 +594,11 @@
                                 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20        0x17059 /* WP */
                         >;
                 };
+
+                pinctrl_wdog: wdoggrp {
+                        fsl,pins = <
+                                MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x30b0
+                        >;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 6a993bfda248..2863c52be6f5 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -547,7 +547,7 @@
                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 
-                                regulator-1p1@110 {
+                                regulator-1p1 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd1p1";
                                         regulator-min-microvolt = <800000>;
@@ -561,7 +561,7 @@
                                         anatop-max-voltage = <1375000>;
                                 };
 
-                                regulator-3p0@120 {
+                                regulator-3p0 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd3p0";
                                         regulator-min-microvolt = <2800000>;
@@ -575,7 +575,7 @@
                                         anatop-max-voltage = <3400000>;
                                 };
 
-                                regulator-2p5@130 {
+                                regulator-2p5 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd2p5";
                                         regulator-min-microvolt = <2100000>;
@@ -589,7 +589,7 @@
                                         anatop-max-voltage = <2875000>;
                                 };
 
-                                reg_arm: regulator-vddcore@140 {
+                                reg_arm: regulator-vddcore {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddarm";
                                         regulator-min-microvolt = <725000>;
@@ -606,7 +606,7 @@
                                         anatop-max-voltage = <1450000>;
                                 };
 
-                                reg_pcie: regulator-vddpcie@140 {
+                                reg_pcie: regulator-vddpcie {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddpcie";
                                         regulator-min-microvolt = <725000>;
@@ -622,7 +622,7 @@
                                         anatop-max-voltage = <1450000>;
                                 };
 
-                                reg_soc: regulator-vddsoc@140 {
+                                reg_soc: regulator-vddsoc {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddsoc";
                                         regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dts b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
index 668a72997590..e281d5087d4a 100644
--- a/arch/arm/boot/dts/imx6ul-14x14-evk.dts
+++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dts
@@ -22,6 +22,14 @@
                 reg = <0x80000000 0x20000000>;
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                status = "okay";
+        };
+
         regulators {
                 compatible = "simple-bus";
                 #address-cells = <1>;
@@ -125,6 +133,46 @@
         };
 };
 
+
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+
+                        timing0: timing0 {
+                                clock-frequency = <9200000>;
+                                hactive = <480>;
+                                vactive = <272>;
+                                hfront-porch = <8>;
+                                hback-porch = <4>;
+                                hsync-len = <41>;
+                                vback-porch = <2>;
+                                vfront-porch = <4>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
 &qspi {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_qspi>;
@@ -146,6 +194,7 @@
                           <&clks IMX6UL_CLK_SAI2>;
         assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
         assigned-clock-rates = <0>, <12288000>;
+        fsl,sai-mclk-direction-output;
         status = "okay";
 };
 
@@ -171,7 +220,7 @@
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
@@ -207,6 +256,12 @@
         status = "okay";
 };
 
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
 &iomuxc {
         pinctrl-names = "default";
 
@@ -435,4 +490,10 @@
                         MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
                 >;
         };
+
+        pinctrl_wdog: wdoggrp {
+                fsl,pins = <
+                        MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY    0x30b0
+                >;
+        };
 };
diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
index 8ce1fec36e86..86f68faded0e 100644
--- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
+++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts
@@ -151,8 +151,8 @@
         phy-mode = "rmii";
         phy-handle = <&ethphy1>;
         status = "okay";
-        phy-reset-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
-        phy-reset-duration = <11>;
+        phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+        phy-reset-duration = <1>;
 
         mdio {
                 #address-cells = <1>;
@@ -286,7 +286,7 @@
 &uart3 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart3>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
index d25899b71575..7c5dd1b316ca 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
+++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
@@ -146,12 +146,12 @@
 
 &uart1 {
         pinctrl-0 = <&pinctrl_uart1>;
-        /delete-property/ fsl,uart-has-rtscts;
+        /delete-property/ uart-has-rtscts;
 };
 
 &uart2 {
         pinctrl-0 = <&pinctrl_uart2>;
-        /delete-property/ fsl,uart-has-rtscts;
+        /delete-property/ uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 437e9aad5920..530e9ca13a74 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -563,21 +563,21 @@
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart2 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
 &uart5 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 4356b655ef02..33b95d78831a 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -36,6 +36,9 @@
                 serial5 = &uart6;
                 serial6 = &uart7;
                 serial7 = &uart8;
+                sai1 = &sai1;
+                sai2 = &sai2;
+                sai3 = &sai3;
                 spi0 = &ecspi1;
                 spi1 = &ecspi2;
                 spi2 = &ecspi3;
@@ -512,7 +515,7 @@
                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 
-                                reg_3p0: regulator-3p0@120 {
+                                reg_3p0: regulator-3p0 {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vdd3p0";
                                         regulator-min-microvolt = <2625000>;
@@ -526,7 +529,7 @@
                                         anatop-enable-bit = <0>;
                                 };
 
-                                reg_arm: regulator-vddcore@140 {
+                                reg_arm: regulator-vddcore {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "cpu";
                                         regulator-min-microvolt = <725000>;
@@ -543,7 +546,7 @@
                                         anatop-max-voltage = <1450000>;
                                 };
 
-                                reg_soc: regulator-vddsoc@140 {
+                                reg_soc: regulator-vddsoc {
                                         compatible = "fsl,anatop-regulator";
                                         regulator-name = "vddsoc";
                                         regulator-min-microvolt = <725000>;
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..1545661df583
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -0,0 +1,148 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&bl {
+        brightness-levels = <0 4 8 16 32 64 128 255>;
+        default-brightness-level = <6>;
+        status = "okay";
+};
+
+&adc1 {
+        status = "okay";
+};
+
+&adc2 {
+        status = "okay";
+};
+
+&fec1 {
+        status = "okay";
+};
+
+&i2c4 {
+        status = "okay";
+
+        /* M41T0M6 real time clock on carrier board */
+        rtc: m41t0m6@68 {
+                compatible = "st,m41t00";
+                reg = <0x68>;
+        };
+};
+
+&lcdif {
+        display = <&display0>;
+        status = "okay";
+
+        display0: lcd-display {
+                bits-per-pixel = <16>;
+                bus-width = <18>;
+
+                display-timings {
+                        native-mode = <&timing_vga>;
+
+                        /* Standard VGA timing */
+                        timing_vga: 640x480 {
+                                clock-frequency = <25175000>;
+                                hactive = <640>;
+                                vactive = <480>;
+                                hback-porch = <40>;
+                                hfront-porch = <24>;
+                                vback-porch = <32>;
+                                vfront-porch = <11>;
+                                hsync-len = <96>;
+                                vsync-len = <2>;
+                                de-active = <1>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&pwm1 {
+        status = "okay";
+};
+
+&pwm2 {
+        status = "okay";
+};
+
+&pwm3 {
+        status = "okay";
+};
+
+&pwm4 {
+        status = "okay";
+};
+
+&uart1 {
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
+
+&uart3 {
+        status = "okay";
+};
+
+&usbotg1 {
+        status = "okay";
+};
+
+&usdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+        no-1-8-v;
+        cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+        keep-power-in-suspend;
+        wakeup-source;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
new file mode 100644
index 000000000000..0a9d3a822fc0
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -0,0 +1,571 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+        bl: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm1 0 5000000>;
+        };
+
+        reg_3p3v: regulator-3p3v {
+                compatible = "regulator-fixed";
+                regulator-name = "3P3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+
+        reg_vref_1v8: regulator-vref-1v8 {
+                compatible = "regulator-fixed";
+                regulator-name = "vref-1v8";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+        };
+};
+
+&adc1 {
+        vref-supply = <&reg_vref_1v8>;
+};
+
+&adc2 {
+        vref-supply = <&reg_vref_1v8>;
+};
+
+&cpu0 {
+        arm-supply = <&reg_DCDC2>;
+};
+
+&fec1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet1>;
+        clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+                <&clks IMX7D_PLL_ENET_MAIN_50M_CLK>;
+        clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+        assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+                          <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+        assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+        assigned-clock-rates = <0>, <100000000>;
+        phy-mode = "rmii";
+        phy-supply = <&reg_LDO1>;
+        fsl,magic-packet;
+};
+
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
+        status = "okay";
+
+        ad7879@2c {
+                compatible = "adi,ad7879-1";
+                reg = <0x2c>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+                touchscreen-max-pressure = <4096>;
+                adi,resistance-plate-x = <120>;
+                adi,first-conversion-delay = /bits/ 8 <3>;
+                adi,acquisition-time = /bits/ 8 <1>;
+                adi,median-filter-size = /bits/ 8 <2>;
+                adi,averaging = /bits/ 8 <1>;
+                adi,conversion-interval = /bits/ 8 <255>;
+        };
+
+        pmic@33 {
+                compatible = "ricoh,rn5t567";
+                reg = <0x33>;
+
+                regulators {
+                        reg_DCDC1: DCDC1 {  /* V1.0_SOC */
+                                regulator-min-microvolt =  <975000>;
+                                regulator-max-microvolt = <1125000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_DCDC2: DCDC2 { /* V1.1_ARM */
+                                regulator-min-microvolt =  <975000>;
+                                regulator-max-microvolt = <1125000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_DCDC3: DCDC3 { /* V1.8 */
+                                regulator-min-microvolt = <1775000>;
+                                regulator-max-microvolt = <1825000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_DCDC4: DCDC4 { /* V1.35_DRAM */
+                                regulator-min-microvolt = <1325000>;
+                                regulator-max-microvolt = <1375000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+
+                        reg_LDO2: LDO2 { /* +V1.8_SD */
+                                regulator-min-microvolt = <1775000>;
+                                regulator-max-microvolt = <3325000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
+                                regulator-min-microvolt = <3275000>;
+                                regulator-max-microvolt = <3325000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_LDO4: LDO4 { /* V1.8_LPSR */
+                                regulator-min-microvolt = <1775000>;
+                                regulator-max-microvolt = <1825000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+
+                        reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
+                                regulator-min-microvolt = <1775000>;
+                                regulator-max-microvolt = <1825000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c4>;
+};
+
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif_dat
+                     &pinctrl_lcdif_ctrl>;
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+};
+
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2>;
+};
+
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+};
+
+&reg_1p0d {
+        vin-supply = <&reg_DCDC3>;
+};
+
+&snvs_pwrkey {
+        status = "disabled";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1 &pinctrl_uart1_ctrl2>;
+        assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
+        assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+        uart-has-rtscts;
+        fsl,dte-mode;
+};
+
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+        assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+        uart-has-rtscts;
+        fsl,dte-mode;
+};
+
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
+        assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
+        fsl,dte-mode;
+};
+
+&usbotg1 {
+        dr_mode = "host";
+};
+
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
+
+        pinctrl_gpio1: gpio1-grp {
+                fsl,pins = <
+                        MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3     0x14 /* SODIMM 55 */
+                        MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2     0x14 /* SODIMM 63 */
+                        MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0X14 /* SODIMM 73 */
+                        MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0X14 /* SODIMM 77 */
+                        MX7D_PAD_EPDC_DATA09__GPIO2_IO9         0x14 /* SODIMM 89 */
+                        MX7D_PAD_EPDC_DATA08__GPIO2_IO8         0x14 /* SODIMM 91 */
+                        MX7D_PAD_LCD_RESET__GPIO3_IO4           0x14 /* SODIMM 93 */
+                        MX7D_PAD_EPDC_DATA13__GPIO2_IO13        0x14 /* SODIMM 95 */
+                        MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11    0x14 /* SODIMM 99 */
+                        MX7D_PAD_EPDC_DATA10__GPIO2_IO10        0x14 /* SODIMM 105 */
+                        MX7D_PAD_EPDC_DATA15__GPIO2_IO15        0x14 /* SODIMM 107 */
+                        MX7D_PAD_EPDC_DATA00__GPIO2_IO0         0x14 /* SODIMM 111 */
+                        MX7D_PAD_EPDC_DATA01__GPIO2_IO1         0x14 /* SODIMM 113 */
+                        MX7D_PAD_EPDC_DATA02__GPIO2_IO2         0x14 /* SODIMM 115 */
+                        MX7D_PAD_EPDC_DATA03__GPIO2_IO3         0x14 /* SODIMM 117 */
+                        MX7D_PAD_EPDC_DATA04__GPIO2_IO4         0x14 /* SODIMM 119 */
+                        MX7D_PAD_EPDC_DATA05__GPIO2_IO5         0x14 /* SODIMM 121 */
+                        MX7D_PAD_EPDC_DATA06__GPIO2_IO6         0x14 /* SODIMM 123 */
+                        MX7D_PAD_EPDC_DATA07__GPIO2_IO7         0x14 /* SODIMM 125 */
+                        MX7D_PAD_EPDC_SDCE2__GPIO2_IO22         0x14 /* SODIMM 127 */
+                        MX7D_PAD_UART3_RTS_B__GPIO4_IO6         0x14 /* SODIMM 131 */
+                        MX7D_PAD_EPDC_GDRL__GPIO2_IO26          0x14 /* SODIMM 133 */
+                        MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x14 /* SODIMM 24 */
+                        MX7D_PAD_SD2_DATA2__GPIO5_IO16          0x14 /* SODIMM 100 */
+                        MX7D_PAD_SD2_DATA3__GPIO5_IO17          0x14 /* SODIMM 102 */
+                        MX7D_PAD_EPDC_GDSP__GPIO2_IO27          0x14 /* SODIMM 104 */
+                        MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x14 /* SODIMM 106 */
+                        MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x14 /* SODIMM 110 */
+                        MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30       0x14 /* SODIMM 112 */
+                        MX7D_PAD_EPDC_SDCLK__GPIO2_IO16         0x14 /* SODIMM 114 */
+                        MX7D_PAD_EPDC_SDLE__GPIO2_IO17          0x14 /* SODIMM 116 */
+                        MX7D_PAD_EPDC_SDOE__GPIO2_IO18          0x14 /* SODIMM 118 */
+                        MX7D_PAD_EPDC_SDSHR__GPIO2_IO19         0x14 /* SODIMM 120 */
+                        MX7D_PAD_EPDC_SDCE0__GPIO2_IO20         0x14 /* SODIMM 122 */
+                        MX7D_PAD_EPDC_SDCE1__GPIO2_IO21         0x14 /* SODIMM 124 */
+                        MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x14 /* SODIMM 126 */
+                        MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31      0x14 /* SODIMM 128 */
+                        MX7D_PAD_EPDC_SDCE3__GPIO2_IO23         0x14 /* SODIMM 130 */
+                        MX7D_PAD_EPDC_GDCLK__GPIO2_IO24         0x14 /* SODIMM 132 */
+                        MX7D_PAD_EPDC_GDOE__GPIO2_IO25          0x14 /* SODIMM 134 */
+                        MX7D_PAD_EPDC_DATA12__GPIO2_IO12        0x14 /* SODIMM 150 */
+                        MX7D_PAD_EPDC_DATA11__GPIO2_IO11        0x14 /* SODIMM 152 */
+                        MX7D_PAD_SD2_CLK__GPIO5_IO12            0x14 /* SODIMM 184 */
+                        MX7D_PAD_SD2_CMD__GPIO5_IO13            0x14 /* SODIMM 186 */
+                >;
+        };
+
+        pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
+                fsl,pins = <
+                        MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x14 /* SODIMM 65 */
+                        MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x14 /* SODIMM 69 */
+                        MX7D_PAD_SD1_WP__GPIO5_IO1              0x14 /* SODIMM 71 */
+                        MX7D_PAD_I2C4_SDA__GPIO4_IO15           0x14 /* SODIMM 75 */
+                        MX7D_PAD_ECSPI1_MISO__GPIO4_IO18        0x14 /* SODIMM 79 */
+                        MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x14 /* SODIMM 81 */
+                        MX7D_PAD_ECSPI2_MISO__GPIO4_IO22        0x14 /* SODIMM 85 */
+                        MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x14 /* SODIMM 97 */
+                        MX7D_PAD_ECSPI1_SCLK__GPIO4_IO16        0x14 /* SODIMM 101 */
+                        MX7D_PAD_ECSPI1_MOSI__GPIO4_IO17        0x14 /* SODIMM 103 */
+                        MX7D_PAD_I2C3_SDA__GPIO4_IO13           0x14 /* SODIMM 94 */
+                        MX7D_PAD_I2C4_SCL__GPIO4_IO14           0x14 /* SODIMM 96 */
+                        MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x14 /* SODIMM 98 */
+                >;
+        };
+
+        pinctrl_gpio3: gpio3-grp { /* LCD 18-23 */
+                fsl,pins = <
+                        MX7D_PAD_LCD_DATA18__GPIO3_IO23         0x14 /* SODIMM 136 */
+                        MX7D_PAD_LCD_DATA19__GPIO3_IO24         0x14 /* SODIMM 138 */
+                        MX7D_PAD_LCD_DATA20__GPIO3_IO25         0x14 /* SODIMM 140 */
+                        MX7D_PAD_LCD_DATA21__GPIO3_IO26         0x14 /* SODIMM 142 */
+                        MX7D_PAD_LCD_DATA22__GPIO3_IO27         0x14 /* SODIMM 146 */
+                        MX7D_PAD_LCD_DATA23__GPIO3_IO28         0x14 /* SODIMM 148 */
+                >;
+        };
+
+        pinctrl_gpio4: gpio4-grp { /* Alternatively CAN2 */
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO15__GPIO1_IO15         0x14 /* SODIMM 178 */
+                        MX7D_PAD_GPIO1_IO14__GPIO1_IO14         0x14 /* SODIMM 188 */
+                >;
+        };
+
+        pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
+                >;
+        };
+
+        pinctrl_enet1: enet1grp {
+                fsl,pins = <
+                        MX7D_PAD_ENET1_CRS__GPIO7_IO14                  0x14
+                        MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
+                        MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x73
+                        MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x73
+                        MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER           0x73
+
+                        MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x73
+                        MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x73
+                        MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x73
+                        MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1          0x73
+                        MX7D_PAD_SD2_CD_B__ENET1_MDIO                   0x3
+                        MX7D_PAD_SD2_WP__ENET1_MDC                      0x3
+                >;
+        };
+
+        pinctrl_ecspi3_cs: ecspi3-cs-grp {
+                fsl,pins = <
+                        MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x14
+                >;
+        };
+
+        pinctrl_ecspi3: ecspi3-grp {
+                fsl,pins = <
+                        MX7D_PAD_I2C1_SCL__ECSPI3_MISO          0x2
+                        MX7D_PAD_I2C1_SDA__ECSPI3_MOSI          0x2
+                        MX7D_PAD_I2C2_SCL__ECSPI3_SCLK          0x2
+                >;
+        };
+
+        pinctrl_flexcan2: flexcan2-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
+                        MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
+                >;
+        };
+
+        pinctrl_gpmi_nand: gpmi-nand-grp {
+                fsl,pins = <
+                        MX7D_PAD_SD3_CLK__NAND_CLE              0x71
+                        MX7D_PAD_SD3_CMD__NAND_ALE              0x71
+                        MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B       0x71
+                        MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B       0x71
+                        MX7D_PAD_SAI1_TX_DATA__NAND_READY_B     0x74
+                        MX7D_PAD_SD3_STROBE__NAND_RE_B          0x71
+                        MX7D_PAD_SD3_RESET_B__NAND_WE_B         0x71
+                        MX7D_PAD_SD3_DATA0__NAND_DATA00         0x71
+                        MX7D_PAD_SD3_DATA1__NAND_DATA01         0x71
+                        MX7D_PAD_SD3_DATA2__NAND_DATA02         0x71
+                        MX7D_PAD_SD3_DATA3__NAND_DATA03         0x71
+                        MX7D_PAD_SD3_DATA4__NAND_DATA04         0x71
+                        MX7D_PAD_SD3_DATA5__NAND_DATA05         0x71
+                        MX7D_PAD_SD3_DATA6__NAND_DATA06         0x71
+                        MX7D_PAD_SD3_DATA7__NAND_DATA07         0x71
+                >;
+        };
+
+        pinctrl_i2c4: i2c4-grp {
+                fsl,pins = <
+                        MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA      0x4000007f
+                        MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL      0x4000007f
+                >;
+        };
+
+        pinctrl_lcdif_dat: lcdif-dat-grp {
+                fsl,pins = <
+                        MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
+                        MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
+                        MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
+                        MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
+                        MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
+                        MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
+                        MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
+                        MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
+                        MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
+                        MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
+                        MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
+                        MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
+                        MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
+                        MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
+                        MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
+                        MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
+                        MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
+                        MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
+                >;
+        };
+
+        pinctrl_lcdif_dat_24: lcdif-dat-24-grp {
+                fsl,pins = <
+                        MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
+                        MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
+                        MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
+                        MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
+                        MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
+                        MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
+                >;
+        };
+
+        pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
+                fsl,pins = <
+                        MX7D_PAD_LCD_CLK__LCD_CLK               0x79
+                        MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
+                        MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
+                        MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
+                >;
+        };
+
+        pinctrl_pwm1: pwm1-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO08__PWM1_OUT           0x79
+                >;
+        };
+
+        pinctrl_pwm2: pwm2-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO09__PWM2_OUT           0x79
+                >;
+        };
+
+        pinctrl_pwm3: pwm3-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO10__PWM3_OUT           0x79
+                >;
+        };
+
+        pinctrl_pwm4: pwm4-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO11__PWM4_OUT           0x79
+                >;
+        };
+
+        pinctrl_uart1: uart1-grp {
+                fsl,pins = <
+                        MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX    0x79
+                        MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX    0x79
+                        MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS    0x79
+                        MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS    0x79
+                >;
+        };
+
+        pinctrl_uart1_ctrl1: uart1-ctrl1-grp {
+                fsl,pins = <
+                        MX7D_PAD_SD2_DATA1__GPIO5_IO15          0x14 /* DCD */
+                        MX7D_PAD_SD2_DATA0__GPIO5_IO14          0x14 /* DTR */
+                >;
+        };
+
+        pinctrl_uart2: uart2-grp {
+                fsl,pins = <
+                        MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX 0x79
+                        MX7D_PAD_UART2_RX_DATA__UART2_DTE_TX 0x79
+                        MX7D_PAD_SAI2_RX_DATA__UART2_DTE_RTS 0x79
+                        MX7D_PAD_SAI2_TX_DATA__UART2_DTE_CTS 0x79
+                >;
+        };
+        pinctrl_uart3: uart3-grp {
+                fsl,pins = <
+                        MX7D_PAD_UART3_TX_DATA__UART3_DTE_RX 0x79
+                        MX7D_PAD_UART3_RX_DATA__UART3_DTE_TX 0x79
+                >;
+        };
+
+        pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
+                fsl,pins = <
+                        MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
+                >;
+        };
+
+        pinctrl_usdhc1: usdhc1-grp {
+                fsl,pins = <
+                        MX7D_PAD_SD1_CMD__SD1_CMD       0x59
+                        MX7D_PAD_SD1_CLK__SD1_CLK       0x19
+                        MX7D_PAD_SD1_DATA0__SD1_DATA0   0x59
+                        MX7D_PAD_SD1_DATA1__SD1_DATA1   0x59
+                        MX7D_PAD_SD1_DATA2__SD1_DATA2   0x59
+                        MX7D_PAD_SD1_DATA3__SD1_DATA3   0x59
+                >;
+        };
+
+        pinctrl_sai1: sai1-grp {
+                fsl,pins = <
+                        MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
+                        MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
+                        MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC     0x1f
+                        MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
+                        MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
+                >;
+        };
+};
+
+&iomuxc_lpsr {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpio_lpsr>;
+
+        pinctrl_gpio_lpsr: gpio1-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO01__GPIO1_IO1  0x59
+                        MX7D_PAD_GPIO1_IO02__GPIO1_IO2  0x59
+                        MX7D_PAD_GPIO1_IO03__GPIO1_IO3  0x59
+                >;
+        };
+
+        pinctrl_i2c1: i2c1-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO05__I2C1_SDA   0x4000007f
+                        MX7D_PAD_GPIO1_IO04__I2C1_SCL   0x4000007f
+                >;
+        };
+
+        pinctrl_cd_usdhc1: usdhc1-cd-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO00__GPIO1_IO0  0x59 /* CD */
+                >;
+        };
+
+        pinctrl_uart1_ctrl2: uart1-ctrl2-grp {
+                fsl,pins = <
+                        MX7D_PAD_GPIO1_IO07__GPIO1_IO7  0x14 /* DSR */
+                        MX7D_PAD_GPIO1_IO06__GPIO1_IO6  0x14 /* RI */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 48634519d13a..58b09bf1ba2d 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -12,7 +12,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
 #include "imx7d.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
new file mode 100644
index 000000000000..bd01d2cc642d
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3";
+        compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d",
+                     "fsl,imx7d";
+
+        reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_usbotg2_reg>;
+                regulator-name = "VCC_USB[1-4]";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
+        };
+};
+
+&usbotg2 {
+        vbus-supply = <&reg_usb_otg2_vbus>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
new file mode 100644
index 000000000000..3c2cb502b388
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx7d.dtsi"
+#include "imx7-colibri.dtsi"
+
+/ {
+        memory {
+                reg = <0x80000000 0x20000000>;
+        };
+};
+
+&usbotg2 {
+        dr_mode = "host";
+};
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index 1ce97800f0c5..ce08f180f213 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -42,7 +42,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
 #include "imx7d.dtsi"
 
 / {
@@ -392,7 +391,7 @@
         pinctrl-0 = <&pinctrl_uart6>;
         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
-        fsl,uart-has-rtscts;
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx7d-pinfunc.h b/arch/arm/boot/dts/imx7d-pinfunc.h
index eeda78347619..3f9f0d9c8094 100644
--- a/arch/arm/boot/dts/imx7d-pinfunc.h
+++ b/arch/arm/boot/dts/imx7d-pinfunc.h
@@ -594,7 +594,7 @@
 #define MX7D_PAD_UART2_RX_DATA__GPIO4_IO2                         0x0130 0x03A0 0x0000 0x5 0x0
 #define MX7D_PAD_UART2_RX_DATA__ENET2_MDIO                        0x0130 0x03A0 0x0000 0x6 0x0
 #define MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX                      0x0134 0x03A4 0x0000 0x0 0x0
-#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                      0x0134 0x03A4 0x0000 0x0 0x0
+#define MX7D_PAD_UART2_TX_DATA__UART2_DTE_RX                      0x0134 0x03A4 0x06FC 0x0 0x3
 #define MX7D_PAD_UART2_TX_DATA__I2C2_SDA                          0x0134 0x03A4 0x05E0 0x1 0x0
 #define MX7D_PAD_UART2_TX_DATA__SAI3_RX_DATA0                     0x0134 0x03A4 0x06C8 0x2 0x0
 #define MX7D_PAD_UART2_TX_DATA__ECSPI1_RDY                        0x0134 0x03A4 0x0000 0x3 0x0
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index b267f79e3059..95ee268ed510 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -42,7 +42,6 @@
 
 /dts-v1/;
 
-#include <dt-bindings/input/input.h>
 #include "imx7d.dtsi"
 
 / {
@@ -111,6 +110,32 @@
         arm-supply = <&sw1a_reg>;
 };
 
+&ecspi3 {
+        fsl,spi-num-chipselects = <1>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi3>;
+        cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+
+        tsc2046@0 {
+                compatible = "ti,tsc2046";
+                reg = <0>;
+                spi-max-frequency = <1000000>;
+                pinctrl-names ="default";
+                pinctrl-0 = <&pinctrl_tsc2046_pendown>;
+                interrupt-parent = <&gpio2>;
+                interrupts = <29 0>;
+                pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
+                ti,x-min = /bits/ 16 <0>;
+                ti,x-max = /bits/ 16 <0>;
+                ti,y-min = /bits/ 16 <0>;
+                ti,y-max = /bits/ 16 <0>;
+                ti,pressure-max = /bits/ 16 <0>;
+                ti,x-plat-ohms = /bits/ 16 <400>;
+                wakeup-source;
+        };
+};
+
 &fec1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_enet1>;
@@ -272,6 +297,44 @@
         };
 };
 
+&lcdif {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_lcdif>;
+        display = <&display0>;
+        status = "okay";
+
+        display0: display {
+                bits-per-pixel = <16>;
+                bus-width = <24>;
+
+                display-timings {
+                        native-mode = <&timing0>;
+
+                        timing0: timing0 {
+                                clock-frequency = <9200000>;
+                                hactive = <480>;
+                                vactive = <272>;
+                                hfront-porch = <8>;
+                                hback-porch = <4>;
+                                hsync-len = <41>;
+                                vback-porch = <2>;
+                                vfront-porch = <4>;
+                                vsync-len = <10>;
+                                hsync-active = <0>;
+                                vsync-active = <0>;
+                                de-active = <1>;
+                                pixelclk-active = <0>;
+                        };
+                };
+        };
+};
+
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+
 &uart1 {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_uart1>;
@@ -314,11 +377,26 @@
         status = "okay";
 };
 
+&wdog1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_wdog>;
+        fsl,ext-reset-output;
+};
+
 &iomuxc {
         pinctrl-names = "default";
         pinctrl-0 = <&pinctrl_hog>;
 
         imx7d-sdb {
+                pinctrl_ecspi3: ecspi3grp {
+                        fsl,pins = <
+                                MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
+                                MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
+                                MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
+                                MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
+                        >;
+                };
+
                 pinctrl_enet1: enet1grp {
                         fsl,pins = <
                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
@@ -390,6 +468,52 @@
                         >;
                 };
 
+                pinctrl_lcdif: lcdifgrp {
+                        fsl,pins = <
+                                MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
+                                MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
+                                MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
+                                MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
+                                MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
+                                MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
+                                MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
+                                MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
+                                MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
+                                MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
+                                MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
+                                MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
+                                MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
+                                MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
+                                MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
+                                MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
+                                MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
+                                MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
+                                MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
+                                MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
+                                MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
+                                MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
+                                MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
+                                MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
+                                MX7D_PAD_LCD_CLK__LCD_CLK               0x79
+                                MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
+                                MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
+                                MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
+                                MX7D_PAD_LCD_RESET__LCD_RESET           0x79
+                        >;
+                };
+
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                MX7D_PAD_GPIO1_IO01__PWM1_OUT           0x110b0
+                        >;
+                };
+
+                pinctrl_tsc2046_pendown: tsc2046_pendown {
+                        fsl,pins = <
+                                MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
+                        >;
+                };
+
                 pinctrl_uart1: uart1grp {
                         fsl,pins = <
                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
@@ -512,5 +636,10 @@
                         >;
                 };
 
+                pinctrl_wdog: wdoggrp {
+                        fsl,pins = <
+                                MX7D_PAD_GPIO1_IO00__WDOD1_WDOG_B       0x74
+                        >;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 6b3faa298417..51c13cbdffb7 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Toradex AG
  *
  * This file is dual-licensed: you can use it either under the terms
  * of the GPL or the X11 license, at your option. Note that this dual
@@ -40,54 +41,10 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
-#include <dt-bindings/clock/imx7d-clock.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "imx7d-pinfunc.h"
-#include "skeleton.dtsi"
+#include "imx7s.dtsi"
 
 / {
-        aliases {
-                gpio0 = &gpio1;
-                gpio1 = &gpio2;
-                gpio2 = &gpio3;
-                gpio3 = &gpio4;
-                gpio4 = &gpio5;
-                gpio5 = &gpio6;
-                gpio6 = &gpio7;
-                i2c0 = &i2c1;
-                i2c1 = &i2c2;
-                i2c2 = &i2c3;
-                i2c3 = &i2c4;
-                mmc0 = &usdhc1;
-                mmc1 = &usdhc2;
-                mmc2 = &usdhc3;
-                serial0 = &uart1;
-                serial1 = &uart2;
-                serial2 = &uart3;
-                serial3 = &uart4;
-                serial4 = &uart5;
-                serial5 = &uart6;
-                serial6 = &uart7;
-        };
-
         cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-
-                cpu0: cpu@0 {
-                        compatible = "arm,cortex-a7";
-                        device_type = "cpu";
-                        reg = <0>;
-                        operating-points = <
-                                /* KHz  uV */
-                                996000  1075000
-                                792000  975000
-                        >;
-                        clock-latency = <61036>; /* two CLK32 periods */
-                        clocks = <&clks IMX7D_CLK_ARM>;
-                };
-
                 cpu1: cpu@1 {
                         compatible = "arm,cortex-a7";
                         device_type = "cpu";
@@ -95,221 +52,6 @@
                 };
         };
 
-        intc: interrupt-controller@31001000 {
-                compatible = "arm,cortex-a7-gic";
-                #interrupt-cells = <3>;
-                interrupt-controller;
-                reg = <0x31001000 0x1000>,
-                      <0x31002000 0x1000>,
-                      <0x31004000 0x2000>,
-                      <0x31006000 0x2000>;
-        };
-
-        ckil: clock-cki {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <32768>;
-                clock-output-names = "ckil";
-        };
-
-        osc: clock-osc {
-                compatible = "fixed-clock";
-                #clock-cells = <0>;
-                clock-frequency = <24000000>;
-                clock-output-names = "osc";
-        };
-
-        timer {
-                compatible = "arm,armv7-timer";
-                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
-                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
-                interrupt-parent = <&intc>;
-        };
-
-        etr@30086000 {
-                compatible = "arm,coresight-tmc", "arm,primecell";
-                reg = <0x30086000 0x1000>;
-                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
-                clock-names = "apb_pclk";
-
-                port {
-                        etr_in_port: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&replicator_out_port1>;
-                        };
-                };
-        };
-
-        tpiu@30087000 {
-                compatible = "arm,coresight-tpiu", "arm,primecell";
-                reg = <0x30087000 0x1000>;
-                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
-                clock-names = "apb_pclk";
-
-                port {
-                        tpiu_in_port: endpoint {
-                                slave-mode;
-                                remote-endpoint = <&replicator_out_port1>;
-                        };
-                };
-        };
-
-        replicator {
-                /*
-                 * non-configurable replicators don't show up on the
-                 * AMBA bus.  As such no need to add "arm,primecell"
-                 */
-                compatible = "arm,coresight-replicator";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* replicator output ports */
-                        port@0 {
-                                reg = <0>;
-                                replicator_out_port0: endpoint {
-                                        remote-endpoint = <&tpiu_in_port>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                replicator_out_port1: endpoint {
-                                        remote-endpoint = <&etr_in_port>;
-                                };
-                        };
-
-                        /* replicator input port */
-                        port@2 {
-                                reg = <0>;
-                                replicator_in_port0: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&etf_out_port>;
-                                };
-                        };
-                };
-        };
-
-        etf@30084000 {
-                compatible = "arm,coresight-tmc", "arm,primecell";
-                reg = <0x30084000 0x1000>;
-                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
-                clock-names = "apb_pclk";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        port@0 {
-                                reg = <0>;
-                                etf_in_port: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&hugo_funnel_out_port0>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <0>;
-                                etf_out_port: endpoint {
-                                        remote-endpoint = <&replicator_in_port0>;
-                                };
-                        };
-                };
-        };
-
-        funnel@30083000 {
-                compatible = "arm,coresight-funnel", "arm,primecell";
-                reg = <0x30083000 0x1000>;
-                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
-                clock-names = "apb_pclk";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel input ports */
-                        port@0 {
-                                reg = <0>;
-                                hugo_funnel_in_port0: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&ca_funnel_out_port0>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                hugo_funnel_in_port1: endpoint {
-                                        slave-mode; /* M4 input */
-                                };
-                        };
-
-                        port@2 {
-                                reg = <0>;
-                                hugo_funnel_out_port0: endpoint {
-                                        remote-endpoint = <&etf_in_port>;
-                                };
-                        };
-
-                        /* the other input ports are not connect to anything */
-                };
-        };
-
-        funnel@30041000 {
-                compatible = "arm,coresight-funnel", "arm,primecell";
-                reg = <0x30041000 0x1000>;
-                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
-                clock-names = "apb_pclk";
-
-                ports {
-                        #address-cells = <1>;
-                        #size-cells = <0>;
-
-                        /* funnel input ports */
-                        port@0 {
-                                reg = <0>;
-                                ca_funnel_in_port0: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&etm0_out_port>;
-                                };
-                        };
-
-                        port@1 {
-                                reg = <1>;
-                                ca_funnel_in_port1: endpoint {
-                                        slave-mode;
-                                        remote-endpoint = <&etm1_out_port>;
-                                };
-                        };
-
-                        /* funnel output port */
-                        port@2 {
-                                reg = <0>;
-                                ca_funnel_out_port0: endpoint {
-                                        remote-endpoint = <&hugo_funnel_in_port0>;
-                                };
-                        };
-
-                        /* the other input ports are not connect to anything */
-                };
-        };
-
-        etm@3007c000 {
-                compatible = "arm,coresight-etm3x", "arm,primecell";
-                reg = <0x3007c000 0x1000>;
-                cpu = <&cpu0>;
-                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
-                clock-names = "apb_pclk";
-
-                port {
-                        etm0_out_port: endpoint {
-                                remote-endpoint = <&ca_funnel_in_port0>;
-                        };
-                };
-        };
-
         etm@3007d000 {
                 compatible = "arm,coresight-etm3x", "arm,primecell";
                 reg = <0x3007d000 0x1000>;
@@ -330,626 +72,57 @@
                         };
                 };
         };
+};
 
-        soc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                compatible = "simple-bus";
-                interrupt-parent = <&intc>;
-                ranges;
-
-                aips1: aips-bus@30000000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x30000000 0x400000>;
-                        ranges;
-
-                        gpio1: gpio@30200000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30200000 0x10000>;
-                                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
-                                             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        gpio2: gpio@30210000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30210000 0x10000>;
-                                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        gpio3: gpio@30220000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30220000 0x10000>;
-                                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        gpio4: gpio@30230000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30230000 0x10000>;
-                                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        gpio5: gpio@30240000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30240000 0x10000>;
-                                interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        gpio6: gpio@30250000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30250000 0x10000>;
-                                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        gpio7: gpio@30260000 {
-                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
-                                reg = <0x30260000 0x10000>;
-                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
-                                interrupt-controller;
-                                #interrupt-cells = <2>;
-                        };
-
-                        wdog1: wdog@30280000 {
-                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
-                                reg = <0x30280000 0x10000>;
-                                interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
-                        };
-
-                        wdog2: wdog@30290000 {
-                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
-                                reg = <0x30290000 0x10000>;
-                                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        wdog3: wdog@302a0000 {
-                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
-                                reg = <0x302a0000 0x10000>;
-                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        wdog4: wdog@302b0000 {
-                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
-                                reg = <0x302b0000 0x10000>;
-                                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        iomuxc_lpsr: iomuxc-lpsr@302c0000 {
-                                compatible = "fsl,imx7d-iomuxc-lpsr";
-                                reg = <0x302c0000 0x10000>;
-                                fsl,input-sel = <&iomuxc>;
-                        };
-
-                        gpt1: gpt@302d0000 {
-                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
-                                reg = <0x302d0000 0x10000>;
-                                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_GPT1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                        };
-
-                        gpt2: gpt@302e0000 {
-                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
-                                reg = <0x302e0000 0x10000>;
-                                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_GPT2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        gpt3: gpt@302f0000 {
-                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
-                                reg = <0x302f0000 0x10000>;
-                                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_GPT3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        gpt4: gpt@30300000 {
-                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
-                                reg = <0x30300000 0x10000>;
-                                interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                         <&clks IMX7D_GPT4_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        iomuxc: iomuxc@30330000 {
-                                compatible = "fsl,imx7d-iomuxc";
-                                reg = <0x30330000 0x10000>;
-                        };
-
-                        gpr: iomuxc-gpr@30340000 {
-                                compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
-                                reg = <0x30340000 0x10000>;
-                        };
-
-                        ocotp: ocotp-ctrl@30350000 {
-                                compatible = "syscon";
-                                reg = <0x30350000 0x10000>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>;
-                                status = "disabled";
-                        };
-
-                        anatop: anatop@30360000 {
-                                compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
-                                        "syscon", "simple-bus";
-                                reg = <0x30360000 0x10000>;
-                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
-                                        <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
-
-                                reg_1p0d: regulator-vdd1p0d@210 {
-                                        compatible = "fsl,anatop-regulator";
-                                        regulator-name = "vdd1p0d";
-                                        regulator-min-microvolt = <800000>;
-                                        regulator-max-microvolt = <1200000>;
-                                        anatop-reg-offset = <0x210>;
-                                        anatop-vol-bit-shift = <8>;
-                                        anatop-vol-bit-width = <5>;
-                                        anatop-min-bit-val = <8>;
-                                        anatop-min-voltage = <800000>;
-                                        anatop-max-voltage = <1200000>;
-                                        anatop-enable-bit = <31>;
-                                };
-                        };
-
-                        snvs: snvs@30370000 {
-                                compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
-                                reg = <0x30370000 0x10000>;
-
-                                snvs_rtc: snvs-rtc-lp {
-                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
-                                        regmap = <&snvs>;
-                                        offset = <0x34>;
-                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
-                                                     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
-                                };
-
-                                snvs_poweroff: snvs-poweroff {
-                                        compatible = "syscon-poweroff";
-                                        regmap = <&snvs>;
-                                        offset = <0x38>;
-                                        mask = <0x60>;
-                                };
-
-                                snvs_pwrkey: snvs-powerkey {
-                                        compatible = "fsl,sec-v4.0-pwrkey";
-                                        regmap = <&snvs>;
-                                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
-                                        linux,keycode = <KEY_POWER>;
-                                        wakeup-source;
-                                };
-                        };
-
-                        clks: ccm@30380000 {
-                                compatible = "fsl,imx7d-ccm";
-                                reg = <0x30380000 0x10000>;
-                                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
-                                             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
-                                #clock-cells = <1>;
-                                clocks = <&ckil>, <&osc>;
-                                clock-names = "ckil", "osc";
-                        };
-
-                        src: src@30390000 {
-                                compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
-                                reg = <0x30390000 0x10000>;
-                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
-                                #reset-cells = <1>;
-                        };
-                };
-
-                aips2: aips-bus@30400000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x30400000 0x400000>;
-                        ranges;
-
-                        adc1: adc@30610000 {
-                                compatible = "fsl,imx7d-adc";
-                                reg = <0x30610000 0x10000>;
-                                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ADC_ROOT_CLK>;
-                                clock-names = "adc";
-                                status = "disabled";
-                        };
-
-                        adc2: adc@30620000 {
-                                compatible = "fsl,imx7d-adc";
-                                reg = <0x30620000 0x10000>;
-                                interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ADC_ROOT_CLK>;
-                                clock-names = "adc";
-                                status = "disabled";
-                        };
-
-                        pwm1: pwm@30660000 {
-                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
-                                reg = <0x30660000 0x10000>;
-                                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
-                                         <&clks IMX7D_PWM1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                #pwm-cells = <2>;
-                                status = "disabled";
-                        };
-
-                        pwm2: pwm@30670000 {
-                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
-                                reg = <0x30670000 0x10000>;
-                                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
-                                         <&clks IMX7D_PWM2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                #pwm-cells = <2>;
-                                status = "disabled";
-                        };
-
-                        pwm3: pwm@30680000 {
-                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
-                                reg = <0x30680000 0x10000>;
-                                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
-                                         <&clks IMX7D_PWM3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                #pwm-cells = <2>;
-                                status = "disabled";
-                        };
-
-                        pwm4: pwm@30690000 {
-                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
-                                reg = <0x30690000 0x10000>;
-                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
-                                         <&clks IMX7D_PWM4_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                #pwm-cells = <2>;
-                                status = "disabled";
-                        };
-
-                        lcdif: lcdif@30730000 {
-                                compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
-                                reg = <0x30730000 0x10000>;
-                                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>;
-                                clock-names = "pix", "axi", "disp_axi";
-                                status = "disabled";
-                        };
-                };
-
-                aips3: aips-bus@30800000 {
-                        compatible = "fsl,aips-bus", "simple-bus";
-                        #address-cells = <1>;
-                        #size-cells = <1>;
-                        reg = <0x30800000 0x400000>;
-                        ranges;
-
-                        uart1: serial@30860000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30860000 0x10000>;
-                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART1_ROOT_CLK>,
-                                        <&clks IMX7D_UART1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        uart2: serial@30890000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30890000 0x10000>;
-                                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART2_ROOT_CLK>,
-                                        <&clks IMX7D_UART2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        uart3: serial@30880000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30880000 0x10000>;
-                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART3_ROOT_CLK>,
-                                        <&clks IMX7D_UART3_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        flexcan1: can@30a00000 {
-                                compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
-                                reg = <0x30a00000 0x10000>;
-                                interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CAN1_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        flexcan2: can@30a10000 {
-                                compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
-                                reg = <0x30a10000 0x10000>;
-                                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CAN2_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        i2c1: i2c@30a20000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
-                                reg = <0x30a20000 0x10000>;
-                                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        i2c2: i2c@30a30000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
-                                reg = <0x30a30000 0x10000>;
-                                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        i2c3: i2c@30a40000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
-                                reg = <0x30a40000 0x10000>;
-                                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        i2c4: i2c@30a50000 {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
-                                reg = <0x30a50000 0x10000>;
-                                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
-                                status = "disabled";
-                        };
-
-                        uart4: serial@30a60000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30a60000 0x10000>;
-                                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART4_ROOT_CLK>,
-                                        <&clks IMX7D_UART4_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        uart5: serial@30a70000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30a70000 0x10000>;
-                                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART5_ROOT_CLK>,
-                                        <&clks IMX7D_UART5_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        uart6: serial@30a80000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30a80000 0x10000>;
-                                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART6_ROOT_CLK>,
-                                        <&clks IMX7D_UART6_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        uart7: serial@30a90000 {
-                                compatible = "fsl,imx7d-uart",
-                                             "fsl,imx6q-uart";
-                                reg = <0x30a90000 0x10000>;
-                                interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_UART7_ROOT_CLK>,
-                                        <&clks IMX7D_UART7_ROOT_CLK>;
-                                clock-names = "ipg", "per";
-                                status = "disabled";
-                        };
-
-                        usbotg1: usb@30b10000 {
-                                compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
-                                reg = <0x30b10000 0x200>;
-                                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_USB_CTRL_CLK>;
-                                fsl,usbphy = <&usbphynop1>;
-                                fsl,usbmisc = <&usbmisc1 0>;
-                                phy-clkgate-delay-us = <400>;
-                                status = "disabled";
-                        };
-
-                        usbotg2: usb@30b20000 {
-                                compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
-                                reg = <0x30b20000 0x200>;
-                                interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_USB_CTRL_CLK>;
-                                fsl,usbphy = <&usbphynop2>;
-                                fsl,usbmisc = <&usbmisc2 0>;
-                                phy-clkgate-delay-us = <400>;
-                                status = "disabled";
-                        };
-
-                        usbh: usb@30b30000 {
-                                compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
-                                reg = <0x30b30000 0x200>;
-                                interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_USB_CTRL_CLK>;
-                                fsl,usbphy = <&usbphynop3>;
-                                fsl,usbmisc = <&usbmisc3 0>;
-                                phy_type = "hsic";
-                                dr_mode = "host";
-                                phy-clkgate-delay-us = <400>;
-                                status = "disabled";
-                        };
-
-                        usbmisc1: usbmisc@30b10200 {
-                                #index-cells = <1>;
-                                compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
-                                reg = <0x30b10200 0x200>;
-                        };
-
-                        usbmisc2: usbmisc@30b20200 {
-                                #index-cells = <1>;
-                                compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
-                                reg = <0x30b20200 0x200>;
-                        };
-
-                        usbmisc3: usbmisc@30b30200 {
-                                #index-cells = <1>;
-                                compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
-                                reg = <0x30b30200 0x200>;
-                        };
-
-                        usbphynop1: usbphynop1 {
-                                compatible = "usb-nop-xceiv";
-                                clocks = <&clks IMX7D_USB_PHY1_CLK>;
-                                clock-names = "main_clk";
-                        };
-
-                        usbphynop2: usbphynop2 {
-                                compatible = "usb-nop-xceiv";
-                                clocks = <&clks IMX7D_USB_PHY2_CLK>;
-                                clock-names = "main_clk";
-                        };
-
-                        usbphynop3: usbphynop3 {
-                                compatible = "usb-nop-xceiv";
-                                clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
-                                clock-names = "main_clk";
-                        };
-
-                        usdhc1: usdhc@30b40000 {
-                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
-                                reg = <0x30b40000 0x10000>;
-                                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_USDHC1_ROOT_CLK>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
+&aips3 {
+        usbotg2: usb@30b20000 {
+                compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+                reg = <0x30b20000 0x200>;
+                interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clks IMX7D_USB_CTRL_CLK>;
+                fsl,usbphy = <&usbphynop2>;
+                fsl,usbmisc = <&usbmisc2 0>;
+                phy-clkgate-delay-us = <400>;
+                status = "disabled";
+        };
 
-                        usdhc2: usdhc@30b50000 {
-                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
-                                reg = <0x30b50000 0x10000>;
-                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_USDHC2_ROOT_CLK>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
+        usbmisc2: usbmisc@30b20200 {
+                #index-cells = <1>;
+                compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+                reg = <0x30b20200 0x200>;
+        };
 
-                        usdhc3: usdhc@30b60000 {
-                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
-                                reg = <0x30b60000 0x10000>;
-                                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_CLK_DUMMY>,
-                                        <&clks IMX7D_USDHC3_ROOT_CLK>;
-                                clock-names = "ipg", "ahb", "per";
-                                bus-width = <4>;
-                                status = "disabled";
-                        };
+        usbphynop2: usbphynop2 {
+                compatible = "usb-nop-xceiv";
+                clocks = <&clks IMX7D_USB_PHY2_CLK>;
+                clock-names = "main_clk";
+        };
 
-                        fec1: ethernet@30be0000 {
-                                compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
-                                reg = <0x30be0000 0x10000>;
-                                interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-                                        <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-                                        <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
-                                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
-                                        <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
-                                        <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
-                                        <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
-                                clock-names = "ipg", "ahb", "ptp",
-                                        "enet_clk_ref", "enet_out";
-                                fsl,num-tx-queues=<3>;
-                                fsl,num-rx-queues=<3>;
-                                status = "disabled";
-                        };
+        fec2: ethernet@30bf0000 {
+                compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+                reg = <0x30bf0000 0x10000>;
+                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+                        <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+                        <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                        <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
+                        <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+                        <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+                clock-names = "ipg", "ahb", "ptp",
+                        "enet_clk_ref", "enet_out";
+                fsl,num-tx-queues=<3>;
+                fsl,num-rx-queues=<3>;
+                status = "disabled";
+        };
+};
 
-                        fec2: ethernet@30bf0000 {
-                                compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
-                                reg = <0x30bf0000 0x10000>;
-                                interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
-                                        <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
-                                        <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
-                                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
-                                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
-                                        <&clks IMX7D_ENET2_TIME_ROOT_CLK>,
-                                        <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
-                                        <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
-                                clock-names = "ipg", "ahb", "ptp",
-                                        "enet_clk_ref", "enet_out";
-                                fsl,num-tx-queues=<3>;
-                                fsl,num-rx-queues=<3>;
-                                status = "disabled";
-                        };
+&ca_funnel_ports {
+        port@1 {
+                reg = <1>;
+                ca_funnel_in_port1: endpoint {
+                        slave-mode;
+                        remote-endpoint = <&etm1_out_port>;
                 };
         };
 };
diff --git a/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
new file mode 100644
index 000000000000..bd2a49c1ade6
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-eval-v3.dts
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-eval-v3.dtsi"
+
+/ {
+        model = "Toradex Colibri iMX7S on Colibri Evaluation Board V3";
+        compatible = "toradex,colibri-imx7s-eval-v3", "toradex,colibri-imx7s",
+                     "fsl,imx7s";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
new file mode 100644
index 000000000000..b81013455b21
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx7s.dtsi"
+#include "imx7-colibri.dtsi"
+
+/ {
+        memory {
+                reg = <0x80000000 0x10000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
new file mode 100644
index 000000000000..1e90bdbe3a6e
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -0,0 +1,933 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/imx7d-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "imx7d-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+        aliases {
+                gpio0 = &gpio1;
+                gpio1 = &gpio2;
+                gpio2 = &gpio3;
+                gpio3 = &gpio4;
+                gpio4 = &gpio5;
+                gpio5 = &gpio6;
+                gpio6 = &gpio7;
+                i2c0 = &i2c1;
+                i2c1 = &i2c2;
+                i2c2 = &i2c3;
+                i2c3 = &i2c4;
+                mmc0 = &usdhc1;
+                mmc1 = &usdhc2;
+                mmc2 = &usdhc3;
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+                serial6 = &uart7;
+                spi0 = &ecspi1;
+                spi1 = &ecspi2;
+                spi2 = &ecspi3;
+                spi3 = &ecspi4;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        compatible = "arm,cortex-a7";
+                        device_type = "cpu";
+                        reg = <0>;
+                        operating-points = <
+                                /* KHz  uV */
+                                996000  1075000
+                                792000  975000
+                        >;
+                        clock-latency = <61036>; /* two CLK32 periods */
+                        clocks = <&clks IMX7D_CLK_ARM>;
+                };
+        };
+
+        intc: interrupt-controller@31001000 {
+                compatible = "arm,cortex-a7-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x31001000 0x1000>,
+                      <0x31002000 0x1000>,
+                      <0x31004000 0x2000>,
+                      <0x31006000 0x2000>;
+        };
+
+        ckil: clock-cki {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <32768>;
+                clock-output-names = "ckil";
+        };
+
+        osc: clock-osc {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <24000000>;
+                clock-output-names = "osc";
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+                interrupt-parent = <&intc>;
+        };
+
+        etr@30086000 {
+                compatible = "arm,coresight-tmc", "arm,primecell";
+                reg = <0x30086000 0x1000>;
+                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+                clock-names = "apb_pclk";
+
+                port {
+                        etr_in_port: endpoint {
+                                slave-mode;
+                                remote-endpoint = <&replicator_out_port1>;
+                        };
+                };
+        };
+
+        tpiu@30087000 {
+                compatible = "arm,coresight-tpiu", "arm,primecell";
+                reg = <0x30087000 0x1000>;
+                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+                clock-names = "apb_pclk";
+
+                port {
+                        tpiu_in_port: endpoint {
+                                slave-mode;
+                                remote-endpoint = <&replicator_out_port1>;
+                        };
+                };
+        };
+
+        replicator {
+                /*
+                 * non-configurable replicators don't show up on the
+                 * AMBA bus.  As such no need to add "arm,primecell"
+                 */
+                compatible = "arm,coresight-replicator";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        /* replicator output ports */
+                        port@0 {
+                                reg = <0>;
+                                replicator_out_port0: endpoint {
+                                        remote-endpoint = <&tpiu_in_port>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                replicator_out_port1: endpoint {
+                                        remote-endpoint = <&etr_in_port>;
+                                };
+                        };
+
+                        /* replicator input port */
+                        port@2 {
+                                reg = <0>;
+                                replicator_in_port0: endpoint {
+                                        slave-mode;
+                                        remote-endpoint = <&etf_out_port>;
+                                };
+                        };
+                };
+        };
+
+        etf@30084000 {
+                compatible = "arm,coresight-tmc", "arm,primecell";
+                reg = <0x30084000 0x1000>;
+                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+                clock-names = "apb_pclk";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        port@0 {
+                                reg = <0>;
+                                etf_in_port: endpoint {
+                                        slave-mode;
+                                        remote-endpoint = <&hugo_funnel_out_port0>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <0>;
+                                etf_out_port: endpoint {
+                                        remote-endpoint = <&replicator_in_port0>;
+                                };
+                        };
+                };
+        };
+
+        funnel@30083000 {
+                compatible = "arm,coresight-funnel", "arm,primecell";
+                reg = <0x30083000 0x1000>;
+                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+                clock-names = "apb_pclk";
+
+                ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        /* funnel input ports */
+                        port@0 {
+                                reg = <0>;
+                                hugo_funnel_in_port0: endpoint {
+                                        slave-mode;
+                                        remote-endpoint = <&ca_funnel_out_port0>;
+                                };
+                        };
+
+                        port@1 {
+                                reg = <1>;
+                                hugo_funnel_in_port1: endpoint {
+                                        slave-mode; /* M4 input */
+                                };
+                        };
+
+                        port@2 {
+                                reg = <0>;
+                                hugo_funnel_out_port0: endpoint {
+                                        remote-endpoint = <&etf_in_port>;
+                                };
+                        };
+
+                        /* the other input ports are not connect to anything */
+                };
+        };
+
+        funnel@30041000 {
+                compatible = "arm,coresight-funnel", "arm,primecell";
+                reg = <0x30041000 0x1000>;
+                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+                clock-names = "apb_pclk";
+
+                ca_funnel_ports: ports {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        /* funnel input ports */
+                        port@0 {
+                                reg = <0>;
+                                ca_funnel_in_port0: endpoint {
+                                        slave-mode;
+                                        remote-endpoint = <&etm0_out_port>;
+                                };
+                        };
+
+                        /* funnel output port */
+                        port@2 {
+                                reg = <0>;
+                                ca_funnel_out_port0: endpoint {
+                                        remote-endpoint = <&hugo_funnel_in_port0>;
+                                };
+                        };
+
+                        /* the other input ports are not connect to anything */
+                };
+        };
+
+        etm@3007c000 {
+                compatible = "arm,coresight-etm3x", "arm,primecell";
+                reg = <0x3007c000 0x1000>;
+                cpu = <&cpu0>;
+                clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
+                clock-names = "apb_pclk";
+
+                port {
+                        etm0_out_port: endpoint {
+                                remote-endpoint = <&ca_funnel_in_port0>;
+                        };
+                };
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&intc>;
+                ranges;
+
+                aips1: aips-bus@30000000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x30000000 0x400000>;
+                        ranges;
+
+                        gpio1: gpio@30200000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30200000 0x10000>;
+                                interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */
+                                             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio2: gpio@30210000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30210000 0x10000>;
+                                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio3: gpio@30220000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30220000 0x10000>;
+                                interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio4: gpio@30230000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30230000 0x10000>;
+                                interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio5: gpio@30240000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30240000 0x10000>;
+                                interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio6: gpio@30250000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30250000 0x10000>;
+                                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        gpio7: gpio@30260000 {
+                                compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
+                                reg = <0x30260000 0x10000>;
+                                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                        };
+
+                        wdog1: wdog@30280000 {
+                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+                                reg = <0x30280000 0x10000>;
+                                interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
+                        };
+
+                        wdog2: wdog@30290000 {
+                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+                                reg = <0x30290000 0x10000>;
+                                interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_WDOG2_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        wdog3: wdog@302a0000 {
+                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+                                reg = <0x302a0000 0x10000>;
+                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_WDOG3_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        wdog4: wdog@302b0000 {
+                                compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
+                                reg = <0x302b0000 0x10000>;
+                                interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_WDOG4_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        iomuxc_lpsr: iomuxc-lpsr@302c0000 {
+                                compatible = "fsl,imx7d-iomuxc-lpsr";
+                                reg = <0x302c0000 0x10000>;
+                                fsl,input-sel = <&iomuxc>;
+                        };
+
+                        gpt1: gpt@302d0000 {
+                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+                                reg = <0x302d0000 0x10000>;
+                                interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                         <&clks IMX7D_GPT1_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                        };
+
+                        gpt2: gpt@302e0000 {
+                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+                                reg = <0x302e0000 0x10000>;
+                                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                         <&clks IMX7D_GPT2_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        gpt3: gpt@302f0000 {
+                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+                                reg = <0x302f0000 0x10000>;
+                                interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                         <&clks IMX7D_GPT3_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        gpt4: gpt@30300000 {
+                                compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt";
+                                reg = <0x30300000 0x10000>;
+                                interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                         <&clks IMX7D_GPT4_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        iomuxc: iomuxc@30330000 {
+                                compatible = "fsl,imx7d-iomuxc";
+                                reg = <0x30330000 0x10000>;
+                        };
+
+                        gpr: iomuxc-gpr@30340000 {
+                                compatible = "fsl,imx7d-iomuxc-gpr", "syscon";
+                                reg = <0x30340000 0x10000>;
+                        };
+
+                        ocotp: ocotp-ctrl@30350000 {
+                                compatible = "syscon";
+                                reg = <0x30350000 0x10000>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>;
+                                status = "disabled";
+                        };
+
+                        anatop: anatop@30360000 {
+                                compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop",
+                                        "syscon", "simple-bus";
+                                reg = <0x30360000 0x10000>;
+                                interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                        <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+
+                                reg_1p0d: regulator-vdd1p0d {
+                                        compatible = "fsl,anatop-regulator";
+                                        regulator-name = "vdd1p0d";
+                                        regulator-min-microvolt = <800000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        anatop-reg-offset = <0x210>;
+                                        anatop-vol-bit-shift = <8>;
+                                        anatop-vol-bit-width = <5>;
+                                        anatop-min-bit-val = <8>;
+                                        anatop-min-voltage = <800000>;
+                                        anatop-max-voltage = <1200000>;
+                                        anatop-enable-bit = <31>;
+                                };
+                        };
+
+                        snvs: snvs@30370000 {
+                                compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+                                reg = <0x30370000 0x10000>;
+
+                                snvs_rtc: snvs-rtc-lp {
+                                        compatible = "fsl,sec-v4.0-mon-rtc-lp";
+                                        regmap = <&snvs>;
+                                        offset = <0x34>;
+                                        interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+                                                     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                                };
+
+                                snvs_poweroff: snvs-poweroff {
+                                        compatible = "syscon-poweroff";
+                                        regmap = <&snvs>;
+                                        offset = <0x38>;
+                                        mask = <0x60>;
+                                };
+
+                                snvs_pwrkey: snvs-powerkey {
+                                        compatible = "fsl,sec-v4.0-pwrkey";
+                                        regmap = <&snvs>;
+                                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                                        linux,keycode = <KEY_POWER>;
+                                        wakeup-source;
+                                };
+                        };
+
+                        clks: ccm@30380000 {
+                                compatible = "fsl,imx7d-ccm";
+                                reg = <0x30380000 0x10000>;
+                                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                                #clock-cells = <1>;
+                                clocks = <&ckil>, <&osc>;
+                                clock-names = "ckil", "osc";
+                        };
+
+                        src: src@30390000 {
+                                compatible = "fsl,imx7d-src", "fsl,imx51-src", "syscon";
+                                reg = <0x30390000 0x10000>;
+                                interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                                #reset-cells = <1>;
+                        };
+                };
+
+                aips2: aips-bus@30400000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x30400000 0x400000>;
+                        ranges;
+
+                        adc1: adc@30610000 {
+                                compatible = "fsl,imx7d-adc";
+                                reg = <0x30610000 0x10000>;
+                                interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
+
+                        adc2: adc@30620000 {
+                                compatible = "fsl,imx7d-adc";
+                                reg = <0x30620000 0x10000>;
+                                interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ADC_ROOT_CLK>;
+                                clock-names = "adc";
+                                status = "disabled";
+                        };
+
+                        ecspi4: ecspi@30630000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                reg = <0x30630000 0x10000>;
+                                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>,
+                                        <&clks IMX7D_ECSPI4_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        pwm1: pwm@30660000 {
+                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+                                reg = <0x30660000 0x10000>;
+                                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
+                                         <&clks IMX7D_PWM1_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                #pwm-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        pwm2: pwm@30670000 {
+                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+                                reg = <0x30670000 0x10000>;
+                                interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
+                                         <&clks IMX7D_PWM2_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                #pwm-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        pwm3: pwm@30680000 {
+                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+                                reg = <0x30680000 0x10000>;
+                                interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
+                                         <&clks IMX7D_PWM3_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                #pwm-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        pwm4: pwm@30690000 {
+                                compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
+                                reg = <0x30690000 0x10000>;
+                                interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
+                                         <&clks IMX7D_PWM4_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                #pwm-cells = <2>;
+                                status = "disabled";
+                        };
+
+                        lcdif: lcdif@30730000 {
+                                compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif";
+                                reg = <0x30730000 0x10000>;
+                                interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>,
+                                        <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CLK_DUMMY>;
+                                clock-names = "pix", "axi", "disp_axi";
+                                status = "disabled";
+                        };
+                };
+
+                aips3: aips-bus@30800000 {
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x30800000 0x400000>;
+                        ranges;
+
+                        ecspi1: ecspi@30820000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                reg = <0x30820000 0x10000>;
+                                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+                                        <&clks IMX7D_ECSPI1_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        ecspi2: ecspi@30830000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                reg = <0x30830000 0x10000>;
+                                interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+                                        <&clks IMX7D_ECSPI2_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        ecspi3: ecspi@30840000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+                                reg = <0x30840000 0x10000>;
+                                interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+                                        <&clks IMX7D_ECSPI3_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart1: serial@30860000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30860000 0x10000>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+                                        <&clks IMX7D_UART1_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart2: serial@30890000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30890000 0x10000>;
+                                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+                                        <&clks IMX7D_UART2_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart3: serial@30880000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30880000 0x10000>;
+                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+                                        <&clks IMX7D_UART3_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        flexcan1: can@30a00000 {
+                                compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+                                reg = <0x30a00000 0x10000>;
+                                interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CAN1_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        flexcan2: can@30a10000 {
+                                compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan";
+                                reg = <0x30a10000 0x10000>;
+                                interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CAN2_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        i2c1: i2c@30a20000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+                                reg = <0x30a20000 0x10000>;
+                                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_I2C1_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        i2c2: i2c@30a30000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+                                reg = <0x30a30000 0x10000>;
+                                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_I2C2_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        i2c3: i2c@30a40000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+                                reg = <0x30a40000 0x10000>;
+                                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_I2C3_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        i2c4: i2c@30a50000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c";
+                                reg = <0x30a50000 0x10000>;
+                                interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_I2C4_ROOT_CLK>;
+                                status = "disabled";
+                        };
+
+                        uart4: serial@30a60000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30a60000 0x10000>;
+                                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART4_ROOT_CLK>,
+                                        <&clks IMX7D_UART4_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart5: serial@30a70000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30a70000 0x10000>;
+                                interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART5_ROOT_CLK>,
+                                        <&clks IMX7D_UART5_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart6: serial@30a80000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30a80000 0x10000>;
+                                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART6_ROOT_CLK>,
+                                        <&clks IMX7D_UART6_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        uart7: serial@30a90000 {
+                                compatible = "fsl,imx7d-uart",
+                                             "fsl,imx6q-uart";
+                                reg = <0x30a90000 0x10000>;
+                                interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_UART7_ROOT_CLK>,
+                                        <&clks IMX7D_UART7_ROOT_CLK>;
+                                clock-names = "ipg", "per";
+                                status = "disabled";
+                        };
+
+                        usbotg1: usb@30b10000 {
+                                compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+                                reg = <0x30b10000 0x200>;
+                                interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_USB_CTRL_CLK>;
+                                fsl,usbphy = <&usbphynop1>;
+                                fsl,usbmisc = <&usbmisc1 0>;
+                                phy-clkgate-delay-us = <400>;
+                                status = "disabled";
+                        };
+
+                        usbh: usb@30b30000 {
+                                compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
+                                reg = <0x30b30000 0x200>;
+                                interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_USB_CTRL_CLK>;
+                                fsl,usbphy = <&usbphynop3>;
+                                fsl,usbmisc = <&usbmisc3 0>;
+                                phy_type = "hsic";
+                                dr_mode = "host";
+                                phy-clkgate-delay-us = <400>;
+                                status = "disabled";
+                        };
+
+                        usbmisc1: usbmisc@30b10200 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+                                reg = <0x30b10200 0x200>;
+                        };
+
+                        usbmisc3: usbmisc@30b30200 {
+                                #index-cells = <1>;
+                                compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
+                                reg = <0x30b30200 0x200>;
+                        };
+
+                        usbphynop1: usbphynop1 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks IMX7D_USB_PHY1_CLK>;
+                                clock-names = "main_clk";
+                        };
+
+                        usbphynop3: usbphynop3 {
+                                compatible = "usb-nop-xceiv";
+                                clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
+                                clock-names = "main_clk";
+                        };
+
+                        usdhc1: usdhc@30b40000 {
+                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+                                reg = <0x30b40000 0x10000>;
+                                interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_USDHC1_ROOT_CLK>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc2: usdhc@30b50000 {
+                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+                                reg = <0x30b50000 0x10000>;
+                                interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_USDHC2_ROOT_CLK>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        usdhc3: usdhc@30b60000 {
+                                compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc";
+                                reg = <0x30b60000 0x10000>;
+                                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_CLK_DUMMY>,
+                                        <&clks IMX7D_USDHC3_ROOT_CLK>;
+                                clock-names = "ipg", "ahb", "per";
+                                bus-width = <4>;
+                                status = "disabled";
+                        };
+
+                        fec1: ethernet@30be0000 {
+                                compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
+                                reg = <0x30be0000 0x10000>;
+                                interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+                                        <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+                                        <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                                        <&clks IMX7D_ENET_AXI_ROOT_CLK>,
+                                        <&clks IMX7D_ENET1_TIME_ROOT_CLK>,
+                                        <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
+                                        <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
+                                clock-names = "ipg", "ahb", "ptp",
+                                        "enet_clk_ref", "enet_out";
+                                fsl,num-tx-queues=<3>;
+                                fsl,num-rx-queues=<3>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/keystone-k2e.dtsi b/arch/arm/boot/dts/keystone-k2e.dtsi
index 96b349fb0430..9a51b8c88581 100644
--- a/arch/arm/boot/dts/keystone-k2e.dtsi
+++ b/arch/arm/boot/dts/keystone-k2e.dtsi
@@ -96,13 +96,16 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         reg =  <0x21021000 0x2000>, <0x21020000 0x1000>, <0x02620128 4>;
-                        ranges = <0x81000000 0 0 0x23260000 0x4000 0x4000
-                                0x82000000 0 0x60000000 0x60000000 0 0x10000000>;
+                        ranges = <0x82000000 0 0x60000000 0x60000000
+                                  0 0x10000000>;
 
                         status = "disabled";
                         device_type = "pci";
                         num-lanes = <2>;
+                        bus-range = <0x00 0xff>;
 
+                        /* error interrupt */
+                        interrupts = <GIC_SPI 385 IRQ_TYPE_EDGE_RISING>;
                         #interrupt-cells = <1>;
                         interrupt-map-mask = <0 0 0 7>;
                         interrupt-map = <0 0 0 1 &pcie_intc1 0>, /* INT A */
diff --git a/arch/arm/boot/dts/keystone-k2g-evm.dts b/arch/arm/boot/dts/keystone-k2g-evm.dts
index 5bfd9e7845f2..692fcbb1434a 100644
--- a/arch/arm/boot/dts/keystone-k2g-evm.dts
+++ b/arch/arm/boot/dts/keystone-k2g-evm.dts
@@ -27,6 +27,17 @@
 
 };
 
+&k2g_pinctrl {
+        uart0_pins: pinmux_uart0_pins {
+                pinctrl-single,pins = <
+                        K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0)      /* uart0_rxd.uart0_rxd */
+                        K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0)      /* uart0_txd.uart0_txd */
+                >;
+        };
+};
+
 &uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/keystone-k2g.dtsi b/arch/arm/boot/dts/keystone-k2g.dtsi
index 7ff2796ae925..3372615b885c 100644
--- a/arch/arm/boot/dts/keystone-k2g.dtsi
+++ b/arch/arm/boot/dts/keystone-k2g.dtsi
@@ -14,6 +14,7 @@
  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/keystone.h>
 #include "skeleton.dtsi"
 
 / {
@@ -75,6 +76,13 @@
                 ranges = <0x0 0x0 0x0 0xc0000000>;
                 dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
 
+                k2g_pinctrl: pinmux@02621000 {
+                        compatible = "pinctrl-single";
+                        reg = <0x02621000 0x410>;
+                        pinctrl-single,register-width = <32>;
+                        pinctrl-single,function-mask = <0x001b0007>;
+                };
+
                 uart0: serial@02530c00 {
                         compatible = "ns16550a";
                         current-speed = <115200>;
diff --git a/arch/arm/boot/dts/keystone-k2l.dtsi b/arch/arm/boot/dts/keystone-k2l.dtsi
index ff22ffc3dee7..2ee3d0ac2816 100644
--- a/arch/arm/boot/dts/keystone-k2l.dtsi
+++ b/arch/arm/boot/dts/keystone-k2l.dtsi
@@ -54,6 +54,155 @@
                         interrupts = <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>;
                 };
 
+                k2l_pmx: pinmux@02620690 {
+                        compatible = "pinctrl-single";
+                        reg = <0x02620690 0xc>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,bit-per-mux;
+                        pinctrl-single,register-width = <32>;
+                        pinctrl-single,function-mask = <0x1>;
+                        status = "disabled";
+
+                        uart3_emifa_pins: pinmux_uart3_emifa_pins {
+                                pinctrl-single,bits = <
+                                        /* UART3_EMIFA_SEL */
+                                        0x0 0x0  0xc0
+                                >;
+                        };
+
+                        uart2_emifa_pins: pinmux_uart2_emifa_pins {
+                        pinctrl-single,bits = <
+                                        /* UART2_EMIFA_SEL */
+                                        0x0 0x0  0x30
+                                >;
+                        };
+
+                        uart01_spi2_pins: pinmux_uart01_spi2_pins {
+                                pinctrl-single,bits = <
+                                        /* UART01_SPI2_SEL */
+                                        0x0 0x0 0x4
+                                >;
+                        };
+
+                        dfesync_rp1_pins: pinmux_dfesync_rp1_pins{
+                                pinctrl-single,bits = <
+                                        /* DFESYNC_RP1_SEL */
+                                        0x0 0x0 0x2
+                                >;
+                        };
+
+                        avsif_pins: pinmux_avsif_pins {
+                                pinctrl-single,bits = <
+                                        /* AVSIF_SEL */
+                                        0x0 0x0 0x1
+                                >;
+                        };
+
+                        gpio_emu_pins: pinmux_gpio_emu_pins {
+                                pinctrl-single,bits = <
+                                /*
+                                 * GPIO_EMU_SEL[31]: 0-GPIO31, 1-EMU33
+                                 * GPIO_EMU_SEL[30]: 0-GPIO30, 1-EMU32
+                                 * GPIO_EMU_SEL[29]: 0-GPIO29, 1-EMU31
+                                 * GPIO_EMU_SEL[28]: 0-GPIO28, 1-EMU30
+                                 * GPIO_EMU_SEL[27]: 0-GPIO27, 1-EMU29
+                                 * GPIO_EMU_SEL[26]: 0-GPIO26, 1-EMU28
+                                 * GPIO_EMU_SEL[25]: 0-GPIO25, 1-EMU27
+                                 * GPIO_EMU_SEL[24]: 0-GPIO24, 1-EMU26
+                                 * GPIO_EMU_SEL[23]: 0-GPIO23, 1-EMU25
+                                 * GPIO_EMU_SEL[22]: 0-GPIO22, 1-EMU24
+                                 * GPIO_EMU_SEL[21]: 0-GPIO21, 1-EMU23
+                                 * GPIO_EMU_SEL[20]: 0-GPIO20, 1-EMU22
+                                 * GPIO_EMU_SEL[19]: 0-GPIO19, 1-EMU21
+                                 * GPIO_EMU_SEL[18]: 0-GPIO18, 1-EMU20
+                                 * GPIO_EMU_SEL[17]: 0-GPIO17, 1-EMU19
+                                 */
+                                        0x4 0x0000 0xFFFE0000
+                                >;
+                        };
+
+                        gpio_timio_pins: pinmux_gpio_timio_pins {
+                                pinctrl-single,bits = <
+                                /*
+                                 * GPIO_TIMIO_SEL[15]: 0-GPIO15, 1-TIMO7
+                                 * GPIO_TIMIO_SEL[14]: 0-GPIO14, 1-TIMO6
+                                 * GPIO_TIMIO_SEL[13]: 0-GPIO13, 1-TIMO5
+                                 * GPIO_TIMIO_SEL[12]: 0-GPIO12, 1-TIMO4
+                                 * GPIO_TIMIO_SEL[11]: 0-GPIO11, 1-TIMO3
+                                 * GPIO_TIMIO_SEL[10]: 0-GPIO10, 1-TIMO2
+                                 * GPIO_TIMIO_SEL[9]: 0-GPIO9, 1-TIMI7
+                                 * GPIO_TIMIO_SEL[8]: 0-GPIO8, 1-TIMI6
+                                 * GPIO_TIMIO_SEL[7]: 0-GPIO7, 1-TIMI5
+                                 * GPIO_TIMIO_SEL[6]: 0-GPIO6, 1-TIMI4
+                                 * GPIO_TIMIO_SEL[5]: 0-GPIO5, 1-TIMI3
+                                 * GPIO_TIMIO_SEL[4]: 0-GPIO4, 1-TIMI2
+                                 */
+                                        0x4 0x0 0xFFF0
+                                >;
+                        };
+
+                        gpio_spi2cs_pins: pinmux_gpio_spi2cs_pins {
+                                pinctrl-single,bits = <
+                                /*
+                                 * GPIO_SPI2CS_SEL[3]: 0-GPIO3, 1-SPI2CS4
+                                 * GPIO_SPI2CS_SEL[2]: 0-GPIO2, 1-SPI2CS3
+                                 * GPIO_SPI2CS_SEL[1]: 0-GPIO1, 1-SPI2CS2
+                                 * GPIO_SPI2CS_SEL[0]: 0-GPIO0, 1-SPI2CS1
+                                 */
+                                        0x4 0x0 0xF
+                                >;
+                        };
+
+                        gpio_dfeio_pins: pinmux_gpio_dfeio_pins {
+                                pinctrl-single,bits = <
+                                /*
+                                 * GPIO_DFEIO_SEL[31]: 0-DFEIO17, 1-GPIO63
+                                 * GPIO_DFEIO_SEL[30]: 0-DFEIO16, 1-GPIO62
+                                 * GPIO_DFEIO_SEL[29]: 0-DFEIO15, 1-GPIO61
+                                 * GPIO_DFEIO_SEL[28]: 0-DFEIO14, 1-GPIO60
+                                 * GPIO_DFEIO_SEL[27]: 0-DFEIO13, 1-GPIO59
+                                 * GPIO_DFEIO_SEL[26]: 0-DFEIO12, 1-GPIO58
+                                 * GPIO_DFEIO_SEL[25]: 0-DFEIO11, 1-GPIO57
+                                 * GPIO_DFEIO_SEL[24]: 0-DFEIO10, 1-GPIO56
+                                 * GPIO_DFEIO_SEL[23]: 0-DFEIO9, 1-GPIO55
+                                 * GPIO_DFEIO_SEL[22]: 0-DFEIO8, 1-GPIO54
+                                 * GPIO_DFEIO_SEL[21]: 0-DFEIO7, 1-GPIO53
+                                 * GPIO_DFEIO_SEL[20]: 0-DFEIO6, 1-GPIO52
+                                 * GPIO_DFEIO_SEL[19]: 0-DFEIO5, 1-GPIO51
+                                 * GPIO_DFEIO_SEL[18]: 0-DFEIO4, 1-GPIO50
+                                 * GPIO_DFEIO_SEL[17]: 0-DFEIO3, 1-GPIO49
+                                 * GPIO_DFEIO_SEL[16]: 0-DFEIO2, 1-GPIO48
+                                 */
+                                        0x8 0x0 0xFFFF0000
+                                >;
+                        };
+
+                        gpio_emifa_pins: pinmux_gpio_emifa_pins {
+                                pinctrl-single,bits = <
+                                /*
+                                 * GPIO_EMIFA_SEL[15]: 0-EMIFA17, 1-GPIO47
+                                 * GPIO_EMIFA_SEL[14]: 0-EMIFA16, 1-GPIO46
+                                 * GPIO_EMIFA_SEL[13]: 0-EMIFA15, 1-GPIO45
+                                 * GPIO_EMIFA_SEL[12]: 0-EMIFA14, 1-GPIO44
+                                 * GPIO_EMIFA_SEL[11]: 0-EMIFA13, 1-GPIO43
+                                 * GPIO_EMIFA_SEL[10]: 0-EMIFA10, 1-GPIO42
+                                 * GPIO_EMIFA_SEL[9]: 0-EMIFA9, 1-GPIO41
+                                 * GPIO_EMIFA_SEL[8]: 0-EMIFA8, 1-GPIO40
+                                 * GPIO_EMIFA_SEL[7]: 0-EMIFA7, 1-GPIO39
+                                 * GPIO_EMIFA_SEL[6]: 0-EMIFA6, 1-GPIO38
+                                 * GPIO_EMIFA_SEL[5]: 0-EMIFA5, 1-GPIO37
+                                 * GPIO_EMIFA_SEL[4]: 0-EMIFA4, 1-GPIO36
+                                 * GPIO_EMIFA_SEL[3]: 0-EMIFA3, 1-GPIO35
+                                 * GPIO_EMIFA_SEL[2]: 0-EMIFA2, 1-GPIO34
+                                 * GPIO_EMIFA_SEL[1]: 0-EMIFA1, 1-GPIO33
+                                 * GPIO_EMIFA_SEL[0]: 0-EMIFA0, 1-GPIO32
+                                 */
+                                        0x8 0x0 0xFFFF
+                                >;
+                        };
+                };
+
                 dspgpio0: keystone_dsp_gpio@02620240 {
                         compatible = "ti,keystone-dsp-gpio";
                         gpio-controller;
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index e34b2265458a..e23f46d15c80 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -294,13 +294,16 @@
                         #address-cells = <3>;
                         #size-cells = <2>;
                         reg =  <0x21801000 0x2000>, <0x21800000 0x1000>, <0x02620128 4>;
-                        ranges = <0x81000000 0 0 0x23250000 0 0x4000
-                                0x82000000 0 0x50000000 0x50000000 0 0x10000000>;
+                        ranges = <0x82000000 0 0x50000000 0x50000000
+                                  0 0x10000000>;
 
                         status = "disabled";
                         device_type = "pci";
                         num-lanes = <2>;
+                        bus-range = <0x00 0xff>;
 
+                        /* error interrupt */
+                        interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
                         #interrupt-cells = <1>;
                         interrupt-map-mask = <0 0 0 7>;
                         interrupt-map = <0 0 0 1 &pcie_intc0 0>, /* INT A */
diff --git a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
index 015f795a8d19..08cce17a25a0 100644
--- a/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
+++ b/arch/arm/boot/dts/logicpd-torpedo-37xx-devkit.dts
@@ -72,7 +72,7 @@
                 };
         };
 
-        pwm10: dmtimer-pwm@10 {
+        pwm10: dmtimer-pwm {
                 compatible = "ti,omap-dmtimer-pwm";
                 pinctrl-names = "default";
                 pinctrl-0 = <&pwm_pins>;
@@ -147,7 +147,7 @@
                 gpio = <&gpio5 27 GPIO_ACTIVE_HIGH>;    /* gpio155, lcd INI */
         };
 
-        lcd0: display@0 {
+        lcd0: display {
                 compatible = "panel-dpi";
                 label = "15";
                 status = "okay";
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 5ae8e9297e9a..368e21934285 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -626,6 +626,7 @@
                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
                         dr_mode = "host";
                         snps,quirk-frame-length-adjustment = <0x20>;
+                        snps,dis_rxdet_inp3_quirk;
                 };
 
                 pcie@3400000 {
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 2bfe401a4da9..fc4080de4b7b 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -46,6 +46,7 @@
 
 #include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8b-gpio.h>
+#include <dt-bindings/reset/amlogic,meson8b-reset.h>
 #include "skeleton.dtsi"
 
 / {
@@ -105,6 +106,12 @@
                         #interrupt-cells = <3>;
                 };
 
+                reset: reset-controller@c1104404 {
+                        compatible = "amlogic,meson8b-reset";
+                        reg = <0xc1104404 0x20>;
+                        #reset-cells = <1>;
+                };
+
                 wdt: watchdog@c1109900 {
                         compatible = "amlogic,meson8b-wdt";
                         reg = <0xc1109900 0x8>;
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index f0f5e1098928..116ce78bea4f 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -17,15 +17,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <18432000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -61,7 +52,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
index ca73722b5ea4..769a346de613 100644
--- a/arch/arm/boot/dts/omap24xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -164,7 +164,7 @@
                 clock-div = <1>;
         };
 
-        func_96m_ck: func_96m_ck {
+        func_96m_ck: func_96m_ck@540 {
                 #clock-cells = <0>;
         };
 
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 01e1e2d5c735..8ffde06281ad 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -91,7 +91,7 @@
                 vcc-supply = <&hsusb2_power>;
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder0 {
                 compatible = "ti,tfp410";
                 powerdown-gpios = <&twl_gpio 2 GPIO_ACTIVE_LOW>;
 
@@ -104,7 +104,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_out>;
                                 };
                         };
@@ -112,14 +112,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector0 {
                 compatible = "dvi-connector";
                 label = "dvi";
 
@@ -134,7 +134,7 @@
                 };
         };
 
-        tv0: connector@1 {
+        tv0: connector1 {
                 compatible = "svideo-connector";
                 label = "tv";
 
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index a4deff0e2d52..a19d907d4850 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -85,7 +85,7 @@
 
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder0 {
                 compatible = "ti,tfp410";
                 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;  /* gpio_170 */
 
@@ -99,7 +99,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_out>;
                                 };
                         };
@@ -107,14 +107,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector0 {
                 compatible = "dvi-connector";
                 label = "dvi";
 
@@ -129,7 +129,7 @@
                 };
         };
 
-        tv0: connector@1 {
+        tv0: connector1 {
                 compatible = "svideo-connector";
                 label = "tv";
 
diff --git a/arch/arm/boot/dts/omap3-cm-t3x.dtsi b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
index a8127bc31fd9..6a0df13fa0f3 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x.dtsi
@@ -57,7 +57,7 @@
                 regulator-max-microvolt = <3300000>;
         };
 
-        tv0: connector@1 {
+        tv0: connector {
                 compatible = "svideo-connector";
                 label = "tv";
 
diff --git a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
index b1b8ebf90c1c..586010179752 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-common.dtsi
@@ -68,7 +68,7 @@
                 };
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder0 {
                 compatible = "ti,tfp410";
                 powerdown-gpios = <&twl_gpio 7 GPIO_ACTIVE_LOW>;
 
@@ -79,7 +79,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_dvi_out>;
                                 };
                         };
@@ -87,14 +87,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector0 {
                 compatible = "dvi-connector";
                 label = "dvi";
 
@@ -109,7 +109,7 @@
                 };
         };
 
-        tv0: connector@1 {
+        tv0: connector1 {
                 compatible = "svideo-connector";
                 label = "tv";
 
@@ -352,7 +352,7 @@
         vdda_dac-supply = <&vdac>;
 
         port {
-                dpi_dvi_out: endpoint@0 {
+                dpi_dvi_out: endpoint {
                         remote-endpoint = <&tfp410_in>;
                         data-lines = <24>;
                 };
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi
index 738910db5c0c..2d64bcffaaa8 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd-common.dtsi
@@ -14,7 +14,7 @@
                 display2 = &tv0;
         };
 
-        lcd0: display@0 {
+        lcd0: display {
                 compatible = "panel-dpi";
                 label = "lcd";
 
@@ -30,7 +30,7 @@
 
 &dss {
         port {
-                dpi_lcd_out: endpoint@1 {
+                dpi_lcd_out: endpoint {
                         remote-endpoint = <&lcd_in>;
                         data-lines = <24>;
                 };
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
index d5705356d52c..d8b16398bfb3 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd43.dts
@@ -16,7 +16,7 @@
         model = "TimLL OMAP3 Devkit8000 with 4.3'' LCD panel";
         compatible = "timll,omap3-devkit8000", "ti,omap3";
 
-        lcd0: display@0 {
+        lcd0: display {
                 panel-timing {
                         clock-frequency = <10164705>;
                         hactive = <480>;
diff --git a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
index 4afad4b233ec..edb37ba80498 100644
--- a/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000-lcd70.dts
@@ -16,7 +16,7 @@
         model = "TimLL OMAP3 Devkit8000 with 7.0'' LCD panel";
         compatible = "timll,omap3-devkit8000", "ti,omap3";
 
-        lcd0: display@0 {
+        lcd0: display {
                 panel-timing {
                         clock-frequency = <40000000>;
                         hactive = <800>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dtsi b/arch/arm/boot/dts/omap3-gta04.dtsi
index ab9fb8f49ff3..c09a0574af90 100644
--- a/arch/arm/boot/dts/omap3-gta04.dtsi
+++ b/arch/arm/boot/dts/omap3-gta04.dtsi
@@ -100,12 +100,28 @@
                 };
         };
 
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm11 0 2000000 0>;
+                pwm-names = "backlight";
+                brightness-levels = <0 11 20 30 40 50 60 70 80 90 100>;
+                default-brightness-level = <9>; /* => 90 */
+                pinctrl-names = "default";
+                pinctrl-0 = <&backlight_pins>;
+        };
+
+        pwm11: dmtimer-pwm {
+                compatible = "ti,omap-dmtimer-pwm";
+                ti,timers = <&timer11>;
+                #pwm-cells = <3>;
+        };
+
         hsusb2_phy: hsusb2_phy {
                 compatible = "usb-nop-xceiv";
                 reset-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
         };
 
-        tv0: connector@1 {
+        tv0: connector {
                 compatible = "svideo-connector";
                 label = "tv";
 
@@ -126,19 +142,24 @@
 
                         port@0 {
                                 reg = <0>;
-                                opa_in: endpoint@0 {
+                                opa_in: endpoint {
                                         remote-endpoint = <&venc_out>;
                                 };
                         };
 
                         port@1 {
                                 reg = <1>;
-                                opa_out: endpoint@0 {
+                                opa_out: endpoint {
                                         remote-endpoint = <&tv_connector_in>;
                                 };
                         };
                 };
         };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&tca6507 0 GPIO_ACTIVE_LOW>;     /* W2CBW003 reset through tca6507 */
+        };
 };
 
 &omap3_pmx_core {
@@ -190,6 +211,12 @@
                 >;
         };
 
+        backlight_pins: backlight_pins_pimnux {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20ba, MUX_MODE3)            /* gpt11/gpio57 */
+                >;
+        };
+
         dss_dpi_pins: pinmux_dss_dpi_pins {
                pinctrl-single,pins = <
                         OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0)   /* dss_pclk.dss_pclk */
@@ -228,6 +255,24 @@
                         OMAP3_CORE1_IOPAD(0x21c6, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda.hdq */
                 >;
         };
+
+        bma180_pins: pinmux_bma180_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x213a, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio115 */
+                >;
+        };
+
+        itg3200_pins: pinmux_itg3200_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x20b8, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio56 */
+                >;
+        };
+
+        hmc5843_pins: pinmux_hmc5843_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2134, PIN_INPUT_PULLUP | MUX_MODE4) /* gpio112 */
+                >;
+        };
 };
 
 &omap3_pmx_core2 {
@@ -298,6 +343,8 @@
         bma180@41 {
                 compatible = "bosch,bma180";
                 reg = <0x41>;
+                pinctrl-names = "default";
+                pintcrl-0 = <&bma180_pins>;
                 interrupt-parent = <&gpio4>;
                 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; /* GPIO_115 */
         };
@@ -306,12 +353,14 @@
         itg3200@68 {
                 compatible = "invensense,itg3200";
                 reg = <0x68>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&itg3200_pins>;
                 interrupt-parent = <&gpio2>;
-                interrupts = <24 0>; /* GPIO_56 */
+                interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* GPIO_56 */
         };
 
-        /* leds */
-        tca6507@45 {
+        /* leds + gpios */
+        tca6507: tca6507@45 {
                 compatible = "ti,tca6507";
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -351,6 +400,10 @@
         hmc5843@1e {
                 compatible = "honeywell,hmc5883l";
                 reg = <0x1e>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&hmc5843_pins>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <16 IRQ_TYPE_EDGE_FALLING>;        /* gpio112 */
         };
 
         /* touchscreen */
@@ -362,6 +415,12 @@
                 gpios = <&gpio6 0 GPIO_ACTIVE_LOW>;
                 ti,x-plate-ohms = <600>;
         };
+
+        /* RFID EEPROM */
+        m24lr64@50 {
+                compatible = "at,24c64";
+                reg = <0x50>;
+        };
 };
 
 &i2c3 {
@@ -398,6 +457,7 @@
         bus-width = <4>;
         ti,non-removable;
         cap-power-off-card;
+        mmc-pwrseq = <&wifi_pwrseq>;
 };
 
 &mmc3 {
diff --git a/arch/arm/boot/dts/omap3-ha-lcd.dts b/arch/arm/boot/dts/omap3-ha-lcd.dts
index 11aa28d73f3a..60af7c2358a3 100644
--- a/arch/arm/boot/dts/omap3-ha-lcd.dts
+++ b/arch/arm/boot/dts/omap3-ha-lcd.dts
@@ -121,7 +121,7 @@
                 display0 = &lcd0;
         };
 
-        lcd0: display@0 {
+        lcd0: display {
                 compatible = "panel-dpi";
                 label = "lcd";
 
diff --git a/arch/arm/boot/dts/omap3-igep0020-common.dtsi b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
index b6971060648a..667f96245729 100644
--- a/arch/arm/boot/dts/omap3-igep0020-common.dtsi
+++ b/arch/arm/boot/dts/omap3-igep0020-common.dtsi
@@ -60,7 +60,7 @@
                 vcc-supply = <&hsusb1_power>;
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder {
                 compatible = "ti,tfp410";
                 powerdown-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>; /* gpio_170 */
 
@@ -71,7 +71,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_out>;
                                 };
                         };
@@ -79,14 +79,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector {
                 compatible = "dvi-connector";
                 label = "dvi";
 
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 2b74a81d1de2..2a6078a8422c 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -143,6 +143,18 @@
                 io-channels = <&twl_madc 0>, <&twl_madc 4>, <&twl_madc 12>;
                 io-channel-names = "temp", "bsi", "vbat";
         };
+
+        pwm9: dmtimer-pwm {
+                compatible = "ti,omap-dmtimer-pwm";
+                #pwm-cells = <3>;
+                ti,timers = <&timer9>;
+                ti,clock-source = <0x00>; /* timer_sys_ck */
+        };
+
+        ir: n900-ir {
+                compatible = "nokia,n900-ir";
+                pwms = <&pwm9 0 26316 0>; /* 38000 Hz */
+        };
 };
 
 &omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
index 802f704f67e5..ae5564abbe2f 100644
--- a/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-dvi.dtsi
@@ -69,7 +69,7 @@
                 display0 = &dvi0;
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder {
                 compatible = "ti,tfp410";
 
                 ports {
@@ -79,7 +79,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_out>;
                                 };
                         };
@@ -87,14 +87,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector {
                 compatible = "dvi-connector";
                 label = "dvi";
 
diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
index 6314da2580f5..ca86da68220c 100644
--- a/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-lcd35.dtsi
@@ -119,7 +119,7 @@
         pinctrl-names = "default";
         pinctrl-0 = <&mcspi1_pins>;
 
-        lcd0: display@0 {
+        lcd0: display {
                 compatible = "lgphilips,lb035q02";
                 label = "lcd35";
 
diff --git a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
index 7e3fe85a8ad9..b0753ef8abd4 100644
--- a/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
+++ b/arch/arm/boot/dts/omap3-overo-common-lcd43.dtsi
@@ -96,7 +96,7 @@
                 display0 = &lcd0;
         };
 
-        lcd0: display@0 {
+        lcd0: display {
                 compatible = "samsung,lte430wq-f0c", "panel-dpi";
                 label = "lcd43";
 
diff --git a/arch/arm/boot/dts/omap3-pandora-common.dtsi b/arch/arm/boot/dts/omap3-pandora-common.dtsi
index bcf39d606b65..dbc4dc721cc2 100644
--- a/arch/arm/boot/dts/omap3-pandora-common.dtsi
+++ b/arch/arm/boot/dts/omap3-pandora-common.dtsi
@@ -27,7 +27,7 @@
                 display0 = &lcd;
         };
 
-        tv: connector@1 {
+        tv: connector {
                 compatible = "connector-analog-tv";
                 label = "tv";
 
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index 827f614261f6..73643fabde5d 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -3,7 +3,7 @@
  */
 
 / {
-        tfp410: encoder@0 {
+        tfp410: encoder {
                 compatible = "ti,tfp410";
 
                 powerdown-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;  /* gpio_54 */
@@ -18,7 +18,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_out>;
                                 };
                         };
@@ -26,14 +26,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector {
                 compatible = "dvi-connector";
                 label = "dvi";
 
diff --git a/arch/arm/boot/dts/omap3-thunder.dts b/arch/arm/boot/dts/omap3-thunder.dts
index d659515ab9b8..9736ba79bb5b 100644
--- a/arch/arm/boot/dts/omap3-thunder.dts
+++ b/arch/arm/boot/dts/omap3-thunder.dts
@@ -85,7 +85,7 @@
                 display0 = &lcd0;
         };
 
-        lcd0: display@0 {
+        lcd0: display {
                 compatible = "samsung,lte430wq-f0c", "panel-dpi";
                 label = "lcd";
 
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 9fbda38528dc..4c3c471d2a83 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -493,6 +493,8 @@
                         dmas = <&sdma 31>,
                                <&sdma 32>;
                         dma-names = "tx", "rx";
+                        clocks = <&mcbsp1_fck>;
+                        clock-names = "fck";
                         status = "disabled";
                 };
 
@@ -511,6 +513,8 @@
                         dmas = <&sdma 33>,
                                <&sdma 34>;
                         dma-names = "tx", "rx";
+                        clocks = <&mcbsp2_fck>, <&mcbsp2_ick>;
+                        clock-names = "fck", "ick";
                         status = "disabled";
                 };
 
@@ -529,6 +533,8 @@
                         dmas = <&sdma 17>,
                                <&sdma 18>;
                         dma-names = "tx", "rx";
+                        clocks = <&mcbsp3_fck>, <&mcbsp3_ick>;
+                        clock-names = "fck", "ick";
                         status = "disabled";
                 };
 
@@ -545,6 +551,8 @@
                         dmas = <&sdma 19>,
                                <&sdma 20>;
                         dma-names = "tx", "rx";
+                        clocks = <&mcbsp4_fck>;
+                        clock-names = "fck";
                         status = "disabled";
                 };
 
@@ -561,6 +569,8 @@
                         dmas = <&sdma 21>,
                                <&sdma 22>;
                         dma-names = "tx", "rx";
+                        clocks = <&mcbsp5_fck>;
+                        clock-names = "fck";
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
index 06c54822ddc2..6b39808b8313 100644
--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -40,7 +40,7 @@
                 };
         };
 
-        hdmi0: connector@0 {
+        hdmi0: connector {
                 compatible = "hdmi-connector";
                 label = "hdmi";
 
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
index f2a94fa62552..a90b582e4c3f 100644
--- a/arch/arm/boot/dts/omap4-duovero.dtsi
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -177,6 +177,7 @@
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
+                #clock-cells = <0>;
                 reg = <0x4b>;
                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;         /* IRQ_SYS_2N cascaded to gic */
                 ti,audpwron-gpio = <&gpio6 0 GPIO_ACTIVE_HIGH>;         /* gpio_160 */
@@ -207,6 +208,10 @@
 &mcpdm {
         pinctrl-names = "default";
         pinctrl-0 = <&mcpdm_pins>;
+
+        clocks = <&twl6040>;
+        clock-names = "pdmclk";
+
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index df2e356ec089..f8f13952cfeb 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -103,7 +103,7 @@
                 enable-active-high;
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder0 {
                 compatible = "ti,tfp410";
                 powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;   /* gpio_0 */
 
@@ -114,7 +114,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_out>;
                                 };
                         };
@@ -122,14 +122,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@0 {
+        dvi0: connector0 {
                 compatible = "dvi-connector";
                 label = "dvi";
 
@@ -144,7 +144,7 @@
                 };
         };
 
-        tpd12s015: encoder@1 {
+        tpd12s015: encoder1 {
                 compatible = "ti,tpd12s015";
 
                 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,   /* 60, CT CP HPD */
@@ -158,7 +158,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tpd12s015_in: endpoint@0 {
+                                tpd12s015_in: endpoint {
                                         remote-endpoint = <&hdmi_out>;
                                 };
                         };
@@ -166,14 +166,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tpd12s015_out: endpoint@0 {
+                                tpd12s015_out: endpoint {
                                         remote-endpoint = <&hdmi_connector_in>;
                                 };
                         };
                 };
         };
 
-        hdmi0: connector@1 {
+        hdmi0: connector1 {
                 compatible = "hdmi-connector";
                 label = "hdmi";
 
@@ -376,6 +376,7 @@
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
+                #clock-cells = <0>;
                 reg = <0x4b>;
 
                 pinctrl-names = "default";
@@ -479,6 +480,10 @@
 &mcpdm {
         pinctrl-names = "default";
         pinctrl-0 = <&mcpdm_pins>;
+
+        clocks = <&twl6040>;
+        clock-names = "pdmclk";
+
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index aae513265dc2..10d73a784050 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -160,7 +160,7 @@
                 enable-active-high;
         };
 
-        tpd12s015: encoder@0 {
+        tpd12s015: encoder {
                 compatible = "ti,tpd12s015";
 
                 gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>,   /* 60, CT CP HPD */
@@ -174,7 +174,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tpd12s015_in: endpoint@0 {
+                                tpd12s015_in: endpoint {
                                         remote-endpoint = <&hdmi_out>;
                                 };
                         };
@@ -182,14 +182,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tpd12s015_out: endpoint@0 {
+                                tpd12s015_out: endpoint {
                                         remote-endpoint = <&hdmi_connector_in>;
                                 };
                         };
                 };
         };
 
-        hdmi0: connector@0 {
+        hdmi0: connector {
                 compatible = "hdmi-connector";
                 label = "hdmi";
 
@@ -367,6 +367,7 @@
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
+                #clock-cells = <0>;
                 reg = <0x4b>;
 
                 pinctrl-names = "default";
@@ -620,6 +621,10 @@
 &mcpdm {
         pinctrl-names = "default";
         pinctrl-0 = <&mcpdm_pins>;
+
+        clocks = <&twl6040>;
+        clock-names = "pdmclk";
+
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
index 6e278d7716a5..74940b6d7719 100644
--- a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
+++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
@@ -45,7 +45,7 @@
                 };
         };
 
-        hdmi0: connector@0 {
+        hdmi0: connector {
                 compatible = "hdmi-connector";
                 pinctrl-names = "default";
                 pinctrl-0 = <&hdmi_hpd_pins>;
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
index a17997f4e9aa..873cfc87260c 100644
--- a/arch/arm/boot/dts/omap4-var-som-om44.dtsi
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -189,6 +189,7 @@
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
+                #clock-cells = <0>;
                 reg = <0x4b>;
 
                 pinctrl-names = "default";
@@ -252,6 +253,10 @@
 &mcpdm {
         pinctrl-names = "default";
         pinctrl-0 = <&mcpdm_pins>;
+
+        clocks = <&twl6040>;
+        clock-names = "pdmclk";
+
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/omap5-board-common.dtsi b/arch/arm/boot/dts/omap5-board-common.dtsi
index 5d5b620b7d9b..5196113202a2 100644
--- a/arch/arm/boot/dts/omap5-board-common.dtsi
+++ b/arch/arm/boot/dts/omap5-board-common.dtsi
@@ -87,7 +87,7 @@
                 };
         };
 
-        tpd12s015: encoder@0 {
+        tpd12s015: encoder {
                 compatible = "ti,tpd12s015";
 
                 pinctrl-names = "default";
@@ -102,7 +102,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tpd12s015_in: endpoint@0 {
+                                tpd12s015_in: endpoint {
                                         remote-endpoint = <&hdmi_out>;
                                 };
                         };
@@ -110,14 +110,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tpd12s015_out: endpoint@0 {
+                                tpd12s015_out: endpoint {
                                         remote-endpoint = <&hdmi_connector_in>;
                                 };
                         };
                 };
         };
 
-        hdmi0: connector@0 {
+        hdmi0: connector {
                 compatible = "hdmi-connector";
                 label = "hdmi";
 
@@ -637,6 +637,7 @@
 
         twl6040: twl@4b {
                 compatible = "ti,twl6040";
+                #clock-cells = <0>;
                 reg = <0x4b>;
 
                 pinctrl-names = "default";
@@ -658,6 +659,10 @@
 &mcpdm {
         pinctrl-names = "default";
         pinctrl-0 = <&mcpdm_pins>;
+
+        clocks = <&twl6040>;
+        clock-names = "pdmclk";
+
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
index 93fdfa96776e..a9765605d53b 100644
--- a/arch/arm/boot/dts/omap5-cm-t54.dts
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -112,7 +112,7 @@
                 };
         };
 
-        hdmi0: connector@0 {
+        hdmi0: connector0 {
                 compatible = "hdmi-connector";
                 label = "hdmi";
 
@@ -130,7 +130,7 @@
                 };
         };
 
-        tfp410: encoder@0 {
+        tfp410: encoder0 {
                 compatible = "ti,tfp410";
 
                 ports {
@@ -140,7 +140,7 @@
                         port@0 {
                                 reg = <0>;
 
-                                tfp410_in: endpoint@0 {
+                                tfp410_in: endpoint {
                                         remote-endpoint = <&dpi_dvi_out>;
                                 };
                         };
@@ -148,14 +148,14 @@
                         port@1 {
                                 reg = <1>;
 
-                                tfp410_out: endpoint@0 {
+                                tfp410_out: endpoint {
                                         remote-endpoint = <&dvi_connector_in>;
                                 };
                         };
                 };
         };
 
-        dvi0: connector@1 {
+        dvi0: connector1 {
                 compatible = "dvi-connector";
                 label = "dvi";
 
@@ -646,12 +646,17 @@
         pinctrl-0 = <&dss_dpi_pins>;
 
         port {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
                 dpi_dvi_out: endpoint@0 {
+                        reg = <0>;
                         remote-endpoint = <&tfp410_in>;
                         data-lines = <24>;
                 };
 
                 dpi_lcd_out: endpoint@1 {
+                        reg = <1>;
                         remote-endpoint = <&lcd_in>;
                         data-lines = <24>;
                 };
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 66afcff67fde..0abd7bf17568 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -21,15 +21,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                       clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/pxa27x.dtsi b/arch/arm/boot/dts/pxa27x.dtsi
index 210192c38df3..9e73dc6b3ed3 100644
--- a/arch/arm/boot/dts/pxa27x.dtsi
+++ b/arch/arm/boot/dts/pxa27x.dtsi
@@ -22,8 +22,15 @@
                         marvell,intc-nr-irqs = <34>;
                 };
 
+                pinctrl: pinctrl@40e00000 {
+                        reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
+                               0x40f00020 0x10>;
+                        compatible = "marvell,pxa27x-pinctrl";
+                };
+
                 gpio: gpio@40e00000 {
                         compatible = "intel,pxa27x-gpio";
+                        gpio-ranges = <&pinctrl 0 0 128>;
                         clocks = <&clks CLK_NONE>;
                 };
 
diff --git a/arch/arm/boot/dts/pxa2xx.dtsi b/arch/arm/boot/dts/pxa2xx.dtsi
index 5e5af078b9b5..3ff077ca4400 100644
--- a/arch/arm/boot/dts/pxa2xx.dtsi
+++ b/arch/arm/boot/dts/pxa2xx.dtsi
@@ -140,5 +140,13 @@
                         reg = <0x40900000 0x3c>;
                         interrupts = <30 31>;
                 };
+
+                lcd-controller@40500000 {
+                        compatible = "marvell,pxa2xx-lcdc";
+                        reg = <0x44000000 0x10000>;
+                        interrupts = <17>;
+                        clocks = <&clks CLK_LCD>;
+                        status = "disabled";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index fec47bcd8292..9d6f3aacedb7 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -1,6 +1,96 @@
 /* The pxa3xx skeleton simply augments the 2xx version */
 #include "pxa2xx.dtsi"
 
+#define MFP_PIN_PXA300(gpio)                            \
+        ((gpio <= 2) ? (0x00b4 + 4 * gpio) :            \
+         (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) :     \
+         (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) :    \
+         (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :   \
+         0)
+
+#define MFP_PIN_PXA310(gpio)                            \
+        ((gpio <= 2) ? (0x00b4 + 4 * gpio) :            \
+         (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) :     \
+         (gpio <= 29) ? (0x0400 + 4 * (gpio - 27)) :    \
+         (gpio <= 98) ? (0x0418 + 4 * (gpio - 30)) :    \
+         (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :   \
+         (gpio <= 262) ? 0 :                            \
+         (gpio <= 268) ? (0x052c + 4 * (gpio - 263)) :  \
+         0)
+
+#define MFP_PIN_PXA320(gpio)                            \
+        ((gpio <= 4) ? (0x0124 + 4 * gpio) :            \
+         (gpio <= 9) ? (0x028c + 4 * (gpio - 5)) :      \
+         (gpio <= 10) ? (0x0458 + 4 * (gpio - 10)) :    \
+         (gpio <= 26) ? (0x02a0 + 4 * (gpio - 11)) :    \
+         (gpio <= 48) ? (0x0400 + 4 * (gpio - 27)) :    \
+         (gpio <= 62) ? (0x045c + 4 * (gpio - 49)) :    \
+         (gpio <= 73) ? (0x04b4 + 4 * (gpio - 63)) :    \
+         (gpio <= 98) ? (0x04f0 + 4 * (gpio - 74)) :    \
+         (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) :   \
+         0)
+
+/*
+ * MFP Alternate functions for pins having a gpio.
+ * Example of use: pinctrl-single,pins = < MFP_PIN_PXA310(21) MFP_AF1 >
+ */
+#define MFP_AF0         (0 << 0)
+#define MFP_AF1         (1 << 0)
+#define MFP_AF2         (2 << 0)
+#define MFP_AF3         (3 << 0)
+#define MFP_AF4         (4 << 0)
+#define MFP_AF5         (5 << 0)
+#define MFP_AF6         (6 << 0)
+
+/*
+ * MFP drive strength functions for pins.
+ * Example of use: pinctrl-single,drive-strength = MFP_DS03X;
+ */
+#define MFP_DSMSK       (0x7 << 10)
+#define MFP_DS01X       < (0x0 << 10) MFP_DSMSK >
+#define MFP_DS02X       < (0x1 << 10) MFP_DSMSK >
+#define MFP_DS03X       < (0x2 << 10) MFP_DSMSK >
+#define MFP_DS04X       < (0x3 << 10) MFP_DSMSK >
+#define MFP_DS06X       < (0x4 << 10) MFP_DSMSK >
+#define MFP_DS08X       < (0x5 << 10) MFP_DSMSK >
+#define MFP_DS10X       < (0x6 << 10) MFP_DSMSK >
+#define MFP_DS13X       < (0x7 << 10) MFP_DSMSK >
+
+/*
+ * MFP low power mode for pins.
+ * Example of use:
+ *   pinctrl-single,low-power-mode = MFP_LPM(MFP_LPM_PULL_LOW|MFP_LPM_EDGE_FALL);
+ *
+ * Table that determines the low power modes outputs, with actual settings
+ * used in parentheses for don't-care values. Except for the float output,
+ * the configured driven and pulled levels match, so if there is a need for
+ * non-LPM pulled output, the same configuration could probably be used.
+ *
+ * Output value  sleep_oe_n  sleep_data  pullup_en  pulldown_en  pull_sel
+ *                 (bit 7)    (bit 8)    (bit 14)     (bit 13)   (bit 15)
+ *
+ * Input            0          X(0)        X(0)        X(0)       0
+ * Drive 0          0          0           0           X(1)       0
+ * Drive 1          0          1           X(1)        0          0
+ * Pull hi (1)      1          X(1)        1           0          0
+ * Pull lo (0)      1          X(0)        0           1          0
+ * Z (float)        1          X(0)        0           0          0
+ */
+#define MFP_LPM(x)              < (x) MFP_LPM_MSK >
+
+#define MFP_LPM_MSK             0xe1f0
+#define MFP_LPM_INPUT           0x0000
+#define MFP_LPM_DRIVE_LOW       0x2000
+#define MFP_LPM_DRIVE_HIGH      0x4100
+#define MFP_LPM_PULL_LOW        0x2080
+#define MFP_LPM_PULL_HIGH       0x4180
+#define MFP_LPM_FLOAT           0x0080
+
+#define MFP_LPM_EDGE_NONE       0x0000
+#define MFP_LPM_EDGE_RISE       0x0010
+#define MFP_LPM_EDGE_FALL       0x0020
+#define MFP_LPM_EDGE_BOTH       0x0030
+
 / {
         model = "Marvell PXA3xx familiy SoC";
         compatible = "marvell,pxa3xx";
@@ -43,6 +133,15 @@
                         marvell,intc-nr-irqs = <56>;
                 };
 
+                pinctrl: pinctrl@40e10000 {
+                        compatible = "pinconf-single";
+                        reg = <0x40e10000 0xffff>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        pinctrl-single,register-width = <32>;
+                        pinctrl-single,function-mask = <0x7>;
+                };
+
                 gpio: gpio@40e00000 {
                         compatible = "intel,pxa3xx-gpio";
                         reg = <0x40e00000 0x10000>;
@@ -92,7 +191,39 @@
                         compatible = "marvell,pxa-ohci";
                         reg = <0x4c000000 0x10000>;
                         interrupts = <3>;
-                        clocks = <&clks CLK_USBHOST>;
+                        clocks = <&clks CLK_USBH>;
+                        status = "disabled";
+                };
+
+                pwm0: pwm@40b00000 {
+                        compatible = "marvell,pxa270-pwm";
+                        reg = <0x40b00000 0x10>;
+                        #pwm-cells = <1>;
+                        clocks = <&clks CLK_PWM0>;
+                        status = "disabled";
+                };
+
+                pwm1: pwm@40b00010 {
+                        compatible = "marvell,pxa270-pwm";
+                        reg = <0x40b00010 0x10>;
+                        #pwm-cells = <1>;
+                        clocks = <&clks CLK_PWM1>;
+                        status = "disabled";
+                };
+
+                pwm2: pwm@40c00000 {
+                        compatible = "marvell,pxa270-pwm";
+                        reg = <0x40c00000 0x10>;
+                        #pwm-cells = <1>;
+                        clocks = <&clks CLK_PWM0>;
+                        status = "disabled";
+                };
+
+                pwm3: pwm@40c00010 {
+                        compatible = "marvell,pxa270-pwm";
+                        reg = <0x40c00010 0x10>;
+                        #pwm-cells = <1>;
+                        clocks = <&clks CLK_PWM1>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
new file mode 100644
index 000000000000..0abc93e5bb00
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts
@@ -0,0 +1,626 @@
+/*
+ * Copyright 2016 Linaro Ltd
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
+#include "qcom-msm8660.dtsi"
+
+/ {
+        model = "Qualcomm APQ8060 Dragonboard";
+        compatible = "qcom,apq8060-dragonboard", "qcom,msm8660";
+
+        aliases {
+                serial0 = &gsbi12_serial;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                /* Main power of the board: 3.7V */
+                vph: regulator-fixed {
+                        compatible = "regulator-fixed";
+                        regulator-min-microvolt = <3700000>;
+                        regulator-max-microvolt = <3700000>;
+                        regulator-name = "VPH";
+                        regulator-type = "voltage";
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+
+                /* This is a levelshifter for SDCC5 */
+                dragon_vio_txb: txb0104rgyr {
+                        compatible = "regulator-fixed";
+                        regulator-name = "Dragon SDCC levelshifter";
+                        vin-supply = <&pm8058_l14>;
+                        regulator-always-on;
+                };
+        };
+
+        soc {
+                pinctrl@800000 {
+                        /* eMMMC pins, all 8 data lines connected */
+                        dragon_sdcc1_pins: sdcc1 {
+                                mux {
+                                        pins = "gpio159", "gpio160", "gpio161",
+                                             "gpio162", "gpio163", "gpio164",
+                                             "gpio165", "gpio166", "gpio167",
+                                             "gpio168";
+                                             function = "sdc1";
+                                };
+                                clk {
+                                        pins = "gpio167"; /* SDC5 CLK */
+                                        drive-strength = <16>;
+                                        bias-disable;
+                                };
+                                cmd {
+                                        pins = "gpio168"; /* SDC5 CMD */
+                                        drive-strength = <10>;
+                                        bias-pull-up;
+                                };
+                                data {
+                                        /* SDC5 D0 to D7 */
+                                        pins = "gpio159", "gpio160", "gpio161", "gpio162",
+                                             "gpio163", "gpio164", "gpio165", "gpio166";
+                                        drive-strength = <10>;
+                                        bias-pull-up;
+                                };
+                        };
+
+                        /*
+                         * The SDCC3 pins are hardcoded (non-muxable) but need some pin
+                         * configuration.
+                         */
+                        dragon_sdcc3_pins: sdcc3 {
+                                clk {
+                                        pins = "sdc3_clk";
+                                        drive-strength = <8>;
+                                        bias-disable;
+                                };
+                                cmd {
+                                        pins = "sdc3_cmd";
+                                        drive-strength = <8>;
+                                        bias-pull-up;
+                                };
+                                data {
+                                        pins = "sdc3_data";
+                                        drive-strength = <8>;
+                                        bias-pull-up;
+                                };
+                        };
+
+                        /* Second SD card slot pins */
+                        dragon_sdcc5_pins: sdcc5 {
+                                mux {
+                                        pins = "gpio95", "gpio96", "gpio97",
+                                            "gpio98", "gpio99", "gpio100";
+                                        function = "sdc5";
+                                };
+                                clk {
+                                        pins = "gpio97"; /* SDC5 CLK */
+                                        drive-strength = <16>;
+                                        bias-disable;
+                                };
+                                cmd {
+                                        pins = "gpio95"; /* SDC5 CMD */
+                                        drive-strength = <10>;
+                                        bias-pull-up;
+                                };
+                                data {
+                                        /* SDC5 D0 to D3 */
+                                        pins = "gpio96", "gpio98", "gpio99", "gpio100";
+                                        drive-strength = <10>;
+                                        bias-pull-up;
+                                };
+                        };
+
+                        dragon_gsbi12_i2c_pins: gsbi12_i2c {
+                                mux {
+                                        pins = "gpio115", "gpio116";
+                                        function = "gsbi12";
+                                };
+                                pinconf {
+                                        pins = "gpio115", "gpio116";
+                                        drive-strength = <16>;
+                                        /* These have external pull-up 4.7kOhm to 1.8V */
+                                        bias-disable;
+                                };
+                        };
+
+                        /* Primary serial port uart 0 pins */
+                        dragon_gsbi12_serial_pins: gsbi12_serial {
+                                mux {
+                                        pins = "gpio117", "gpio118";
+                                        function = "gsbi12";
+                                };
+                                tx {
+                                        pins = "gpio117";
+                                        drive-strength = <8>;
+                                        bias-disable;
+                                };
+                                rx {
+                                        pins = "gpio118";
+                                        drive-strength = <2>;
+                                        bias-pull-up;
+                                };
+                        };
+                };
+
+                qcom,ssbi@500000 {
+                        pmic@0 {
+                                keypad@148 {
+                                        linux,keymap = <
+                                        MATRIX_KEY(0, 0, KEY_MENU)
+                                        MATRIX_KEY(0, 2, KEY_1)
+                                        MATRIX_KEY(0, 3, KEY_4)
+                                        MATRIX_KEY(0, 4, KEY_7)
+                                        MATRIX_KEY(1, 0, KEY_UP)
+                                        MATRIX_KEY(1, 1, KEY_LEFT)
+                                        MATRIX_KEY(1, 2, KEY_DOWN)
+                                        MATRIX_KEY(1, 3, KEY_5)
+                                        MATRIX_KEY(1, 3, KEY_8)
+                                        MATRIX_KEY(2, 0, KEY_HOME)
+                                        MATRIX_KEY(2, 1, KEY_REPLY)
+                                        MATRIX_KEY(2, 2, KEY_2)
+                                        MATRIX_KEY(2, 3, KEY_6)
+                                        MATRIX_KEY(3, 0, KEY_VOLUMEUP)
+                                        MATRIX_KEY(3, 1, KEY_RIGHT)
+                                        MATRIX_KEY(3, 2, KEY_3)
+                                        MATRIX_KEY(3, 3, KEY_9)
+                                        MATRIX_KEY(3, 4, KEY_SWITCHVIDEOMODE)
+                                        MATRIX_KEY(4, 0, KEY_VOLUMEDOWN)
+                                        MATRIX_KEY(4, 1, KEY_BACK)
+                                        MATRIX_KEY(4, 2, KEY_CAMERA)
+                                        MATRIX_KEY(4, 3, KEY_KBDILLUMTOGGLE)
+                                        >;
+                                        keypad,num-rows = <6>;
+                                        keypad,num-columns = <5>;
+                                };
+
+                                gpio@150 {
+                                        dragon_bmp085_gpios: bmp085-gpios {
+                                                pinconf {
+                                                        pins = "gpio16";
+                                                        function = "normal";
+                                                        input-enable;
+                                                        bias-disable;
+                                                        power-source = <PM8058_GPIO_S3>;
+                                                };
+                                        };
+                                        dragon_sdcc3_gpios: sdcc3-gpios {
+                                                pinconf {
+                                                        pins = "gpio22";
+                                                        function = "normal";
+                                                        input-enable;
+                                                        bias-disable;
+                                                        power-source = <PM8058_GPIO_S3>;
+                                                };
+                                        };
+                                        dragon_sdcc5_gpios: sdcc5-gpios {
+                                                pinconf {
+                                                        pins = "gpio26";
+                                                        function = "normal";
+                                                        input-enable;
+                                                        bias-pull-up;
+                                                        qcom,pull-up-strength = <PMIC_GPIO_PULL_UP_30>;
+                                                        power-source = <PM8058_GPIO_S3>;
+                                                };
+                                        };
+                                        dragon_ak8975_gpios: ak8975-gpios {
+                                                pinconf {
+                                                        pins = "gpio33";
+                                                        function = "normal";
+                                                        input-enable;
+                                                        bias-disable;
+                                                        power-source = <PM8058_GPIO_S3>;
+                                                };
+                                        };
+                                };
+                        };
+                };
+
+                gsbi@19c00000 {
+                        status = "ok";
+                        qcom,mode = <GSBI_PROT_I2C_UART>;
+
+                        serial@19c40000 {
+                                status = "ok";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&dragon_gsbi12_serial_pins>;
+                        };
+
+                        i2c@19c80000 {
+                                status = "ok";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&dragon_gsbi12_i2c_pins>;
+
+                                ak8975@0c {
+                                        compatible = "asahi-kasei,ak8975";
+                                        reg = <0x0c>;
+                                        /* GPIO33 has interrupt 224 on the PM8058 */
+                                        interrupt-parent = <&pm8058_gpio>;
+                                        interrupts = <224 IRQ_TYPE_EDGE_RISING>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&dragon_ak8975_gpios>;
+                                        vid-supply = <&pm8058_lvs0>; // 1.8V
+                                        vdd-supply = <&pm8058_l14>; // 2.85V
+                                };
+                                bmp085@77 {
+                                        compatible = "bosch,bmp085";
+                                        reg = <0x77>;
+                                        /* GPIO16 has interrupt 207 on the PM8058 */
+                                        interrupt-parent = <&pm8058_gpio>;
+                                        interrupts = <207 IRQ_TYPE_EDGE_RISING>;
+                                        reset-gpios = <&tlmm 86 GPIO_ACTIVE_LOW>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&dragon_bmp085_gpios>;
+                                        vddd-supply = <&pm8058_lvs0>; // 1.8V
+                                        vdda-supply = <&pm8058_l14>; // 2.85V
+                                };
+                        };
+                };
+
+                rpm@104000 {
+                        /*
+                         * Set up of the PMIC RPM regulators for this board
+                         * PM8901 supplies "preliminary regulators" whatever
+                         * that means
+                         */
+                        pm8901-regulators {
+                                vdd_l0-supply = <&pm8901_s4>;
+                                vdd_l1-supply = <&vph>;
+                                vdd_l2-supply = <&vph>;
+                                vdd_l3-supply = <&vph>;
+                                vdd_l4-supply = <&vph>;
+                                vdd_l5-supply = <&vph>;
+                                vdd_l6-supply = <&vph>;
+                                /* vdd_s0-supply, vdd_s1-supply: SAW regulators */
+                                vdd_s2-supply = <&vph>;
+                                vdd_s3-supply = <&vph>;
+                                vdd_s4-supply = <&vph>;
+                                lvs0_in-supply = <&pm8058_s3>;
+                                lvs1_in-supply = <&pm8901_s4>;
+                                lvs2_in-supply = <&pm8058_l0>;
+                                lvs3_in-supply = <&pm8058_s2>;
+                                mvs_in-supply = <&pm8058_s3>;
+
+                                l0 {
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                };
+                                l1 {
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        bias-pull-down;
+                                };
+                                l2 {
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        bias-pull-down;
+                                };
+                                l3 {
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        bias-pull-down;
+                                };
+                                l4 {
+                                        regulator-min-microvolt = <2600000>;
+                                        regulator-max-microvolt = <2600000>;
+                                        bias-pull-down;
+                                };
+                                l5 {
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        bias-pull-down;
+                                };
+                                l6 {
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                        bias-pull-down;
+                                };
+
+                                /* s0 and s1 are SAW regulators controlled over SPM */
+                                s2 {
+                                        regulator-min-microvolt = <1300000>;
+                                        regulator-max-microvolt = <1300000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        bias-pull-down;
+                                };
+                                s3 {
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        bias-pull-down;
+                                };
+                                s4 {
+                                        regulator-min-microvolt = <1225000>;
+                                        regulator-max-microvolt = <1225000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        bias-pull-down;
+                                };
+
+                                /* LVS0 thru 3 and mvs0 are just switches */
+                                lvs0 {
+                                        regulator-always-on;
+                                };
+                                lvs1 { };
+                                lvs2 { };
+                                lvs3 { };
+                                mvs0 {};
+
+                        };
+
+                        pm8058-regulators {
+                                vdd_l0_l1_lvs-supply = <&pm8058_s3>;
+                                vdd_l2_l11_l12-supply = <&vph>;
+                                vdd_l3_l4_l5-supply = <&vph>;
+                                vdd_l6_l7-supply = <&vph>;
+                                vdd_l8-supply = <&vph>;
+                                vdd_l9-supply = <&vph>;
+                                vdd_l10-supply = <&vph>;
+                                vdd_l13_l16-supply = <&pm8058_s4>;
+                                vdd_l14_l15-supply = <&vph>;
+                                vdd_l17_l18-supply = <&vph>;
+                                vdd_l19_l20-supply = <&vph>;
+                                vdd_l21-supply = <&pm8058_s3>;
+                                vdd_l22-supply = <&pm8058_s3>;
+                                vdd_l23_l24_l25-supply = <&pm8058_s3>;
+                                vdd_s0-supply = <&vph>;
+                                vdd_s1-supply = <&vph>;
+                                vdd_s2-supply = <&vph>;
+                                vdd_s3-supply = <&vph>;
+                                vdd_s4-supply = <&vph>;
+                                vdd_ncp-supply = <&vph>;
+
+                                l0 {
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                };
+                                l1 {
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                };
+                                l2 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <2600000>;
+                                        bias-pull-down;
+                                };
+                                l3 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        bias-pull-down;
+                                };
+                                l4 {
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        bias-pull-down;
+                                };
+                                l5 {
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        bias-pull-down;
+                                };
+                                l6 {
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3600000>;
+                                        bias-pull-down;
+                                };
+                                l7 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        bias-pull-down;
+                                };
+                                l8 {
+                                        regulator-min-microvolt = <2900000>;
+                                        regulator-max-microvolt = <3050000>;
+                                        bias-pull-down;
+                                };
+                                l9 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        bias-pull-down;
+                                };
+                                l10 {
+                                        regulator-min-microvolt = <2600000>;
+                                        regulator-max-microvolt = <2600000>;
+                                        bias-pull-down;
+                                };
+                                l11 {
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        bias-pull-down;
+                                };
+                                l12 {
+                                        regulator-min-microvolt = <2900000>;
+                                        regulator-max-microvolt = <2900000>;
+                                        bias-pull-down;
+                                };
+                                l13 {
+                                        regulator-min-microvolt = <2050000>;
+                                        regulator-max-microvolt = <2050000>;
+                                        bias-pull-down;
+                                };
+                                l14 {
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                };
+                                l15 {
+                                        regulator-min-microvolt = <2850000>;
+                                        regulator-max-microvolt = <2850000>;
+                                        bias-pull-down;
+                                };
+                                l16 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        bias-pull-down;
+                                        regulator-always-on;
+                                };
+                                l17 {
+                                        // 1.5V according to schematic
+                                        regulator-min-microvolt = <2600000>;
+                                        regulator-max-microvolt = <2600000>;
+                                        bias-pull-down;
+                                };
+                                l18 {
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                        bias-pull-down;
+                                };
+                                l19 {
+                                        regulator-min-microvolt = <2500000>;
+                                        regulator-max-microvolt = <2500000>;
+                                        bias-pull-down;
+                                };
+                                l20 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        bias-pull-down;
+                                };
+                                l21 {
+                                        // 1.1 V according to schematic
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                        regulator-always-on;
+                                };
+                                l22 {
+                                        // 1.2 V according to schematic
+                                        regulator-min-microvolt = <1150000>;
+                                        regulator-max-microvolt = <1150000>;
+                                        bias-pull-down;
+                                };
+                                l23 {
+                                        // Unused
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                };
+                                l24 {
+                                        // Unused
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                };
+                                l25 {
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        bias-pull-down;
+                                };
+
+                                s0 {
+                                        // regulator-min-microvolt = <500000>;
+                                        // regulator-max-microvolt = <1325000>;
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        bias-pull-down;
+                                };
+                                s1 {
+                                        // regulator-min-microvolt = <500000>;
+                                        // regulator-max-microvolt = <1250000>;
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        bias-pull-down;
+                                };
+                                s2 {
+                                        // 1.3 V according to schematic
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        bias-pull-down;
+                                };
+                                s3 {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        regulator-always-on;
+                                        bias-pull-down;
+                                };
+                                s4 {
+                                        regulator-min-microvolt = <2200000>;
+                                        regulator-max-microvolt = <2200000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        regulator-always-on;
+                                        bias-pull-down;
+                                };
+
+                                /* LVS0 and LVS1 are just switches */
+                                lvs0 {
+                                        bias-pull-down;
+                                };
+                                lvs1 {
+                                        bias-pull-down;
+                                };
+
+                                ncp {
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                };
+                        };
+                };
+                amba {
+                        /* Internal 3.69 GiB eMMC */
+                        sdcc@12400000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&dragon_sdcc1_pins>;
+                                vmmc-supply = <&pm8901_l5>;
+                                vqmmc-supply = <&pm8901_lvs0>;
+                        };
+
+                        /* External micro SD card, directly connected, pulled up to 2.85 V */
+                        sdcc@12180000 {
+                                status = "okay";
+                                /* Enable SSBI GPIO 22 as input, use for card detect */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&dragon_sdcc3_pins>, <&dragon_sdcc3_gpios>;
+                                cd-gpios = <&pm8058_gpio 22 GPIO_ACTIVE_LOW>;
+                                wp-gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>;
+                                vmmc-supply = <&pm8058_l14>;
+                        };
+
+                        /*
+                         * Second external micro SD card, using two TXB104RGYR levelshifters
+                         * to lift from 1.8 V to 2.85 V
+                         */
+                        sdcc@12200000 {
+                                status = "okay";
+                                /* Enable SSBI GPIO 26 as input, use for card detect */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&dragon_sdcc5_pins>, <&dragon_sdcc5_gpios>;
+                                cd-gpios = <&pm8058_gpio 26 GPIO_ACTIVE_LOW>;
+                                wp-gpios = <&tlmm 106 GPIO_ACTIVE_HIGH>;
+                                vmmc-supply = <&pm8058_l14>;
+                                vqmmc-supply = <&dragon_vio_txb>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi
index a3efb9704fcd..a3efb9704fcd 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval-pins.dtsi
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index e01b27ea7fba..39ae2bc8cb08 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-db600c.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -1,10 +1,11 @@
 #include "qcom-apq8064-v2.0.dtsi"
-#include "qcom-apq8064-arrow-db600c-pins.dtsi"
+#include "qcom-apq8064-arrow-sd-600eval-pins.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
 
 / {
-        model = "Arrow Electronics, APQ8064 DB600c";
-        compatible = "arrow,db600c", "qcom,apq8064";
+        model = "Arrow Electronics, APQ8064 SD_600eval";
+        compatible = "arrow,sd_600eval", "qcom,apq8064";
 
         aliases {
                 serial0 = &gsbi7_serial;
@@ -82,7 +83,8 @@
                                 s4 {
                                         regulator-min-microvolt = <1800000>;
                                         regulator-max-microvolt = <1800000>;
-                                        qcom,switch-mode-frequency = <3200000>;
+                                        qcom,switch-mode-frequency = <1600000>;
+                                        qcom,force-mode = <QCOM_RPM_FORCE_MODE_AUTO>;
                                         bias-pull-down;
                                         regulator-always-on;
                                 };
diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
index 32fedfa149d0..7b05f072bfc2 100644
--- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts
@@ -29,12 +29,6 @@
 
         gpio-keys {
                 compatible = "gpio-keys";
-                power {
-                        label = "Power";
-                        gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
-                        linux,code = <KEY_POWER>;
-                        gpio-key,wakeup;
-                };
                 volume_up {
                         label = "Volume Up";
                         gpios = <&pm8921_gpio 4 GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 4102a98f475b..6b801e7e57a2 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -7,6 +7,46 @@
                 };
         };
 
+        sdcc1_pins: sdcc1-pin-active {
+                clk {
+                        pins = "sdc1_clk";
+                        drive-strengh = <16>;
+                        bias-disable;
+                };
+
+                cmd {
+                        pins = "sdc1_cmd";
+                        drive-strengh = <10>;
+                        bias-pull-up;
+                };
+
+                data {
+                        pins = "sdc1_data";
+                        drive-strengh = <10>;
+                        bias-pull-up;
+                };
+        };
+
+        sdcc3_pins: sdcc3-pin-active {
+                clk {
+                        pins = "sdc3_clk";
+                        drive-strengh = <8>;
+                        bias-disable;
+                };
+
+                cmd {
+                        pins = "sdc3_cmd";
+                        drive-strengh = <8>;
+                        bias-pull-up;
+                };
+
+                data {
+                        pins = "sdc3_data";
+                        drive-strengh = <8>;
+                        bias-pull-up;
+                };
+        };
+
         ps_hold: ps_hold {
                 mux {
                         pins = "gpio78";
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
index 06b3c76c3e41..ebd675ca94b4 100644
--- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
@@ -70,45 +70,6 @@
                                 };
                         };
 
-                        sdcc1_pin_a: sdcc1-pin-active {
-                                clk {
-                                        pins = "sdc1_clk";
-                                        drive-strengh = <16>;
-                                        bias-disable;
-                                };
-
-                                cmd {
-                                        pins = "sdc1_cmd";
-                                        drive-strengh = <10>;
-                                        bias-pull-up;
-                                };
-
-                                data {
-                                        pins = "sdc1_data";
-                                        drive-strengh = <10>;
-                                        bias-pull-up;
-                                };
-                        };
-
-                        sdcc3_pin_a: sdcc3-pin-active {
-                                clk {
-                                        pins = "sdc3_clk";
-                                        drive-strengh = <8>;
-                                        bias-disable;
-                                };
-
-                                cmd {
-                                        pins = "sdc3_cmd";
-                                        drive-strengh = <8>;
-                                        bias-pull-up;
-                                };
-
-                                data {
-                                        pins = "sdc3_data";
-                                        drive-strengh = <8>;
-                                        bias-pull-up;
-                                };
-                        };
 
                         sdcc3_cd_pin_a: sdcc3-cd-pin-active {
                                 pins = "gpio26";
@@ -417,9 +378,6 @@
 
                                 vmmc-supply = <&pm8921_l5>;
                                 vqmmc-supply = <&pm8921_s4>;
-
-                                pinctrl-names = "default";
-                                pinctrl-0 = <&sdcc1_pin_a>;
                         };
 
                         sdcc3: sdcc@12180000 {
@@ -429,7 +387,7 @@
                                 cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_LOW>;
 
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&sdcc3_pin_a>, <&sdcc3_cd_pin_a>;
+                                pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index e318d04319a0..74a9b6c394f5 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -177,7 +177,7 @@
 
                 apps_smsm: apps@0 {
                         reg = <0>;
-                        #qcom,state-cells = <1>;
+                        #qcom,smem-state-cells = <1>;
                 };
 
                 modem_smsm: modem@1 {
@@ -213,6 +213,12 @@
                 };
         };
 
+        firmware {
+                scm {
+                        compatible = "qcom,scm-apq8064";
+                };
+        };
+
         soc: soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -854,6 +860,8 @@
                         sdcc1: sdcc@12400000 {
                                 status          = "disabled";
                                 compatible      = "arm,pl18x", "arm,primecell";
+                                pinctrl-names   = "default";
+                                pinctrl-0       = <&sdcc1_pins>;
                                 arm,primecell-periphid = <0x00051180>;
                                 reg             = <0x12400000 0x2000>;
                                 interrupts      = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index c0e205315042..ad51df27dfb7 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -25,11 +25,23 @@
                         bus-width = <8>;
                         non-removable;
                         status = "ok";
+
+                        vmmc-supply = <&pm8941_l20>;
+                        vqmmc-supply = <&pm8941_s3>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&sdhc1_pin_a>;
                 };
 
                 sdhci@f98a4900 {
                         cd-gpios = <&msmgpio 62 0x1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&sdhc2_pin_a>, <&sdhc2_cd_pin_a>;
                         bus-width = <4>;
+                        status = "ok";
+
+                        vmmc-supply = <&pm8941_l21>;
+                        vqmmc-supply = <&pm8941_l13>;
                 };
 
 
@@ -59,6 +71,42 @@
                                         function = "blsp_spi8";
                                 };
                         };
+
+                        sdhc1_pin_a: sdhc1-pin-active {
+                                clk {
+                                        pins = "sdc1_clk";
+                                        drive-strength = <16>;
+                                        bias-disable;
+                                };
+
+                                cmd-data {
+                                        pins = "sdc1_cmd", "sdc1_data";
+                                        drive-strength = <10>;
+                                        bias-pull-up;
+                                };
+                        };
+
+                        sdhc2_cd_pin_a: sdhc2-cd-pin-active {
+                                pins = "gpio62";
+                                function = "gpio";
+
+                                drive-strength = <2>;
+                                bias-disable;
+                        };
+
+                        sdhc2_pin_a: sdhc2-pin-active {
+                                clk {
+                                        pins = "sdc2_clk";
+                                        drive-strength = <10>;
+                                        bias-disable;
+                                };
+
+                                cmd-data {
+                                        pins = "sdc2_cmd", "sdc2_data";
+                                        drive-strength = <6>;
+                                        bias-pull-up;
+                                };
+                        };
                 };
 
                 i2c@f9967000 {
@@ -75,4 +123,203 @@
                         };
                 };
         };
+
+        smd {
+                rpm {
+                        rpm_requests {
+                                pm8841-regulators {
+                                        s1 {
+                                                regulator-min-microvolt = <675000>;
+                                                regulator-max-microvolt = <1050000>;
+                                        };
+
+                                        s2 {
+                                                regulator-min-microvolt = <500000>;
+                                                regulator-max-microvolt = <1050000>;
+                                        };
+
+                                        s3 {
+                                                regulator-min-microvolt = <500000>;
+                                                regulator-max-microvolt = <1050000>;
+                                        };
+
+                                        s4 {
+                                                regulator-min-microvolt = <500000>;
+                                                regulator-max-microvolt = <1050000>;
+                                        };
+                                };
+
+                                pm8941-regulators {
+                                        vdd_l1_l3-supply = <&pm8941_s1>;
+                                        vdd_l2_lvs1_2_3-supply = <&pm8941_s3>;
+                                        vdd_l4_l11-supply = <&pm8941_s1>;
+                                        vdd_l5_l7-supply = <&pm8941_s2>;
+                                        vdd_l6_l12_l14_l15-supply = <&pm8941_s2>;
+                                        vin_5vs-supply = <&pm8941_5v>;
+
+                                        s1 {
+                                                regulator-min-microvolt = <1300000>;
+                                                regulator-max-microvolt = <1300000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        s2 {
+                                                regulator-min-microvolt = <2150000>;
+                                                regulator-max-microvolt = <2150000>;
+                                                regulator-boot-on;
+                                        };
+
+                                        s3 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        l1 {
+                                                regulator-min-microvolt = <1225000>;
+                                                regulator-max-microvolt = <1225000>;
+
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        l2 {
+                                                regulator-min-microvolt = <1200000>;
+                                                regulator-max-microvolt = <1200000>;
+                                        };
+
+                                        l3 {
+                                                regulator-min-microvolt = <1225000>;
+                                                regulator-max-microvolt = <1225000>;
+                                        };
+
+                                        l4 {
+                                                regulator-min-microvolt = <1225000>;
+                                                regulator-max-microvolt = <1225000>;
+                                        };
+
+                                        l5 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                        };
+
+                                        l6 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+
+                                                regulator-boot-on;
+                                        };
+
+                                        l7 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+
+                                                regulator-boot-on;
+                                        };
+
+                                        l8 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                        };
+
+                                        l9 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <2950000>;
+                                        };
+
+                                        l10 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                        };
+
+                                        l11 {
+                                                regulator-min-microvolt = <1300000>;
+                                                regulator-max-microvolt = <1300000>;
+                                        };
+
+                                        l12 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+
+                                        l13 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <2950000>;
+
+                                                regulator-boot-on;
+                                        };
+
+                                        l14 {
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                        };
+
+                                        l15 {
+                                                regulator-min-microvolt = <2050000>;
+                                                regulator-max-microvolt = <2050000>;
+                                        };
+
+                                        l16 {
+                                                regulator-min-microvolt = <2700000>;
+                                                regulator-max-microvolt = <2700000>;
+                                        };
+
+                                        l17 {
+                                                regulator-min-microvolt = <2700000>;
+                                                regulator-max-microvolt = <2700000>;
+                                        };
+
+                                        l18 {
+                                                regulator-min-microvolt = <2850000>;
+                                                regulator-max-microvolt = <2850000>;
+                                        };
+
+                                        l19 {
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                        };
+
+                                        l20 {
+                                                regulator-min-microvolt = <2950000>;
+                                                regulator-max-microvolt = <2950000>;
+
+                                                regulator-allow-set-load;
+                                                regulator-boot-on;
+                                                regulator-system-load = <200000>;
+                                        };
+
+                                        l21 {
+                                                regulator-min-microvolt = <2950000>;
+                                                regulator-max-microvolt = <2950000>;
+
+                                                regulator-boot-on;
+                                        };
+
+                                        l22 {
+                                                regulator-min-microvolt = <3000000>;
+                                                regulator-max-microvolt = <3000000>;
+                                        };
+
+                                        l23 {
+                                                regulator-min-microvolt = <3000000>;
+                                                regulator-max-microvolt = <3000000>;
+                                        };
+
+                                        l24 {
+                                                regulator-min-microvolt = <3075000>;
+                                                regulator-max-microvolt = <3075000>;
+
+                                                regulator-boot-on;
+                                        };
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
index a33a09f6821e..7c2df062a025 100644
--- a/arch/arm/boot/dts/qcom-apq8084.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -86,6 +86,14 @@
                 };
         };
 
+        firmware {
+                scm {
+                        compatible = "qcom,scm";
+                        clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
+                        clock-names = "core", "bus", "iface";
+                };
+        };
+
         cpu-pmu {
                 compatible = "qcom,krait-pmu";
                 interrupts = <1 7 0xf04>;
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index e625656a608a..b7a24af8f47b 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -84,6 +84,12 @@
                 };
         };
 
+        pmu {
+                compatible = "arm,cortex-a7-pmu";
+                interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
+                                         IRQ_TYPE_LEVEL_HIGH)>;
+        };
+
         clocks {
                 sleep_clk: sleep_clk {
                         compatible = "fixed-clock";
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index b17f379e8c2a..23de764558ab 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -23,15 +23,26 @@
                         };
                 };
 
+                /* Temporary fixed regulator */
+                vsdcc_fixed: vsdcc-regulator {
+                        compatible = "regulator-fixed";
+                        regulator-name = "SDCC Power";
+                        regulator-min-microvolt = <2700000>;
+                        regulator-max-microvolt = <2700000>;
+                        regulator-always-on;
+                };
+
                 amba {
                         /* eMMC */
                         sdcc1: sdcc@12400000 {
                                 status = "okay";
+                                vmmc-supply = <&vsdcc_fixed>;
                         };
 
                         /* External micro SD card */
                         sdcc3: sdcc@12180000 {
                                 status = "okay";
+                                vmmc-supply = <&vsdcc_fixed>;
                         };
                 };
         };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index cd214030b84a..acbe71febe13 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -122,11 +122,22 @@
                                 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                 reg = <0x19c40000 0x1000>,
                                       <0x19c00000 0x1000>;
-                                interrupts = <0 195 0x0>;
+                                interrupts = <0 195 IRQ_TYPE_NONE>;
                                 clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
                                 clock-names = "core", "iface";
                                 status = "disabled";
                         };
+
+                        gsbi12_i2c: i2c@19c80000 {
+                                compatible = "qcom,i2c-qup-v1.1.1";
+                                reg = <0x19c80000 0x1000>;
+                                interrupts = <0 196 IRQ_TYPE_NONE>;
+                                clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
+                                clock-names = "core", "iface";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                status = "disabled";
+                        };
                 };
 
                 qcom,ssbi@500000 {
@@ -143,6 +154,44 @@
                                 #address-cells = <1>;
                                 #size-cells = <0>;
 
+                                pm8058_gpio: gpio@150 {
+                                        compatible = "qcom,pm8058-gpio",
+                                                     "qcom,ssbi-gpio";
+                                        reg = <0x150>;
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts = <192 1>, <193 1>, <194 1>,
+                                                     <195 1>, <196 1>, <197 1>,
+                                                     <198 1>, <199 1>, <200 1>,
+                                                     <201 1>, <202 1>, <203 1>,
+                                                     <204 1>, <205 1>, <206 1>,
+                                                     <207 1>, <208 1>, <209 1>,
+                                                     <210 1>, <211 1>, <212 1>,
+                                                     <213 1>, <214 1>, <215 1>,
+                                                     <216 1>, <217 1>, <218 1>,
+                                                     <219 1>, <220 1>, <221 1>,
+                                                     <222 1>, <223 1>, <224 1>,
+                                                     <225 1>, <226 1>, <227 1>,
+                                                     <228 1>, <229 1>, <230 1>,
+                                                     <231 1>, <232 1>, <233 1>,
+                                                     <234 1>, <235 1>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+
+                                };
+
+                                pm8058_mpps: mpps@50 {
+                                        compatible = "qcom,pm8058-mpp",
+                                                     "qcom,ssbi-mpp";
+                                        reg = <0x50>;
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        interrupt-parent = <&pmicintc>;
+                                        interrupts =
+                                        <128 1>, <129 1>, <130 1>, <131 1>,
+                                        <132 1>, <133 1>, <134 1>, <135 1>,
+                                        <136 1>, <137 1>, <138 1>, <139 1>;
+                                };
+
                                 pwrkey@1c {
                                         compatible = "qcom,pm8058-pwrkey";
                                         reg = <0x1c>;
@@ -162,11 +211,11 @@
                                         row-hold = <91500>;
                                 };
 
-                                rtc@11d {
+                                rtc@1e8 {
                                         compatible = "qcom,pm8058-rtc";
+                                        reg = <0x1e8>;
                                         interrupt-parent = <&pmicintc>;
                                         interrupts = <39 1>;
-                                        reg = <0x11d>;
                                         allow-set-time;
                                 };
 
@@ -177,13 +226,93 @@
                         };
                 };
 
-                /* Temporary fixed regulator */
-                vsdcc_fixed: vsdcc-regulator {
-                        compatible = "regulator-fixed";
-                        regulator-name = "SDCC Power";
-                        regulator-min-microvolt = <2700000>;
-                        regulator-max-microvolt = <2700000>;
-                        regulator-always-on;
+                l2cc: clock-controller@2082000 {
+                        compatible      = "syscon";
+                        reg             = <0x02082000 0x1000>;
+                };
+
+                rpm: rpm@104000 {
+                        compatible      = "qcom,rpm-msm8660";
+                        reg             = <0x00104000 0x1000>;
+                        qcom,ipc        = <&l2cc 0x8 2>;
+
+                        interrupts      = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
+                                          <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
+                                          <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+                        interrupt-names = "ack", "err", "wakeup";
+                        clocks = <&gcc RPM_MSG_RAM_H_CLK>;
+                        clock-names = "ram";
+
+                        rpmcc: clock-controller {
+                                compatible      = "qcom,rpmcc-apq8660", "qcom,rpmcc";
+                                #clock-cells = <1>;
+                        };
+
+                        pm8901-regulators {
+                                compatible = "qcom,rpm-pm8901-regulators";
+
+                                pm8901_l0: l0 {};
+                                pm8901_l1: l1 {};
+                                pm8901_l2: l2 {};
+                                pm8901_l3: l3 {};
+                                pm8901_l4: l4 {};
+                                pm8901_l5: l5 {};
+                                pm8901_l6: l6 {};
+
+                                /* S0 and S1 Handled as SAW regulators by SPM */
+                                pm8901_s2: s2 {};
+                                pm8901_s3: s3 {};
+                                pm8901_s4: s4 {};
+
+                                pm8901_lvs0: lvs0 {};
+                                pm8901_lvs1: lvs1 {};
+                                pm8901_lvs2: lvs2 {};
+                                pm8901_lvs3: lvs3 {};
+
+                                pm8901_mvs: mvs {};
+                        };
+
+                        pm8058-regulators {
+                                compatible = "qcom,rpm-pm8058-regulators";
+
+                                pm8058_l0: l0 {};
+                                pm8058_l1: l1 {};
+                                pm8058_l2: l2 {};
+                                pm8058_l3: l3 {};
+                                pm8058_l4: l4 {};
+                                pm8058_l5: l5 {};
+                                pm8058_l6: l6 {};
+                                pm8058_l7: l7 {};
+                                pm8058_l8: l8 {};
+                                pm8058_l9: l9 {};
+                                pm8058_l10: l10 {};
+                                pm8058_l11: l11 {};
+                                pm8058_l12: l12 {};
+                                pm8058_l13: l13 {};
+                                pm8058_l14: l14 {};
+                                pm8058_l15: l15 {};
+                                pm8058_l16: l16 {};
+                                pm8058_l17: l17 {};
+                                pm8058_l18: l18 {};
+                                pm8058_l19: l19 {};
+                                pm8058_l20: l20 {};
+                                pm8058_l21: l21 {};
+                                pm8058_l22: l22 {};
+                                pm8058_l23: l23 {};
+                                pm8058_l24: l24 {};
+                                pm8058_l25: l25 {};
+
+                                pm8058_s0: s0 {};
+                                pm8058_s1: s1 {};
+                                pm8058_s2: s2 {};
+                                pm8058_s3: s3 {};
+                                pm8058_s4: s4 {};
+
+                                pm8058_lvs0: lvs0 {};
+                                pm8058_lvs1: lvs1 {};
+
+                                pm8058_ncp: ncp {};
+                        };
                 };
 
                 amba {
@@ -205,7 +334,6 @@
                                 non-removable;
                                 cap-sd-highspeed;
                                 cap-mmc-highspeed;
-                                vmmc-supply = <&vsdcc_fixed>;
                         };
 
                         sdcc3: sdcc@12180000 {
@@ -222,7 +350,21 @@
                                 cap-mmc-highspeed;
                                 max-frequency   = <48000000>;
                                 no-1-8-v;
-                                vmmc-supply = <&vsdcc_fixed>;
+                        };
+
+                        sdcc5: sdcc@12200000 {
+                                compatible      = "arm,pl18x", "arm,primecell";
+                                arm,primecell-periphid = <0x00051180>;
+                                status          = "disabled";
+                                reg             = <0x12200000 0x8000>;
+                                interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+                                interrupt-names = "cmd_irq";
+                                clocks          = <&gcc SDC5_CLK>, <&gcc SDC5_H_CLK>;
+                                clock-names     = "mclk", "apb_pclk";
+                                bus-width       = <4>;
+                                cap-sd-highspeed;
+                                cap-mmc-highspeed;
+                                max-frequency   = <48000000>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
index a0398b69f4f2..3fb4dada6b0d 100644
--- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
+++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-honami.dts
@@ -367,6 +367,10 @@
                 };
 
         };
+
+        dma-controller@f9944000 {
+                qcom,controlled-remotely;
+        };
 };
 
 &spmi_bus {
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 6f164266a010..561d4d136762 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,6 @@
 /dts-v1/;
 
-#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
 #include "skeleton.dtsi"
 
@@ -182,7 +182,7 @@
 
                 modem_smp2p_out: master-kernel {
                         qcom,entry-name = "master-kernel";
-                        #qcom,state-cells = <1>;
+                        #qcom,smem-state-cells = <1>;
                 };
 
                 modem_smp2p_in: slave-kernel {
@@ -208,7 +208,7 @@
                 wcnss_smp2p_out: master-kernel {
                         qcom,entry-name = "master-kernel";
 
-                        #qcom,state-cells = <1>;
+                        #qcom,smem-state-cells = <1>;
                 };
 
                 wcnss_smp2p_in: slave-kernel {
@@ -232,7 +232,7 @@
                 apps_smsm: apps@0 {
                         reg = <0>;
 
-                        #qcom,state-cells = <1>;
+                        #qcom,smem-state-cells = <1>;
                 };
 
                 modem_smsm: modem@1 {
@@ -260,6 +260,14 @@
                 };
         };
 
+        firmware {
+                scm {
+                        compatible = "qcom,scm";
+                        clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
+                        clock-names = "core", "bus", "iface";
+                };
+        };
+
         soc: soc {
                 #address-cells = <1>;
                 #size-cells = <1>;
@@ -501,6 +509,8 @@
                         clock-names = "core", "iface";
                         #address-cells = <1>;
                         #size-cells = <0>;
+                        dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
+                        dma-names = "tx", "rx";
                 };
 
                 spmi_bus: spmi@fc4cf000 {
@@ -518,6 +528,16 @@
                         interrupt-controller;
                         #interrupt-cells = <4>;
                 };
+
+                blsp2_dma: dma-controller@f9944000 {
+                        compatible = "qcom,bam-v1.4.0";
+                        reg = <0xf9944000 0x19000>;
+                        interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+                        clock-names = "bam_clk";
+                        #dma-cells = <1>;
+                        qcom,ee = <0>;
+                };
         };
 
         smd {
diff --git a/arch/arm/boot/dts/qcom-pma8084.dtsi b/arch/arm/boot/dts/qcom-pma8084.dtsi
index 4e9bd3f88473..82d258094156 100644
--- a/arch/arm/boot/dts/qcom-pma8084.dtsi
+++ b/arch/arm/boot/dts/qcom-pma8084.dtsi
@@ -12,15 +12,23 @@
 
                 rtc@6000 {
                         compatible = "qcom,pm8941-rtc";
-                        reg = <0x6000 0x100>,
-                              <0x6100 0x100>;
+                        reg = <0x6000>,
+                              <0x6100>;
                         reg-names = "rtc", "alarm";
                         interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
                 };
 
+                pwrkey@800 {
+                        compatible = "qcom,pm8941-pwrkey";
+                        reg = <0x800>;
+                        interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
+                        debounce = <15625>;
+                        bias-pull-up;
+                };
+
                 pma8084_gpios: gpios@c000 {
                         compatible = "qcom,pma8084-gpio", "qcom,spmi-gpio";
-                        reg = <0xc000 0x1600>;
+                        reg = <0xc000>;
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
@@ -49,7 +57,7 @@
 
                 pma8084_mpps: mpps@a000 {
                         compatible = "qcom,pma8084-mpp", "qcom,spmi-mpp";
-                        reg = <0xa000 0x800>;
+                        reg = <0xa000>;
                         gpio-controller;
                         #gpio-cells = <2>;
                         interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
@@ -64,7 +72,7 @@
 
                 pma8084_temp: temp-alarm@2400 {
                         compatible = "qcom,spmi-temp-alarm";
-                        reg = <0x2400 0x100>;
+                        reg = <0x2400>;
                         interrupts = <0 0x24 0 IRQ_TYPE_EDGE_RISING>;
                         #thermal-sensor-cells = <0>;
                         io-channels = <&pma8084_vadc VADC_DIE_TEMP>;
@@ -73,7 +81,7 @@
 
                 pma8084_vadc: vadc@3100 {
                         compatible = "qcom,spmi-vadc";
-                        reg = <0x3100 0x100>;
+                        reg = <0x3100>;
                         interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
                         #address-cells = <1>;
                         #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index a9da7a89fc4b..118a8e2b86bd 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -17,15 +17,15 @@
         compatible = "renesas,genmai", "renesas,r7s72100";
 
         aliases {
-                serial2 = &scif2;
+                serial0 = &scif2;
         };
 
         chosen {
                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
-                stdout-path = &scif2;
+                stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@8000000 {
                 device_type = "memory";
                 reg = <0x08000000 0x08000000>;
         };
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index 93ace33e3e36..ec7c86e06538 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -36,7 +36,7 @@
                 reg = <2 0x00000000 0 0x40000000>;
         };
 
-        vcc_mmc0: regulator@0 {
+        vcc_mmc0: regulator-mmc0 {
                 compatible = "regulator-fixed";
                 regulator-name = "MMC0 Vcc";
                 regulator-min-microvolt = <2800000>;
@@ -44,7 +44,7 @@
                 regulator-always-on;
         };
 
-        vcc_sdhi0: regulator@1 {
+        vcc_sdhi0: regulator-sdhi0 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI0 Vcc";
@@ -56,7 +56,7 @@
         };
 
         /* Common 1.8V and 3.3V rails, used by several devices on APE6EVM */
-        ape6evm_fixed_1v8: regulator@2 {
+        ape6evm_fixed_1v8: regulator-1v8 {
                 compatible = "regulator-fixed";
                 regulator-name = "1V8";
                 regulator-min-microvolt = <1800000>;
@@ -64,7 +64,7 @@
                 regulator-always-on;
         };
 
-        ape6evm_fixed_3v3: regulator@3 {
+        ape6evm_fixed_3v3: regulator-3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "3V3";
                 regulator-min-microvolt = <3300000>;
@@ -188,12 +188,12 @@
 };
 
 &pfc {
-        scifa0_pins: serial0 {
+        scifa0_pins: scifa0 {
                 groups = "scifa0_data";
                 function = "scifa0";
         };
 
-        mmc0_pins: mmc {
+        mmc0_pins: mmc0 {
                 groups = "mmc0_data8", "mmc0_ctrl";
                 function = "mmc0";
         };
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 6954912a3753..ca8672778fe0 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -31,6 +31,24 @@
                         power-domains = <&pd_a2sl>;
                         next-level-cache = <&L2_CA15>;
                 };
+
+                L2_CA15: cache-controller@0 {
+                        compatible = "cache";
+                        reg = <0>;
+                        clocks = <&cpg_clocks R8A73A4_CLK_Z>;
+                        power-domains = <&pd_a3sm>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                L2_CA7: cache-controller@100 {
+                        compatible = "cache";
+                        reg = <0x100>;
+                        clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
+                        power-domains = <&pd_a3km>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
         };
 
         ptm {
@@ -46,22 +64,6 @@
                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
         };
 
-        L2_CA15: cache-controller@0 {
-                compatible = "cache";
-                clocks = <&cpg_clocks R8A73A4_CLK_Z>;
-                power-domains = <&pd_a3sm>;
-                cache-unified;
-                cache-level = <2>;
-        };
-
-        L2_CA7: cache-controller@1 {
-                compatible = "cache";
-                clocks = <&cpg_clocks R8A73A4_CLK_Z2>;
-                power-domains = <&pd_a3km>;
-                cache-unified;
-                cache-level = <2>;
-        };
-
         dbsc1: memory-controller@e6790000 {
                 compatible = "renesas,dbsc-r8a73a4";
                 reg = <0 0xe6790000 0 0x10000>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 2c82dab2b6f4..7885075428bb 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -20,20 +20,20 @@
         compatible = "renesas,armadillo800eva", "renesas,r8a7740";
 
         aliases {
-                serial1 = &scifa1;
+                serial0 = &scifa1;
         };
 
         chosen {
-                bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
-                stdout-path = &scifa1;
+                bootargs = "earlyprintk ignore_loglevel root=/dev/nfs ip=dhcp rw";
+                stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0x20000000>;
         };
 
-        reg_3p3v: regulator@0 {
+        reg_3p3v: regulator-3p3v {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -42,7 +42,7 @@
                 regulator-boot-on;
         };
 
-        vcc_sdhi0: regulator@1 {
+        vcc_sdhi0: regulator-vcc-sdhi0 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI0 Vcc";
@@ -53,7 +53,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi0: regulator@2 {
+        vccq_sdhi0: regulator-vccq-sdhi0 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI0 VccQ";
@@ -69,7 +69,7 @@
                 enable-active-high;
         };
 
-        reg_5p0v: regulator@3 {
+        reg_5p0v: regulator-5p0v {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-5.0V";
                 regulator-min-microvolt = <5000000>;
@@ -127,7 +127,7 @@
                 };
         };
 
-        i2c2: i2c@2 {
+        i2c2: i2c-2 {
                 #address-cells = <1>;
                 #size-cells = <0>;
                 compatible = "i2c-gpio";
@@ -232,7 +232,7 @@
                 function = "gether";
         };
 
-        scifa1_pins: serial1 {
+        scifa1_pins: scifa1 {
                 groups = "scifa1_data";
                 function = "scifa1";
         };
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 39b2f88ad151..159e04eb1b9e 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -39,7 +39,7 @@
                       <0xc2000000 0x1000>;
         };
 
-        L2: cache-controller {
+        L2: cache-controller@f0100000 {
                 compatible = "arm,pl310-cache";
                 reg = <0xf0100000 0x1000>;
                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index e0dab1464648..211d239d9041 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -32,12 +32,12 @@
                 stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@60000000 {
                 device_type = "memory";
                 reg = <0x60000000 0x10000000>;
         };
 
-        fixedregulator3v3: fixedregulator@0 {
+        fixedregulator3v3: regulator-3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -129,7 +129,7 @@
         pinctrl-0 = <&scif_clk_pins>;
         pinctrl-names = "default";
 
-        scif0_pins: serial0 {
+        scif0_pins: scif0 {
                 groups = "scif0_data_a", "scif0_ctrl";
                 function = "scif0";
         };
@@ -223,6 +223,7 @@
         pinctrl-0 = <&scif0_pins>;
         pinctrl-names = "default";
 
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index fe787b4751d2..e571d66ea0fe 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -276,23 +276,23 @@
                 status = "disabled";
 
                 rcar_sound,src {
-                        src3: src@3 { };
-                        src4: src@4 { };
-                        src5: src@5 { };
-                        src6: src@6 { };
-                        src7: src@7 { };
-                        src8: src@8 { };
-                        src9: src@9 { };
+                        src3: src-3 { };
+                        src4: src-4 { };
+                        src5: src-5 { };
+                        src6: src-6 { };
+                        src7: src-7 { };
+                        src8: src-8 { };
+                        src9: src-9 { };
                 };
 
                 rcar_sound,ssi {
-                        ssi3: ssi@3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi4: ssi@4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi5: ssi@5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi6: ssi@6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi7: ssi@7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi8: ssi@8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
-                        ssi9: ssi@9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi3: ssi-3 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi4: ssi-4 { interrupts = <GIC_SPI 0x85 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi5: ssi-5 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi6: ssi-6 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi7: ssi-7 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi8: ssi-8 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
+                        ssi9: ssi-9 { interrupts = <GIC_SPI 0x86 IRQ_TYPE_LEVEL_HIGH>; };
                 };
         };
 
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
index b795da6f5503..541678df90a9 100644
--- a/arch/arm/boot/dts/r8a7779-marzen.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -25,15 +25,15 @@
 
         chosen {
                 bootargs = "ignore_loglevel root=/dev/nfs ip=on";
-                stdout-path = &scif2;
+                stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@60000000 {
                 device_type = "memory";
                 reg = <0x60000000 0x40000000>;
         };
 
-        fixedregulator3v3: fixedregulator@0 {
+        fixedregulator3v3: regulator-3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -195,12 +195,12 @@
                 };
         };
 
-        scif2_pins: serial2 {
+        scif2_pins: scif2 {
                 groups = "scif2_data_c";
                 function = "scif2";
         };
 
-        scif4_pins: serial4 {
+        scif4_pins: scif4 {
                 groups = "scif4_data";
                 function = "scif4";
         };
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 749ba02b6a53..52b56fcaddf2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -76,28 +76,28 @@
         keyboard {
                 compatible = "gpio-keys";
 
-                button@1 {
+                one {
                         linux,code = <KEY_1>;
                         label = "SW2-1";
                         wakeup-source;
                         debounce-interval = <20>;
                         gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
                 };
-                button@2 {
+                two {
                         linux,code = <KEY_2>;
                         label = "SW2-2";
                         wakeup-source;
                         debounce-interval = <20>;
                         gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
                 };
-                button@3 {
+                three {
                         linux,code = <KEY_3>;
                         label = "SW2-3";
                         wakeup-source;
                         debounce-interval = <20>;
                         gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
                 };
-                button@4 {
+                four {
                         linux,code = <KEY_4>;
                         label = "SW2-4";
                         wakeup-source;
@@ -119,7 +119,7 @@
                 };
         };
 
-        fixedregulator3v3: fixedregulator@0 {
+        fixedregulator3v3: regulator-3v3 {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -128,7 +128,7 @@
                 regulator-always-on;
         };
 
-        vcc_sdhi0: regulator@1 {
+        vcc_sdhi0: regulator-vcc-sdhi0 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI0 Vcc";
@@ -139,7 +139,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi0: regulator@2 {
+        vccq_sdhi0: regulator-vccq-sdhi0 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI0 VccQ";
@@ -152,7 +152,7 @@
                           1800000 0>;
         };
 
-        vcc_sdhi2: regulator@3 {
+        vcc_sdhi2: regulator-vcc-sdhi2 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI2 Vcc";
@@ -163,7 +163,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi2: regulator@4 {
+        vccq_sdhi2: regulator-vccq-sdhi2 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI2 VccQ";
@@ -263,7 +263,7 @@
          * instantiate the slave device at runtime according to the documentation.
          * You can then communicate with the slave via IIC3.
          */
-        i2cexio: i2c@8 {
+        i2cexio: i2c-8 {
                 compatible = "i2c-demux-pinctrl";
                 i2c-parent = <&iic0>, <&i2c0>;
                 i2c-bus-name = "i2c-exio";
@@ -317,7 +317,7 @@
                 function = "du";
         };
 
-        scif0_pins: serial0 {
+        scif0_pins: scif0 {
                 groups = "scif0_data";
                 function = "scif0";
         };
@@ -337,7 +337,7 @@
                 function = "intc";
         };
 
-        scifa1_pins: serial1 {
+        scifa1_pins: scifa1 {
                 groups = "scifa1_data";
                 function = "scifa1";
         };
@@ -371,12 +371,12 @@
                 function = "mmc1";
         };
 
-        qspi_pins: spi0 {
+        qspi_pins: qspi {
                 groups = "qspi_ctrl", "qspi_data4";
                 function = "qspi";
         };
 
-        msiof1_pins: spi2 {
+        msiof1_pins: msiof1 {
                 groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
                                  "msiof1_tx";
                 function = "msiof1";
@@ -427,7 +427,7 @@
                 function = "usb2";
         };
 
-        vin1_pins: vin {
+        vin1_pins: vin1 {
                 groups = "vin1_data8", "vin1_clk";
                 function = "vin1";
         };
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 83cf23cd26bb..d18558f21102 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -44,6 +44,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "renesas,apmu";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -92,7 +93,7 @@
                         next-level-cache = <&L2_CA15>;
                 };
 
-                cpu4: cpu@4 {
+                cpu4: cpu@100 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x100>;
@@ -101,7 +102,7 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
-                cpu5: cpu@5 {
+                cpu5: cpu@101 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x101>;
@@ -110,7 +111,7 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
-                cpu6: cpu@6 {
+                cpu6: cpu@102 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x102>;
@@ -119,7 +120,7 @@
                         next-level-cache = <&L2_CA7>;
                 };
 
-                cpu7: cpu@7 {
+                cpu7: cpu@103 {
                         device_type = "cpu";
                         compatible = "arm,cortex-a7";
                         reg = <0x103>;
@@ -127,6 +128,22 @@
                         power-domains = <&sysc R8A7790_PD_CA7_CPU3>;
                         next-level-cache = <&L2_CA7>;
                 };
+
+                L2_CA15: cache-controller@0 {
+                        compatible = "cache";
+                        reg = <0>;
+                        power-domains = <&sysc R8A7790_PD_CA15_SCU>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+
+                L2_CA7: cache-controller@100 {
+                        compatible = "cache";
+                        reg = <0x100>;
+                        power-domains = <&sysc R8A7790_PD_CA7_SCU>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
         };
 
         thermal-zones {
@@ -148,18 +165,16 @@
                 };
         };
 
-        L2_CA15: cache-controller@0 {
-                compatible = "cache";
-                power-domains = <&sysc R8A7790_PD_CA15_SCU>;
-                cache-unified;
-                cache-level = <2>;
+        apmu@e6151000 {
+                compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+                reg = <0 0xe6151000 0 0x188>;
+                cpus = <&cpu4 &cpu5 &cpu6 &cpu7>;
         };
 
-        L2_CA7: cache-controller@1 {
-                compatible = "cache";
-                power-domains = <&sysc R8A7790_PD_CA7_SCU>;
-                cache-unified;
-                cache-level = <2>;
+        apmu@e6152000 {
+                compatible = "renesas,r8a7790-apmu", "renesas,apmu";
+                reg = <0 0xe6152000 0 0x188>;
+                cpus = <&cpu0 &cpu1 &cpu2 &cpu3>;
         };
 
         gic: interrupt-controller@f1001000 {
@@ -517,8 +532,9 @@
                 reg = <0 0xe6500000 0 0x425>;
                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                       <&dmac1 0x61>, <&dmac1 0x62>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -530,8 +546,9 @@
                 reg = <0 0xe6510000 0 0x425>;
                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                       <&dmac1 0x65>, <&dmac1 0x66>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -543,8 +560,9 @@
                 reg = <0 0xe6520000 0 0x425>;
                 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
-                dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x69>, <&dmac0 0x6a>,
+                       <&dmac1 0x69>, <&dmac1 0x6a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -556,8 +574,9 @@
                 reg = <0 0xe60b0000 0 0x425>;
                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
-                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                       <&dmac1 0x77>, <&dmac1 0x78>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -567,8 +586,9 @@
                 reg = <0 0xee200000 0 0x80>;
                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                       <&dmac1 0xd1>, <&dmac1 0xd2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 reg-io-width = <4>;
                 status = "disabled";
@@ -580,8 +600,9 @@
                 reg = <0 0xee220000 0 0x80>;
                 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
-                dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
+                       <&dmac1 0xe1>, <&dmac1 0xe2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 reg-io-width = <4>;
                 status = "disabled";
@@ -598,8 +619,9 @@
                 reg = <0 0xee100000 0 0x328>;
                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
-                dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                       <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx", "tx", "rx";
                 max-frequency = <195000000>;
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
@@ -610,8 +632,9 @@
                 reg = <0 0xee120000 0 0x328>;
                 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
-                dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
+                       <&dmac1 0xc9>, <&dmac1 0xca>;
+                dma-names = "tx", "rx", "tx", "rx";
                 max-frequency = <195000000>;
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
@@ -622,8 +645,9 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
-                dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                       <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 max-frequency = <97500000>;
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
@@ -634,8 +658,9 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
-                dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                       <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx", "tx", "rx";
                 max-frequency = <97500000>;
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
@@ -648,8 +673,9 @@
                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                       <&dmac1 0x21>, <&dmac1 0x22>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -661,8 +687,9 @@
                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                       <&dmac1 0x25>, <&dmac1 0x26>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -674,8 +701,9 @@
                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                       <&dmac1 0x27>, <&dmac1 0x28>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -687,8 +715,9 @@
                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                       <&dmac1 0x3d>, <&dmac1 0x3e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -700,8 +729,9 @@
                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                       <&dmac1 0x19>, <&dmac1 0x1a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -713,8 +743,9 @@
                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                       <&dmac1 0x1d>, <&dmac1 0x1e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -727,8 +758,9 @@
                 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                       <&dmac1 0x29>, <&dmac1 0x2a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -741,8 +773,9 @@
                 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                       <&dmac1 0x2d>, <&dmac1 0x2e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -755,8 +788,9 @@
                 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                       <&dmac1 0x2b>, <&dmac1 0x2c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -769,8 +803,9 @@
                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                       <&dmac1 0x39>, <&dmac1 0x3a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -783,8 +818,9 @@
                 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                       <&dmac1 0x4d>, <&dmac1 0x4e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -1469,8 +1505,9 @@
                 reg = <0 0xe6b10000 0 0x2c>;
                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                       <&dmac1 0x17>, <&dmac1 0x18>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 num-cs = <1>;
                 #address-cells = <1>;
@@ -1483,8 +1520,9 @@
                 reg = <0 0xe6e20000 0 0x0064>;
                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
-                dmas = <&dmac0 0x51>, <&dmac0 0x52>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                       <&dmac1 0x51>, <&dmac1 0x52>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1496,8 +1534,9 @@
                 reg = <0 0xe6e10000 0 0x0064>;
                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
-                dmas = <&dmac0 0x55>, <&dmac0 0x56>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                       <&dmac1 0x55>, <&dmac1 0x56>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1509,8 +1548,9 @@
                 reg = <0 0xe6e00000 0 0x0064>;
                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
-                dmas = <&dmac0 0x41>, <&dmac0 0x42>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                       <&dmac1 0x41>, <&dmac1 0x42>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1522,8 +1562,9 @@
                 reg = <0 0xe6c90000 0 0x0064>;
                 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
-                dmas = <&dmac0 0x45>, <&dmac0 0x46>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x45>, <&dmac0 0x46>,
+                       <&dmac1 0x45>, <&dmac1 0x46>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1702,79 +1743,79 @@
                 status = "disabled";
 
                 rcar_sound,dvc {
-                        dvc0: dvc@0 {
+                        dvc0: dvc-0 {
                                 dmas = <&audma0 0xbc>;
                                 dma-names = "tx";
                         };
-                        dvc1: dvc@1 {
+                        dvc1: dvc-1 {
                                 dmas = <&audma0 0xbe>;
                                 dma-names = "tx";
                         };
                 };
 
                 rcar_sound,mix {
-                        mix0: mix@0 { };
-                        mix1: mix@1 { };
+                        mix0: mix-0 { };
+                        mix1: mix-1 { };
                 };
 
                 rcar_sound,ctu {
-                        ctu00: ctu@0 { };
-                        ctu01: ctu@1 { };
-                        ctu02: ctu@2 { };
-                        ctu03: ctu@3 { };
-                        ctu10: ctu@4 { };
-                        ctu11: ctu@5 { };
-                        ctu12: ctu@6 { };
-                        ctu13: ctu@7 { };
+                        ctu00: ctu-0 { };
+                        ctu01: ctu-1 { };
+                        ctu02: ctu-2 { };
+                        ctu03: ctu-3 { };
+                        ctu10: ctu-4 { };
+                        ctu11: ctu-5 { };
+                        ctu12: ctu-6 { };
+                        ctu13: ctu-7 { };
                 };
 
                 rcar_sound,src {
-                        src0: src@0 {
+                        src0: src-0 {
                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
                                 dma-names = "rx", "tx";
                         };
-                        src1: src@1 {
+                        src1: src-1 {
                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
                                 dma-names = "rx", "tx";
                         };
-                        src2: src@2 {
+                        src2: src-2 {
                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
                                 dma-names = "rx", "tx";
                         };
-                        src3: src@3 {
+                        src3: src-3 {
                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
                                 dma-names = "rx", "tx";
                         };
-                        src4: src@4 {
+                        src4: src-4 {
                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
                                 dma-names = "rx", "tx";
                         };
-                        src5: src@5 {
+                        src5: src-5 {
                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
                                 dma-names = "rx", "tx";
                         };
-                        src6: src@6 {
+                        src6: src-6 {
                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
                                 dma-names = "rx", "tx";
                         };
-                        src7: src@7 {
+                        src7: src-7 {
                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
                                 dma-names = "rx", "tx";
                         };
-                        src8: src@8 {
+                        src8: src-8 {
                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
                                 dma-names = "rx", "tx";
                         };
-                        src9: src@9 {
+                        src9: src-9 {
                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
                                 dma-names = "rx", "tx";
@@ -1782,52 +1823,52 @@
                 };
 
                 rcar_sound,ssi {
-                        ssi0: ssi@0 {
+                        ssi0: ssi-0 {
                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi1: ssi@1 {
+                        ssi1: ssi-1 {
                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi2: ssi@2 {
+                        ssi2: ssi-2 {
                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi3: ssi@3 {
+                        ssi3: ssi-3 {
                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi4: ssi@4 {
+                        ssi4: ssi-4 {
                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi5: ssi@5 {
+                        ssi5: ssi-5 {
                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi6: ssi@6 {
+                        ssi6: ssi-6 {
                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi7: ssi@7 {
+                        ssi7: ssi-7 {
                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi8: ssi@8 {
+                        ssi8: ssi-8 {
                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi9: ssi@9 {
+                        ssi9: ssi-9 {
                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
                                 dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index da59c2844b8a..f8a7d090fd01 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -170,7 +170,7 @@
                 };
         };
 
-        vcc_sdhi0: regulator@0 {
+        vcc_sdhi0: regulator-vcc-sdhi0 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI0 Vcc";
@@ -181,7 +181,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi0: regulator@1 {
+        vccq_sdhi0: regulator-vccq-sdhi0 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI0 VccQ";
@@ -194,7 +194,7 @@
                           1800000 0>;
         };
 
-        vcc_sdhi1: regulator@2 {
+        vcc_sdhi1: regulator-vcc-sdhi1 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI1 Vcc";
@@ -205,7 +205,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi1: regulator@3 {
+        vccq_sdhi1: regulator-vccq-sdhi1 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI1 VccQ";
@@ -218,7 +218,7 @@
                           1800000 0>;
         };
 
-        vcc_sdhi2: regulator@4 {
+        vcc_sdhi2: regulator-vcc-sdhi2 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI2 Vcc";
@@ -229,7 +229,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi2: regulator@5 {
+        vccq_sdhi2: regulator-vccq-sdhi2 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI2 VccQ";
@@ -332,12 +332,12 @@
                 function = "du";
         };
 
-        scif0_pins: serial0 {
+        scif0_pins: scif0 {
                 groups = "scif0_data_d";
                 function = "scif0";
         };
 
-        scif1_pins: serial1 {
+        scif1_pins: scif1 {
                 groups = "scif1_data_d";
                 function = "scif1";
         };
@@ -372,12 +372,12 @@
                 function = "sdhi2";
         };
 
-        qspi_pins: spi0 {
+        qspi_pins: qspi {
                 groups = "qspi_ctrl", "qspi_data4";
                 function = "qspi";
         };
 
-        msiof0_pins: spi1 {
+        msiof0_pins: msiof0 {
                 groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
                                  "msiof0_tx";
                 function = "msiof0";
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 6a1bb1a8209b..6761d11d3f9e 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -46,7 +46,7 @@
                 reg = <2 0x00000000 0 0x40000000>;
         };
 
-        vcc_sdhi0: regulator@0 {
+        vcc_sdhi0: regulator-vcc-sdhi0 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI0 Vcc";
@@ -55,7 +55,7 @@
                 regulator-always-on;
         };
 
-        vccq_sdhi0: regulator@1 {
+        vccq_sdhi0: regulator-vccq-sdhi0 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI0 VccQ";
@@ -68,7 +68,7 @@
                           1800000 0>;
         };
 
-        vcc_sdhi2: regulator@2 {
+        vcc_sdhi2: regulator-vcc-sdhi2 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI2 Vcc";
@@ -77,7 +77,7 @@
                 regulator-always-on;
         };
 
-        vccq_sdhi2: regulator@3 {
+        vccq_sdhi2: regulator-vccq-sdhi2 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI2 VccQ";
@@ -142,7 +142,7 @@
 };
 
 &pfc {
-        scif0_pins: serial0 {
+        scif0_pins: scif0 {
                 groups = "scif0_data_d";
                 function = "scif0";
         };
@@ -167,7 +167,7 @@
                 function = "sdhi2";
         };
 
-        qspi_pins: spi0 {
+        qspi_pins: qspi {
                 groups = "qspi_ctrl", "qspi_data4";
                 function = "qspi";
         };
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index db67e342c585..8f0086bbd96b 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -43,6 +43,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "renesas,apmu";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -72,6 +73,14 @@
                         power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
                         next-level-cache = <&L2_CA15>;
                 };
+
+                L2_CA15: cache-controller@0 {
+                        compatible = "cache";
+                        reg = <0>;
+                        power-domains = <&sysc R8A7791_PD_CA15_SCU>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
         };
 
         thermal-zones {
@@ -93,11 +102,10 @@
                 };
         };
 
-        L2_CA15: cache-controller@0 {
-                compatible = "cache";
-                power-domains = <&sysc R8A7791_PD_CA15_SCU>;
-                cache-unified;
-                cache-level = <2>;
+        apmu@e6152000 {
+                compatible = "renesas,r8a7791-apmu", "renesas,apmu";
+                reg = <0 0xe6152000 0 0x188>;
+                cpus = <&cpu0 &cpu1>;
         };
 
         gic: interrupt-controller@f1001000 {
@@ -514,8 +522,9 @@
                 reg = <0 0xe60b0000 0 0x425>;
                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
-                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                       <&dmac1 0x77>, <&dmac1 0x78>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -527,8 +536,9 @@
                 reg = <0 0xe6500000 0 0x425>;
                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                       <&dmac1 0x61>, <&dmac1 0x62>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -540,8 +550,9 @@
                 reg = <0 0xe6510000 0 0x425>;
                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                       <&dmac1 0x65>, <&dmac1 0x66>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -556,8 +567,9 @@
                 reg = <0 0xee200000 0 0x80>;
                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                       <&dmac1 0xd1>, <&dmac1 0xd2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 reg-io-width = <4>;
                 status = "disabled";
@@ -569,8 +581,9 @@
                 reg = <0 0xee100000 0 0x328>;
                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
-                dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                       <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -580,8 +593,9 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
-                dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                       <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -591,8 +605,9 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
-                dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                       <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -604,8 +619,9 @@
                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                       <&dmac1 0x21>, <&dmac1 0x22>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -617,8 +633,9 @@
                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                       <&dmac1 0x25>, <&dmac1 0x26>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -630,8 +647,9 @@
                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                       <&dmac1 0x27>, <&dmac1 0x28>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -643,8 +661,9 @@
                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                       <&dmac1 0x1b>, <&dmac1 0x1c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -656,8 +675,9 @@
                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                       <&dmac1 0x1f>, <&dmac1 0x20>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -669,8 +689,9 @@
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x23>, <&dmac0 0x24>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                       <&dmac1 0x23>, <&dmac1 0x24>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -682,8 +703,9 @@
                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                       <&dmac1 0x3d>, <&dmac1 0x3e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -695,8 +717,9 @@
                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                       <&dmac1 0x19>, <&dmac1 0x1a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -708,8 +731,9 @@
                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                       <&dmac1 0x1d>, <&dmac1 0x1e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -722,8 +746,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                       <&dmac1 0x29>, <&dmac1 0x2a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -736,8 +761,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                       <&dmac1 0x2d>, <&dmac1 0x2e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -750,8 +776,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                       <&dmac1 0x2b>, <&dmac1 0x2c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -764,8 +791,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                       <&dmac1 0x2f>, <&dmac1 0x30>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -778,8 +806,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                       <&dmac1 0xfb>, <&dmac1 0xfc>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -792,8 +821,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                       <&dmac1 0xfd>, <&dmac1 0xfe>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -806,8 +836,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                       <&dmac1 0x39>, <&dmac1 0x3a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -820,8 +851,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                       <&dmac1 0x4d>, <&dmac1 0x4e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -834,8 +866,9 @@
                 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                       <&dmac1 0x3b>, <&dmac1 0x3c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -1478,8 +1511,9 @@
                 reg = <0 0xe6b10000 0 0x2c>;
                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                       <&dmac1 0x17>, <&dmac1 0x18>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 num-cs = <1>;
                 #address-cells = <1>;
@@ -1492,8 +1526,9 @@
                 reg = <0 0xe6e20000 0 0x0064>;
                 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
-                dmas = <&dmac0 0x51>, <&dmac0 0x52>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x51>, <&dmac0 0x52>,
+                       <&dmac1 0x51>, <&dmac1 0x52>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1505,8 +1540,9 @@
                 reg = <0 0xe6e10000 0 0x0064>;
                 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
-                dmas = <&dmac0 0x55>, <&dmac0 0x56>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x55>, <&dmac0 0x56>,
+                       <&dmac1 0x55>, <&dmac1 0x56>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1518,8 +1554,9 @@
                 reg = <0 0xe6e00000 0 0x0064>;
                 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
-                dmas = <&dmac0 0x41>, <&dmac0 0x42>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x41>, <&dmac0 0x42>,
+                       <&dmac1 0x41>, <&dmac1 0x42>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -1737,79 +1774,79 @@
                 status = "disabled";
 
                 rcar_sound,dvc {
-                        dvc0: dvc@0 {
+                        dvc0: dvc-0 {
                                 dmas = <&audma0 0xbc>;
                                 dma-names = "tx";
                         };
-                        dvc1: dvc@1 {
+                        dvc1: dvc-1 {
                                 dmas = <&audma0 0xbe>;
                                 dma-names = "tx";
                         };
                 };
 
                 rcar_sound,mix {
-                        mix0: mix@0 { };
-                        mix1: mix@1 { };
+                        mix0: mix-0 { };
+                        mix1: mix-1 { };
                 };
 
                 rcar_sound,ctu {
-                        ctu00: ctu@0 { };
-                        ctu01: ctu@1 { };
-                        ctu02: ctu@2 { };
-                        ctu03: ctu@3 { };
-                        ctu10: ctu@4 { };
-                        ctu11: ctu@5 { };
-                        ctu12: ctu@6 { };
-                        ctu13: ctu@7 { };
+                        ctu00: ctu-0 { };
+                        ctu01: ctu-1 { };
+                        ctu02: ctu-2 { };
+                        ctu03: ctu-3 { };
+                        ctu10: ctu-4 { };
+                        ctu11: ctu-5 { };
+                        ctu12: ctu-6 { };
+                        ctu13: ctu-7 { };
                 };
 
                 rcar_sound,src {
-                        src0: src@0 {
+                        src0: src-0 {
                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
                                 dma-names = "rx", "tx";
                         };
-                        src1: src@1 {
+                        src1: src-1 {
                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
                                 dma-names = "rx", "tx";
                         };
-                        src2: src@2 {
+                        src2: src-2 {
                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
                                 dma-names = "rx", "tx";
                         };
-                        src3: src@3 {
+                        src3: src-3 {
                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
                                 dma-names = "rx", "tx";
                         };
-                        src4: src@4 {
+                        src4: src-4 {
                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
                                 dma-names = "rx", "tx";
                         };
-                        src5: src@5 {
+                        src5: src-5 {
                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
                                 dma-names = "rx", "tx";
                         };
-                        src6: src@6 {
+                        src6: src-6 {
                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
                                 dma-names = "rx", "tx";
                         };
-                        src7: src@7 {
+                        src7: src-7 {
                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
                                 dma-names = "rx", "tx";
                         };
-                        src8: src@8 {
+                        src8: src-8 {
                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
                                 dma-names = "rx", "tx";
                         };
-                        src9: src@9 {
+                        src9: src-9 {
                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
                                 dma-names = "rx", "tx";
@@ -1817,52 +1854,52 @@
                 };
 
                 rcar_sound,ssi {
-                        ssi0: ssi@0 {
+                        ssi0: ssi-0 {
                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi1: ssi@1 {
+                        ssi1: ssi-1 {
                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi2: ssi@2 {
+                        ssi2: ssi-2 {
                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi3: ssi@3 {
+                        ssi3: ssi-3 {
                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi4: ssi@4 {
+                        ssi4: ssi-4 {
                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi5: ssi@5 {
+                        ssi5: ssi-5 {
                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi6: ssi@6 {
+                        ssi6: ssi-6 {
                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi7: ssi@7 {
+                        ssi7: ssi-7 {
                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi8: ssi@8 {
+                        ssi8: ssi-8 {
                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi9: ssi@9 {
+                        ssi9: ssi-9 {
                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
                                 dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts
new file mode 100644
index 000000000000..e7b40f0e7da6
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7792-blanche.dts
@@ -0,0 +1,66 @@
+/*
+ * Device Tree Source for the Blanche board
+ *
+ * Copyright (C) 2014 Renesas Electronics Corporation
+ * Copyright (C) 2016 Cogent  Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7792.dtsi"
+
+/ {
+        model = "Blanche";
+        compatible = "renesas,blanche", "renesas,r8a7792";
+
+        aliases {
+                serial0 = &scif0;
+                serial1 = &scif3;
+        };
+
+        chosen {
+                bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
+                stdout-path = "serial0:115200n8";
+        };
+
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+
+        d3_3v: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "D3.3V";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
+
+        ethernet@18000000 {
+                compatible = "smsc,lan89218", "smsc,lan9115";
+                reg = <0 0x18000000 0 0x100>;
+                phy-mode = "mii";
+                interrupt-parent = <&irqc>;
+                interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+                smsc,irq-push-pull;
+                reg-io-width = <4>;
+                vddvario-supply = <&d3_3v>;
+                vdd33a-supply = <&d3_3v>;
+        };
+};
+
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+
+&scif0 {
+        status = "okay";
+};
+
+&scif3 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
new file mode 100644
index 000000000000..3fd61d7ab906
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -0,0 +1,385 @@
+/*
+ * Device Tree Source for the r8a7792 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/clock/r8a7792-clock.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/power/r8a7792-sysc.h>
+
+/ {
+        compatible = "renesas,r8a7792";
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                enable-method = "renesas,apmu";
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                        clock-frequency = <1000000000>;
+                        clocks = <&cpg_clocks R8A7792_CLK_Z>;
+                        power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
+                        next-level-cache = <&L2_CA15>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                        clock-frequency = <1000000000>;
+                        power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
+                        next-level-cache = <&L2_CA15>;
+                };
+
+                L2_CA15: cache-controller@0 {
+                        compatible = "cache";
+                        reg = <0>;
+                        cache-unified;
+                        cache-level = <2>;
+                        power-domains = <&sysc R8A7792_PD_CA15_SCU>;
+                };
+        };
+
+        soc {
+                compatible = "simple-bus";
+                interrupt-parent = <&gic>;
+
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                apmu@e6152000 {
+                        compatible = "renesas,r8a7792-apmu", "renesas,apmu";
+                        reg = <0 0xe6152000 0 0x188>;
+                        cpus = <&cpu0 &cpu1>;
+                };
+
+                gic: interrupt-controller@f1001000 {
+                        compatible = "arm,gic-400";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0 0xf1001000 0 0x1000>,
+                              <0 0xf1002000 0 0x1000>,
+                              <0 0xf1004000 0 0x2000>,
+                              <0 0xf1006000 0 0x2000>;
+                        interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+                                      IRQ_TYPE_LEVEL_HIGH)>;
+                };
+
+                irqc: interrupt-controller@e61c0000 {
+                        compatible = "renesas,irqc-r8a7792", "renesas,irqc";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        reg = <0 0xe61c0000 0 0x200>;
+                        interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+                                     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                };
+
+                timer {
+                        compatible = "arm,armv7-timer";
+                        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+                                      IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+                                      IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+                                      IRQ_TYPE_LEVEL_LOW)>,
+                                     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+                                      IRQ_TYPE_LEVEL_LOW)>;
+                };
+
+                sysc: system-controller@e6180000 {
+                        compatible = "renesas,r8a7792-sysc";
+                        reg = <0 0xe6180000 0 0x0200>;
+                        #power-domain-cells = <1>;
+                };
+
+                dmac0: dma-controller@e6700000 {
+                        compatible = "renesas,dmac-r8a7792",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6700000 0 0x20000>;
+                        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
+
+                dmac1: dma-controller@e6720000 {
+                        compatible = "renesas,dmac-r8a7792",
+                                     "renesas,rcar-dmac";
+                        reg = <0 0xe6720000 0 0x20000>;
+                        interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+                                      GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "error",
+                                          "ch0", "ch1", "ch2", "ch3",
+                                          "ch4", "ch5", "ch6", "ch7",
+                                          "ch8", "ch9", "ch10", "ch11",
+                                          "ch12", "ch13", "ch14";
+                        clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
+                        clock-names = "fck";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        #dma-cells = <1>;
+                        dma-channels = <15>;
+                };
+
+                scif0: serial@e6e60000 {
+                        compatible = "renesas,scif-r8a7792",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e60000 0 64>;
+                        interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                               <&dmac1 0x29>, <&dmac1 0x2a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        status = "disabled";
+                };
+
+                scif1: serial@e6e68000 {
+                        compatible = "renesas,scif-r8a7792",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e68000 0 64>;
+                        interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                               <&dmac1 0x2d>, <&dmac1 0x2e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        status = "disabled";
+                };
+
+                scif2: serial@e6e58000 {
+                        compatible = "renesas,scif-r8a7792",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6e58000 0 64>;
+                        interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                               <&dmac1 0x2b>, <&dmac1 0x2c>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        status = "disabled";
+                };
+
+                scif3: serial@e6ea8000 {
+                        compatible = "renesas,scif-r8a7792",
+                                     "renesas,rcar-gen2-scif", "renesas,scif";
+                        reg = <0 0xe6ea8000 0 64>;
+                        interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                               <&dmac1 0x2f>, <&dmac1 0x30>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        status = "disabled";
+                };
+
+                hscif0: serial@e62c0000 {
+                        compatible = "renesas,hscif-r8a7792",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c0000 0 96>;
+                        interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                               <&dmac1 0x39>, <&dmac1 0x3a>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        status = "disabled";
+                };
+
+                hscif1: serial@e62c8000 {
+                        compatible = "renesas,hscif-r8a7792",
+                                     "renesas,rcar-gen2-hscif", "renesas,hscif";
+                        reg = <0 0xe62c8000 0 96>;
+                        interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
+                                 <&scif_clk>;
+                        clock-names = "fck", "brg_int", "scif_clk";
+                        dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                               <&dmac1 0x4d>, <&dmac1 0x4e>;
+                        dma-names = "tx", "rx", "tx", "rx";
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                        status = "disabled";
+                };
+
+                jpu: jpeg-codec@fe980000 {
+                        compatible = "renesas,jpu-r8a7792",
+                                     "renesas,rcar-gen2-jpu";
+                        reg = <0 0xfe980000 0 0x10300>;
+                        interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&mstp1_clks R8A7792_CLK_JPU>;
+                        power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
+                };
+
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@e6150000 {
+                        compatible = "renesas,r8a7792-cpg-clocks",
+                                     "renesas,rcar-gen2-cpg-clocks";
+                        reg = <0 0xe6150000 0 0x1000>;
+                        clocks = <&extal_clk>;
+                        #clock-cells = <1>;
+                        clock-output-names = "main", "pll0", "pll1", "pll3",
+                                             "lb", "qspi", "z";
+                        #power-domain-cells = <0>;
+                };
+
+                /* Fixed factor clocks */
+                pll1_div2_clk: pll1_div2 {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+                zs_clk: zs {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <6>;
+                        clock-mult = <1>;
+                };
+                p_clk: p {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <24>;
+                        clock-mult = <1>;
+                };
+                cp_clk: cp {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <48>;
+                        clock-mult = <1>;
+                };
+                m2_clk: m2 {
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+                        #clock-cells = <0>;
+                        clock-div = <8>;
+                        clock-mult = <1>;
+                };
+
+                /* Gate clocks */
+                mstp1_clks: mstp1_clks@e6150134 {
+                        compatible = "renesas,r8a7792-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
+                        clocks = <&m2_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <R8A7792_CLK_JPU>;
+                        clock-output-names = "jpu";
+                };
+                mstp2_clks: mstp2_clks@e6150138 {
+                        compatible = "renesas,r8a7792-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
+                        clocks = <&zs_clk>, <&zs_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
+                        >;
+                        clock-output-names = "sys-dmac1", "sys-dmac0";
+                };
+                mstp4_clks: mstp4_clks@e6150140 {
+                        compatible = "renesas,r8a7792-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
+                        clocks = <&cp_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <R8A7792_CLK_IRQC>;
+                        clock-output-names = "irqc";
+                };
+                mstp7_clks: mstp7_clks@e615014c {
+                        compatible = "renesas,r8a7792-mstp-clocks",
+                                     "renesas,cpg-mstp-clocks";
+                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
+                        clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
+                                 <&p_clk>, <&p_clk>;
+                        #clock-cells = <1>;
+                        clock-indices = <
+                                R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
+                                R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
+                                R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
+                        >;
+                        clock-output-names = "hscif1", "hscif0", "scif3",
+                                             "scif2", "scif1", "scif0";
+                };
+        };
+
+        /* External root clock */
+        extal_clk: extal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
+
+        /* External SCIF clock */
+        scif_clk: scif {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                /* This value must be overridden by the board. */
+                clock-frequency = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 0ebc3ee34923..90af18600124 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -158,7 +158,7 @@
                 };
         };
 
-        vcc_sdhi0: regulator@0 {
+        vcc_sdhi0: regulator-vcc-sdhi0 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI0 Vcc";
@@ -169,7 +169,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi0: regulator@1 {
+        vccq_sdhi0: regulator-vccq-sdhi0 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI0 VccQ";
@@ -182,7 +182,7 @@
                           1800000 0>;
         };
 
-        vcc_sdhi1: regulator@2 {
+        vcc_sdhi1: regulator-vcc-sdhi1 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI1 Vcc";
@@ -193,7 +193,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi1: regulator@3 {
+        vccq_sdhi1: regulator-vccq-sdhi1 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI1 VccQ";
@@ -206,7 +206,7 @@
                           1800000 0>;
         };
 
-        vcc_sdhi2: regulator@4 {
+        vcc_sdhi2: regulator-vcc-sdhi2 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI2 Vcc";
@@ -217,7 +217,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi2: regulator@5 {
+        vccq_sdhi2: regulator-vccq-sdhi2 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI2 VccQ";
@@ -320,12 +320,12 @@
                 function = "du";
         };
 
-        scif0_pins: serial0 {
+        scif0_pins: scif0 {
                 groups = "scif0_data_d";
                 function = "scif0";
         };
 
-        scif1_pins: serial1 {
+        scif1_pins: scif1 {
                 groups = "scif1_data_d";
                 function = "scif1";
         };
@@ -360,7 +360,7 @@
                 renesas,function = "sdhi2";
         };
 
-        qspi_pins: spi0 {
+        qspi_pins: qspi {
                 groups = "qspi_ctrl", "qspi_data4";
                 function = "qspi";
         };
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 1dd6d202cd4c..8d02aacf2892 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -35,6 +35,7 @@
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
+                enable-method = "renesas,apmu";
 
                 cpu0: cpu@0 {
                         device_type = "cpu";
@@ -55,6 +56,28 @@
                                            < 375000 1000000>;
                         next-level-cache = <&L2_CA15>;
                 };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                        clock-frequency = <1500000000>;
+                        power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+                };
+
+                L2_CA15: cache-controller@0 {
+                        compatible = "cache";
+                        reg = <0>;
+                        power-domains = <&sysc R8A7793_PD_CA15_SCU>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
+        };
+
+        apmu@e6152000 {
+                compatible = "renesas,r8a7793-apmu", "renesas,apmu";
+                reg = <0 0xe6152000 0 0x188>;
+                cpus = <&cpu0 &cpu1>;
         };
 
         thermal-zones {
@@ -76,13 +99,6 @@
                 };
         };
 
-        L2_CA15: cache-controller@0 {
-                compatible = "cache";
-                power-domains = <&sysc R8A7793_PD_CA15_SCU>;
-                cache-unified;
-                cache-level = <2>;
-        };
-
         gic: interrupt-controller@f1001000 {
                 compatible = "arm,gic-400";
                 #interrupt-cells = <3>;
@@ -473,8 +489,9 @@
                 reg = <0 0xe60b0000 0 0x425>;
                 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>;
-                dmas = <&dmac0 0x77>, <&dmac0 0x78>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x77>, <&dmac0 0x78>,
+                       <&dmac1 0x77>, <&dmac1 0x78>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -486,8 +503,9 @@
                 reg = <0 0xe6500000 0 0x425>;
                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7793_CLK_IIC0>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                       <&dmac1 0x61>, <&dmac1 0x62>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -499,8 +517,9 @@
                 reg = <0 0xe6510000 0 0x425>;
                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7793_CLK_IIC1>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                       <&dmac1 0x65>, <&dmac1 0x66>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -515,8 +534,9 @@
                 reg = <0 0xee100000 0 0x328>;
                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
-                dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                       <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -526,8 +546,9 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
-                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                       <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -537,10 +558,25 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
-                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                       <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx", "tx", "rx";
+                power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                status = "disabled";
+        };
+
+        mmcif0: mmc@ee200000 {
+                compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif";
+                reg = <0 0xee200000 0 0x80>;
+                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>;
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                       <&dmac1 0xd1>, <&dmac1 0xd2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
+                reg-io-width = <4>;
                 status = "disabled";
+                max-frequency = <97500000>;
         };
 
         scifa0: serial@e6c40000 {
@@ -550,8 +586,9 @@
                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                       <&dmac1 0x21>, <&dmac1 0x22>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -563,8 +600,9 @@
                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                       <&dmac1 0x25>, <&dmac1 0x26>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -576,8 +614,9 @@
                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                       <&dmac1 0x27>, <&dmac1 0x28>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -589,8 +628,9 @@
                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                       <&dmac1 0x1b>, <&dmac1 0x1c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -602,8 +642,9 @@
                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                       <&dmac1 0x1f>, <&dmac1 0x20>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -615,8 +656,9 @@
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x23>, <&dmac0 0x24>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                       <&dmac1 0x23>, <&dmac1 0x24>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -628,8 +670,9 @@
                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                       <&dmac1 0x3d>, <&dmac1 0x3e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -641,8 +684,9 @@
                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                       <&dmac1 0x19>, <&dmac1 0x1a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -654,8 +698,9 @@
                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                       <&dmac1 0x1d>, <&dmac1 0x1e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -668,8 +713,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                       <&dmac1 0x29>, <&dmac1 0x2a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -682,8 +728,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                       <&dmac1 0x2d>, <&dmac1 0x2e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -696,8 +743,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                       <&dmac1 0x2b>, <&dmac1 0x2c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -710,8 +758,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                       <&dmac1 0x2f>, <&dmac1 0x30>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -724,8 +773,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                       <&dmac1 0xfb>, <&dmac1 0xfc>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -738,8 +788,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                       <&dmac1 0xfd>, <&dmac1 0xfe>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -752,8 +803,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                       <&dmac1 0x39>, <&dmac1 0x3a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -766,8 +818,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                       <&dmac1 0x4d>, <&dmac1 0x4e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -780,8 +833,9 @@
                 clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                       <&dmac1 0x3b>, <&dmac1 0x3c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -803,8 +857,9 @@
                 reg = <0 0xe6b10000 0 0x2c>;
                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                       <&dmac1 0x17>, <&dmac1 0x18>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7793_PD_ALWAYS_ON>;
                 num-cs = <1>;
                 #address-cells = <1>;
@@ -1330,63 +1385,63 @@
                 status = "disabled";
 
                 rcar_sound,dvc {
-                        dvc0: dvc@0 {
+                        dvc0: dvc-0 {
                                 dmas = <&audma0 0xbc>;
                                 dma-names = "tx";
                         };
-                        dvc1: dvc@1 {
+                        dvc1: dvc-1 {
                                 dmas = <&audma0 0xbe>;
                                 dma-names = "tx";
                         };
                 };
 
                 rcar_sound,src {
-                        src0: src@0 {
+                        src0: src-0 {
                                 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x85>, <&audma1 0x9a>;
                                 dma-names = "rx", "tx";
                         };
-                        src1: src@1 {
+                        src1: src-1 {
                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x87>, <&audma1 0x9c>;
                                 dma-names = "rx", "tx";
                         };
-                        src2: src@2 {
+                        src2: src-2 {
                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x89>, <&audma1 0x9e>;
                                 dma-names = "rx", "tx";
                         };
-                        src3: src@3 {
+                        src3: src-3 {
                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
                                 dma-names = "rx", "tx";
                         };
-                        src4: src@4 {
+                        src4: src-4 {
                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
                                 dma-names = "rx", "tx";
                         };
-                        src5: src@5 {
+                        src5: src-5 {
                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
                                 dma-names = "rx", "tx";
                         };
-                        src6: src@6 {
+                        src6: src-6 {
                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x91>, <&audma1 0xb4>;
                                 dma-names = "rx", "tx";
                         };
-                        src7: src@7 {
+                        src7: src-7 {
                                 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x93>, <&audma1 0xb6>;
                                 dma-names = "rx", "tx";
                         };
-                        src8: src@8 {
+                        src8: src-8 {
                                 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x95>, <&audma1 0xb8>;
                                 dma-names = "rx", "tx";
                         };
-                        src9: src@9 {
+                        src9: src-9 {
                                 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x97>, <&audma1 0xba>;
                                 dma-names = "rx", "tx";
@@ -1394,52 +1449,52 @@
                 };
 
                 rcar_sound,ssi {
-                        ssi0: ssi@0 {
+                        ssi0: ssi-0 {
                                 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi1: ssi@1 {
+                        ssi1: ssi-1 {
                                  interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi2: ssi@2 {
+                        ssi2: ssi-2 {
                                 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi3: ssi@3 {
+                        ssi3: ssi-3 {
                                 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi4: ssi@4 {
+                        ssi4: ssi-4 {
                                 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi5: ssi@5 {
+                        ssi5: ssi-5 {
                                 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi6: ssi@6 {
+                        ssi6: ssi-6 {
                                 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi7: ssi@7 {
+                        ssi7: ssi-7 {
                                 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi8: ssi@8 {
+                        ssi8: ssi-8 {
                                 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
                                 dma-names = "rx", "tx", "rxu", "txu";
                         };
-                        ssi9: ssi@9 {
+                        ssi9: ssi-9 {
                                 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
                                 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
                                 dma-names = "rx", "tx", "rxu", "txu";
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 383ad791f1db..1ad37d431a2a 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -111,7 +111,7 @@
                 function = "du";
         };
 
-        scif2_pins: serial2 {
+        scif2_pins: scif2 {
                 groups = "scif2_data";
                 function = "scif2";
         };
@@ -147,7 +147,7 @@
 };
 
 &pfc {
-        qspi_pins: spi0 {
+        qspi_pins: qspi {
                 groups = "qspi_ctrl", "qspi_data4";
                 function = "qspi";
         };
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 56d98d5b2185..cf24f45fff22 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -32,7 +32,7 @@
                 reg = <0 0x40000000 0 0x40000000>;
         };
 
-        d3_3v: regulator@0 {
+        d3_3v: regulator-d3-3v {
                 compatible = "regulator-fixed";
                 regulator-name = "D3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -41,7 +41,7 @@
                 regulator-always-on;
         };
 
-        vcc_sdhi1: regulator@3 {
+        vcc_sdhi1: regulator-vcc-sdhi1 {
                 compatible = "regulator-fixed";
 
                 regulator-name = "SDHI1 Vcc";
@@ -52,7 +52,7 @@
                 enable-active-high;
         };
 
-        vccq_sdhi1: regulator@4 {
+        vccq_sdhi1: regulator-vccq-sdhi1 {
                 compatible = "regulator-gpio";
 
                 regulator-name = "SDHI1 VccQ";
@@ -129,7 +129,7 @@
         pinctrl-0 = <&scif_clk_pins>;
         pinctrl-names = "default";
 
-        scif2_pins: serial2 {
+        scif2_pins: scif2 {
                 groups = "scif2_data";
                 function = "scif2";
         };
@@ -164,7 +164,7 @@
                 function = "sdhi1";
         };
 
-        qspi_pins: spi0 {
+        qspi_pins: qspi {
                 groups = "qspi_ctrl", "qspi_data4";
                 function = "qspi";
         };
@@ -183,6 +183,16 @@
                 groups = "usb1";
                 function = "usb1";
         };
+
+        du0_pins: du0 {
+                groups = "du0_rgb888", "du0_sync", "du0_disp", "du0_clk0_out";
+                function = "du0";
+        };
+
+        du1_pins: du1 {
+                groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+                function = "du1";
+        };
 };
 
 &scif2 {
@@ -360,6 +370,8 @@
 };
 
 &du {
+        pinctrl-0 = <&du0_pins &du1_pins>;
+        pinctrl-names = "default";
         status = "okay";
 
         clocks = <&mstp7_clks R8A7794_CLK_DU0>,
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index f334a3a715f2..685f986cf962 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -55,13 +55,14 @@
                         power-domains = <&sysc R8A7794_PD_CA7_CPU1>;
                         next-level-cache = <&L2_CA7>;
                 };
-        };
 
-        L2_CA7: cache-controller@1 {
-                compatible = "cache";
-                power-domains = <&sysc R8A7794_PD_CA7_SCU>;
-                cache-unified;
-                cache-level = <2>;
+                L2_CA7: cache-controller@0 {
+                        compatible = "cache";
+                        reg = <0>;
+                        power-domains = <&sysc R8A7794_PD_CA7_SCU>;
+                        cache-unified;
+                        cache-level = <2>;
+                };
         };
 
         gic: interrupt-controller@f1001000 {
@@ -302,8 +303,9 @@
                 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x21>, <&dmac0 0x22>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+                       <&dmac1 0x21>, <&dmac1 0x22>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -315,8 +317,9 @@
                 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x25>, <&dmac0 0x26>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+                       <&dmac1 0x25>, <&dmac1 0x26>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -328,8 +331,9 @@
                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x27>, <&dmac0 0x28>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+                       <&dmac1 0x27>, <&dmac1 0x28>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -341,8 +345,9 @@
                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+                       <&dmac1 0x1b>, <&dmac1 0x1c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -354,8 +359,9 @@
                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1f>, <&dmac0 0x20>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+                       <&dmac1 0x1f>, <&dmac1 0x20>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -367,8 +373,9 @@
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x23>, <&dmac0 0x24>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+                       <&dmac1 0x23>, <&dmac1 0x24>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -380,8 +387,9 @@
                 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+                       <&dmac1 0x3d>, <&dmac1 0x3e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -393,8 +401,9 @@
                 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+                       <&dmac1 0x19>, <&dmac1 0x1a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -406,8 +415,9 @@
                 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>;
                 clock-names = "fck";
-                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+                       <&dmac1 0x1d>, <&dmac1 0x1e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -420,8 +430,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+                       <&dmac1 0x29>, <&dmac1 0x2a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -434,8 +445,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+                       <&dmac1 0x2d>, <&dmac1 0x2e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -448,8 +460,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+                       <&dmac1 0x2b>, <&dmac1 0x2c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -462,8 +475,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x2f>, <&dmac0 0x30>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+                       <&dmac1 0x2f>, <&dmac1 0x30>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -476,8 +490,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+                       <&dmac1 0xfb>, <&dmac1 0xfc>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -490,8 +505,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+                       <&dmac1 0xfd>, <&dmac1 0xfe>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -504,8 +520,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+                       <&dmac1 0x39>, <&dmac1 0x3a>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -518,8 +535,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+                       <&dmac1 0x4d>, <&dmac1 0x4e>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -532,8 +550,9 @@
                 clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>,
                          <&scif_clk>;
                 clock-names = "fck", "brg_int", "scif_clk";
-                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+                       <&dmac1 0x3b>, <&dmac1 0x3c>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -640,8 +659,9 @@
                 reg = <0 0xe6500000 0 0x425>;
                 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
-                dmas = <&dmac0 0x61>, <&dmac0 0x62>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x61>, <&dmac0 0x62>,
+                       <&dmac1 0x61>, <&dmac1 0x62>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -653,8 +673,9 @@
                 reg = <0 0xe6510000 0 0x425>;
                 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
-                dmas = <&dmac0 0x65>, <&dmac0 0x66>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x65>, <&dmac0 0x66>,
+                       <&dmac1 0x65>, <&dmac1 0x66>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -666,8 +687,9 @@
                 reg = <0 0xee200000 0 0x80>;
                 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>;
-                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
+                       <&dmac1 0xd1>, <&dmac1 0xd2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 reg-io-width = <4>;
                 status = "disabled";
@@ -678,6 +700,9 @@
                 reg = <0 0xee100000 0 0x200>;
                 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
+                dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
+                       <&dmac1 0xcd>, <&dmac1 0xce>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -687,6 +712,9 @@
                 reg = <0 0xee140000 0 0x100>;
                 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
+                dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
+                       <&dmac1 0xc1>, <&dmac1 0xc2>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -696,6 +724,9 @@
                 reg = <0 0xee160000 0 0x100>;
                 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
+                dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
+                       <&dmac1 0xd3>, <&dmac1 0xd4>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 status = "disabled";
         };
@@ -705,8 +736,9 @@
                 reg = <0 0xe6b10000 0 0x2c>;
                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>;
-                dmas = <&dmac0 0x17>, <&dmac0 0x18>;
-                dma-names = "tx", "rx";
+                dmas = <&dmac0 0x17>, <&dmac0 0x18>,
+                       <&dmac1 0x17>, <&dmac1 0x18>;
+                dma-names = "tx", "rx", "tx", "rx";
                 power-domains = <&sysc R8A7794_PD_ALWAYS_ON>;
                 num-cs = <1>;
                 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
index 5956e8246abe..904668e2e666 100644
--- a/arch/arm/boot/dts/rk3228-evb.dts
+++ b/arch/arm/boot/dts/rk3228-evb.dts
@@ -40,7 +40,7 @@
 
 /dts-v1/;
 
-#include "rk3228.dtsi"
+#include "rk322x.dtsi"
 
 / {
         model = "Rockchip RK3228 Evaluation board";
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
new file mode 100644
index 000000000000..b6a12035a6bb
--- /dev/null
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -0,0 +1,90 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *  Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk322x.dtsi"
+
+/ {
+        model = "Rockchip RK3229 Evaluation board";
+        compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
+
+        memory {
+                device_type = "memory";
+                reg = <0x60000000 0x40000000>;
+        };
+
+        ext_gmac: ext_gmac {
+                compatible = "fixed-clock";
+                clock-frequency = <125000000>;
+                clock-output-names = "ext_gmac";
+                #clock-cells = <0>;
+        };
+
+        vcc_phy: vcc-phy-regulator {
+                compatible = "regulator-fixed";
+                enable-active-high;
+                regulator-name = "vcc_phy";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+
+&gmac {
+        assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
+        assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
+        clock_in_out = "input";
+        phy-supply = <&vcc_phy>;
+        phy-mode = "rgmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&rgmii_pins>;
+        snps,reset-gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+        snps,reset-active-low;
+        snps,reset-delays-us = <0 10000 1000000>;
+        tx_delay = <0x30>;
+        rx_delay = <0x10>;
+        status = "okay";
+};
+
+&uart2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/rk3228.dtsi b/arch/arm/boot/dts/rk322x.dtsi
index e23a22e29155..9e6bf0e311bb 100644
--- a/arch/arm/boot/dts/rk3228.dtsi
+++ b/arch/arm/boot/dts/rk322x.dtsi
@@ -47,8 +47,6 @@
 #include "skeleton.dtsi"
 
 / {
-        compatible = "rockchip,rk3228";
-
         interrupt-parent = <&gic>;
 
         aliases {
@@ -140,6 +138,47 @@
                 #clock-cells = <0>;
         };
 
+        i2s1: i2s1@100b0000 {
+                compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+                reg = <0x100b0000 0x4000>;
+                interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clock-names = "i2s_clk", "i2s_hclk";
+                clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
+                dmas = <&pdma 14>, <&pdma 15>;
+                dma-names = "tx", "rx";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2s1_bus>;
+                status = "disabled";
+        };
+
+        i2s0: i2s0@100c0000 {
+                compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+                reg = <0x100c0000 0x4000>;
+                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clock-names = "i2s_clk", "i2s_hclk";
+                clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
+                dmas = <&pdma 11>, <&pdma 12>;
+                dma-names = "tx", "rx";
+                status = "disabled";
+        };
+
+        i2s2: i2s2@100e0000 {
+                compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
+                reg = <0x100e0000 0x4000>;
+                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clock-names = "i2s_clk", "i2s_hclk";
+                clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
+                dmas = <&pdma 0>, <&pdma 1>;
+                dma-names = "tx", "rx";
+                status = "disabled";
+        };
+
         grf: syscon@11000000 {
                 compatible = "syscon";
                 reg = <0x11000000 0x1000>;
@@ -376,6 +415,25 @@
                 status = "disabled";
         };
 
+        gmac: ethernet@30200000 {
+                compatible = "rockchip,rk3228-gmac";
+                reg = <0x30200000 0x10000>;
+                interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+                interrupt-names = "macirq";
+                clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
+                        <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
+                        <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
+                        <&cru PCLK_GMAC>;
+                clock-names = "stmmaceth", "mac_clk_rx",
+                        "mac_clk_tx", "clk_mac_ref",
+                        "clk_mac_refout", "aclk_mac",
+                        "pclk_mac";
+                resets = <&cru SRST_GMAC>;
+                reset-names = "stmmaceth";
+                rockchip,grf = <&grf>;
+                status = "disabled";
+        };
+
         gic: interrupt-controller@32010000 {
                 compatible = "arm,gic-400";
                 interrupt-controller;
@@ -460,6 +518,10 @@
                         bias-disable;
                 };
 
+                pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+                        drive-strength = <12>;
+                };
+
                 emmc {
                         emmc_clk: emmc-clk {
                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
@@ -481,6 +543,44 @@
                         };
                 };
 
+                gmac {
+                        rgmii_pins: rgmii-pins {
+                                rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 12 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 25 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 17 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 16 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 21 RK_FUNC_2 &pcfg_pull_none>,
+                                                <2 20 RK_FUNC_2 &pcfg_pull_none>,
+                                                <2 11 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 8 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        rmii_pins: rmii-pins {
+                                rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 12 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 25 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
+                                                <2 17 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 16 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 8 RK_FUNC_1 &pcfg_pull_none>,
+                                                <2 15 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+
+                        phy_pins: phy-pins {
+                                rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
+                                                <2 8 RK_FUNC_2 &pcfg_pull_none>;
+                        };
+                };
+
                 i2c0 {
                         i2c0_xfer: i2c0-xfer {
                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
@@ -509,6 +609,20 @@
                         };
                 };
 
+                i2s1 {
+                        i2s1_bus: i2s1-bus {
+                                rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
+                                                <0 9 RK_FUNC_1 &pcfg_pull_none>,
+                                                <0 11 RK_FUNC_1 &pcfg_pull_none>,
+                                                <0 12 RK_FUNC_1 &pcfg_pull_none>,
+                                                <0 13 RK_FUNC_1 &pcfg_pull_none>,
+                                                <0 14 RK_FUNC_1 &pcfg_pull_none>,
+                                                <1 2 RK_FUNC_1 &pcfg_pull_none>,
+                                                <1 4 RK_FUNC_1 &pcfg_pull_none>,
+                                                <1 5 RK_FUNC_1 &pcfg_pull_none>;
+                        };
+                };
+
                 pwm0 {
                         pwm0_pin: pwm0-pin {
                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
diff --git a/arch/arm/boot/dts/rk3288-firefly.dtsi b/arch/arm/boot/dts/rk3288-firefly.dtsi
index d6cf9ada13c9..114c90fb65e2 100644
--- a/arch/arm/boot/dts/rk3288-firefly.dtsi
+++ b/arch/arm/boot/dts/rk3288-firefly.dtsi
@@ -64,22 +64,6 @@
                 clock-output-names = "ext_gmac";
         };
 
-        io_domains: io-domains {
-                compatible = "rockchip,rk3288-io-voltage-domain";
-                rockchip,grf = <&grf>;
-
-                audio-supply = <&vcca_33>;
-                bb-supply = <&vcc_io>;
-                dvp-supply = <&dovdd_1v8>;
-                flash0-supply = <&vcc_flash>;
-                flash1-supply = <&vcc_lan>;
-                gpio30-supply = <&vcc_io>;
-                gpio1830-supply = <&vcc_io>;
-                lcdc-supply = <&vcc_io>;
-                sdcard-supply = <&vccio_sd>;
-                wifi-supply = <&vccio_wl>;
-        };
-
         ir: ir-receiver {
                 compatible = "gpio-ir-receiver";
                 pinctrl-names = "default";
@@ -397,6 +381,21 @@
         status = "okay";
 };
 
+&io_domains {
+        status = "okay";
+
+        audio-supply = <&vcca_33>;
+        bb-supply = <&vcc_io>;
+        dvp-supply = <&dovdd_1v8>;
+        flash0-supply = <&vcc_flash>;
+        flash1-supply = <&vcc_lan>;
+        gpio30-supply = <&vcc_io>;
+        gpio1830-supply = <&vcc_io>;
+        lcdc-supply = <&vcc_io>;
+        sdcard-supply = <&vccio_sd>;
+        wifi-supply = <&vccio_wl>;
+};
+
 &pinctrl {
         pcfg_output_high: pcfg-output-high {
                 output-high;
diff --git a/arch/arm/boot/dts/rk3288-miqi.dts b/arch/arm/boot/dts/rk3288-miqi.dts
index 8643103d8cd8..24488421f0f0 100644
--- a/arch/arm/boot/dts/rk3288-miqi.dts
+++ b/arch/arm/boot/dts/rk3288-miqi.dts
@@ -64,19 +64,6 @@
                 clock-output-names = "ext_gmac";
         };
 
-        io_domains: io-domains {
-                compatible = "rockchip,rk3288-io-voltage-domain";
-
-                audio-supply = <&vcca_33>;
-                flash0-supply = <&vcc_flash>;
-                flash1-supply = <&vcc_lan>;
-                gpio30-supply = <&vcc_io>;
-                gpio1830-supply = <&vcc_io>;
-                lcdc-supply = <&vcc_io>;
-                sdcard-supply = <&vccio_sd>;
-                wifi-supply = <&vcc_18>;
-        };
-
         leds {
                 compatible = "gpio-leds";
 
@@ -321,6 +308,19 @@
         status = "okay";
 };
 
+&io_domains {
+        status = "okay";
+
+        audio-supply = <&vcca_33>;
+        flash0-supply = <&vcc_flash>;
+        flash1-supply = <&vcc_lan>;
+        gpio30-supply = <&vcc_io>;
+        gpio1830-supply = <&vcc_io>;
+        lcdc-supply = <&vcc_io>;
+        sdcard-supply = <&vccio_sd>;
+        wifi-supply = <&vcc_18>;
+};
+
 &pinctrl {
         pcfg_output_high: pcfg-output-high {
                 output-high;
diff --git a/arch/arm/boot/dts/rk3288-popmetal.dts b/arch/arm/boot/dts/rk3288-popmetal.dts
index 720717bb3614..dda8d259bb6d 100644
--- a/arch/arm/boot/dts/rk3288-popmetal.dts
+++ b/arch/arm/boot/dts/rk3288-popmetal.dts
@@ -77,22 +77,6 @@
                 };
         };
 
-        io_domains: io-domains {
-                compatible = "rockchip,rk3288-io-voltage-domain";
-                rockchip,grf = <&grf>;
-
-                audio-supply = <&vcca_33>;
-                bb-supply = <&vcc_io>;
-                dvp-supply = <&vcc18_dvp>;
-                flash0-supply = <&vcc_flash>;
-                flash1-supply = <&vcc_lan>;
-                gpio30-supply = <&vcc_io>;
-                gpio1830-supply = <&vcc_io>;
-                lcdc-supply = <&vcc_io>;
-                sdcard-supply = <&vccio_sd>;
-                wifi-supply = <&vccio_wl>;
-        };
-
         ir: ir-receiver {
                 compatible = "gpio-ir-receiver";
                 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
@@ -437,6 +421,21 @@
         status = "okay";
 };
 
+&io_domains {
+        status = "okay";
+
+        audio-supply = <&vcca_33>;
+        bb-supply = <&vcc_io>;
+        dvp-supply = <&vcc18_dvp>;
+        flash0-supply = <&vcc_flash>;
+        flash1-supply = <&vcc_lan>;
+        gpio30-supply = <&vcc_io>;
+        gpio1830-supply = <&vcc_io>;
+        lcdc-supply = <&vcc_io>;
+        sdcard-supply = <&vccio_sd>;
+        wifi-supply = <&vccio_wl>;
+};
+
 &pinctrl {
         ak8963 {
                 comp_int: comp-int {
diff --git a/arch/arm/boot/dts/rk3288-rock2-som.dtsi b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
index e1ee9f949035..bb1f01e037ba 100644
--- a/arch/arm/boot/dts/rk3288-rock2-som.dtsi
+++ b/arch/arm/boot/dts/rk3288-rock2-som.dtsi
@@ -61,22 +61,6 @@
                 clock-output-names = "ext_gmac";
         };
 
-        io_domains: io-domains {
-                compatible = "rockchip,rk3288-io-voltage-domain";
-                rockchip,grf = <&grf>;
-
-                audio-supply = <&vcc_io>;
-                bb-supply = <&vcc_io>;
-                dvp-supply = <&vcc_18>;
-                flash0-supply = <&vcc_flash>;
-                flash1-supply = <&vccio_pmu>;
-                gpio30-supply = <&vccio_pmu>;
-                gpio1830 = <&vcc_io>;
-                lcdc-supply = <&vcc_io>;
-                sdcard-supply = <&vccio_sd>;
-                wifi-supply = <&vcc_18>;
-        };
-
         vcc_flash: flash-regulator {
                 compatible = "regulator-fixed";
                 regulator-name = "vcc_sys";
@@ -259,6 +243,21 @@
         };
 };
 
+&io_domains {
+        status = "okay";
+
+        audio-supply = <&vcc_io>;
+        bb-supply = <&vcc_io>;
+        dvp-supply = <&vcc_18>;
+        flash0-supply = <&vcc_flash>;
+        flash1-supply = <&vccio_pmu>;
+        gpio30-supply = <&vccio_pmu>;
+        gpio1830 = <&vcc_io>;
+        lcdc-supply = <&vcc_io>;
+        sdcard-supply = <&vccio_sd>;
+        wifi-supply = <&vcc_18>;
+};
+
 &pinctrl {
         pcfg_output_high: pcfg-output-high {
                 output-high;
diff --git a/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
new file mode 100644
index 000000000000..6d105914a4f3
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-veyron-analog-audio.dtsi
@@ -0,0 +1,101 @@
+/*
+ * Google Veyron (and derivatives) fragment for the  max98090 audio
+ * codec and analog headphone jack.
+ *
+ * Copyright 2016 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+        sound {
+                compatible = "rockchip,rockchip-audio-max98090";
+                pinctrl-names = "default";
+                pinctrl-0 = <&mic_det>, <&hp_det>;
+                rockchip,model = "VEYRON-I2S";
+                rockchip,i2s-controller = <&i2s>;
+                rockchip,audio-codec = <&max98090>;
+                rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>;
+                rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
+                rockchip,headset-codec = <&headsetcodec>;
+        };
+};
+
+&i2c2 {
+        max98090: max98090@10 {
+                compatible = "maxim,max98090";
+                reg = <0x10>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+                clock-names = "mclk";
+                clocks = <&cru SCLK_I2S0_OUT>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&int_codec>;
+        };
+};
+
+&i2c4 {
+        headsetcodec: ts3a227e@3b {
+                compatible = "ti,ts3a227e";
+                reg = <0x3b>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&ts3a227e_int_l>;
+                ti,micbias = <7>;               /* MICBIAS = 2.8V */
+        };
+};
+
+&i2s {
+        status = "okay";
+};
+
+&io_domains {
+        audio-supply = <&vcc18_codec>;
+};
+
+&rk808 {
+        vcc10-supply = <&vcc33_sys>;
+
+        regulators {
+                vcc18_codec: LDO_REG6 {
+                        regulator-name = "vcc18_codec";
+                        regulator-always-on;
+                        regulator-boot-on;
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        regulator-state-mem {
+                                regulator-off-in-suspend;
+                        };
+                };
+        };
+};
+
+&pinctrl {
+        codec {
+                hp_det: hp-det {
+                        rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+
+                /*
+                 * HACK: We're going to _pull down_ this _active low_ interrupt
+                 * so that it never fires.  We don't need this interrupt because
+                 * we've got a ts3a227e chip but the driver requires it.
+                 */
+                int_codec: int-codec {
+                        rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_down>;
+                };
+
+                mic_det: mic-det {
+                        rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+
+        headset {
+                ts3a227e_int_l: ts3a227e-int-l {
+                        rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
index 2958c36d12a0..ce1f87980bcb 100644
--- a/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
@@ -46,6 +46,7 @@
 #include <dt-bindings/clock/rockchip,rk808.h>
 #include <dt-bindings/input/input.h>
 #include "rk3288-veyron.dtsi"
+#include "rk3288-veyron-analog-audio.dtsi"
 #include "rk3288-veyron-sdmmc.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/rk3288-veyron.dtsi b/arch/arm/boot/dts/rk3288-veyron.dtsi
index b2557bf5a58f..3dd2cca48c11 100644
--- a/arch/arm/boot/dts/rk3288-veyron.dtsi
+++ b/arch/arm/boot/dts/rk3288-veyron.dtsi
@@ -83,19 +83,6 @@
                 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
         };
 
-        io_domains: io-domains {
-                compatible = "rockchip,rk3288-io-voltage-domain";
-                rockchip,grf = <&grf>;
-
-                bb-supply = <&vcc33_io>;
-                dvp-supply = <&vcc_18>;
-                flash0-supply = <&vcc18_flashio>;
-                gpio1830-supply = <&vcc33_io>;
-                gpio30-supply = <&vcc33_io>;
-                lcdc-supply = <&vcc33_lcd>;
-                wifi-supply = <&vcc18_wl>;
-        };
-
         sdio_pwrseq: sdio-pwrseq {
                 compatible = "mmc-pwrseq-simple";
                 clocks = <&rk808 RK808_CLKOUT1>;
@@ -355,6 +342,18 @@
         i2c-scl-rising-time-ns = <1000>;
 };
 
+&io_domains {
+        status = "okay";
+
+        bb-supply = <&vcc33_io>;
+        dvp-supply = <&vcc_18>;
+        flash0-supply = <&vcc18_flashio>;
+        gpio1830-supply = <&vcc33_io>;
+        gpio30-supply = <&vcc33_io>;
+        lcdc-supply = <&vcc33_lcd>;
+        wifi-supply = <&vcc18_wl>;
+};
+
 &pwm1 {
         status = "okay";
 };
@@ -383,6 +382,12 @@
         status = "okay";
 
         rx-sample-delay-ns = <12>;
+
+        flash@0 {
+                compatible = "jedec,spi-nor";
+                spi-max-frequency = <50000000>;
+                reg = <0>;
+        };
 };
 
 &tsadc {
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 3ebee530f2b0..cd33f0170890 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -827,6 +827,11 @@
                         #phy-cells = <0>;
                         status = "disabled";
                 };
+
+                io_domains: io-domains {
+                        compatible = "rockchip,rk3288-io-voltage-domain";
+                        status = "disabled";
+                };
         };
 
         wdt: watchdog@ff800000 {
diff --git a/arch/arm/boot/dts/sama5d2.dtsi b/arch/arm/boot/dts/sama5d2.dtsi
index 5dd2734e67ba..353d0e5ec83b 100644
--- a/arch/arm/boot/dts/sama5d2.dtsi
+++ b/arch/arm/boot/dts/sama5d2.dtsi
@@ -72,6 +72,11 @@
                 };
         };
 
+        pmu {
+                compatible = "arm,cortex-a5-pmu";
+                interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
+        };
+
         memory {
                 reg = <0x20000000 0x20000000>;
         };
@@ -112,13 +117,13 @@
                         clock-names = "pclk", "hclk";
                         status = "disabled";
 
-                        ep0 {
+                        ep@0 {
                                 reg = <0>;
                                 atmel,fifo-size = <64>;
                                 atmel,nb-banks = <1>;
                         };
 
-                        ep1 {
+                        ep@1 {
                                 reg = <1>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <3>;
@@ -126,7 +131,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep2 {
+                        ep@2 {
                                 reg = <2>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <3>;
@@ -134,7 +139,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep3 {
+                        ep@3 {
                                 reg = <3>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -142,7 +147,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep4 {
+                        ep@4 {
                                 reg = <4>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -150,7 +155,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep5 {
+                        ep@5 {
                                 reg = <5>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -158,7 +163,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep6 {
+                        ep@6 {
                                 reg = <6>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -166,7 +171,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep7 {
+                        ep@7 {
                                 reg = <7>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -174,56 +179,56 @@
                                 atmel,can-isoc;
                         };
 
-                        ep8 {
+                        ep@8 {
                                 reg = <8>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep9 {
+                        ep@9 {
                                 reg = <9>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep10 {
+                        ep@10 {
                                 reg = <10>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep11 {
+                        ep@11 {
                                 reg = <11>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep12 {
+                        ep@12 {
                                 reg = <12>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep13 {
+                        ep@13 {
                                 reg = <13>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep14 {
+                        ep@14 {
                                 reg = <14>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep15 {
+                        ep@15 {
                                 reg = <15>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index 36301bd9a14a..4c84d333fc7e 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -326,26 +326,22 @@
                                 atmel,adc-res-names = "lowres", "highres";
                                 status = "disabled";
 
-                                trigger@0 {
-                                        reg = <0>;
+                                trigger0 {
                                         trigger-name = "external-rising";
                                         trigger-value = <0x1>;
                                         trigger-external;
                                 };
-                                trigger@1 {
-                                        reg = <1>;
+                                trigger1 {
                                         trigger-name = "external-falling";
                                         trigger-value = <0x2>;
                                         trigger-external;
                                 };
-                                trigger@2 {
-                                        reg = <2>;
+                                trigger2 {
                                         trigger-name = "external-any";
                                         trigger-value = <0x3>;
                                         trigger-external;
                                 };
-                                trigger@3 {
-                                        reg = <3>;
+                                trigger3 {
                                         trigger-name = "continuous";
                                         trigger-value = <0x6>;
                                 };
@@ -1341,13 +1337,13 @@
                         clock-names = "pclk", "hclk";
                         status = "disabled";
 
-                        ep0 {
+                        ep@0 {
                                 reg = <0>;
                                 atmel,fifo-size = <64>;
                                 atmel,nb-banks = <1>;
                         };
 
-                        ep1 {
+                        ep@1 {
                                 reg = <1>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <3>;
@@ -1355,7 +1351,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep2 {
+                        ep@2 {
                                 reg = <2>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <3>;
@@ -1363,84 +1359,84 @@
                                 atmel,can-isoc;
                         };
 
-                        ep3 {
+                        ep@3 {
                                 reg = <3>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-dma;
                         };
 
-                        ep4 {
+                        ep@4 {
                                 reg = <4>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-dma;
                         };
 
-                        ep5 {
+                        ep@5 {
                                 reg = <5>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-dma;
                         };
 
-                        ep6 {
+                        ep@6 {
                                 reg = <6>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-dma;
                         };
 
-                        ep7 {
+                        ep@7 {
                                 reg = <7>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-dma;
                         };
 
-                        ep8 {
+                        ep@8 {
                                 reg = <8>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep9 {
+                        ep@9 {
                                 reg = <9>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep10 {
+                        ep@10 {
                                 reg = <10>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep11 {
+                        ep@11 {
                                 reg = <11>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep12 {
+                        ep@12 {
                                 reg = <12>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep13 {
+                        ep@13 {
                                 reg = <13>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep14 {
+                        ep@14 {
                                 reg = <14>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                         };
 
-                        ep15 {
+                        ep@15 {
                                 reg = <15>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts
index 04eec0dfcf7d..25e4c0b2d786 100644
--- a/arch/arm/boot/dts/sama5d31ek.dts
+++ b/arch/arm/boot/dts/sama5d31ek.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 #include "sama5d31.dtsi"
 #include "sama5d3xmb.dtsi"
+#include "sama5d3xmb_emac.dtsi"
 #include "sama5d3xdm.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/sama5d33ek.dts b/arch/arm/boot/dts/sama5d33ek.dts
index cbd6a3ff1545..c517b87a1de2 100644
--- a/arch/arm/boot/dts/sama5d33ek.dts
+++ b/arch/arm/boot/dts/sama5d33ek.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 #include "sama5d33.dtsi"
 #include "sama5d3xmb.dtsi"
+#include "sama5d3xmb_gmac.dtsi"
 #include "sama5d3xdm.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts
index 878aa164275a..c8b8449fdc3e 100644
--- a/arch/arm/boot/dts/sama5d34ek.dts
+++ b/arch/arm/boot/dts/sama5d34ek.dts
@@ -9,6 +9,7 @@
 /dts-v1/;
 #include "sama5d34.dtsi"
 #include "sama5d3xmb.dtsi"
+#include "sama5d3xmb_gmac.dtsi"
 #include "sama5d3xdm.dtsi"
 
 / {
diff --git a/arch/arm/boot/dts/sama5d35ek.dts b/arch/arm/boot/dts/sama5d35ek.dts
index e812f5c1bf70..6e261fcf576c 100644
--- a/arch/arm/boot/dts/sama5d35ek.dts
+++ b/arch/arm/boot/dts/sama5d35ek.dts
@@ -9,6 +9,8 @@
 /dts-v1/;
 #include "sama5d35.dtsi"
 #include "sama5d3xmb.dtsi"
+#include "sama5d3xmb_emac.dtsi"
+#include "sama5d3xmb_gmac.dtsi"
 
 / {
         model = "Atmel SAMA5D35-EK";
diff --git a/arch/arm/boot/dts/sama5d36ek.dts b/arch/arm/boot/dts/sama5d36ek.dts
index 59576c6f9826..cd458b85a205 100644
--- a/arch/arm/boot/dts/sama5d36ek.dts
+++ b/arch/arm/boot/dts/sama5d36ek.dts
@@ -10,6 +10,8 @@
 #include "sama5d36.dtsi"
 #include "sama5d3xmb.dtsi"
 #include "sama5d3xdm.dtsi"
+#include "sama5d3xmb_emac.dtsi"
+#include "sama5d3xmb_gmac.dtsi"
 
 / {
         model = "Atmel SAMA5D36-EK";
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 2cf9c3611db6..b5e111b29da1 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -34,40 +34,6 @@
                         spi0: spi@f0004000 {
                                 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
                         };
-
-                        macb0: ethernet@f0028000 {
-                                phy-mode = "rgmii";
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                ethernet-phy@1 {
-                                        reg = <0x1>;
-                                        interrupt-parent = <&pioB>;
-                                        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
-                                        txen-skew-ps = <800>;
-                                        txc-skew-ps = <3000>;
-                                        rxdv-skew-ps = <400>;
-                                        rxc-skew-ps = <3000>;
-                                        rxd0-skew-ps = <400>;
-                                        rxd1-skew-ps = <400>;
-                                        rxd2-skew-ps = <400>;
-                                        rxd3-skew-ps = <400>;
-                                };
-
-                                ethernet-phy@7 {
-                                        reg = <0x7>;
-                                        interrupt-parent = <&pioB>;
-                                        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
-                                        txen-skew-ps = <800>;
-                                        txc-skew-ps = <3000>;
-                                        rxdv-skew-ps = <400>;
-                                        rxc-skew-ps = <3000>;
-                                        rxd0-skew-ps = <400>;
-                                        rxd1-skew-ps = <400>;
-                                        rxd2-skew-ps = <400>;
-                                        rxd3-skew-ps = <400>;
-                                };
-                        };
                 };
 
                 nand0: nand@60000000 {
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 89010422812d..6d252ad050f6 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -117,18 +117,6 @@
                                 status = "okay";
                         };
 
-                        macb1: ethernet@f802c000 {
-                                phy-mode = "rmii";
-
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-                                phy0: ethernet-phy@1 {
-                                        interrupt-parent = <&pioE>;
-                                        interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
-                                        reg = <1>;
-                                };
-                        };
-
                         pinctrl@fffff200 {
                                 board {
                                         pinctrl_mmc0_cd: mmc0_cd {
diff --git a/arch/arm/boot/dts/sama5d3xmb_emac.dtsi b/arch/arm/boot/dts/sama5d3xmb_emac.dtsi
new file mode 100644
index 000000000000..2fd14f371a04
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xmb_emac.dtsi
@@ -0,0 +1,26 @@
+/*
+ * sama5d3xmb_emac.dts - Device Tree Include file for SAMA5D3x mother board
+ * Ethernet
+ *
+ *  Copyright (C) 2016 Atmel,
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        ahb {
+                apb {
+                        macb1: ethernet@f802c000 {
+                                phy-mode = "rmii";
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                phy0: ethernet-phy@1 {
+                                        interrupt-parent = <&pioE>;
+                                        interrupts = <30 IRQ_TYPE_EDGE_FALLING>;
+                                        reg = <1>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi b/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi
new file mode 100644
index 000000000000..65aea7a75b1d
--- /dev/null
+++ b/arch/arm/boot/dts/sama5d3xmb_gmac.dtsi
@@ -0,0 +1,48 @@
+/*
+ * sama5d3xmb_gmac.dtsi - Device Tree Include file for SAMA5D3x motherboard
+ * Gigabit Ethernet
+ *
+ *  Copyright (C) 2016 Atmel,
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/ {
+        ahb {
+                apb {
+                        macb0: ethernet@f0028000 {
+                                phy-mode = "rgmii";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                ethernet-phy@1 {
+                                        reg = <0x1>;
+                                        interrupt-parent = <&pioB>;
+                                        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+                                        txen-skew-ps = <800>;
+                                        txc-skew-ps = <3000>;
+                                        rxdv-skew-ps = <400>;
+                                        rxc-skew-ps = <3000>;
+                                        rxd0-skew-ps = <400>;
+                                        rxd1-skew-ps = <400>;
+                                        rxd2-skew-ps = <400>;
+                                        rxd3-skew-ps = <400>;
+                                };
+
+                                ethernet-phy@7 {
+                                        reg = <0x7>;
+                                        interrupt-parent = <&pioB>;
+                                        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
+                                        txen-skew-ps = <800>;
+                                        txc-skew-ps = <3000>;
+                                        rxdv-skew-ps = <400>;
+                                        rxc-skew-ps = <3000>;
+                                        rxd0-skew-ps = <400>;
+                                        rxd1-skew-ps = <400>;
+                                        rxd2-skew-ps = <400>;
+                                        rxd3-skew-ps = <400>;
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sama5d4.dtsi b/arch/arm/boot/dts/sama5d4.dtsi
index 4e2cc30d6615..65e725fb5679 100644
--- a/arch/arm/boot/dts/sama5d4.dtsi
+++ b/arch/arm/boot/dts/sama5d4.dtsi
@@ -135,13 +135,13 @@
                         clock-names = "pclk", "hclk";
                         status = "disabled";
 
-                        ep0 {
+                        ep@0 {
                                 reg = <0>;
                                 atmel,fifo-size = <64>;
                                 atmel,nb-banks = <1>;
                         };
 
-                        ep1 {
+                        ep@1 {
                                 reg = <1>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <3>;
@@ -149,7 +149,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep2 {
+                        ep@2 {
                                 reg = <2>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <3>;
@@ -157,7 +157,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep3 {
+                        ep@3 {
                                 reg = <3>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -165,7 +165,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep4 {
+                        ep@4 {
                                 reg = <4>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -173,7 +173,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep5 {
+                        ep@5 {
                                 reg = <5>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -181,7 +181,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep6 {
+                        ep@6 {
                                 reg = <6>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -189,7 +189,7 @@
                                 atmel,can-isoc;
                         };
 
-                        ep7 {
+                        ep@7 {
                                 reg = <7>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -197,56 +197,56 @@
                                 atmel,can-isoc;
                         };
 
-                        ep8 {
+                        ep@8 {
                                 reg = <8>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep9 {
+                        ep@9 {
                                 reg = <9>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep10 {
+                        ep@10 {
                                 reg = <10>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep11 {
+                        ep@11 {
                                 reg = <11>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep12 {
+                        ep@12 {
                                 reg = <12>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep13 {
+                        ep@13 {
                                 reg = <13>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep14 {
+                        ep@14 {
                                 reg = <14>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
                                 atmel,can-isoc;
                         };
 
-                        ep15 {
+                        ep@15 {
                                 reg = <15>;
                                 atmel,fifo-size = <1024>;
                                 atmel,nb-banks = <2>;
@@ -1226,22 +1226,22 @@
                                 atmel,adc-ts-pressure-threshold = <10000>;
                                 status = "disabled";
 
-                                trigger@0 {
+                                trigger0 {
                                         trigger-name = "external-rising";
                                         trigger-value = <0x1>;
                                         trigger-external;
                                 };
-                                trigger@1 {
+                                trigger1 {
                                         trigger-name = "external-falling";
                                         trigger-value = <0x2>;
                                         trigger-external;
                                 };
-                                trigger@2 {
+                                trigger2 {
                                         trigger-name = "external-any";
                                         trigger-value = <0x3>;
                                         trigger-external;
                                 };
-                                trigger@3 {
+                                trigger3 {
                                         trigger-name = "continuous";
                                         trigger-value = <0x6>;
                                 };
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index c2d8a080e392..3d65f1f6d78b 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -22,7 +22,7 @@
         compatible = "renesas,kzm9g", "renesas,sh73a0";
 
         aliases {
-                serial4 = &scifa4;
+                serial0 = &scifa4;
         };
 
         cpus {
@@ -39,16 +39,16 @@
         };
 
         chosen {
-                bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
-                stdout-path = &scifa4;
+                bootargs = "root=/dev/nfs ip=dhcp ignore_loglevel rw";
+                stdout-path = "serial0:115200n8";
         };
 
-        memory {
+        memory@40000000 {
                 device_type = "memory";
                 reg = <0x40000000 0x20000000>;
         };
 
-        reg_1p8v: regulator@0 {
+        reg_1p8v: regulator-1p8v {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-1.8V";
                 regulator-min-microvolt = <1800000>;
@@ -57,7 +57,7 @@
                 regulator-boot-on;
         };
 
-        reg_3p3v: regulator@1 {
+        reg_3p3v: regulator-3p3v {
                 compatible = "regulator-fixed";
                 regulator-name = "fixed-3.3V";
                 regulator-min-microvolt = <3300000>;
@@ -66,7 +66,7 @@
                 regulator-boot-on;
         };
 
-        vmmc_sdhi0: regulator@2 {
+        vmmc_sdhi0: regulator-vmmc-sdhi0 {
                 compatible = "regulator-fixed";
                 regulator-name = "SDHI0 Vcc";
                 regulator-min-microvolt = <3300000>;
@@ -75,7 +75,7 @@
                 enable-active-high;
         };
 
-        vmmc_sdhi2: regulator@3 {
+        vmmc_sdhi2: regulator-vmmc-sdhi2 {
                 compatible = "regulator-fixed";
                 regulator-name = "SDHI2 Vcc";
                 regulator-min-microvolt = <3300000>;
@@ -352,7 +352,7 @@
                 };
         };
 
-        scifa4_pins: serial4 {
+        scifa4_pins: scifa4 {
                 groups = "scifa4_data", "scifa4_ctrl";
                 function = "scifa4";
         };
@@ -378,6 +378,7 @@
         pinctrl-0 = <&scifa4_pins>;
         pinctrl-names = "default";
 
+        uart-has-rtscts;
         status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index c4f434cdec60..032fe2f14b16 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -55,7 +55,7 @@
                       <0xf0000100 0x100>;
         };
 
-        L2: cache-controller {
+        L2: cache-controller@f0100000 {
                 compatible = "arm,pl310-cache";
                 reg = <0xf0100000 0x1000>;
                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index 5820b70c95b3..94000cbe576b 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -22,11 +22,6 @@
         #address-cells = <1>;
         #size-cells = <1>;
 
-        aliases {
-                serial0 = &uart0;
-                serial1 = &uart1;
-        };
-
         cpus {
                 #address-cells = <1>;
                 #size-cells = <0>;
@@ -572,12 +567,6 @@
                         reg = <0xffcfb100 0x80>;
                 };
 
-                sdramedac {
-                        compatible = "altr,sdram-edac-a10";
-                        altr,sdr-syscon = <&sdr>;
-                        interrupts = <0 2 4>, <0 0 4>;
-                };
-
                 L2: l2-cache@fffff000 {
                         compatible = "arm,pl310-cache";
                         reg = <0xfffff000 0x1000>;
@@ -610,16 +599,29 @@
                         #size-cells = <1>;
                         interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
                                      <0 0 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
                         ranges;
 
+                        sdramedac {
+                                compatible = "altr,sdram-edac-a10";
+                                altr,sdr-syscon = <&sdr>;
+                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH>,
+                                             <49 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+
                         l2-ecc@ffd06010 {
                                 compatible = "altr,socfpga-a10-l2-ecc";
                                 reg = <0xffd06010 0x4>;
+                                interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
+                                             <32 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
                         ocram-ecc@ff8c3000 {
                                 compatible = "altr,socfpga-a10-ocram-ecc";
                                 reg = <0xff8c3000 0x400>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
+                                             <33 IRQ_TYPE_LEVEL_HIGH>;
                         };
 
                         emac0-rx-ecc@ff8c0800 {
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index 567df98f1bb5..8e3a4adc389f 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -20,9 +20,14 @@
         model = "Altera SOCFPGA Arria 10";
         compatible = "altr,socfpga-arria10", "altr,socfpga";
 
+        aliases {
+                ethernet0 = &gmac0;
+                serial0 = &uart1;
+        };
+
         chosen {
                 bootargs = "earlyprintk";
-                stdout-path = "serial1:115200n8";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index 6ae56838bd3a..d309314f3a36 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -604,6 +604,7 @@
                                 #interrupt-cells = <2>;
 
                                 ab8500_gpio: ab8500-gpio {
+                                        compatible = "stericsson,ab8500-gpio";
                                         gpio-controller;
                                         #gpio-cells = <2>;
                                 };
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index fc5e8ce700c3..3c9f2f068c2f 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -99,46 +99,69 @@
                                 vddio-supply = <&db8500_vsmps2_reg>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&accel_tvk_mode>;
-                                interrupt-parent = <&gpio2>;
-                                interrupts = <18 IRQ_TYPE_EDGE_FALLING>,
-                                             <19 IRQ_TYPE_EDGE_FALLING>;
-                        };
-                        lsm303dlh@1e {
                                 /*
-                                 * This magnetometer is packaged with
-                                 * the accelerometer, and has a DRDY line,
-                                 * however it is not connected on this
-                                 * board so it can not generate interrupts.
+                                 * These interrupts cannot be used: the other component
+                                 * ST-Micro L3D4200D gyro that is connected to the same lines
+                                 * cannot set its DRDY line to open drain, so it cannot be
+                                 * shared with other peripherals. The should be defined for
+                                 * the falling edge if they could be wired together.
+                                 *
+                                 * interrupts-extended =
+                                 * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+                                 * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
                                  */
+                        };
+                        lsm303dlh@1e {
+                                /* Magnetometer */
                                 compatible = "st,lsm303dlh-magn";
                                 reg = <0x1e>;
                                 vdd-supply = <&ab8500_ldo_aux1_reg>;
                                 vddio-supply = <&db8500_vsmps2_reg>;
+                                /*
+                                 * These interrupts cannot be used: the other component
+                                 * ST-Micro L3D4200D gyro that is connected to the same lines
+                                 * cannot set its DRDY line to open drain, so it cannot be
+                                 * shared with other peripherals. The should be defined for
+                                 * the falling edge if they could be wired together.
+                                 *
+                                 * interrupts-extended =
+                                 * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+                                 * <&gpio2 19 IRQ_TYPE_EDGE_FALLING>;
+                                 */
                         };
                         lis331dl@1c {
                                 /* Accelerometer */
                                 compatible = "st,lis331dl-accel";
                                 st,drdy-int-pin = <1>;
-                                drive-open-drain;
                                 reg = <0x1c>;
                                 vdd-supply = <&ab8500_ldo_aux1_reg>;
                                 vddio-supply = <&db8500_vsmps2_reg>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&accel_tvk_mode>;
                                 interrupt-parent = <&gpio2>;
-                                interrupts = <18 IRQ_TYPE_EDGE_FALLING>,
-                                             <19 IRQ_TYPE_EDGE_FALLING>;
+                                /* INT2 would need to be open drain */
+                                interrupts = <18 IRQ_TYPE_EDGE_RISING>,
+                                             <19 IRQ_TYPE_EDGE_RISING>;
                         };
                         ak8974@0f {
                                 /* Magnetometer */
                                 compatible = "asahi-kasei,ak8974";
                                 reg = <0x0f>;
-                                vdd-supply = <&ab8500_ldo_aux1_reg>;
-                                vddio-supply = <&db8500_vsmps2_reg>;
+                                avdd-supply = <&ab8500_ldo_aux1_reg>;
+                                dvdd-supply = <&db8500_vsmps2_reg>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&gyro_magn_tvk_mode>;
-                                interrupt-parent = <&gpio1>;
-                                interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                                /*
+                                 * These interrupts cannot be used: the other component
+                                 * ST-Micro L3D4200D gyro that is connected to the same lines
+                                 * cannot set its DRDY line to open drain, so it cannot be
+                                 * shared with other peripherals. The should be defined for
+                                 * the falling edge if they could be wired together.
+                                 *
+                                 * interrupts-extended =
+                                 * <&gpio1 0 IRQ_TYPE_EDGE_FALLING>,
+                                 * <&gpio0 31 IRQ_TYPE_EDGE_FALLING>;
+                                 */
                         };
                         l3g4200d@68 {
                                 /* Gyroscope */
@@ -149,8 +172,9 @@
                                 vddio-supply = <&db8500_vsmps2_reg>;
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&gyro_magn_tvk_mode>;
-                                interrupt-parent = <&gpio1>;
-                                interrupts = <0 IRQ_TYPE_EDGE_RISING>;
+                                interrupts-extended =
+                                <&gpio1 0 IRQ_TYPE_EDGE_RISING>,
+                                <&gpio0 31 IRQ_TYPE_EDGE_RISING>;
                         };
                         lsp001wm@5c {
                                 /* Barometer/pressure sensor */
@@ -218,7 +242,7 @@
                                         /* Accelerometer interrupt lines 1 & 2 */
                                         tvk_cfg {
                                                 pins = "GPIO82_C1", "GPIO83_D3";
-                                                ste,config = <&gpio_in_pu>;
+                                                ste,config = <&gpio_in_pd>;
                                         };
                                 };
                         };
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 6d8ce154347e..48dc38482633 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -223,7 +223,6 @@
                 prcmu@80157000 {
                         ab8500 {
                                 ab8500-gpio {
-                                        compatible = "stericsson,ab8500-gpio";
                                 };
 
                                 ab8500-regulators {
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index 45d7af326718..7187676836be 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -18,6 +18,126 @@
         compatible = "st-ericsson,hrefv60+", "st-ericsson,u8500";
 
         soc {
+                /* Name the GPIO muxed rails on the HREF boards */
+                gpio@8012e000 {
+                        /* GPIOs 0 - 31 */
+                        gpio-line-names =
+                                     /* GPIO0,1 used for UART0 BT RX/TX */
+                                     "", "",
+                                     "UART_WAKE",
+                                     "BT_WAKE",
+                                     "",
+                                     "SDMMC_1V8_3V_SEL",
+                                     "FLASH_LED_SYNC (FLASH_CTRL_0)",
+                                     "XENON_READY (FLASH_CTRL_1)",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "",
+                                     "",
+                                     "FLASH_LED_EN (FLASH_CTRL_3)",
+                                     "", "",
+                                     "", "", "", "", "",
+                                     /* Used by UART2 (console) */
+                                     "", "",
+                                     "MAGNETOMETER_INT";
+                };
+
+                gpio@8012e080 {
+                        /* GPIOs 32 - 63 */
+                        gpio-line-names =
+                                     "MAGNETOMETER_DRDY",
+                                     "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8000e000 {
+                        /* GPIOs 64 - 95 */
+                        gpio-line-names = "XENON_EN2 (FLASH_CTRL_4)",
+                                     "DISP1_RST",
+                                     "DISP2_RST",
+                                     "TOUCH_INT2",
+                                     "LCD_VSI0_A",
+                                     "LCD_VSI1_A",
+                                     /* GPIO 70-77 used for ETM */
+                                     "", "", "", "", "", "", "", "",
+                                     /* GPIO 78-81 used for YCBCR */
+                                     "", "", "", "",
+                                     "ACCELEROMETER_INT1_RDY",
+                                     "ACCELEROMETER_INT2",
+                                     "TOUCH_INT",
+                                     "WLAN_ENA",
+                                     "", "", "", "", "",
+                                     "FORCE_SENSING_INT",
+                                     "FORCE_SENSING_RESET",
+                                     "", "",
+                                     "SDMMC_CD";
+                };
+
+                gpio@8000e080 {
+                        /* GPIOs 96 - 127 */
+                        gpio-line-names = "",
+                                     "FORCE_SENSING_WU",
+                                     "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8000e100 {
+                        /* GPIOs 128 - 159 */
+                        gpio-line-names = "", "", "", "", "", "", "", "",
+                                     "", "", "",
+                                     "DIPRO_INT", /* GPIO139 */
+                                     "XSHUTDOWN_SECONDARY_SENSOR",
+                                     "XSHUTDOWN_PRIMARY_SENSOR",
+                                     "NFC_RST (NFC_CTRL_",
+                                     "TOUCH_RST",
+                                     "NFC_IRQ (NFC_CTRL_1)",
+                                     "HAL_SW",
+                                     "TOUCH_RST2",
+                                     "", "",
+                                     "VAUDIO_HF_EN", /* GPIO149 */
+                                     "", "", "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8000e180 {
+                        /* GPIOs 160 - 191 */
+                        gpio-line-names = "", "", "", "", "", "", "", "",
+                                     "",
+                                     "SDMMC_EN",
+                                     "XENON_CHARGE (FLASH_CONTROL_5)",
+                                     "GBF_ENA_RESET",
+                                     "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8011e000 {
+                        /* GPIOs 192 - 223 */
+                        gpio-line-names = "HDTV_INTN",
+                                     "", "", "",
+                                     "HDTV_RSTN",
+                                     "", "", "",
+                                     "", /* GPIO200 */
+                                     "", "", "", "", "", "", "",
+                                     /* GPIO208-216 used for WGBF_MC1 */
+                                     "", "", "", "", "", "", "", "", "",
+                                     "SW_FRONT_PROXIMITY", /* GPIO217 */
+                                     "KPD_CTRL_INT", /* Keypad controller */
+                                     "", "", "", "", "";
+                };
+
+                gpio@8011e080 {
+                        /* GPIOs 224 - 255 */
+                        gpio-line-names = "", "",
+                                     "HSIT_ACWAKE0",
+                                     "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
                 // External Micro SD slot
                 sdi0_per1@80126000 {
                         cd-gpios  = <&gpio2 31 GPIO_ACTIVE_HIGH>; // 95
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 36e84efc401c..b3df1c60d465 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -95,6 +95,70 @@
         };
 
         soc {
+                /* Name the GPIO muxed rails on the Snowball board */
+                gpio@8012e000 {
+                        /* GPIOs 0 - 31 */
+                        gpio-line-names = "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "",
+                                     "AP_GPIO31";
+                };
+
+                gpio@8012e080 {
+                        /* GPIOs 32 - 63 */
+                        gpio-line-names = "USR PB", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8000e000 {
+                        /* GPIOs 64 - 95 */
+                        gpio-line-names = "", "", "", "", "AP_GPIO68", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8000e100 {
+                        /* GPIOs 128 - 159 */
+                        gpio-line-names = "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "IRQ_LAN", "RSTn_LAN",
+                                     "USR_LED", "", "", "", "", "", "",
+                                     "", "", "AP_GPIO151", "AP_GPIO152",
+                                     "", "", "", "", "", "", "";
+                };
+
+                gpio@8000e180 {
+                        /* GPIOs 160 - 191 */
+                        gpio-line-names = "", "AP_GPIO161", "AP_GPIO162",
+                                     "ACCELEROMETER_INT1_RDY",
+                                     "ACCELEROMETER_INT2", "MAG_DRDY",
+                                     "GYRO_DRDY", "RSTn_MLC", "RSTn_SLC",
+                                     "GYRO_INT", "UART_WAKE", "GBF_RESET",
+                                     "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
+                gpio@8011e000 {
+                        /* GPIOs 192 - 223 */
+                        gpio-line-names = "HDTV_INTn", "", "", "", "HDTV_RST",
+                                     "", "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "", "",
+                                     "WLAN_RESETN", "WLAN_IRQ", "MMC_EN",
+                                     "MMC_CD", "", "", "", "", "";
+                };
+
+                gpio@8011e080 {
+                        /* GPIOs 224 - 255 */
+                        gpio-line-names = "", "", "", "", "SD_SEL", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "",
+                                     "", "", "", "", "", "", "", "";
+                };
+
                 usb_per5@a03e0000 {
                         pinctrl-names = "default", "sleep";
                         pinctrl-0 = <&musb_default_mode>;
@@ -352,7 +416,25 @@
 
                         ab8500 {
                                 ab8500-gpio {
-                                        compatible = "stericsson,ab8500-gpio";
+                                        /*
+                                         * AB8500 GPIOs are numbered starting from 1, so the first
+                                         * index 0 is what in the datasheet is called "GPIO1", and
+                                         * the second is "GPIO2" and so forth. Confusingly, the
+                                         * Snowball schematic then names the "GPIO2" line "PM_GPIO1".
+                                         * while later naming "GPIO4" as "PM_GPIO4".
+                                         */
+                                        gpio-line-names = "", /* AB8500 GPIO1 */
+                                                     "PM_GPIO1", /* AB8500 GPIO2 */
+                                                     "WLAN_CLK_REQ", /* AB8500 GPIO3 */
+                                                     "PM_GPIO4", /* AB8500 GPIO4 */
+                                                     "", "", "", "", "", "", "", "", "", "", "",
+                                                     "EN_3V6", /* AB8500 GPIO16 */
+                                                     "", "", "", "" ,"", "", "", "", "",
+                                                     "EN_3V3", /* AB8500 GPIO26 */
+                                                     "", "", "", "", "", "", "", "", "", "", "", "", "",
+                                                     "PM_GPIO40", /* AB8500 GPIO40 */
+                                                     "PM_GPIO41", /* AB8500 GPIO41 */
+                                                     "PM_GPIO42"; /* AB8500 GPIO42 */
                                 };
 
                                 ext_regulators: ab8500-ext-regulators {
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
index d1f2acafc9b6..fd5049682181 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -103,6 +103,7 @@
                                 clocks = <&clk_sysin>;
 
                                 clock-output-names = "clk-s-a0-pll-ofd-0";
+                                clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
                         };
 
                         clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -115,6 +116,7 @@
 
                                 clock-output-names = "clk-ic-lmi0",
                                                      "clk-ic-lmi1";
+                                clock-critical = <CLK_IC_LMI0>;
                         };
                 };
 
@@ -129,6 +131,7 @@
                                              "clk-s-c0-fs0-ch1",
                                              "clk-s-c0-fs0-ch2",
                                              "clk-s-c0-fs0-ch3";
+                        clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
                 };
 
                 clk_s_c0: clockgen-c@09103000 {
@@ -142,6 +145,7 @@
                                 clocks = <&clk_sysin>;
 
                                 clock-output-names = "clk-s-c0-pll0-odf-0";
+                                clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
                         };
 
                         clk_s_c0_pll1: clk-s-c0-pll1 {
@@ -204,6 +208,11 @@
                                                      "clk-clust-hades",
                                                      "clk-hwpe-hades",
                                                      "clk-fc-hades";
+                                clock-critical = <CLK_ICN_CPU>,
+                                                 <CLK_TX_ICN_DMU>,
+                                                 <CLK_EXT2F_A9>,
+                                                 <CLK_ICN_LMI>,
+                                                 <CLK_ICN_SBC>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index c92a1ae33a1e..39e368ec3428 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -72,8 +72,9 @@
                 };
 
                 blue {
-                        label = "a1000:blue:usr";
+                        label = "a1000:blue:pwr";
                         gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
                 };
         };
 
@@ -84,6 +85,7 @@
                 regulator-name = "emac-3v3";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
+                startup-delay-us = <20000>;
                 enable-active-high;
                 gpio = <&pio 7 15 GPIO_ACTIVE_HIGH>;
         };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 2b17c5199151..6de83a6187d0 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -66,6 +66,7 @@
                 regulator-name = "emac-3v3";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
+                startup-delay-us = <20000>;
                 enable-active-high;
                 gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>;
         };
diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
index 7afc7a64eef1..e28f080b1fd5 100644
--- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
+++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
@@ -80,6 +80,7 @@
                 regulator-name = "emac-3v3";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
+                startup-delay-us = <20000>;
                 enable-active-high;
                 gpio = <&pio 7 19 GPIO_ACTIVE_HIGH>;   /* PH19 */
         };
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index ca58eb279d55..7e7dfc2b43db 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -65,9 +65,9 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0-hdmi";
-                        clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-                                 <&ahb_gates 43>, <&ahb_gates 44>,
-                                 <&dram_gates 26>;
+                        clocks = <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>, <&de_be0_clk>,
+                                 <&tcon0_ch1_clk>, <&dram_gates 26>;
                         status = "disabled";
                 };
 
@@ -75,9 +75,9 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
-                        clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-                                 <&ahb_gates 43>, <&ahb_gates 44>,
-                                 <&ahb_gates 46>,
+                        clocks = <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>, <&ahb_gates 46>,
+                                 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch1_clk>,
                                  <&dram_gates 25>, <&dram_gates 26>;
                         status = "disabled";
                 };
@@ -86,8 +86,8 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
-                        clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-                                 <&ahb_gates 44>, <&ahb_gates 46>,
+                        clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&ahb_gates 46>,
+                                 <&de_be0_clk>, <&de_fe0_clk>, <&tcon0_ch0_clk>,
                                  <&dram_gates 25>, <&dram_gates 26>;
                         status = "disabled";
                 };
@@ -96,10 +96,11 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
-                        clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
-                                 <&ahb_gates 36>, <&ahb_gates 44>,
-                                 <&ahb_gates 46>,
-                                 <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
+                        clocks = <&ahb_gates 34>, <&ahb_gates 36>,
+                                 <&ahb_gates 44>, <&ahb_gates 46>,
+                                 <&de_be0_clk>, <&de_fe0_clk>,
+                                 <&tcon0_ch1_clk>, <&dram_gates 5>,
+                                 <&dram_gates 25>, <&dram_gates 26>;
                         status = "disabled";
                 };
         };
@@ -577,6 +578,81 @@
                                              "dram_de_mp", "dram_ace";
                 };
 
+                de_be0_clk: clk@01c20104 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20104 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-be0";
+                };
+
+                de_be1_clk: clk@01c20108 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20108 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-be1";
+                };
+
+                de_fe0_clk: clk@01c2010c {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c2010c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-fe0";
+                };
+
+                de_fe1_clk: clk@01c20110 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20110 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-fe1";
+                };
+
+
+                tcon0_ch0_clk: clk@01c20118 {
+                        #clock-cells = <0>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+                        reg = <0x01c20118 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon0-ch0-sclk";
+
+                };
+
+                tcon1_ch0_clk: clk@01c2011c {
+                        #clock-cells = <0>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+                        reg = <0x01c2011c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon1-ch0-sclk";
+
+                };
+
+                tcon0_ch1_clk: clk@01c2012c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+                        reg = <0x01c2012c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon0-ch1-sclk";
+
+                };
+
+                tcon1_ch1_clk: clk@01c20130 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+                        reg = <0x01c20130 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon1-ch1-sclk";
+
+                };
+
                 ve_clk: clk@01c2013c {
                         #clock-cells = <0>;
                         #reset-cells = <0>;
@@ -645,6 +721,19 @@
                         #dma-cells = <2>;
                 };
 
+                nfc: nand@01c03000 {
+                        compatible = "allwinner,sun4i-a10-nand";
+                        reg = <0x01c03000 0x1000>;
+                        interrupts = <37>;
+                        clocks = <&ahb_gates 13>, <&nand_clk>;
+                        clock-names = "ahb", "mod";
+                        dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+                        dma-names = "rxtx";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
@@ -884,69 +973,62 @@
                         #interrupt-cells = <3>;
                         #gpio-cells = <3>;
 
-                        pwm0_pins_a: pwm0@0 {
-                                allwinner,pins = "PB2";
-                                allwinner,function = "pwm";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-                        };
-
-                        pwm1_pins_a: pwm1@0 {
-                                allwinner,pins = "PI3";
-                                allwinner,function = "pwm";
+                        emac_pins_a: emac0@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "emac";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart0_pins_a: uart0@0 {
-                                allwinner,pins = "PB22", "PB23";
-                                allwinner,function = "uart0";
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart0_pins_b: uart0@1 {
-                                allwinner,pins = "PF2", "PF4";
-                                allwinner,function = "uart0";
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB18", "PB19";
+                                allwinner,function = "i2c1";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart1_pins_a: uart1@0 {
-                                allwinner,pins = "PA10", "PA11";
-                                allwinner,function = "uart1";
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB20", "PB21";
+                                allwinner,function = "i2c2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c0_pins_a: i2c0@0 {
-                                allwinner,pins = "PB0", "PB1";
-                                allwinner,function = "i2c0";
+                        ir0_rx_pins_a: ir0@0 {
+                                allwinner,pins = "PB4";
+                                allwinner,function = "ir0";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c1_pins_a: i2c1@0 {
-                                allwinner,pins = "PB18", "PB19";
-                                allwinner,function = "i2c1";
+                        ir0_tx_pins_a: ir0@1 {
+                                allwinner,pins = "PB3";
+                                allwinner,function = "ir0";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c2_pins_a: i2c2@0 {
-                                allwinner,pins = "PB20", "PB21";
-                                allwinner,function = "i2c2";
+                        ir1_rx_pins_a: ir1@0 {
+                                allwinner,pins = "PB23";
+                                allwinner,function = "ir1";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        emac_pins_a: emac0@0 {
-                                allwinner,pins = "PA0", "PA1", "PA2",
-                                                "PA3", "PA4", "PA5", "PA6",
-                                                "PA7", "PA8", "PA9", "PA10",
-                                                "PA11", "PA12", "PA13", "PA14",
-                                                "PA15", "PA16";
-                                allwinner,function = "emac";
+                        ir1_tx_pins_a: ir1@1 {
+                                allwinner,pins = "PB22";
+                                allwinner,function = "ir1";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
@@ -966,34 +1048,41 @@
                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
                         };
 
-                        ir0_rx_pins_a: ir0@0 {
-                                allwinner,pins = "PB4";
-                                allwinner,function = "ir0";
+                        ps20_pins_a: ps20@0 {
+                                allwinner,pins = "PI20", "PI21";
+                                allwinner,function = "ps2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir0_tx_pins_a: ir0@1 {
-                                allwinner,pins = "PB3";
-                                allwinner,function = "ir0";
+                        ps21_pins_a: ps21@0 {
+                                allwinner,pins = "PH12", "PH13";
+                                allwinner,function = "ps2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir1_rx_pins_a: ir1@0 {
-                                allwinner,pins = "PB23";
-                                allwinner,function = "ir1";
+                        pwm0_pins_a: pwm0@0 {
+                                allwinner,pins = "PB2";
+                                allwinner,function = "pwm";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir1_tx_pins_a: ir1@1 {
-                                allwinner,pins = "PB22";
-                                allwinner,function = "ir1";
+                        pwm1_pins_a: pwm1@0 {
+                                allwinner,pins = "PI3";
+                                allwinner,function = "pwm";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
+                        spdif_tx_pins_a: spdif@0 {
+                                allwinner,pins = "PB13";
+                                allwinner,function = "spdif";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+                        };
+
                         spi0_pins_a: spi0@0 {
                                 allwinner,pins = "PI11", "PI12", "PI13";
                                 allwinner,function = "spi0";
@@ -1050,25 +1139,25 @@
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ps20_pins_a: ps20@0 {
-                                allwinner,pins = "PI20", "PI21";
-                                allwinner,function = "ps2";
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB22", "PB23";
+                                allwinner,function = "uart0";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ps21_pins_a: ps21@0 {
-                                allwinner,pins = "PH12", "PH13";
-                                allwinner,function = "ps2";
+                        uart0_pins_b: uart0@1 {
+                                allwinner,pins = "PF2", "PF4";
+                                allwinner,function = "uart0";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        spdif_tx_pins_a: spdif@0 {
-                                allwinner,pins = "PB13";
-                                allwinner,function = "spdif";
+                        uart1_pins_a: uart1@0 {
+                                allwinner,pins = "PA10", "PA11";
+                                allwinner,function = "uart1";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
                 };
 
diff --git a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
index a790ec8adb75..2150e15e115a 100644
--- a/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-auxtek-t004.dts
@@ -124,7 +124,18 @@
         status = "okay";
 };
 
+&otg_sram {
+        status = "okay";
+};
+
 &pio {
+        usb0_id_detect_pin: usb0_id_detect_pin@0 {
+                allwinner,pins = "PG12";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+
         mmc0_cd_pin_t004: mmc0_cd_pin@0 {
                 allwinner,pins = "PG1";
                 allwinner,function = "gpio_in";
@@ -158,11 +169,19 @@
         status = "okay";
 };
 
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
 &usb1_vbus_pin_a {
         allwinner,pins = "PG13";
 };
 
 &usbphy {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_id_detect_pin>;
+        usb0_id_det-gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
         usb1_vbus-supply = <&reg_usb1_vbus>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s-mk802.dts b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
index 46ff9407826d..c84ac005342e 100644
--- a/arch/arm/boot/dts/sun5i-a10s-mk802.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-mk802.dts
@@ -73,6 +73,20 @@
         status = "okay";
 };
 
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins_a>;
+        status = "okay";
+
+        axp152: pmic@30 {
+                compatible = "x-powers,axp152";
+                reg = <0x30>;
+                interrupts = <0>;
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+};
+
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mk802>;
@@ -83,10 +97,23 @@
         status = "okay";
 };
 
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+};
+
 &ohci0 {
         status = "okay";
 };
 
+&otg_sram {
+        status = "okay";
+};
+
 &pio {
         led_pins_mk802: led_pins@0 {
                 allwinner,pins = "PB2";
@@ -122,6 +149,11 @@
         status = "okay";
 };
 
+&usb_otg {
+        dr_mode = "peripheral";
+        status = "okay";
+};
+
 &usbphy {
         usb1_vbus-supply = <&reg_usb1_vbus>;
         status = "okay";
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 86d046a502e6..aef91476f9ae 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -248,6 +248,13 @@
         status = "okay";
 };
 
+&spi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&spi2_pins_a>,
+                    <&spi2_cs0_pins_a>;
+        status = "okay";
+};
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
index 9fea918f949e..b5de75f4c710 100644
--- a/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-wobo-i5.dts
@@ -79,6 +79,7 @@
                 regulator-name = "emac-3v3";
                 regulator-min-microvolt = <3300000>;
                 regulator-max-microvolt = <3300000>;
+                startup-delay-us = <20000>;
                 enable-active-high;
                 gpio = <&pio 0 2 GPIO_ACTIVE_HIGH>;
         };
@@ -195,7 +196,14 @@
         regulator-always-on;
         regulator-min-microvolt = <3300000>;
         regulator-max-microvolt = <3300000>;
-        regulator-name = "vcc-wifi";
+        regulator-name = "vcc-wifi1";
+};
+
+&reg_ldo4 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi2";
 };
 
 &reg_usb1_vbus {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 367f33012493..c41a2ba34dde 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -242,6 +242,20 @@
                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
         };
+
+        spi2_pins_a: spi2@0 {
+                allwinner,pins = "PB12", "PB13", "PB14";
+                allwinner,function = "spi2";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        spi2_cs0_pins_a: spi2_cs0@0 {
+                allwinner,pins = "PB11";
+                allwinner,function = "spi2";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
 };
 
 &sram_a {
diff --git a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts
index 6546fa02901d..894c4c4f9a1f 100644
--- a/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts
+++ b/arch/arm/boot/dts/sun5i-a13-difrnce-dit4350.dts
@@ -42,185 +42,9 @@
 
 /dts-v1/;
 #include "sun5i-a13.dtsi"
-#include "sunxi-common-regulators.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/pwm/pwm.h>
+#include "sun5i-reference-design-tablet.dtsi"
 
 / {
         model = "Difrnce DIT4350";
         compatible = "difrnce,dit4350", "allwinner,sun5i-a13";
-
-        aliases {
-                serial0 = &uart1;
-        };
-
-        backlight: backlight {
-                compatible = "pwm-backlight";
-                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
-                default-brightness-level = <8>;
-                /* TODO: backlight uses axp gpio1 as enable pin */
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-};
-
-&cpu0 {
-        cpu-supply = <&reg_dcdc2>;
-};
-
-&ehci0 {
-        status = "okay";
-};
-
-&i2c0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c0_pins_a>;
-        status = "okay";
-
-        axp209: pmic@34 {
-                reg = <0x34>;
-                interrupts = <0>;
-        };
-};
-
-#include "axp209.dtsi"
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins_a>;
-        status = "okay";
-
-        pcf8563: rtc@51 {
-                compatible = "nxp,pcf8563";
-                reg = <0x51>;
-        };
-};
-
-&lradc {
-        vref-supply = <&reg_ldo2>;
-        status = "okay";
-
-        button@200 {
-                label = "Volume Up";
-                linux,code = <KEY_VOLUMEUP>;
-                channel = <0>;
-                voltage = <200000>;
-        };
-
-        button@400 {
-                label = "Volume Down";
-                linux,code = <KEY_VOLUMEDOWN>;
-                channel = <0>;
-                voltage = <400000>;
-        };
-};
-
-&mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_d709>;
-        vmmc-supply = <&reg_vcc3v3>;
-        bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
-        status = "okay";
-};
-
-&otg_sram {
-        status = "okay";
-};
-
-&pio {
-        mmc0_cd_pin_d709: mmc0_cd_pin@0 {
-                allwinner,pins = "PG0";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-
-        usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
-                allwinner,pins = "PG1";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
-        };
-
-        usb0_id_detect_pin: usb0_id_detect_pin@0 {
-                allwinner,pins = "PG2";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-};
-
-&pwm {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pwm0_pins>;
-        status = "okay";
-};
-
-&reg_dcdc2 {
-        regulator-always-on;
-        regulator-min-microvolt = <1000000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-cpu";
-};
-
-&reg_dcdc3 {
-        regulator-always-on;
-        regulator-min-microvolt = <1250000>;
-        regulator-max-microvolt = <1250000>;
-        regulator-name = "vdd-int-pll";
-};
-
-&reg_ldo1 {
-        regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-        regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "avcc";
-};
-
-&reg_ldo3 {
-        regulator-min-microvolt = <3300000>;
-        regulator-max-microvolt = <3300000>;
-        regulator-name = "vcc-wifi";
-};
-
-&reg_usb0_vbus {
-        gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
-        status = "okay";
-};
-
-&uart1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&uart1_pins_b>;
-        status = "okay";
-};
-
-&usb_otg {
-        dr_mode = "otg";
-        status = "okay";
-};
-
-&usb0_vbus_pin_a {
-        allwinner,pins = "PG12";
-};
-
-&usbphy {
-        pinctrl-names = "default";
-        pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-        usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-        usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        usb0_vbus-supply = <&reg_usb0_vbus>;
-        usb1_vbus-supply = <&reg_ldo3>;
-        status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
index 72e93acb5a9e..a89f29fa3e40 100644
--- a/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun5i-a13-q8-tablet.dts
@@ -42,19 +42,45 @@
 
 /dts-v1/;
 #include "sun5i-a13.dtsi"
-#include "sun5i-q8-common.dtsi"
+#include "sun5i-reference-design-tablet.dtsi"
 
 / {
         model = "Q8 A13 Tablet";
         compatible = "allwinner,q8-a13", "allwinner,sun5i-a13";
+
+        panel: panel {
+                compatible = "urt,umsh-8596md-t", "simple-panel";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                port@0 {
+                        reg = <0>;
+                        /* TODO: lcd panel uses axp gpio0 as enable pin */
+                        backlight = <&backlight>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        panel_input: endpoint@0 {
+                                reg = <0>;
+                                remote-endpoint = <&tcon0_out_lcd>;
+                        };
+                };
+        };
+};
+
+&be0 {
+        status = "okay";
 };
 
-&reg_ldo3 {
-        regulator-min-microvolt = <3300000>;
-        regulator-max-microvolt = <3300000>;
-        regulator-name = "vcc-wifi";
+&tcon0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&lcd_rgb666_pins>;
+        status = "okay";
 };
 
-&usbphy {
-        usb1_vbus-supply = <&reg_ldo3>;
+&tcon0_out {
+        tcon0_out_lcd: endpoint@0 {
+                reg = <0>;
+                remote-endpoint = <&panel_input>;
+        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
index fa9ddfdcfe96..a8b0bcc04514 100644
--- a/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
+++ b/arch/arm/boot/dts/sun5i-a13-utoo-p66.dts
@@ -42,24 +42,20 @@
 
 /dts-v1/;
 #include "sun5i-a13.dtsi"
-#include "sunxi-common-regulators.dtsi"
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
+#include "sun5i-reference-design-tablet.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/pwm/pwm.h>
 
 / {
         model = "Utoo P66";
         compatible = "utoo,p66", "allwinner,sun5i-a13";
 
-        backlight: backlight {
-                compatible = "pwm-backlight";
-                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
-                /* Note levels of 10 / 20% result in backlight off */
-                brightness-levels = <0 30 40 50 60 70 80 90 100>;
-                default-brightness-level = <6>;
-                /* TODO: backlight uses axp gpio1 as enable pin */
+        /* The P66 uses the uart pins as gpios */
+        aliases {
+                /delete-property/serial0;
+        };
+
+        chosen {
+                /delete-property/stdout-path;
         };
 
         i2c_lcd: i2c@0 {
@@ -73,39 +69,21 @@
         };
 };
 
-&codec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&codec_pa_pin>;
-        allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */
-        status = "okay";
-};
-
-&cpu0 {
-        cpu-supply = <&reg_dcdc2>;
+&backlight {
+        /* Note levels of 10 / 20% result in backlight off */
+        brightness-levels = <0 30 40 50 60 70 80 90 100>;
+        default-brightness-level = <6>;
 };
 
-&ehci0 {
-        status = "okay";
+&codec {
+        allwinner,pa-gpios = <&pio 6 3 GPIO_ACTIVE_HIGH>; /* PG3 */
 };
 
-&i2c0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c0_pins_a>;
-        status = "okay";
-
-        axp209: pmic@34 {
-                reg = <0x34>;
-                interrupts = <0>;
-        };
+&codec_pa_pin {
+        allwinner,pins = "PG3";
 };
 
-#include "axp209.dtsi"
-
 &i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins_a>;
-        status = "okay";
-
         icn8318: touchscreen@40 {
                 compatible = "chipone,icn8318";
                 reg = <0x40>;
@@ -119,40 +97,6 @@
                 touchscreen-inverted-x;
                 touchscreen-swapped-x-y;
         };
-
-        pcf8563: rtc@51 {
-                compatible = "nxp,pcf8563";
-                reg = <0x51>;
-        };
-};
-
-&lradc {
-        vref-supply = <&reg_ldo2>;
-        status = "okay";
-
-        button@200 {
-                label = "Volume Up";
-                linux,code = <KEY_VOLUMEUP>;
-                channel = <0>;
-                voltage = <200000>;
-        };
-
-        button@400 {
-                label = "Volume Down";
-                linux,code = <KEY_VOLUMEDOWN>;
-                channel = <0>;
-                voltage = <400000>;
-        };
-};
-
-&mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_p66>;
-        vmmc-supply = <&reg_vcc3v3>;
-        bus-width = <4>;
-        cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
-        cd-inverted;
-        status = "okay";
 };
 
 &mmc2 {
@@ -170,39 +114,7 @@
         };
 };
 
-&otg_sram {
-        status = "okay";
-};
-
 &pio {
-        codec_pa_pin: codec_pa_pin@0 {
-                allwinner,pins = "PG3";
-                allwinner,function = "gpio_out";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-        };
-
-        mmc0_cd_pin_p66: mmc0_cd_pin@0 {
-                allwinner,pins = "PG0";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-
-        usb0_vbus_detect_pin: usb0_vbus_detect_pin@0 {
-                allwinner,pins = "PG1";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_DOWN>;
-        };
-
-        usb0_id_detect_pin: usb0_id_detect_pin@0 {
-                allwinner,pins = "PG2";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-
         i2c_lcd_pins: i2c_lcd_pin@0 {
                 allwinner,pins = "PG10", "PG12";
                 allwinner,function = "gpio_out";
@@ -217,67 +129,17 @@
                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
         };
 
-        usb0_vbus_pin_a: usb0_vbus_pin@0 {
-                allwinner,pins = "PB4";
-                allwinner,function = "gpio_out";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-        };
-};
-
-&pwm {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pwm0_pins>;
-        status = "okay";
-};
-
-&reg_dcdc2 {
-        regulator-always-on;
-        regulator-min-microvolt = <1000000>;
-        regulator-max-microvolt = <1500000>;
-        regulator-name = "vdd-cpu";
-};
-
-&reg_dcdc3 {
-        regulator-always-on;
-        regulator-min-microvolt = <1000000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-int-pll";
-};
-
-&reg_ldo1 {
-        regulator-name = "vdd-rtc";
-};
-
-&reg_ldo2 {
-        regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "avcc";
-};
-
-&reg_ldo3 {
-        regulator-min-microvolt = <3300000>;
-        regulator-max-microvolt = <3300000>;
-        regulator-name = "vcc-wifi";
 };
 
 &reg_usb0_vbus {
         gpio = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        status = "okay";
 };
 
-&usb_otg {
-        dr_mode = "otg";
-        status = "okay";
+&uart1 {
+        /* The P66 uses the uart pins as gpios */
+        status = "disabled";
 };
 
-&usbphy {
-        pinctrl-names = "default";
-        pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
-        usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
-        usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
-        usb0_vbus-supply = <&reg_usb0_vbus>;
-        usb1_vbus-supply = <&reg_ldo3>;
-        status = "okay";
+&usb0_vbus_pin_a {
+        allwinner,pins = "PB4";
 };
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 263d46dbc7e6..e012890e0cf2 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -207,7 +207,50 @@
                 };
         };
 
+        display-engine {
+                compatible = "allwinner,sun5i-a13-display-engine";
+                allwinner,pipelines = <&fe0>;
+        };
+
         soc@01c00000 {
+                tcon0: lcd-controller@01c0c000 {
+                        compatible = "allwinner,sun5i-a13-tcon";
+                        reg = <0x01c0c000 0x1000>;
+                        interrupts = <44>;
+                        resets = <&tcon_ch0_clk 1>;
+                        reset-names = "lcd";
+                        clocks = <&ahb_gates 36>,
+                                 <&tcon_ch0_clk>,
+                                 <&tcon_ch1_clk>;
+                        clock-names = "ahb",
+                                      "tcon-ch0",
+                                      "tcon-ch1";
+                        clock-output-names = "tcon-pixel-clock";
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                tcon0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        tcon0_in_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_out_tcon0>;
+                                        };
+                                };
+
+                                tcon0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+                                };
+                        };
+                };
+
                 pwm: pwm@01c20e00 {
                         compatible = "allwinner,sun5i-a13-pwm";
                         reg = <0x01c20e00 0xc>;
@@ -215,6 +258,75 @@
                         #pwm-cells = <3>;
                         status = "disabled";
                 };
+
+                fe0: display-frontend@01e00000 {
+                        compatible = "allwinner,sun5i-a13-display-frontend";
+                        reg = <0x01e00000 0x20000>;
+                        interrupts = <47>;
+                        clocks = <&ahb_gates 46>, <&de_fe_clk>,
+                                 <&dram_gates 25>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_fe_clk>;
+                        status = "disabled";
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                fe0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        fe0_out_be0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&be0_in_fe0>;
+                                        };
+                                };
+                        };
+                };
+
+                be0: display-backend@01e60000 {
+                        compatible = "allwinner,sun5i-a13-display-backend";
+                        reg = <0x01e60000 0x10000>;
+                        clocks = <&ahb_gates 44>, <&de_be_clk>,
+                                 <&dram_gates 26>;
+                        clock-names = "ahb", "mod",
+                                      "ram";
+                        resets = <&de_be_clk>;
+                        status = "disabled";
+
+                        assigned-clocks = <&de_be_clk>;
+                        assigned-clock-rates = <300000000>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                be0_in: port@0 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <0>;
+
+                                        be0_in_fe0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&fe0_out_be0>;
+                                        };
+                                };
+
+                                be0_out: port@1 {
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        reg = <1>;
+
+                                        be0_out_tcon0: endpoint@0 {
+                                                reg = <0>;
+                                                remote-endpoint = <&tcon0_in_be0>;
+                                        };
+                                };
+                        };
+                };
         };
 };
 
@@ -237,6 +349,16 @@
 &pio {
         compatible = "allwinner,sun5i-a13-pinctrl";
 
+        lcd_rgb666_pins: lcd_rgb666@0 {
+                allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
+                                 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
+                                 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
+                                 "PD24", "PD25", "PD26", "PD27";
+                allwinner,function = "lcd0";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
         uart1_pins_a: uart1@0 {
                 allwinner,pins = "PE10", "PE11";
                 allwinner,function = "uart1";
diff --git a/arch/arm/boot/dts/sun5i-r8.dtsi b/arch/arm/boot/dts/sun5i-r8.dtsi
index c04cf690b858..8b058f53b7dc 100644
--- a/arch/arm/boot/dts/sun5i-r8.dtsi
+++ b/arch/arm/boot/dts/sun5i-r8.dtsi
@@ -76,122 +76,12 @@
                                 };
                         };
                 };
-
-                tcon0: lcd-controller@01c0c000 {
-                        compatible = "allwinner,sun5i-a13-tcon";
-                        reg = <0x01c0c000 0x1000>;
-                        interrupts = <44>;
-                        resets = <&tcon_ch0_clk 1>;
-                        reset-names = "lcd";
-                        clocks = <&ahb_gates 36>,
-                                 <&tcon_ch0_clk>,
-                                 <&tcon_ch1_clk>;
-                        clock-names = "ahb",
-                                      "tcon-ch0",
-                                      "tcon-ch1";
-                        clock-output-names = "tcon-pixel-clock";
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                tcon0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        tcon0_in_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_out_tcon0>;
-                                        };
-                                };
-
-                                tcon0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        tcon0_out_tve0: endpoint@1 {
-                                                reg = <1>;
-                                                remote-endpoint = <&tve0_in_tcon0>;
-                                        };
-                                };
-                        };
-                };
-
-                fe0: display-frontend@01e00000 {
-                        compatible = "allwinner,sun5i-a13-display-frontend";
-                        reg = <0x01e00000 0x20000>;
-                        interrupts = <47>;
-                        clocks = <&ahb_gates 46>, <&de_fe_clk>,
-                                 <&dram_gates 25>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&de_fe_clk>;
-                        status = "disabled";
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                fe0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        fe0_out_be0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&be0_in_fe0>;
-                                        };
-                                };
-                        };
-                };
-
-                be0: display-backend@01e60000 {
-                        compatible = "allwinner,sun5i-a13-display-backend";
-                        reg = <0x01e60000 0x10000>;
-                        clocks = <&ahb_gates 44>, <&de_be_clk>,
-                                 <&dram_gates 26>;
-                        clock-names = "ahb", "mod",
-                                      "ram";
-                        resets = <&de_be_clk>;
-                        status = "disabled";
-
-                        assigned-clocks = <&de_be_clk>;
-                        assigned-clock-rates = <300000000>;
-
-                        ports {
-                                #address-cells = <1>;
-                                #size-cells = <0>;
-
-                                be0_in: port@0 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <0>;
-
-                                        be0_in_fe0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&fe0_out_be0>;
-                                        };
-                                };
-
-                                be0_out: port@1 {
-                                        #address-cells = <1>;
-                                        #size-cells = <0>;
-                                        reg = <1>;
-
-                                        be0_out_tcon0: endpoint@0 {
-                                                reg = <0>;
-                                                remote-endpoint = <&tcon0_in_be0>;
-                                        };
-                                };
-                        };
-                };
         };
+};
 
-        display-engine {
-                compatible = "allwinner,sun5i-a13-display-engine";
-                allwinner,pipelines = <&fe0>;
+&tcon0_out {
+        tcon0_out_tve0: endpoint@1 {
+                reg = <1>;
+                remote-endpoint = <&tve0_in_tcon0>;
         };
 };
diff --git a/arch/arm/boot/dts/sun5i-q8-common.dtsi b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
index a78e189f6653..20cc940f5f91 100644
--- a/arch/arm/boot/dts/sun5i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun5i-reference-design-tablet.dtsi
@@ -39,7 +39,7 @@
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "sunxi-q8-common.dtsi"
+#include "sunxi-reference-design-tablet.dtsi"
 
 #include <dt-bindings/pwm/pwm.h>
 
@@ -61,6 +61,13 @@
         };
 };
 
+&codec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&codec_pa_pin>;
+        allwinner,pa-gpios = <&pio 6 10 GPIO_ACTIVE_HIGH>; /* PG10 */
+        status = "okay";
+};
+
 &cpu0 {
         cpu-supply = <&reg_dcdc2>;
 };
@@ -85,9 +92,13 @@
 
 #include "axp209.dtsi"
 
+&lradc {
+        vref-supply = <&reg_ldo2>;
+};
+
 &mmc0 {
         pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
+        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
         vmmc-supply = <&reg_vcc3v0>;
         bus-width = <4>;
         cd-gpios = <&pio 6 0 GPIO_ACTIVE_HIGH>; /* PG0 */
@@ -100,7 +111,14 @@
 };
 
 &pio {
-        mmc0_cd_pin_q8: mmc0_cd_pin@0 {
+        codec_pa_pin: codec_pa_pin@0 {
+                allwinner,pins = "PG10";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        mmc0_cd_pin: mmc0_cd_pin@0 {
                 allwinner,pins = "PG0";
                 allwinner,function = "gpio_in";
                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
@@ -154,6 +172,12 @@
         regulator-name = "avcc";
 };
 
+&reg_ldo3 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi";
+};
+
 &reg_usb0_vbus {
         gpio = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
         status = "okay";
@@ -170,11 +194,17 @@
         status = "okay";
 };
 
+&usb_power_supply {
+        status = "okay";
+};
+
 &usbphy {
         pinctrl-names = "default";
         pinctrl-0 = <&usb0_id_detect_pin>, <&usb0_vbus_detect_pin>;
         usb0_id_det-gpio = <&pio 6 2 GPIO_ACTIVE_HIGH>; /* PG2 */
         usb0_vbus_det-gpio = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+        usb0_vbus_power-supply = <&usb_power_supply>;
         usb0_vbus-supply = <&reg_usb0_vbus>;
+        usb1_vbus-supply = <&reg_ldo3>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 0840612b5ed6..e374f4fc8073 100644
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -130,7 +130,7 @@
                 };
 
                 pll3x2: pll3x2_clk {
-                        compatible = "fixed-factor-clock";
+                        compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
                         #clock-cells = <0>;
                         clock-div = <1>;
                         clock-mult = <2>;
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
index 6e0e5687a09c..29016a13a2c1 100644
--- a/arch/arm/boot/dts/sun6i-a31-m9.dts
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -65,12 +65,17 @@
                 pinctrl-0 = <&led_pins_m9>;
 
                 blue {
-                        label = "m9:blue:usr";
+                        label = "m9:blue:pwr";
                         gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
                 };
         };
 };
 
+&cpu0 {
+        cpu-supply = <&reg_dcdc3>;
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -84,6 +89,7 @@
         pinctrl-0 = <&gmac_pins_mii_a>;
         phy = <&phy1>;
         phy-mode = "mii";
+        phy-supply = <&reg_dldo1>;
         status = "okay";
 
         phy1: ethernet-phy@1 {
@@ -100,13 +106,26 @@
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
-        vmmc-supply = <&reg_vcc3v3>;
+        vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
         cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
         cd-inverted;
         status = "okay";
 };
 
+&p2wi {
+        status = "okay";
+
+        axp22x: pmic@68 {
+                compatible = "x-powers,axp221";
+                reg = <0x68>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+#include "axp22x.dtsi"
+
 &pio {
         led_pins_m9: led_pins@0 {
                 allwinner,pins = "PH13";
@@ -130,6 +149,78 @@
         };
 };
 
+&reg_aldo1 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi";
+};
+
+&reg_aldo3 {
+        regulator-always-on;
+        regulator-min-microvolt = <2700000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "avcc";
+};
+
+&reg_dc5ldo {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-cpus"; /* This is an educated guess */
+};
+
+&reg_dcdc1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-gpu";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc4 {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-sys-dll";
+};
+
+&reg_dcdc5 {
+        regulator-always-on;
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1500000>;
+        regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-ethernet-phy";
+};
+
+/*
+ * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached
+ * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is
+ * marked as regulator-always-on.
+ */
+&reg_dldo4 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-usb-hub";
+};
+
 &reg_usb1_vbus {
         pinctrl-names = "default";
         pinctrl-0 = <&usb1_vbus_pin_m9>;
@@ -145,5 +236,6 @@
 
 &usbphy {
         usb1_vbus-supply = <&reg_usb1_vbus>;
+        usb2_vbus-supply = <&reg_aldo1>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
index 4dd70cce2127..5faeae429e2a 100644
--- a/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
+++ b/arch/arm/boot/dts/sun6i-a31-mele-a1000g-quad.dts
@@ -65,12 +65,17 @@
                 pinctrl-0 = <&led_pins_m9>;
 
                 blue {
-                        label = "m9:blue:usr";
+                        label = "a1000g:blue:pwr";
                         gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
                 };
         };
 };
 
+&cpu0 {
+        cpu-supply = <&reg_dcdc3>;
+};
+
 &ehci0 {
         status = "okay";
 };
@@ -84,6 +89,7 @@
         pinctrl-0 = <&gmac_pins_mii_a>;
         phy = <&phy1>;
         phy-mode = "mii";
+        phy-supply = <&reg_dldo1>;
         status = "okay";
 
         phy1: ethernet-phy@1 {
@@ -100,13 +106,26 @@
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
-        vmmc-supply = <&reg_vcc3v3>;
+        vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
         cd-gpios = <&pio 7 22 GPIO_ACTIVE_HIGH>; /* PH22 */
         cd-inverted;
         status = "okay";
 };
 
+&p2wi {
+        status = "okay";
+
+        axp22x: pmic@68 {
+                compatible = "x-powers,axp221";
+                reg = <0x68>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+
+#include "axp22x.dtsi"
+
 &pio {
         led_pins_m9: led_pins@0 {
                 allwinner,pins = "PH13";
@@ -130,6 +149,78 @@
         };
 };
 
+&reg_aldo1 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi";
+};
+
+&reg_aldo3 {
+        regulator-always-on;
+        regulator-min-microvolt = <2700000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "avcc";
+};
+
+&reg_dc5ldo {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-cpus"; /* This is an educated guess */
+};
+
+&reg_dcdc1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-3v3";
+};
+
+&reg_dcdc2 {
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-gpu";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc4 {
+        regulator-always-on;
+        regulator-min-microvolt = <700000>;
+        regulator-max-microvolt = <1320000>;
+        regulator-name = "vdd-sys-dll";
+};
+
+&reg_dcdc5 {
+        regulator-always-on;
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1500000>;
+        regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-ethernet-phy";
+};
+
+/*
+ * Both reg_usb1_vbus and reg_dldo4 need to be on for the hub attached
+ * to usb1 to work, and we can list only one usb1_vbus-supply, so dldo4 is
+ * marked as regulator-always-on.
+ */
+&reg_dldo4 {
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-usb-hub";
+};
+
 &reg_usb1_vbus {
         pinctrl-names = "default";
         pinctrl-0 = <&usb1_vbus_pin_m9>;
@@ -150,5 +241,6 @@
 
 &usbphy {
         usb1_vbus-supply = <&reg_usb1_vbus>;
+        usb2_vbus-supply = <&reg_aldo1>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
new file mode 100644
index 000000000000..ba5bca0fe997
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-bananapi-m1-plus.dts
@@ -0,0 +1,229 @@
+/*
+ * Copyright 2016 Luo Yi <luoyi.ly@gmail.com>
+ *
+ * Thanks to the original work by Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun7i-a20.dtsi"
+#include "sunxi-common-regulators.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+        model = "Banana Pi BPI-M1-Plus";
+        compatible = "sinovoip,bpi-m1-plus", "allwinner,sun7i-a20";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_bpi_m1p>;
+
+                green {
+                        label = "bananapi-m1-plus:green:usr";
+                        gpios = <&pio 7 24 GPIO_ACTIVE_HIGH>;
+                };
+
+                pwr {
+                        label = "bananapi-m1-plus:pwr:usr";
+                        gpios = <&pio 7 25 GPIO_ACTIVE_HIGH>;
+                        default-state = "on";
+                };
+        };
+
+        mmc3_pwrseq: mmc3_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                pinctrl-0 = <&mmc3_pwrseq_pin_bpi_m1p>;
+                reset-gpios = <&pio 7 22 GPIO_ACTIVE_LOW>; /* PH22 WL-PMU-EN */
+        };
+
+        reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gmac_power_pin_bpi_m1p>;
+                regulator-name = "gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <100000>;
+                enable-active-high;
+                gpio = <&pio 7 23 GPIO_ACTIVE_HIGH>;
+        };
+};
+
+&ahci {
+        status = "okay";
+};
+
+&codec {
+        status = "okay";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&gmac {
+        pinctrl-names = "default";
+        pinctrl-0 = <&gmac_pins_rgmii_a>;
+        phy = <&phy1>;
+        phy-mode = "rgmii";
+        phy-supply = <&reg_gmac_3v3>;
+        status = "okay";
+
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+
+&i2c0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c0_pins_a>;
+        status = "okay";
+
+        axp209: pmic@34 {
+                compatible = "x-powers,axp209";
+                reg = <0x34>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+                interrupt-controller;
+                #interrupt-cells = <1>;
+        };
+};
+
+&ir0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ir0_rx_pins_a>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_bpi_m1p>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
+        cd-inverted;
+        status = "okay";
+};
+
+&mmc3 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc3_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&mmc3_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        enable-sdio-wakeup;
+        status = "okay";
+
+        brcmf: bcrmf@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&pio>;
+                interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
+                interrupt-names = "host-wake";
+        };
+};
+
+&mmc3_pins_a {
+        /* AP6210 requires pull-up */
+        allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&pio {
+        gmac_power_pin_bpi_m1p: gmac_power_pin@0 {
+                allwinner,pins = "PH23";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        led_pins_bpi_m1p: led_pins@0 {
+                allwinner,pins = "PH24", "PH25";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        mmc0_cd_pin_bpi_m1p: mmc0_cd_pin@0 {
+                allwinner,pins = "PH10";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+
+        mmc3_pwrseq_pin_bpi_m1p: mmc3_pwrseq_pin@0 {
+                allwinner,pins = "PH22";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index 5ee43d8bf174..73c05dab0a69 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -95,6 +95,10 @@
         status = "okay";
 };
 
+&codec {
+        status = "okay";
+};
+
 &cpu0 {
         cpu-supply = <&reg_dcdc2>;
 };
@@ -110,13 +114,67 @@
 &gmac {
         pinctrl-names = "default";
         pinctrl-0 = <&gmac_pins_rgmii_a>;
-        phy = <&phy1>;
         phy-mode = "rgmii";
         phy-supply = <&reg_gmac_3v3>;
         status = "okay";
 
-        phy1: ethernet-phy@1 {
-                reg = <1>;
+        fixed-link {
+                speed = <1000>;
+                full-duplex;
+        };
+
+        mdio {
+                compatible = "snps,dwmac-mdio";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                switch: ethernet-switch@1e {
+                        compatible = "brcm,bcm53125";
+                        reg = <30>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        ports {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                port0: port@0 {
+                                        reg = <0>;
+                                        label = "lan2";
+                                };
+
+                                port1: port@1 {
+                                        reg = <1>;
+                                        label = "lan3";
+                                };
+
+                                port2: port@2 {
+                                        reg = <2>;
+                                        label = "lan4";
+                                };
+
+                                port3: port@3 {
+                                        reg = <3>;
+                                        label = "wan";
+                                };
+
+                                port4: port@4 {
+                                        reg = <4>;
+                                        label = "lan1";
+                                };
+
+                                port8: port@8 {
+                                        reg = <8>;
+                                        label = "cpu";
+                                        ethernet = <&gmac>;
+                                        phy-mode = "rgmii";
+                                        fixed-link {
+                                                speed = <1000>;
+                                                full-duplex;
+                                        };
+                                };
+                        };
+                };
         };
 };
 
@@ -158,10 +216,6 @@
         status = "okay";
 };
 
-&ohci1 {
-        status = "okay";
-};
-
 &otg_sram {
         status = "okay";
 };
@@ -199,7 +253,7 @@
 #include "axp209.dtsi"
 
 &reg_ahci_5v {
-        gpio = <&pio 1 3 0>; /* PB3 */
+        gpio = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
         status = "okay";
 };
 
@@ -232,11 +286,8 @@
         status = "okay";
 };
 
-&reg_usb1_vbus {
-        status = "okay";
-};
-
 &reg_usb2_vbus {
+        gpio = <&pio 7 12 GPIO_ACTIVE_HIGH>; /* PH12 */
         status = "okay";
 };
 
@@ -275,13 +326,16 @@
         status = "okay";
 };
 
+&usb2_vbus_pin_a {
+        allwinner,pins = "PH12";
+};
+
 &usbphy {
         pinctrl-names = "default";
         pinctrl-0 = <&usb0_id_detect_pin>;
         usb0_id_det-gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
         usb0_vbus_power-supply = <&usb_power_supply>;
         usb0_vbus-supply = <&reg_usb0_vbus>;
-        usb1_vbus-supply = <&reg_usb1_vbus>;
         usb2_vbus-supply = <&reg_usb2_vbus>;
         status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 2c34bbbb9570..bd0c47660243 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -67,9 +67,9 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0-hdmi";
-                        clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-                                 <&ahb_gates 43>, <&ahb_gates 44>,
-                                 <&dram_gates 26>;
+                        clocks = <&ahb_gates 36>, <&ahb_gates 43>,
+                                 <&ahb_gates 44>, <&de_be0_clk>,
+                                 <&tcon0_ch1_clk>, <&dram_gates 26>;
                         status = "disabled";
                 };
 
@@ -77,8 +77,9 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0";
-                        clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
-                                 <&ahb_gates 44>, <&dram_gates 26>;
+                        clocks = <&ahb_gates 36>, <&ahb_gates 44>,
+                                 <&de_be0_clk>, <&tcon0_ch0_clk>,
+                                 <&dram_gates 26>;
                         status = "disabled";
                 };
 
@@ -86,8 +87,9 @@
                         compatible = "allwinner,simple-framebuffer",
                                      "simple-framebuffer";
                         allwinner,pipeline = "de_be0-lcd0-tve0";
-                        clocks = <&pll3>, <&pll5 1>,
-                                 <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
+                        clocks = <&ahb_gates 34>, <&ahb_gates 36>,
+                                 <&ahb_gates 44>,
+                                 <&de_be0_clk>, <&tcon0_ch1_clk>,
                                  <&dram_gates 5>, <&dram_gates 26>;
                         status = "disabled";
                 };
@@ -369,9 +371,9 @@
                                         <5>, <6>, <7>,
                                         <8>, <10>;
                         clock-output-names = "apb0_codec", "apb0_spdif",
-                                "apb0_ac97", "apb0_iis0", "apb0_iis1",
+                                "apb0_ac97", "apb0_i2s0", "apb0_i2s1",
                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
-                                "apb0_iis2", "apb0_keypad";
+                                "apb0_i2s2", "apb0_keypad";
                 };
 
                 apb1: clk@01c20058 {
@@ -521,6 +523,28 @@
                         clock-output-names = "ir1";
                 };
 
+                i2s0_clk: clk@01c200b8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod1-clk";
+                        reg = <0x01c200b8 0x4>;
+                        clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+                                 <&pll2 SUN4I_A10_PLL2_4X>,
+                                 <&pll2 SUN4I_A10_PLL2_2X>,
+                                 <&pll2 SUN4I_A10_PLL2_1X>;
+                        clock-output-names = "i2s0";
+                };
+
+                ac97_clk: clk@01c200bc {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod1-clk";
+                        reg = <0x01c200bc 0x4>;
+                        clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+                                 <&pll2 SUN4I_A10_PLL2_4X>,
+                                 <&pll2 SUN4I_A10_PLL2_2X>,
+                                 <&pll2 SUN4I_A10_PLL2_1X>;
+                        clock-output-names = "ac97";
+                };
+
                 spdif_clk: clk@01c200c0 {
                         #clock-cells = <0>;
                         compatible = "allwinner,sun4i-a10-mod1-clk";
@@ -558,6 +582,28 @@
                         clock-output-names = "spi3";
                 };
 
+                i2s1_clk: clk@01c200d8 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod1-clk";
+                        reg = <0x01c200d8 0x4>;
+                        clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+                                 <&pll2 SUN4I_A10_PLL2_4X>,
+                                 <&pll2 SUN4I_A10_PLL2_2X>,
+                                 <&pll2 SUN4I_A10_PLL2_1X>;
+                        clock-output-names = "i2s1";
+                };
+
+                i2s2_clk: clk@01c200dc {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod1-clk";
+                        reg = <0x01c200dc 0x4>;
+                        clocks = <&pll2 SUN4I_A10_PLL2_8X>,
+                                 <&pll2 SUN4I_A10_PLL2_4X>,
+                                 <&pll2 SUN4I_A10_PLL2_2X>,
+                                 <&pll2 SUN4I_A10_PLL2_1X>;
+                        clock-output-names = "i2s2";
+                };
+
                 dram_gates: clk@01c20100 {
                         #clock-cells = <1>;
                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
@@ -583,6 +629,80 @@
                                              "dram_de_mp", "dram_ace";
                 };
 
+                de_be0_clk: clk@01c20104 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20104 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-be0";
+                };
+
+                de_be1_clk: clk@01c20108 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20108 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-be1";
+                };
+
+                de_fe0_clk: clk@01c2010c {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c2010c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-fe0";
+                };
+
+                de_fe1_clk: clk@01c20110 {
+                        #clock-cells = <0>;
+                        #reset-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-display-clk";
+                        reg = <0x01c20110 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll5 1>;
+                        clock-output-names = "de-fe1";
+                };
+
+                tcon0_ch0_clk: clk@01c20118 {
+                        #clock-cells = <0>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+                        reg = <0x01c20118 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon0-ch0-sclk";
+
+                };
+
+                tcon1_ch0_clk: clk@01c2011c {
+                        #clock-cells = <0>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+                        reg = <0x01c2011c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon1-ch0-sclk";
+
+                };
+
+                tcon0_ch1_clk: clk@01c2012c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch0-clk";
+                        reg = <0x01c2012c 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon0-ch1-sclk";
+
+                };
+
+                tcon1_ch1_clk: clk@01c20130 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-tcon-ch1-clk";
+                        reg = <0x01c20130 0x4>;
+                        clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>;
+                        clock-output-names = "tcon1-ch1-sclk";
+
+                };
+
                 ve_clk: clk@01c2013c {
                         #clock-cells = <0>;
                         #reset-cells = <0>;
@@ -726,6 +846,19 @@
                         #dma-cells = <2>;
                 };
 
+                nfc: nand@01c03000 {
+                        compatible = "allwinner,sun4i-a10-nand";
+                        reg = <0x01c03000 0x1000>;
+                        interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&ahb_gates 13>, <&nand_clk>;
+                        clock-names = "ahb", "mod";
+                        dmas = <&dma SUN4I_DMA_DEDICATED 3>;
+                        dma-names = "rxtx";
+                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
                 spi0: spi@01c05000 {
                         compatible = "allwinner,sun4i-a10-spi";
                         reg = <0x01c05000 0x1000>;
@@ -958,160 +1091,177 @@
                         #interrupt-cells = <3>;
                         #gpio-cells = <3>;
 
-                        pwm0_pins_a: pwm0@0 {
-                                allwinner,pins = "PB2";
-                                allwinner,function = "pwm";
+                        clk_out_a_pins_a: clk_out_a@0 {
+                                allwinner,pins = "PI12";
+                                allwinner,function = "clk_out_a";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        pwm1_pins_a: pwm1@0 {
-                                allwinner,pins = "PI3";
-                                allwinner,function = "pwm";
+                        clk_out_b_pins_a: clk_out_b@0 {
+                                allwinner,pins = "PI13";
+                                allwinner,function = "clk_out_b";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart0_pins_a: uart0@0 {
-                                allwinner,pins = "PB22", "PB23";
-                                allwinner,function = "uart0";
+                        emac_pins_a: emac0@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "emac";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart2_pins_a: uart2@0 {
-                                allwinner,pins = "PI16", "PI17", "PI18", "PI19";
-                                allwinner,function = "uart2";
+                        gmac_pins_mii_a: gmac_mii@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA9", "PA10",
+                                                "PA11", "PA12", "PA13", "PA14",
+                                                "PA15", "PA16";
+                                allwinner,function = "gmac";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart3_pins_a: uart3@0 {
-                                allwinner,pins = "PG6", "PG7", "PG8", "PG9";
-                                allwinner,function = "uart3";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                        gmac_pins_rgmii_a: gmac_rgmii@0 {
+                                allwinner,pins = "PA0", "PA1", "PA2",
+                                                "PA3", "PA4", "PA5", "PA6",
+                                                "PA7", "PA8", "PA10",
+                                                "PA11", "PA12", "PA13",
+                                                "PA15", "PA16";
+                                allwinner,function = "gmac";
+                                /*
+                                 * data lines in RGMII mode use DDR mode
+                                 * and need a higher signal drive strength
+                                 */
+                                allwinner,drive = <SUN4I_PINCTRL_40_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart3_pins_b: uart3@1 {
-                                allwinner,pins = "PH0", "PH1";
-                                allwinner,function = "uart3";
+                        i2c0_pins_a: i2c0@0 {
+                                allwinner,pins = "PB0", "PB1";
+                                allwinner,function = "i2c0";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart4_pins_a: uart4@0 {
-                                allwinner,pins = "PG10", "PG11";
-                                allwinner,function = "uart4";
+                        i2c1_pins_a: i2c1@0 {
+                                allwinner,pins = "PB18", "PB19";
+                                allwinner,function = "i2c1";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart4_pins_b: uart4@1 {
-                                allwinner,pins = "PH4", "PH5";
-                                allwinner,function = "uart4";
+                        i2c2_pins_a: i2c2@0 {
+                                allwinner,pins = "PB20", "PB21";
+                                allwinner,function = "i2c2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart5_pins_a: uart5@0 {
-                                allwinner,pins = "PI10", "PI11";
-                                allwinner,function = "uart5";
+                        i2c3_pins_a: i2c3@0 {
+                                allwinner,pins = "PI0", "PI1";
+                                allwinner,function = "i2c3";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart6_pins_a: uart6@0 {
-                                allwinner,pins = "PI12", "PI13";
-                                allwinner,function = "uart6";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        ir0_rx_pins_a: ir0@0 {
+                                    allwinner,pins = "PB4";
+                                    allwinner,function = "ir0";
+                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        uart7_pins_a: uart7@0 {
-                                allwinner,pins = "PI20", "PI21";
-                                allwinner,function = "uart7";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        ir0_tx_pins_a: ir0@1 {
+                                    allwinner,pins = "PB3";
+                                    allwinner,function = "ir0";
+                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c0_pins_a: i2c0@0 {
-                                allwinner,pins = "PB0", "PB1";
-                                allwinner,function = "i2c0";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        ir1_rx_pins_a: ir1@0 {
+                                    allwinner,pins = "PB23";
+                                    allwinner,function = "ir1";
+                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c1_pins_a: i2c1@0 {
-                                allwinner,pins = "PB18", "PB19";
-                                allwinner,function = "i2c1";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        ir1_tx_pins_a: ir1@1 {
+                                    allwinner,pins = "PB22";
+                                    allwinner,function = "ir1";
+                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c2_pins_a: i2c2@0 {
-                                allwinner,pins = "PB20", "PB21";
-                                allwinner,function = "i2c2";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0", "PF1", "PF2",
+                                                 "PF3", "PF4", "PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        i2c3_pins_a: i2c3@0 {
-                                allwinner,pins = "PI0", "PI1";
-                                allwinner,function = "i2c3";
+                        mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+                                allwinner,pins = "PH1";
+                                allwinner,function = "gpio_in";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+                        };
+
+                        mmc2_pins_a: mmc2@0 {
+                                allwinner,pins = "PC6", "PC7", "PC8",
+                                                 "PC9", "PC10", "PC11";
+                                allwinner,function = "mmc2";
+                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+                        };
+
+                        mmc3_pins_a: mmc3@0 {
+                                allwinner,pins = "PI4", "PI5", "PI6",
+                                                 "PI7", "PI8", "PI9";
+                                allwinner,function = "mmc3";
+                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        emac_pins_a: emac0@0 {
-                                allwinner,pins = "PA0", "PA1", "PA2",
-                                                "PA3", "PA4", "PA5", "PA6",
-                                                "PA7", "PA8", "PA9", "PA10",
-                                                "PA11", "PA12", "PA13", "PA14",
-                                                "PA15", "PA16";
-                                allwinner,function = "emac";
+                        ps20_pins_a: ps20@0 {
+                                allwinner,pins = "PI20", "PI21";
+                                allwinner,function = "ps2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        clk_out_a_pins_a: clk_out_a@0 {
-                                allwinner,pins = "PI12";
-                                allwinner,function = "clk_out_a";
+                        ps21_pins_a: ps21@0 {
+                                allwinner,pins = "PH12", "PH13";
+                                allwinner,function = "ps2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        clk_out_b_pins_a: clk_out_b@0 {
-                                allwinner,pins = "PI13";
-                                allwinner,function = "clk_out_b";
+                        pwm0_pins_a: pwm0@0 {
+                                allwinner,pins = "PB2";
+                                allwinner,function = "pwm";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        gmac_pins_mii_a: gmac_mii@0 {
-                                allwinner,pins = "PA0", "PA1", "PA2",
-                                                "PA3", "PA4", "PA5", "PA6",
-                                                "PA7", "PA8", "PA9", "PA10",
-                                                "PA11", "PA12", "PA13", "PA14",
-                                                "PA15", "PA16";
-                                allwinner,function = "gmac";
+                        pwm1_pins_a: pwm1@0 {
+                                allwinner,pins = "PI3";
+                                allwinner,function = "pwm";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        gmac_pins_rgmii_a: gmac_rgmii@0 {
-                                allwinner,pins = "PA0", "PA1", "PA2",
-                                                "PA3", "PA4", "PA5", "PA6",
-                                                "PA7", "PA8", "PA10",
-                                                "PA11", "PA12", "PA13",
-                                                "PA15", "PA16";
-                                allwinner,function = "gmac";
-                                /*
-                                 * data lines in RGMII mode use DDR mode
-                                 * and need a higher signal drive strength
-                                 */
-                                allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        spdif_tx_pins_a: spdif@0 {
+                                allwinner,pins = "PB13";
+                                allwinner,function = "spdif";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
                         };
 
                         spi0_pins_a: spi0@0 {
@@ -1177,84 +1327,67 @@
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        mmc0_pins_a: mmc0@0 {
-                                allwinner,pins = "PF0", "PF1", "PF2",
-                                                 "PF3", "PF4", "PF5";
-                                allwinner,function = "mmc0";
-                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PB22", "PB23";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
-                                allwinner,pins = "PH1";
-                                allwinner,function = "gpio_in";
+                        uart2_pins_a: uart2@0 {
+                                allwinner,pins = "PI16", "PI17", "PI18", "PI19";
+                                allwinner,function = "uart2";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-                        };
-
-                        mmc2_pins_a: mmc2@0 {
-                                allwinner,pins = "PC6", "PC7", "PC8",
-                                                 "PC9", "PC10", "PC11";
-                                allwinner,function = "mmc2";
-                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-                        };
-
-                        mmc3_pins_a: mmc3@0 {
-                                allwinner,pins = "PI4", "PI5", "PI6",
-                                                 "PI7", "PI8", "PI9";
-                                allwinner,function = "mmc3";
-                                allwinner,drive = <SUN4I_PINCTRL_30_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir0_rx_pins_a: ir0@0 {
-                                    allwinner,pins = "PB4";
-                                    allwinner,function = "ir0";
-                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        uart3_pins_a: uart3@0 {
+                                allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir0_tx_pins_a: ir0@1 {
-                                    allwinner,pins = "PB3";
-                                    allwinner,function = "ir0";
-                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        uart3_pins_b: uart3@1 {
+                                allwinner,pins = "PH0", "PH1";
+                                allwinner,function = "uart3";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir1_rx_pins_a: ir1@0 {
-                                    allwinner,pins = "PB23";
-                                    allwinner,function = "ir1";
-                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        uart4_pins_a: uart4@0 {
+                                allwinner,pins = "PG10", "PG11";
+                                allwinner,function = "uart4";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ir1_tx_pins_a: ir1@1 {
-                                    allwinner,pins = "PB22";
-                                    allwinner,function = "ir1";
-                                    allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                    allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        uart4_pins_b: uart4@1 {
+                                allwinner,pins = "PH4", "PH5";
+                                allwinner,function = "uart4";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ps20_pins_a: ps20@0 {
-                                allwinner,pins = "PI20", "PI21";
-                                allwinner,function = "ps2";
+                        uart5_pins_a: uart5@0 {
+                                allwinner,pins = "PI10", "PI11";
+                                allwinner,function = "uart5";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        ps21_pins_a: ps21@0 {
-                                allwinner,pins = "PH12", "PH13";
-                                allwinner,function = "ps2";
+                        uart6_pins_a: uart6@0 {
+                                allwinner,pins = "PI12", "PI13";
+                                allwinner,function = "uart6";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
 
-                        spdif_tx_pins_a: spdif@0 {
-                                allwinner,pins = "PB13";
-                                allwinner,function = "spdif";
+                        uart7_pins_a: uart7@0 {
+                                allwinner,pins = "PI20", "PI21";
+                                allwinner,function = "uart7";
                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
                 };
 
@@ -1320,6 +1453,32 @@
                         status = "disabled";
                 };
 
+                i2s1: i2s@01c22000 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-i2s";
+                        reg = <0x01c22000 0x400>;
+                        interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb0_gates 4>, <&i2s1_clk>;
+                        clock-names = "apb", "mod";
+                        dmas = <&dma SUN4I_DMA_NORMAL 4>,
+                               <&dma SUN4I_DMA_NORMAL 4>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
+                i2s0: i2s@01c22400 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-i2s";
+                        reg = <0x01c22400 0x400>;
+                        interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb0_gates 3>, <&i2s0_clk>;
+                        clock-names = "apb", "mod";
+                        dmas = <&dma SUN4I_DMA_NORMAL 3>,
+                               <&dma SUN4I_DMA_NORMAL 3>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
                 lradc: lradc@01c22800 {
                         compatible = "allwinner,sun4i-a10-lradc-keys";
                         reg = <0x01c22800 0x100>;
@@ -1345,6 +1504,19 @@
                         reg = <0x01c23800 0x200>;
                 };
 
+                i2s2: i2s@01c24400 {
+                        #sound-dai-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-i2s";
+                        reg = <0x01c24400 0x400>;
+                        interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&apb0_gates 8>, <&i2s2_clk>;
+                        clock-names = "apb", "mod";
+                        dmas = <&dma SUN4I_DMA_NORMAL 6>,
+                               <&dma SUN4I_DMA_NORMAL 6>;
+                        dma-names = "rx", "tx";
+                        status = "disabled";
+                };
+
                 rtp: rtp@01c25000 {
                         compatible = "allwinner,sun5i-a13-ts";
                         reg = <0x01c25000 0x100>;
diff --git a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts
new file mode 100644
index 000000000000..0f9f71b14047
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sun8i-reference-design-tablet.dtsi"
+
+/ {
+        model = "INet-86DZ Rev 01";
+        compatible = "primux,inet86dz", "allwinner,sun8i-a23";
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&usbphy {
+        usb1_vbus-supply = <&reg_dldo1>;
+};
diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
new file mode 100644
index 000000000000..e3004428e7a7
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2016 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a23.dtsi"
+#include "sun8i-reference-design-tablet.dtsi"
+
+/ {
+        model = "Polaroid MID2407PXE03 tablet";
+        compatible = "polaroid,mid2407pxe03", "allwinner,sun8i-a23";
+};
diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
index cb5daafcb7c2..6d06e24d446b 100644
--- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
+++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts
@@ -42,202 +42,9 @@
 
 /dts-v1/;
 #include "sun8i-a23.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
-#include <dt-bindings/pwm/pwm.h>
+#include "sun8i-reference-design-tablet.dtsi"
 
 / {
         model = "Polaroid MID2809PXE04 tablet";
         compatible = "polaroid,mid2809pxe04", "allwinner,sun8i-a23";
-
-        aliases {
-                serial0 = &r_uart;
-        };
-
-        backlight: backlight {
-                compatible = "pwm-backlight";
-                pinctrl-names = "default";
-                pinctrl-0 = <&bl_en_pin_mid2809>;
-                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
-                default-brightness-level = <8>;
-                enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-};
-
-&ehci0 {
-        status = "okay";
-};
-
-&i2c0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c0_pins_a>;
-        status = "okay";
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins_a>;
-        status = "okay";
-};
-
-&lradc {
-        vref-supply = <&reg_vcc3v0>;
-        status = "okay";
-
-        button@200 {
-                label = "Volume Up";
-                linux,code = <KEY_VOLUMEUP>;
-                channel = <0>;
-                voltage = <200000>;
-        };
-
-        button@400 {
-                label = "Volume Down";
-                linux,code = <KEY_VOLUMEDOWN>;
-                channel = <0>;
-                voltage = <400000>;
-        };
-};
-
-&mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_mid2809>;
-        vmmc-supply = <&reg_dcdc1>;
-        bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
-        status = "okay";
-};
-
-&pio {
-        bl_en_pin_mid2809: bl_en_pin@0 {
-                allwinner,pins = "PH6";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-        };
-
-        mmc0_cd_pin_mid2809: mmc0_cd_pin@0 {
-                allwinner,pins = "PB4";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-};
-
-&pwm {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pwm0_pins>;
-        status = "okay";
-};
-
-&r_rsb {
-        status = "okay";
-
-        axp22x: pmic@3a3 {
-                compatible = "x-powers,axp223";
-                reg = <0x3a3>;
-                interrupt-parent = <&nmi_intc>;
-                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-                eldoin-supply = <&reg_dcdc1>;
-        };
-};
-
-&r_uart {
-        pinctrl-names = "default";
-        pinctrl-0 = <&r_uart_pins_a>;
-        status = "okay";
-};
-
-#include "axp22x.dtsi"
-
-&reg_aldo1 {
-        regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "vcc-io";
-};
-
-&reg_aldo2 {
-        regulator-always-on;
-        regulator-min-microvolt = <2350000>;
-        regulator-max-microvolt = <2650000>;
-        regulator-name = "vdd-dll";
-};
-
-&reg_aldo3 {
-        regulator-always-on;
-        regulator-min-microvolt = <2700000>;
-        regulator-max-microvolt = <3300000>;
-        regulator-name = "vcc-pll-avcc";
-};
-
-&reg_dc1sw {
-        regulator-name = "vcc-lcd";
-};
-
-&reg_dc5ldo {
-        regulator-always-on;
-        regulator-min-microvolt = <900000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-cpus";
-};
-
-&reg_dcdc1 {
-        regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "vcc-3v0";
-};
-
-&reg_dcdc2 {
-        regulator-always-on;
-        regulator-min-microvolt = <900000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-sys";
-};
-
-&reg_dcdc3 {
-        regulator-always-on;
-        regulator-min-microvolt = <900000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-cpu";
-};
-
-&reg_dcdc5 {
-        regulator-always-on;
-        regulator-min-microvolt = <1500000>;
-        regulator-max-microvolt = <1500000>;
-        regulator-name = "vcc-dram";
-};
-
-&reg_rtc_ldo {
-        regulator-name = "vcc-rtc";
-};
-
-&simplefb_lcd {
-        vcc-lcd-supply = <&reg_dc1sw>;
-};
-
-/*
- * FIXME for now we only support host mode and rely on u-boot to have
- * turned on Vbus which is controlled by the axp223 pmic on the board.
- *
- * Once we have axp223 support we should switch to fully supporting otg.
- */
-&usb_otg {
-        dr_mode = "host";
-        status = "okay";
-};
-
-&usbphy {
-        status = "okay";
 };
diff --git a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
index 6062ea7a9903..956320a6cc78 100644
--- a/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a23-q8-tablet.dts
@@ -48,18 +48,3 @@
         model = "Q8 A23 Tablet";
         compatible = "allwinner,q8-a23", "allwinner,sun8i-a23";
 };
-
-/*
- * FIXME for now we only support host mode and rely on u-boot to have
- * turned on Vbus which is controlled by the axp223 pmic on the board.
- *
- * Once we have axp223 support we should switch to fully supporting otg.
- */
-&usb_otg {
-        dr_mode = "host";
-        status = "okay";
-};
-
-&usbphy {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
index 1aefc6793e25..65660324005c 100644
--- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
+++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts
@@ -42,59 +42,18 @@
 
 /dts-v1/;
 #include "sun8i-a33.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sun8i-reference-design-tablet.dtsi"
 
 / {
         model = "Allwinner GA10H Quad Core Tablet (v1.1)";
         compatible = "allwinner,ga10h-v1.1", "allwinner,sun8i-a33";
-
-        aliases {
-                serial0 = &r_uart;
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
 };
 
 &ehci0 {
         status = "okay";
 };
 
-&i2c0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c0_pins_a>;
-        status = "okay";
-};
-
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&i2c1_pins_a>;
-        status = "okay";
-};
-
 &lradc {
-        vref-supply = <&reg_vcc3v0>;
-        status = "okay";
-
-        button@200 {
-                label = "Volume Up";
-                linux,code = <KEY_VOLUMEUP>;
-                channel = <0>;
-                voltage = <200000>;
-        };
-
-        button@400 {
-                label = "Volume Down";
-                linux,code = <KEY_VOLUMEDOWN>;
-                channel = <0>;
-                voltage = <400000>;
-        };
-
         button@600 {
                 label = "Back";
                 linux,code = <KEY_BACK>;
@@ -103,40 +62,6 @@
         };
 };
 
-&mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8h>;
-        vmmc-supply = <&reg_vcc3v0>;
-        bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
-        status = "okay";
-};
-
 &ohci0 {
         status = "okay";
 };
-
-&pio {
-        mmc0_cd_pin_q8h: mmc0_cd_pin@0 {
-                allwinner,pins = "PB4";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-};
-
-&r_uart {
-        pinctrl-names = "default";
-        pinctrl-0 = <&r_uart_pins_a>;
-        status = "okay";
-};
-
-&usb_otg {
-        dr_mode = "host";
-        status = "okay";
-};
-
-&usbphy {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
index 44b32296a025..b0bc2360f8c4 100644
--- a/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
+++ b/arch/arm/boot/dts/sun8i-a33-q8-tablet.dts
@@ -48,18 +48,3 @@
         model = "Q8 A33 Tablet";
         compatible = "allwinner,q8-a33", "allwinner,sun8i-a33";
 };
-
-/*
- * FIXME for now we only support host mode and rely on u-boot to have
- * turned on Vbus which is controlled by the axp223 pmic on the board.
- *
- * Once we have axp223 support we should switch to fully supporting otg.
- */
-&usb_otg {
-        dr_mode = "host";
-        status = "okay";
-};
-
-&usbphy {
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
new file mode 100644
index 000000000000..f3b1d5f6dbd2
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+        model = "Banana Pi BPI-M2-Plus";
+        compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
+
+        aliases {
+                serial0 = &uart0;
+                serial1 = &uart1;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pwr_led_bpi_m2p>;
+
+                pwr_led {
+                        label = "bananapi-m2-plus:red:pwr";
+                        gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+                        default-state = "on";
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&sw_r_bpi_m2p>;
+
+                sw4 {
+                        label = "power";
+                        linux,code = <BTN_0>;
+                        gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+                };
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                pinctrl-names = "default";
+                pinctrl-0 = <&wifi_en_bpi_m2p>;
+                reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+        };
+};
+
+&ehci1 {
+        status = "okay";
+};
+
+&ehci2 {
+        status = "okay";
+};
+
+&ir {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ir_pins_a>;
+        status = "okay";
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <4>;
+        cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+        cd-inverted;
+        status = "okay";
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+
+        brcmf: bcrmf@1 {
+                reg = <1>;
+                compatible = "brcm,bcm4329-fmac";
+                interrupt-parent = <&pio>;
+                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 / EINT10 */
+                interrupt-names = "host-wake";
+        };
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_vcc3v3>;
+        vqmmc-supply = <&reg_vcc3v3>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+};
+
+&ohci1 {
+        status = "okay";
+};
+
+&ohci2 {
+        status = "okay";
+};
+
+&r_pio {
+        pwr_led_bpi_m2p: led_pins@0 {
+                allwinner,pins = "PL10";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        sw_r_bpi_m2p: key_pins@0 {
+                allwinner,pins = "PL3";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        wifi_en_bpi_m2p: wifi_en_pin {
+                allwinner,pins = "PL7";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_a>;
+        status = "okay";
+};
+
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins_a>;
+        status = "okay";
+};
+
+&usbphy {
+        /* USB VBUS is on as long as VCC-IO is on */
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 9871bad34742..fdf9fdbda267 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -327,13 +327,6 @@
                         interrupt-controller;
                         #interrupt-cells = <3>;
 
-                        uart0_pins_a: uart0@0 {
-                                allwinner,pins = "PA4", "PA5";
-                                allwinner,function = "uart0";
-                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-                        };
-
                         mmc0_pins_a: mmc0@0 {
                                 allwinner,pins = "PF0", "PF1", "PF2", "PF3",
                                                  "PF4", "PF5";
@@ -366,6 +359,20 @@
                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
                         };
+
+                        uart0_pins_a: uart0@0 {
+                                allwinner,pins = "PA4", "PA5";
+                                allwinner,function = "uart0";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        };
+
+                        uart1_pins_a: uart1@0 {
+                                allwinner,pins = "PG6", "PG7", "PG8", "PG9";
+                                allwinner,function = "uart1";
+                                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+                        };
                 };
 
                 timer@01c20c00 {
diff --git a/arch/arm/boot/dts/sun8i-q8-common.dtsi b/arch/arm/boot/dts/sun8i-q8-common.dtsi
index 346a49d805a7..60fa9585022b 100644
--- a/arch/arm/boot/dts/sun8i-q8-common.dtsi
+++ b/arch/arm/boot/dts/sun8i-q8-common.dtsi
@@ -39,140 +39,13 @@
  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
-#include "sunxi-q8-common.dtsi"
+#include "sunxi-reference-design-tablet.dtsi"
+#include "sun8i-reference-design-tablet.dtsi"
 
-#include <dt-bindings/pwm/pwm.h>
-
-/ {
-        aliases {
-                serial0 = &r_uart;
-        };
-
-        backlight: backlight {
-                compatible = "pwm-backlight";
-                pinctrl-names = "default";
-                pinctrl-0 = <&bl_en_pin_q8>;
-                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
-                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
-                default-brightness-level = <8>;
-                enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
-        };
-
-        chosen {
-                stdout-path = "serial0:115200n8";
-        };
-};
-
-&mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_q8>;
-        vmmc-supply = <&reg_dcdc1>;
-        bus-width = <4>;
-        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
-        cd-inverted;
-        status = "okay";
-};
-
-&pio {
-        bl_en_pin_q8: bl_en_pin@0 {
-                allwinner,pins = "PH6";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-        };
-
-        mmc0_cd_pin_q8: mmc0_cd_pin@0 {
-                allwinner,pins = "PB4";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-};
-
-&r_rsb {
-        status = "okay";
-
-        axp22x: pmic@3a3 {
-                compatible = "x-powers,axp223";
-                reg = <0x3a3>;
-                interrupt-parent = <&nmi_intc>;
-                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
-                eldoin-supply = <&reg_dcdc1>;
-        };
-};
-
-#include "axp22x.dtsi"
-
-&reg_aldo1 {
-        regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "vcc-io";
-};
-
-&reg_aldo2 {
-        regulator-always-on;
-        regulator-min-microvolt = <2350000>;
-        regulator-max-microvolt = <2650000>;
-        regulator-name = "vdd-dll";
-};
-
-&reg_aldo3 {
-        regulator-always-on;
-        regulator-min-microvolt = <2700000>;
-        regulator-max-microvolt = <3300000>;
-        regulator-name = "vcc-pll-avcc";
-};
-
-&reg_dc1sw {
-        regulator-name = "vcc-lcd";
-};
-
-&reg_dc5ldo {
-        regulator-always-on;
-        regulator-min-microvolt = <900000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-cpus";
-};
-
-&reg_dcdc1 {
-        regulator-always-on;
-        regulator-min-microvolt = <3000000>;
-        regulator-max-microvolt = <3000000>;
-        regulator-name = "vcc-3v0";
-};
-
-&reg_dcdc2 {
-        regulator-always-on;
-        regulator-min-microvolt = <900000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-sys";
-};
-
-&reg_dcdc3 {
-        regulator-always-on;
-        regulator-min-microvolt = <900000>;
-        regulator-max-microvolt = <1400000>;
-        regulator-name = "vdd-cpu";
-};
-
-&reg_dcdc5 {
-        regulator-always-on;
-        regulator-min-microvolt = <1500000>;
-        regulator-max-microvolt = <1500000>;
-        regulator-name = "vcc-dram";
-};
-
-&reg_rtc_ldo {
-        regulator-name = "vcc-rtc";
-};
-
-&r_uart {
-        pinctrl-names = "default";
-        pinctrl-0 = <&r_uart_pins_a>;
-        status = "okay";
+&ehci0 {
+        status  = "okay";
 };
 
-&simplefb_lcd {
-        vcc-lcd-supply = <&reg_dc1sw>;
+&usbphy {
+        usb1_vbus-supply = <&reg_dldo1>;
 };
diff --git a/arch/arm/boot/dts/sun8i-r16-parrot.dts b/arch/arm/boot/dts/sun8i-r16-parrot.dts
new file mode 100644
index 000000000000..47553e522982
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-r16-parrot.dts
@@ -0,0 +1,351 @@
+/*
+ * Copyright 2016 Quentin Schulz
+ *
+ * Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-a33.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+        model = "Allwinner R16 EVB (Parrot)";
+        compatible = "allwinner,parrot", "allwinner,sun8i-a33";
+
+        aliases {
+                serial0 = &uart0;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_parrot>;
+
+                led1 {
+                        label = "parrot:led1:usr";
+                        gpio = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
+                };
+
+                led2 {
+                        label = "parrot:led2:usr";
+                        gpio = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+                };
+        };
+
+        wifi_pwrseq: wifi_pwrseq {
+                compatible = "mmc-pwrseq-simple";
+                reset-gpios = <&r_pio 0 6 GPIO_ACTIVE_LOW>; /* PL06 */
+        };
+
+};
+
+&ehci0 {
+        status = "okay";
+};
+
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins_a>;
+        status = "okay";
+
+        /*
+         * FIXME: An as-yet-unknown accelerometer is connected to this
+         * i2c bus.
+         */
+};
+
+&lradc {
+        vref-supply = <&reg_aldo3>;
+        status = "okay";
+
+        button@0 {
+                label = "V+";
+                linux,code = <KEY_VOLUMEUP>;
+                channel = <0>;
+                voltage = <190000>;
+        };
+
+        button@1 {
+                label = "V-";
+                linux,code = <KEY_VOLUMEDOWN>;
+                channel = <0>;
+                voltage = <390000>;
+        };
+
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_parrot>;
+        vmmc-supply = <&reg_dcdc1>;
+        cd-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
+        bus-width = <4>;
+        status = "okay";
+};
+
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins_a>, <&wifi_reset_pin_parrot>;
+        vmmc-supply = <&reg_aldo1>;
+        mmc-pwrseq = <&wifi_pwrseq>;
+        bus-width = <4>;
+        non-removable;
+        status = "okay";
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_dcdc1>;
+        bus-width = <8>;
+        non-removable;
+        cap-mmc-hw-reset;
+        status = "okay";
+};
+
+&mmc2_8bit_pins {
+        allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+        allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&ohci0 {
+        status = "okay";
+};
+
+&pio {
+        mmc0_cd_pin_parrot: mmc0_cd_pin@0 {
+                allwinner,pins = "PD14";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+
+        led_pins_parrot: led_pins@0 {
+                allwinner,pins = "PE16", "PE17";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        usb0_id_det: usb0_id_detect_pin@0 {
+                allwinner,pins = "PD10";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+
+        usb1_vbus_pin_parrot: usb1_vbus_pin@0 {
+                allwinner,pins = "PD12";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+};
+
+&r_pio {
+        wifi_reset_pin_parrot: wifi_reset_pin@0 {
+                allwinner,pins = "PL6";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+};
+
+&r_rsb {
+        status = "okay";
+
+        axp22x: pmic@3a3 {
+                compatible = "x-powers,axp223";
+                reg = <0x3a3>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                drivevbus-supply = <&reg_vcc5v0>;
+                x-powers,drive-vbus-en;
+        };
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+        regulator-always-on;
+        regulator-min-microvolt = <2350000>;
+        regulator-max-microvolt = <2650000>;
+        regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+        regulator-always-on;
+        regulator-min-microvolt = <2700000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc5ldo {
+        regulator-always-on;
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+        regulator-always-on;
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+        regulator-always-on;
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1500000>;
+        regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+        /*
+         * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
+         * Remove next line once it is possible to sync two regulators.
+         */
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi0";
+};
+
+&reg_dldo2 {
+        /*
+         * TODO: WiFi chip needs dldo1 AND dldo2 to be on to be powered.
+         * Remove next line once it is possible to sync two regulators.
+         */
+        regulator-always-on;
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi1";
+};
+
+&reg_dldo3 {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-3v0-csi";
+};
+
+&reg_drivevbus {
+        regulator-name = "usb0-vbus";
+        status = "okay";
+};
+
+&reg_eldo1 {
+        regulator-min-microvolt = <1200000>;
+        regulator-max-microvolt = <1200000>;
+        regulator-name = "vcc-1v2-hsic";
+};
+
+&reg_eldo2 {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-dsp";
+};
+
+&reg_eldo3 {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "eldo3";
+};
+
+&reg_usb1_vbus {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_vbus_pin_parrot>;
+        gpio = <&pio 3 12 GPIO_ACTIVE_HIGH>; /* PD12 */
+        status = "okay";
+};
+
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart0_pins_b>;
+        status = "okay";
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usb_power_supply {
+        status = "okay";
+};
+
+&usbphy {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_id_det>;
+        usb0_vbus-supply = <&reg_drivevbus>;
+        usb0_id_det-gpios = <&pio 3 10 GPIO_ACTIVE_HIGH>; /* PD10 */
+        usb0_vbus_power-supply = <&usb_power_supply>;
+        usb1_vbus-supply = <&reg_usb1_vbus>;
+};
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
new file mode 100644
index 000000000000..9d9036140511
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -0,0 +1,216 @@
+/*
+ * Copyright 2015 Hans de Goede <hdegoede@redhat.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "sunxi-reference-design-tablet.dtsi"
+
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+        aliases {
+                serial0 = &r_uart;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pinctrl-names = "default";
+                pinctrl-0 = <&bl_en_pin>;
+                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
+                default-brightness-level = <8>;
+                enable-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+};
+
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+        vmmc-supply = <&reg_dcdc1>;
+        bus-width = <4>;
+        cd-gpios = <&pio 1 4 GPIO_ACTIVE_HIGH>; /* PB4 */
+        cd-inverted;
+        status = "okay";
+};
+
+&pio {
+        bl_en_pin: bl_en_pin@0 {
+                allwinner,pins = "PH6";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        mmc0_cd_pin: mmc0_cd_pin@0 {
+                allwinner,pins = "PB4";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+
+        usb0_id_detect_pin: usb0_id_detect_pin@0 {
+                allwinner,pins = "PH8";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+};
+
+&r_rsb {
+        status = "okay";
+
+        axp22x: pmic@3a3 {
+                compatible = "x-powers,axp223";
+                reg = <0x3a3>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                eldoin-supply = <&reg_dcdc1>;
+                drivevbus-supply = <&reg_vcc5v0>;
+                x-powers,drive-vbus-en;
+        };
+};
+
+#include "axp22x.dtsi"
+
+&reg_aldo1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-io";
+};
+
+&reg_aldo2 {
+        regulator-always-on;
+        regulator-min-microvolt = <2350000>;
+        regulator-max-microvolt = <2650000>;
+        regulator-name = "vdd-dll";
+};
+
+&reg_aldo3 {
+        regulator-always-on;
+        regulator-min-microvolt = <2700000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-pll-avcc";
+};
+
+&reg_dc1sw {
+        regulator-name = "vcc-lcd";
+};
+
+&reg_dc5ldo {
+        regulator-always-on;
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-cpus";
+};
+
+&reg_dcdc1 {
+        regulator-always-on;
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-name = "vcc-3v0";
+};
+
+&reg_dcdc2 {
+        regulator-always-on;
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-sys";
+};
+
+&reg_dcdc3 {
+        regulator-always-on;
+        regulator-min-microvolt = <900000>;
+        regulator-max-microvolt = <1400000>;
+        regulator-name = "vdd-cpu";
+};
+
+&reg_dcdc5 {
+        regulator-always-on;
+        regulator-min-microvolt = <1500000>;
+        regulator-max-microvolt = <1500000>;
+        regulator-name = "vcc-dram";
+};
+
+&reg_dldo1 {
+        regulator-min-microvolt = <3300000>;
+        regulator-max-microvolt = <3300000>;
+        regulator-name = "vcc-wifi";
+};
+
+&reg_drivevbus {
+        regulator-name = "usb0-vbus";
+        status = "okay";
+};
+
+&reg_rtc_ldo {
+        regulator-name = "vcc-rtc";
+};
+
+&r_uart {
+        pinctrl-names = "default";
+        pinctrl-0 = <&r_uart_pins_a>;
+        status = "okay";
+};
+
+&simplefb_lcd {
+        vcc-lcd-supply = <&reg_dc1sw>;
+};
+
+&usb_otg {
+        dr_mode = "otg";
+        status = "okay";
+};
+
+&usb_power_supply {
+        status = "okay";
+};
+
+&usbphy {
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb0_id_detect_pin>;
+        usb0_id_det-gpio = <&pio 7 8 GPIO_ACTIVE_HIGH>; /* PH8 */
+        usb0_vbus_power-supply = <&usb_power_supply>;
+        usb0_vbus-supply = <&reg_drivevbus>;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
index eb2ccd0a3bd5..1526b41c70f1 100644
--- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
+++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts
@@ -45,7 +45,6 @@
 
 /dts-v1/;
 #include "sun9i-a80.dtsi"
-#include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
@@ -79,26 +78,10 @@
         };
 };
 
-&pio {
-        led_pins_cubieboard4: led-pins@0 {
-                allwinner,pins = "PH6", "PH17";
-                allwinner,function = "gpio_out";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
-        };
-
-        mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 {
-                allwinner,pins = "PH18";
-                allwinner,function = "gpio_in";
-                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
-                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
-        };
-};
-
 &mmc0 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_cubieboard4>;
-        vmmc-supply = <&reg_vcc3v0>;
+        vmmc-supply = <&reg_dcdc1>;
         bus-width = <4>;
         cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH18 */
         cd-inverted;
@@ -108,7 +91,7 @@
 &mmc2 {
         pinctrl-names = "default";
         pinctrl-0 = <&mmc2_8bit_pins>;
-        vmmc-supply = <&reg_vcc3v0>;
+        vmmc-supply = <&reg_dcdc1>;
         bus-width = <8>;
         non-removable;
         cap-mmc-hw-reset;
@@ -120,14 +103,157 @@
         allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 };
 
+&pio {
+        led_pins_cubieboard4: led-pins@0 {
+                allwinner,pins = "PH6", "PH17";
+                allwinner,function = "gpio_out";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+        };
+
+        mmc0_cd_pin_cubieboard4: mmc0_cd_pin@0 {
+                allwinner,pins = "PH18";
+                allwinner,function = "gpio_in";
+                allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+                allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+        };
+};
+
 &r_ir {
         status = "okay";
 };
 
 &r_rsb {
         status = "okay";
+
+        axp809: pmic@3a3 {
+                reg = <0x3a3>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+                regulators {
+                        reg_aldo1: aldo1 {
+                                /*
+                                 * TODO: This should be handled by the
+                                 * USB PHY driver.
+                                 */
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc33-usbh";
+                        };
+
+                        reg_aldo2: aldo2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-pb-io-cam";
+                        };
+
+                        aldo3 {
+                                /* unused */
+                        };
+
+                        reg_dc5ldo: dc5ldo {
+                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-cpus-09-usbh";
+                        };
+
+                        reg_dcdc1: dcdc1 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-3v";
+                        };
+
+                        reg_dcdc2: dcdc2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-gpu";
+                        };
+
+                        reg_dcdc3: dcdc3 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-cpua";
+                        };
+
+                        reg_dcdc4: dcdc4 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-sys-usb0-hdmi";
+                        };
+
+                        reg_dcdc5: dcdc5 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1425000>;
+                                regulator-max-microvolt = <1575000>;
+                                regulator-name = "vcc-dram";
+                        };
+
+                        reg_dldo1: dldo1 {
+                                /*
+                                 * The WiFi chip supports a wide range
+                                 * (3.0 ~ 4.8V) of voltages, and so does
+                                 * this regulator (3.0 ~ 4.2V), but
+                                 * Allwinner SDK always sets it to 3.3V.
+                                 */
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-wifi";
+                        };
+
+                        reg_dldo2: dldo2 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-pl";
+                        };
+
+                        reg_eldo1: eldo1 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-name = "vcc-dvdd-cam";
+                        };
+
+                        reg_eldo2: eldo2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-pe";
+                        };
+
+                        reg_eldo3: eldo3 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-pm-codec-io1";
+                        };
+
+                        reg_ldo_io0: ldo_io0 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-pg";
+                        };
+
+                        reg_ldo_io1: ldo_io1 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-name = "vcc-pa-gmac-2v5";
+                        };
+
+                        reg_rtc_ldo: rtc_ldo {
+                                regulator-name = "vcc-rtc-vdd1v8-io";
+                        };
+                };
+        };
 };
 
+#include "axp809.dtsi"
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts
index d7a20d92b114..7fd22e888602 100644
--- a/arch/arm/boot/dts/sun9i-a80-optimus.dts
+++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts
@@ -44,7 +44,6 @@
 
 /dts-v1/;
 #include "sun9i-a80.dtsi"
-#include "sunxi-common-regulators.dtsi"
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/sun4i-a10.h>
@@ -85,6 +84,17 @@
                 };
         };
 
+        reg_usb1_vbus: usb1-vbus {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb1_vbus_pin_optimus>;
+                regulator-name = "usb1-vbus";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                enable-active-high;
+                gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
+        };
+
         reg_usb3_vbus: usb3-vbus {
                 compatible = "regulator-fixed";
                 pinctrl-names = "default";
@@ -109,6 +119,31 @@
         status = "okay";
 };
 
+&mmc0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
+        vmmc-supply = <&reg_dcdc1>;
+        bus-width = <4>;
+        cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
+        cd-inverted;
+        status = "okay";
+};
+
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_8bit_pins>;
+        vmmc-supply = <&reg_dcdc1>;
+        bus-width = <8>;
+        non-removable;
+        cap-mmc-hw-reset;
+        status = "okay";
+};
+
+&mmc2_8bit_pins {
+        /* Increase drive strength for DDR modes */
+        allwinner,drive = <SUN4I_PINCTRL_40_MA>;
+};
+
 &ohci0 {
         status = "okay";
 };
@@ -147,37 +182,6 @@
         };
 };
 
-&mmc0 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin_optimus>;
-        vmmc-supply = <&reg_vcc3v0>;
-        bus-width = <4>;
-        cd-gpios = <&pio 7 18 GPIO_ACTIVE_HIGH>; /* PH8 */
-        cd-inverted;
-        status = "okay";
-};
-
-&mmc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&mmc2_8bit_pins>;
-        vmmc-supply = <&reg_vcc3v0>;
-        bus-width = <8>;
-        non-removable;
-        cap-mmc-hw-reset;
-        status = "okay";
-};
-
-&mmc2_8bit_pins {
-        /* Increase drive strength for DDR modes */
-        allwinner,drive = <SUN4I_PINCTRL_40_MA>;
-};
-
-&reg_usb1_vbus {
-        pinctrl-0 = <&usb1_vbus_pin_optimus>;
-        gpio = <&pio 7 4 GPIO_ACTIVE_HIGH>; /* PH4 */
-        status = "okay";
-};
-
 &r_ir {
         status = "okay";
 };
@@ -193,8 +197,135 @@
 
 &r_rsb {
         status = "okay";
+
+        axp809: pmic@3a3 {
+                reg = <0x3a3>;
+                interrupt-parent = <&nmi_intc>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+                regulators {
+                        reg_aldo1: aldo1 {
+                                /*
+                                 * TODO: This should be handled by the
+                                 * USB PHY driver.
+                                 */
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc33-usbh";
+                        };
+
+                        reg_aldo2: aldo2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-pb-io-cam";
+                        };
+
+                        aldo3 {
+                                /* unused */
+                        };
+
+                        reg_dc5ldo: dc5ldo {
+                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-cpus-09-usbh";
+                        };
+
+                        reg_dcdc1: dcdc1 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-3v";
+                        };
+
+                        reg_dcdc2: dcdc2 {
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-gpu";
+                        };
+
+                        reg_dcdc3: dcdc3 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-cpua";
+                        };
+
+                        reg_dcdc4: dcdc4 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-name = "vdd-sys-usb0-hdmi";
+                        };
+
+                        reg_dcdc5: dcdc5 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <1425000>;
+                                regulator-max-microvolt = <1575000>;
+                                regulator-name = "vcc-dram";
+                        };
+
+                        reg_dldo1: dldo1 {
+                                /*
+                                 * The WiFi chip supports a wide range
+                                 * (3.0 ~ 4.8V) of voltages, and so does
+                                 * this regulator (3.0 ~ 4.2V), but
+                                 * Allwinner SDK always sets it to 3.3V.
+                                 */
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-name = "vcc-wifi";
+                        };
+
+                        reg_dldo2: dldo2 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-pl";
+                        };
+
+                        reg_eldo1: eldo1 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-name = "vcc-dvdd-cam";
+                        };
+
+                        reg_eldo2: eldo2 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-name = "vcc-pe";
+                        };
+
+                        reg_eldo3: eldo3 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-pm-codec-io1";
+                        };
+
+                        reg_ldo_io0: ldo_io0 {
+                                regulator-always-on;
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-name = "vcc-pg";
+                        };
+
+                        reg_ldo_io1: ldo_io1 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-name = "vcc-pa-gmac-2v5";
+                        };
+
+                        reg_rtc_ldo: rtc_ldo {
+                                regulator-name = "vcc-rtc-vdd1v8-io";
+                        };
+                };
+        };
 };
 
+#include "axp809.dtsi"
+
 &uart0 {
         pinctrl-names = "default";
         pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sunxi-q8-common.dtsi b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
index b8241462fcea..b8241462fcea 100644
--- a/arch/arm/boot/dts/sunxi-q8-common.dtsi
+++ b/arch/arm/boot/dts/sunxi-reference-design-tablet.dtsi
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index c970bf65c74c..1dfc492cc004 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -1149,7 +1149,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 9d868af97b8e..70cf40996c3f 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -1020,9 +1020,9 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
index 89047edb5c5f..17dd14545862 100644
--- a/arch/arm/boot/dts/tegra114-tn7.dts
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -277,7 +277,7 @@
                 #address-cells = <1>;
                 #size-cells = <0>;
 
-                clk32k_in: clock {
+                clk32k_in: clock@0 {
                         compatible = "fixed-clock";
                         reg = <0>;
                         #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
new file mode 100644
index 000000000000..ca2c3a557895
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi
@@ -0,0 +1,1502 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/ {
+        clock@60006000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+                                nvidia,parent-clock-frequency = <408000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_P>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+                                nvidia,parent-clock-frequency = <528000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+                                nvidia,parent-clock-frequency = <600000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_C_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+                                nvidia,parent-clock-frequency = <792000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+                                nvidia,parent-clock-frequency = <924000000>;
+                                clocks = <&tegra_car TEGRA124_CLK_PLL_M_UD>;
+                                clock-names = "emc-parent";
+                        };
+                };
+        };
+
+        emc@7001b000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000 0x00000003
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000a 0x00000005
+                                        0x0000000b 0x00000000
+                                        0x00000000 0x00000003
+                                        0x00000003 0x00000000
+                                        0x00000006 0x00000006
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00010000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000c 0x0000000d
+                                        0x0000000f 0x00000060
+                                        0x00000000 0x00000018
+                                        0x00000002 0x00000002
+                                        0x00000001 0x00000000
+                                        0x00000007 0x0000000f
+                                        0x00000005 0x00000005
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000000
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00000064
+                                        0x00000000 0x00000000
+                                        0x00000000 0x106aa298
+                                        0x002c00a0 0x00008000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x000fc000 0x000fc000
+                                        0x000fc000 0x000fc000
+                                        0x0000fc00 0x0000fc00
+                                        0x0000fc00 0x0000fc00
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000e0e 0x81f1f108
+                                        0x07070004 0x0000003f
+                                        0x016eeeee 0x51451400
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x00000007 0x00000000
+                                        0x00000042 0x000e000e
+                                        0x00000000 0x00000003
+                                        0x0000f2f3 0x800001c5
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000000 0x00000005
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000a 0x00000005
+                                        0x0000000b 0x00000000
+                                        0x00000000 0x00000003
+                                        0x00000003 0x00000000
+                                        0x00000006 0x00000006
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00010000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000c 0x0000000d
+                                        0x0000000f 0x0000009a
+                                        0x00000000 0x00000026
+                                        0x00000002 0x00000002
+                                        0x00000001 0x00000000
+                                        0x00000007 0x0000000f
+                                        0x00000006 0x00000006
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000000
+                                        0x00000000 0x00000005
+                                        0x00000005 0x000000a0
+                                        0x00000000 0x00000000
+                                        0x00000000 0x106aa298
+                                        0x002c00a0 0x00008000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x000fc000 0x000fc000
+                                        0x000fc000 0x000fc000
+                                        0x0000fc00 0x0000fc00
+                                        0x0000fc00 0x0000fc00
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000e0e 0x81f1f108
+                                        0x07070004 0x0000003f
+                                        0x016eeeee 0x51451400
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x0000000b 0x00000000
+                                        0x00000042 0x000e000e
+                                        0x00000000 0x00000003
+                                        0x0000f2f3 0x8000023a
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000001 0x0000000a
+                                        0x00000000 0x00000001
+                                        0x00000000 0x00000004
+                                        0x0000000a 0x00000005
+                                        0x0000000b 0x00000000
+                                        0x00000000 0x00000003
+                                        0x00000003 0x00000000
+                                        0x00000006 0x00000006
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00010000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000c 0x0000000d
+                                        0x0000000f 0x00000134
+                                        0x00000000 0x0000004d
+                                        0x00000002 0x00000002
+                                        0x00000001 0x00000000
+                                        0x00000008 0x0000000f
+                                        0x0000000c 0x0000000c
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000000
+                                        0x00000000 0x00000005
+                                        0x00000005 0x0000013f
+                                        0x00000000 0x00000000
+                                        0x00000000 0x106aa298
+                                        0x002c00a0 0x00008000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x000fc000 0x000fc000
+                                        0x000fc000 0x000fc000
+                                        0x0000fc00 0x0000fc00
+                                        0x0000fc00 0x0000fc00
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000e0e 0x81f1f108
+                                        0x07070004 0x0000003f
+                                        0x016eeeee 0x51451400
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x00000015 0x00000000
+                                        0x00000042 0x000e000e
+                                        0x00000000 0x00000003
+                                        0x0000f2f3 0x80000370
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000003 0x00000011
+                                        0x00000000 0x00000002
+                                        0x00000000 0x00000004
+                                        0x0000000a 0x00000005
+                                        0x0000000b 0x00000000
+                                        0x00000000 0x00000003
+                                        0x00000003 0x00000000
+                                        0x00000006 0x00000006
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00010000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000c 0x0000000d
+                                        0x0000000f 0x00000202
+                                        0x00000000 0x00000080
+                                        0x00000002 0x00000002
+                                        0x00000001 0x00000000
+                                        0x0000000f 0x0000000f
+                                        0x00000013 0x00000013
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000001
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00000213
+                                        0x00000000 0x00000000
+                                        0x00000000 0x106aa298
+                                        0x002c00a0 0x00008000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x000fc000 0x000fc000
+                                        0x000fc000 0x000fc000
+                                        0x0000fc00 0x0000fc00
+                                        0x0000fc00 0x0000fc00
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000e0e 0x81f1f108
+                                        0x07070004 0x0000003f
+                                        0x016eeeee 0x51451400
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x00000022 0x00000000
+                                        0x00000042 0x000e000e
+                                        0x00000000 0x00000003
+                                        0x0000f2f3 0x8000050e
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008c5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00000000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000004 0x0000001a
+                                        0x00000000 0x00000003
+                                        0x00000001 0x00000004
+                                        0x0000000a 0x00000005
+                                        0x0000000b 0x00000001
+                                        0x00000001 0x00000003
+                                        0x00000003 0x00000000
+                                        0x00000006 0x00000006
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00010000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000004
+                                        0x0000000c 0x0000000d
+                                        0x0000000f 0x00000304
+                                        0x00000000 0x000000c1
+                                        0x00000002 0x00000002
+                                        0x00000001 0x00000000
+                                        0x00000018 0x0000000f
+                                        0x0000001c 0x0000001c
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000002
+                                        0x00000000 0x00000005
+                                        0x00000005 0x0000031c
+                                        0x00000000 0x00000000
+                                        0x00000000 0x106aa298
+                                        0x002c00a0 0x00008000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x000fc000 0x000fc000
+                                        0x000fc000 0x000fc000
+                                        0x0000fc00 0x0000fc00
+                                        0x0000fc00 0x0000fc00
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000e0e 0x81f1f108
+                                        0x07070004 0x0000003f
+                                        0x016eeeee 0x51451400
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x00000033 0x00000000
+                                        0x00000042 0x000e000e
+                                        0x00000000 0x00000003
+                                        0x0000f2f3 0x80000713
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000008>;
+                                nvidia,emc-cfg = <0x73240000>;
+                                nvidia,emc-cfg-2 = <0x000008cd>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100003>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80001221>;
+                                nvidia,emc-mrs-wait-cnt = <0x000e000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000009 0x00000035
+                                        0x00000000 0x00000006
+                                        0x00000002 0x00000005
+                                        0x0000000a 0x00000005
+                                        0x0000000b 0x00000002
+                                        0x00000002 0x00000003
+                                        0x00000003 0x00000000
+                                        0x00000005 0x00000005
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000004
+                                        0x00000006 0x00010000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000003
+                                        0x0000000d 0x0000000f
+                                        0x00000011 0x00000607
+                                        0x00000000 0x00000181
+                                        0x00000002 0x00000002
+                                        0x00000001 0x00000000
+                                        0x00000032 0x0000000f
+                                        0x00000038 0x00000038
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000006
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00000638
+                                        0x00000000 0x00000000
+                                        0x00000000 0x106aa298
+                                        0x002c00a0 0x00008000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00080000 0x00080000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00008000 0x00000000
+                                        0x00000000 0x00008000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00090000 0x00090000
+                                        0x00090000 0x00090000
+                                        0x00009000 0x00009000
+                                        0x00009000 0x00009000
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000707 0x81f1f108
+                                        0x07070004 0x0000003f
+                                        0x016eeeee 0x51451400
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x00000066 0x00000000
+                                        0x00000100 0x000e000e
+                                        0x00000000 0x00000003
+                                        0x0000d2b3 0x80000d22
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x000008d5>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000321>;
+                                nvidia,emc-mrs-wait-cnt = <0x0173000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040128>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000000d 0x0000004d
+                                        0x00000000 0x00000009
+                                        0x00000003 0x00000004
+                                        0x00000008 0x00000002
+                                        0x00000009 0x00000003
+                                        0x00000003 0x00000002
+                                        0x00000002 0x00000000
+                                        0x00000003 0x00000003
+                                        0x00000005 0x00000002
+                                        0x00000000 0x00000002
+                                        0x00000007 0x00020000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000001
+                                        0x0000000e 0x00000010
+                                        0x00000012 0x000008e4
+                                        0x00000000 0x00000239
+                                        0x00000001 0x00000008
+                                        0x00000001 0x00000000
+                                        0x0000004b 0x0000000e
+                                        0x00000052 0x00000200
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000008
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00000924
+                                        0x00000000 0x00000000
+                                        0x00000000 0x104ab098
+                                        0x002c00a0 0x00008000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00098000 0x00098000
+                                        0x00000000 0x00098000
+                                        0x00098000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00050000 0x00050000
+                                        0x00050000 0x00050000
+                                        0x00005000 0x00005000
+                                        0x00005000 0x00005000
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000505 0x81f1f108
+                                        0x07070004 0x00000000
+                                        0x016eeeee 0x51451420
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x00000096 0x00000000
+                                        0x00000100 0x0173000e
+                                        0x00000000 0x00000003
+                                        0x000052a3 0x800012d7
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73340000>;
+                                nvidia,emc-cfg-2 = <0x00000895>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200000>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000521>;
+                                nvidia,emc-mrs-wait-cnt = <0x015b000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x01231339>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000011 0x00000066
+                                        0x00000000 0x0000000c
+                                        0x00000004 0x00000004
+                                        0x00000008 0x00000002
+                                        0x0000000a 0x00000004
+                                        0x00000004 0x00000002
+                                        0x00000002 0x00000000
+                                        0x00000003 0x00000003
+                                        0x00000005 0x00000002
+                                        0x00000000 0x00000001
+                                        0x00000008 0x00020000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x0000000f 0x00000010
+                                        0x00000012 0x00000bd1
+                                        0x00000000 0x000002f4
+                                        0x00000001 0x00000008
+                                        0x00000001 0x00000000
+                                        0x00000063 0x0000000f
+                                        0x0000006c 0x00000200
+                                        0x00000004 0x00000005
+                                        0x00000004 0x0000000b
+                                        0x00000000 0x00000005
+                                        0x00000005 0x00000c11
+                                        0x00000000 0x00000000
+                                        0x00000000 0x104ab098
+                                        0x002c00a0 0x00008000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00030000 0x00030000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00070000 0x00070000
+                                        0x00000000 0x00070000
+                                        0x00070000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00038000 0x00038000
+                                        0x00038000 0x00038000
+                                        0x00003800 0x00003800
+                                        0x00003800 0x00003800
+                                        0x10000280 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc081
+                                        0x00000505 0x81f1f108
+                                        0x07070004 0x00000000
+                                        0x016eeeee 0x51451420
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0000003f
+                                        0x000000c6 0x00000000
+                                        0x00000100 0x015b000e
+                                        0x00000000 0x00000003
+                                        0x000052a3 0x8000188b
+                                        0x00000009
+                                >;
+                        };
+
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200008>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000941>;
+                                nvidia,emc-mrs-wait-cnt = <0x0139000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0123133d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000018 0x00000088
+                                        0x00000000 0x00000010
+                                        0x00000006 0x00000006
+                                        0x00000009 0x00000002
+                                        0x0000000d 0x00000006
+                                        0x00000006 0x00000002
+                                        0x00000002 0x00000000
+                                        0x00000003 0x00000003
+                                        0x00000006 0x00000002
+                                        0x00000000 0x00000001
+                                        0x00000009 0x00030000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000010 0x00000012
+                                        0x00000014 0x00000fd6
+                                        0x00000000 0x000003f5
+                                        0x00000002 0x0000000b
+                                        0x00000001 0x00000000
+                                        0x00000085 0x00000012
+                                        0x00000090 0x00000200
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000010
+                                        0x00000000 0x00000006
+                                        0x00000006 0x00001017
+                                        0x00000000 0x00000000
+                                        0x00000000 0x104ab098
+                                        0xe01200b1 0x00008000
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00054000 0x00054000
+                                        0x00000000 0x00054000
+                                        0x00054000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x0000000c 0x0000000c
+                                        0x0000000c 0x0000000c
+                                        0x0000000c 0x0000000c
+                                        0x0000000c 0x0000000c
+                                        0x100002a0 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc085
+                                        0x00000505 0x81f1f108
+                                        0x07070004 0x00000000
+                                        0x016eeeee 0x51451420
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0606003f
+                                        0x00000000 0x00000000
+                                        0x00000100 0x0139000e
+                                        0x00000000 0x00000003
+                                        0x000042a0 0x80002062
+                                        0x0000000a
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200010>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000b61>;
+                                nvidia,emc-mrs-wait-cnt = <0x0127000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040008>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0121113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000001b 0x0000009b
+                                        0x00000000 0x00000013
+                                        0x00000007 0x00000007
+                                        0x0000000b 0x00000003
+                                        0x00000010 0x00000007
+                                        0x00000007 0x00000002
+                                        0x00000002 0x00000000
+                                        0x00000005 0x00000005
+                                        0x0000000a 0x00000002
+                                        0x00000000 0x00000003
+                                        0x0000000b 0x00070000
+                                        0x00000003 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000002
+                                        0x00000012 0x00000016
+                                        0x00000018 0x00001208
+                                        0x00000000 0x00000482
+                                        0x00000002 0x0000000d
+                                        0x00000001 0x00000000
+                                        0x00000097 0x00000015
+                                        0x000000a3 0x00000200
+                                        0x00000004 0x00000005
+                                        0x00000004 0x00000013
+                                        0x00000000 0x00000006
+                                        0x00000006 0x00001248
+                                        0x00000000 0x00000000
+                                        0x00000000 0x104ab098
+                                        0xe00e00b1 0x00008000
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00048000 0x00048000
+                                        0x00000000 0x00048000
+                                        0x00048000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x0000000d 0x0000000d
+                                        0x0000000d 0x0000000d
+                                        0x0000000d 0x0000000d
+                                        0x0000000d 0x0000000d
+                                        0x100002a0 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc085
+                                        0x00000505 0x81f1f108
+                                        0x07070004 0x00000000
+                                        0x016eeeee 0x51451420
+                                        0x00514514 0x00514514
+                                        0x51451400 0x0606003f
+                                        0x00000000 0x00000000
+                                        0x00000100 0x0127000e
+                                        0x00000000 0x00000003
+                                        0x000040a0 0x800024aa
+                                        0x0000000e
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430000>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200018>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000d71>;
+                                nvidia,emc-mrs-wait-cnt = <0x00f7000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x00000042>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x00000024 0x000000cd
+                                        0x00000000 0x00000019
+                                        0x0000000a 0x00000008
+                                        0x0000000d 0x00000004
+                                        0x00000013 0x0000000a
+                                        0x0000000a 0x00000004
+                                        0x00000002 0x00000000
+                                        0x00000006 0x00000006
+                                        0x0000000b 0x00000002
+                                        0x00000000 0x00000002
+                                        0x0000000d 0x00080000
+                                        0x00000004 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000001
+                                        0x00000014 0x00000018
+                                        0x0000001a 0x000017e2
+                                        0x00000000 0x000005f8
+                                        0x00000003 0x00000011
+                                        0x00000001 0x00000000
+                                        0x000000c7 0x00000018
+                                        0x000000d7 0x00000200
+                                        0x00000005 0x00000006
+                                        0x00000005 0x00000019
+                                        0x00000000 0x00000008
+                                        0x00000008 0x00001822
+                                        0x00000000 0x00000000
+                                        0x00000000 0x104ab098
+                                        0xe00700b1 0x00008000
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x007fc008 0x007fc008
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00034000 0x00034000
+                                        0x00000000 0x00034000
+                                        0x00034000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x00000005 0x00000005
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x0000000a 0x0000000a
+                                        0x100002a0 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc085
+                                        0x00000000 0x81f1f108
+                                        0x07070004 0x00000000
+                                        0x016eeeee 0x61861820
+                                        0x00514514 0x00514514
+                                        0x61861800 0x0606003f
+                                        0x00000000 0x00000000
+                                        0x00000100 0x00f7000e
+                                        0x00000000 0x00000004
+                                        0x00004080 0x80003012
+                                        0x0000000f
+                                >;
+                        };
+
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+
+                                nvidia,emc-auto-cal-config = <0xa1430303>;
+                                nvidia,emc-auto-cal-config2 = <0x00000000>;
+                                nvidia,emc-auto-cal-config3 = <0x00000000>;
+                                nvidia,emc-auto-cal-interval = <0x001fffff>;
+                                nvidia,emc-bgbias-ctl0 = <0x00000000>;
+                                nvidia,emc-cfg = <0x73300000>;
+                                nvidia,emc-cfg-2 = <0x0000089d>;
+                                nvidia,emc-ctt-term-ctrl = <0x00000802>;
+                                nvidia,emc-mode-1 = <0x80100002>;
+                                nvidia,emc-mode-2 = <0x80200020>;
+                                nvidia,emc-mode-4 = <0x00000000>;
+                                nvidia,emc-mode-reset = <0x80000f15>;
+                                nvidia,emc-mrs-wait-cnt = <0x00cd000e>;
+                                nvidia,emc-sel-dpd-ctrl = <0x00040000>;
+                                nvidia,emc-xm2dqspadctrl2 = <0x0120113d>;
+                                nvidia,emc-zcal-cnt-long = <0x0000004c>;
+                                nvidia,emc-zcal-interval = <0x00020000>;
+
+                                nvidia,emc-configuration = <
+                                        0x0000002b 0x000000f0
+                                        0x00000000 0x0000001e
+                                        0x0000000b 0x00000009
+                                        0x0000000f 0x00000005
+                                        0x00000016 0x0000000b
+                                        0x0000000b 0x00000004
+                                        0x00000002 0x00000000
+                                        0x00000007 0x00000007
+                                        0x0000000d 0x00000002
+                                        0x00000000 0x00000002
+                                        0x0000000f 0x000a0000
+                                        0x00000004 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000001
+                                        0x00000016 0x0000001a
+                                        0x0000001c 0x00001be7
+                                        0x00000000 0x000006f9
+                                        0x00000004 0x00000015
+                                        0x00000001 0x00000000
+                                        0x000000e7 0x0000001b
+                                        0x000000fb 0x00000200
+                                        0x00000006 0x00000007
+                                        0x00000006 0x0000001e
+                                        0x00000000 0x0000000a
+                                        0x0000000a 0x00001c28
+                                        0x00000000 0x00000000
+                                        0x00000000 0x104ab898
+                                        0xe00400b1 0x00008000
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x007f800a 0x007f800a
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x0002c000 0x0002c000
+                                        0x00000000 0x0002c000
+                                        0x0002c000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000000 0x00000000
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000004 0x00000004
+                                        0x00000008 0x00000008
+                                        0x00000008 0x00000008
+                                        0x00000008 0x00000008
+                                        0x00000008 0x00000008
+                                        0x100002a0 0x00000000
+                                        0x00111111 0x00000000
+                                        0x00000000 0x77ffc085
+                                        0x00000000 0x81f1f108
+                                        0x07070004 0x00000000
+                                        0x016eeeee 0x5d75d720
+                                        0x00514514 0x00514514
+                                        0x5d75d700 0x0606003f
+                                        0x00000000 0x00000000
+                                        0x00000128 0x00cd000e
+                                        0x00000000 0x00000004
+                                        0x00004080 0x800037ea
+                                        0x00000011
+                                >;
+                        };
+
+                };
+        };
+
+        memory-controller@70019000 {
+                emc-timings-1 {
+                        nvidia,ram-code = <1>;
+
+                        timing-12750000 {
+                                clock-frequency = <12750000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40040001 0x8000000a
+                                        0x00000001 0x00000001
+                                        0x00000002 0x00000000
+                                        0x00000002 0x00000001
+                                        0x00000003 0x00000008
+                                        0x00000003 0x00000002
+                                        0x00000003 0x00000006
+                                        0x06030203 0x000a0502
+                                        0x77e30303 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-20400000 {
+                                clock-frequency = <20400000>;
+
+                                nvidia,emem-configuration = <
+                                        0x40020001 0x80000012
+                                        0x00000001 0x00000001
+                                        0x00000002 0x00000000
+                                        0x00000002 0x00000001
+                                        0x00000003 0x00000008
+                                        0x00000003 0x00000002
+                                        0x00000003 0x00000006
+                                        0x06030203 0x000a0502
+                                        0x76230303 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-40800000 {
+                                clock-frequency = <40800000>;
+
+                                nvidia,emem-configuration = <
+                                        0xa0000001 0x80000017
+                                        0x00000001 0x00000001
+                                        0x00000002 0x00000000
+                                        0x00000002 0x00000001
+                                        0x00000003 0x00000008
+                                        0x00000003 0x00000002
+                                        0x00000003 0x00000006
+                                        0x06030203 0x000a0502
+                                        0x74a30303 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-68000000 {
+                                clock-frequency = <68000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000001 0x8000001e
+                                        0x00000001 0x00000001
+                                        0x00000002 0x00000000
+                                        0x00000002 0x00000001
+                                        0x00000003 0x00000008
+                                        0x00000003 0x00000002
+                                        0x00000003 0x00000006
+                                        0x06030203 0x000a0502
+                                        0x74230403 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-102000000 {
+                                clock-frequency = <102000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000001 0x80000026
+                                        0x00000001 0x00000001
+                                        0x00000003 0x00000000
+                                        0x00000002 0x00000001
+                                        0x00000003 0x00000008
+                                        0x00000003 0x00000002
+                                        0x00000003 0x00000006
+                                        0x06030203 0x000a0503
+                                        0x73c30504 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-204000000 {
+                                clock-frequency = <204000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x01000003 0x80000040
+                                        0x00000001 0x00000001
+                                        0x00000004 0x00000002
+                                        0x00000003 0x00000001
+                                        0x00000003 0x00000008
+                                        0x00000003 0x00000002
+                                        0x00000004 0x00000006
+                                        0x06040203 0x000a0504
+                                        0x73840a05 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-300000000 {
+                                clock-frequency = <300000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x08000004 0x80000040
+                                        0x00000001 0x00000002
+                                        0x00000007 0x00000004
+                                        0x00000004 0x00000001
+                                        0x00000002 0x00000007
+                                        0x00000002 0x00000002
+                                        0x00000004 0x00000006
+                                        0x06040202 0x000b0607
+                                        0x77450e08 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-396000000 {
+                                clock-frequency = <396000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000005 0x80000040
+                                        0x00000001 0x00000002
+                                        0x00000009 0x00000005
+                                        0x00000006 0x00000001
+                                        0x00000002 0x00000008
+                                        0x00000002 0x00000002
+                                        0x00000004 0x00000006
+                                        0x06040202 0x000d0709
+                                        0x7586120a 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-528000000 {
+                                clock-frequency = <528000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0f000007 0x80000040
+                                        0x00000002 0x00000003
+                                        0x0000000c 0x00000007
+                                        0x00000008 0x00000001
+                                        0x00000002 0x00000009
+                                        0x00000002 0x00000002
+                                        0x00000005 0x00000006
+                                        0x06050202 0x0010090c
+                                        0x7428180d 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-600000000 {
+                                clock-frequency = <600000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x00000009 0x80000040
+                                        0x00000003 0x00000004
+                                        0x0000000e 0x00000009
+                                        0x0000000a 0x00000001
+                                        0x00000003 0x0000000b
+                                        0x00000002 0x00000002
+                                        0x00000005 0x00000007
+                                        0x07050202 0x00130b0e
+                                        0x73a91b0f 0x70000f03
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-792000000 {
+                                clock-frequency = <792000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0e00000b 0x80000040
+                                        0x00000004 0x00000005
+                                        0x00000013 0x0000000c
+                                        0x0000000d 0x00000002
+                                        0x00000003 0x0000000c
+                                        0x00000002 0x00000002
+                                        0x00000006 0x00000008
+                                        0x08060202 0x00170e13
+                                        0x736c2414 0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+
+                        timing-924000000 {
+                                clock-frequency = <924000000>;
+
+                                nvidia,emem-configuration = <
+                                        0x0e00000d 0x80000040
+                                        0x00000005 0x00000006
+                                        0x00000016 0x0000000e
+                                        0x0000000f 0x00000002
+                                        0x00000004 0x0000000e
+                                        0x00000002 0x00000002
+                                        0x00000006 0x00000009
+                                        0x09060202 0x001a1016
+                                        0x734e2a17 0x70000f02
+                                        0x001f0000
+                                >;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
new file mode 100644
index 000000000000..653044a44f0d
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -0,0 +1,284 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include "tegra124-apalis.dtsi"
+
+/ {
+        model = "Toradex Apalis TK1 on Apalis Evaluation Board";
+        compatible = "toradex,apalis-tk1-eval", "toradex,apalis-tk1",
+                     "nvidia,tegra124";
+
+        aliases {
+                rtc0 = "/i2c@7000c000/rtc@68";
+                rtc1 = "/i2c@7000d000/pmic@40";
+                rtc2 = "/rtc@7000e000";
+                serial0 = &uarta;
+                serial1 = &uartb;
+                serial2 = &uartc;
+                serial3 = &uartd;
+        };
+
+        chosen {
+                stdout-path = "serial0:115200n8";
+        };
+
+        pcie-controller@01003000 {
+                pci@1,0 {
+                        status = "okay";
+                };
+        };
+
+        host1x@50000000 {
+                hdmi@54280000 {
+                        status = "okay";
+                };
+        };
+
+        /* Apalis UART1 */
+        serial@70006000 {
+                status = "okay";
+        };
+
+        /* Apalis UART2 */
+        serial@70006040 {
+                status = "okay";
+        };
+
+        /* Apalis UART3 */
+        serial@70006200 {
+                status = "okay";
+        };
+
+        /* Apalis UART4 */
+        serial@70006300 {
+                status = "okay";
+        };
+
+        pwm@7000a000 {
+                status = "okay";
+        };
+
+        /*
+         * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
+         * board)
+         */
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                pcie-switch@58 {
+                        compatible = "plx,pex8605";
+                        reg = <0x58>;
+                };
+
+                /* M41T0M6 real time clock on carrier board */
+                rtc@68 {
+                        compatible = "st,m41t00";
+                        reg = <0x68>;
+                };
+        };
+
+        /*
+         * GEN2_I2C: I2C2_SDA/SCL (DDC) on MXM3 pin 205/207 (e.g. display EDID)
+         */
+        hdmi_ddc: i2c@7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        /*
+         * CAM_I2C: I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor
+         * on carrier board)
+         */
+        i2c@7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+
+        /* I2C4 (DDC): unused */
+
+        /* SPI1: Apalis SPI1 */
+        spi@7000d400 {
+                status = "okay";
+                spi-max-frequency = <50000000>;
+
+                spidev0: spidev@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+                };
+        };
+
+        /* SPI4: Apalis SPI2 */
+        spi@7000da00 {
+                status = "okay";
+                spi-max-frequency = <50000000>;
+
+                spidev1: spidev@0 {
+                        compatible = "spidev";
+                        reg = <0>;
+                        spi-max-frequency = <50000000>;
+                };
+        };
+
+        /* Apalis Serial ATA */
+        sata@70020000 {
+                status = "okay";
+        };
+
+        hda@70030000 {
+                status = "okay";
+        };
+
+        usb@70090000 {
+                status = "okay";
+        };
+
+        /* Apalis MMC1 */
+        sdhci@700b0000 {
+                status = "okay";
+                /* MMC1_CD# */
+                cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
+                bus-width = <4>;
+                vqmmc-supply = <&vddio_sdmmc1>;
+        };
+
+        /* Apalis SD1 */
+        sdhci@700b0400 {
+                status = "okay";
+                /*
+                 * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
+                 * features some magic properties even though the external
+                 * loopback is disabled and the internal loopback used as per
+                 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1 bits being
+                 * set to 0xfffd according to the TRM!
+                 * cd-gpios = <&gpio TEGRA_GPIO(EE, 4) GPIO_ACTIVE_LOW>;
+                 */
+                bus-width = <4>;
+                vqmmc-supply = <&vddio_sdmmc3>;
+        };
+
+        /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
+        usb@7d000000 {
+                status = "okay";
+                dr_mode = "otg";
+        };
+
+        usb-phy@7d000000 {
+                status = "okay";
+                vbus-supply = <&reg_usbo1_vbus>;
+        };
+
+        /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
+        usb@7d004000 {
+                status = "okay";
+        };
+
+        usb-phy@7d004000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        /* EHCI instance 2: USB3_DP/N -> USBH4_DP/N */
+        usb@7d008000 {
+                status = "okay";
+        };
+
+        usb-phy@7d008000 {
+                status = "okay";
+                vbus-supply = <&reg_usbh_vbus>;
+        };
+
+        backlight: backlight {
+                compatible = "pwm-backlight";
+
+                /* BKL1_PWM */
+                pwms = <&pwm 3 5000000>;
+                brightness-levels = <255 231 223 207 191 159 127 0>;
+                default-brightness-level = <6>;
+                /* BKL1_ON */
+                enable-gpios = <&gpio TEGRA_GPIO(BB, 5) GPIO_ACTIVE_HIGH>;
+        };
+
+        gpio-keys {
+                compatible = "gpio-keys";
+
+                wakeup {
+                        label = "WAKE1_MICO";
+                        gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_WAKEUP>;
+                        debounce-interval = <10>;
+                        wakeup-source;
+                };
+        };
+
+        reg_5v0: regulator-5v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "5V_SW";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+        };
+
+        /* USBO1_EN */
+        reg_usbo1_vbus: regulator-usbo1-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBO1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+
+        /* USBH_EN */
+        reg_usbh_vbus: regulator-usbh-vbus {
+                compatible = "regulator-fixed";
+                regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_5v0>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi
new file mode 100644
index 000000000000..e7a73db17613
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis.dtsi
@@ -0,0 +1,2100 @@
+/*
+ * Copyright 2016 Toradex AG
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License
+ *     version 2 as published by the Free Software Foundation.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "tegra124.dtsi"
+#include "tegra124-apalis-emc.dtsi"
+
+/*
+ * Toradex Apalis TK1 Module Device Tree
+ * Compatible for Revisions 2GB: V1.0A
+ */
+/ {
+        model = "Toradex Apalis TK1";
+        compatible = "toradex,apalis-tk1", "nvidia,tegra124";
+
+        memory {
+                reg = <0x0 0x80000000 0x0 0x80000000>;
+        };
+
+        pcie-controller@01003000 {
+                status = "okay";
+
+                avddio-pex-supply = <&vdd_1v05>;
+                avdd-pex-pll-supply = <&vdd_1v05>;
+                avdd-pll-erefe-supply = <&avdd_1v05>;
+                dvddio-pex-supply = <&vdd_1v05>;
+                hvdd-pex-pll-e-supply = <&reg_3v3>;
+                hvdd-pex-supply = <&reg_3v3>;
+                vddio-pex-ctl-supply = <&reg_3v3>;
+
+                /* Apalis PCIe (additional lane Apalis type specific) */
+                pci@1,0 {
+                        /* PCIE1_RX/TX and TS_DIFF1/2 */
+                        phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
+                               <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
+                        phy-names = "pcie-0", "pcie-1";
+                };
+
+                /* I210 Gigabit Ethernet Controller (On-module) */
+                pci@2,0 {
+                        phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
+                        phy-names = "pcie-0";
+                        status = "okay";
+                };
+        };
+
+        host1x@50000000 {
+                hdmi@54280000 {
+                        pll-supply = <&reg_1v05_avdd_hdmi_pll>;
+                        vdd-supply = <&reg_3v3_avdd_hdmi>;
+
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+        };
+
+        gpu@0,57000000 {
+                /*
+                 * Node left disabled on purpose - the bootloader will enable
+                 * it after having set the VPR up
+                 */
+                vdd-supply = <&vdd_gpu>;
+        };
+
+        pinmux: pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        /* Analogue Audio (On-module) */
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis BKL1_ON */
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "vgp5";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis BKL1_PWM */
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,function = "pwm3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis CAM1_MCLK */
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis Digital Audio */
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "hda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb3 { /* DAP1_RESET */
+                                nvidia,pins = "pbb3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis GPIO */
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_rst_n_pdd1 {
+                                nvidia,pins = "pex_l0_rst_n_pdd1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l0_clkreq_n_pdd2 {
+                                nvidia,pins = "pex_l0_clkreq_n_pdd2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_rst_n_pdd5 {
+                                nvidia,pins = "pex_l1_rst_n_pdd5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pex_l1_clkreq_n_pdd6 {
+                                nvidia,pins = "pex_l1_clkreq_n_pdd6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dp_hpd_pff0 {
+                                nvidia,pins = "dp_hpd_pff0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis HDMI1_CEC */
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis HDMI1_HPD */
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis I2C1 */
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C2 (DDC) */
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis I2C3 (CAM) */
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis MMC1 */
+                        sdmmc1_cd_n_pv3 { /* CD# GPIO */
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_out_pw5 { /* D5 GPIO */
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 { /* D4 GPIO */
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /*
+                         * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
+                         * features some magic properties even though the
+                         * external loopback is disabled and the internal
+                         * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
+                         * register's SDMMC_SPARE1 bits being set to 0xfffd
+                         * according to the TRM!
+                         */
+                        sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en2_pff1 { /* D7 GPIO */
+                                nvidia,pins = "usb_vbus_en2_pff1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis PWM */
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* PWM3 active on pu6 being Apalis BKL1_PWM */
+                        ph3 {
+                                nvidia,pins = "ph3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SATA1_ACT# */
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SD1 */
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /*
+                         * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
+                         * features some magic properties even though the
+                         * external loopback is disabled and the internal
+                         * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
+                         * register's SDMMC_SPARE1 bits being set to 0xfffd
+                         * according to the TRM!
+                         */
+                        sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SPDIF */
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis SPI1 */
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis SPI2 */
+                        pg5 {
+                                nvidia,pins = "pg5";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART1 */
+                        pb1 { /* DCD GPIO */
+                                nvidia,pins = "pb1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk7 { /* RI GPIO */
+                                nvidia,pins = "pk7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart1_txd_pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart1_rxd_pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart1_cts_n_pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart1_rts_n_pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_cts_n_pa1 { /* DSR GPIO */
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 { /* DTR GPIO */
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART2 */
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis UART3 */
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis UART4 */
+                        uart4_rxd_pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart4_txd_pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_EN */
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBH_OC# */
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vgp6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis USBO1_EN */
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Apalis USBO1_OC# */
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* Apalis WAKE1_MICO */
+                        pex_wake_n_pdd3 {
+                                nvidia,pins = "pex_wake_n_pdd3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* CORE_PWR_REQ */
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* CPU_PWR_REQ */
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* DVFS */
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* eMMC */
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* JTAG_RTCK */
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN_DEV_OFF# */
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN_RESET# */
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* LAN_WAKE# */
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT1# */
+                        pk2 {
+                                nvidia,pins = "pk2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT2# */
+                        pj2 {
+                                nvidia,pins = "pj2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT3# */
+                        pi5 {
+                                nvidia,pins = "pi5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_INT4# */
+                        pj0 {
+                                nvidia,pins = "pj0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* MCU_RESET */
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* MCU SPI */
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x5_aud_px5 {
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x6_aud_px6 { /* MCU_CS */
+                                nvidia,pins = "gpio_x6_aud_px6";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_w2_aud_pw2 { /* MCU_CSEZP */
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "spi2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* PMIC_CLK_32K */
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "clk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* PMIC_CPU_OC_INT */
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* PWR_I2C */
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* PWR_INT_N */
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* RESET_MOCI_CTRL */
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* RESET_OUT_N */
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* SHIFT_CTRL_DIR_IN */
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* Configure level-shifter as output for HDA */
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* SHIFT_CTRL_DIR_OUT */
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* SHIFT_CTRL_OE */
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+
+                        /* GPIO_PI6 aka TEMP_ALERT_L */
+                        pi6 {
+                                nvidia,pins = "pi6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        /* TOUCH_INT */
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+
+                        pc7 { /* NC */
+                                nvidia,pins = "pc7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg0 { /* NC */
+                                nvidia,pins = "pg0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg1 { /* NC */
+                                nvidia,pins = "pg1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg2 { /* NC */
+                                nvidia,pins = "pg2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg3 { /* NC */
+                                nvidia,pins = "pg3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg4 { /* NC */
+                                nvidia,pins = "pg4";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 { /* NC */
+                                nvidia,pins = "ph4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph5 { /* NC */
+                                nvidia,pins = "ph5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 { /* NC */
+                                nvidia,pins = "ph6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph7 { /* NC */
+                                nvidia,pins = "ph7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi0 { /* NC */
+                                nvidia,pins = "pi0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi1 { /* NC */
+                                nvidia,pins = "pi1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi2 { /* NC */
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 { /* NC */
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi7 { /* NC */
+                                nvidia,pins = "pi7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk0 { /* NC */
+                                nvidia,pins = "pk0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk1 { /* NC */
+                                nvidia,pins = "pk1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk3 { /* NC */
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk4 { /* NC */
+                                nvidia,pins = "pk4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_fs_pn0 { /* NC */
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 { /* NC */
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 { /* NC */
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 { /* NC */
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data0_po1 { /* NC */
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data1_po2 { /* NC */
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data2_po3 { /* NC */
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data3_po4 { /* NC */
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 { /* NC */
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 { /* NC */
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_din_pp5 { /* NC */
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_dout_pp6 { /* NC */
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_sclk_pp7 { /* NC */
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col3_pq3 { /* NC */
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 { /* NC */
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 { /* NC */
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row5_pr5 { /* NC */
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 { /* NC */
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row7_pr7 { /* NC */
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row8_ps0 { /* NC */
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row9_ps1 { /* NC */
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 { /* NC */
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row13_ps5 { /* NC */
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row14_ps6 { /* NC */
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 { /* NC */
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row16_pt0 { /* NC */
+                                nvidia,pins = "kb_row16_pt0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 { /* NC */
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu5 { /* NC */
+                                nvidia,pins = "pu5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv0 { /* NC */
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv1 { /* NC */
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 { /* NC */
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 { /* NC */
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x3_aud_px3 { /* NC */
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 { /* NC */
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 { /* NC */
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc2 { /* NC */
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 { /* NC */
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 { /* NC */
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                };
+        };
+
+        serial@70006040 {
+                compatible = "nvidia,tegra124-hsuart";
+        };
+
+        serial@70006200 {
+                compatible = "nvidia,tegra124-hsuart";
+        };
+
+        serial@70006300 {
+                compatible = "nvidia,tegra124-hsuart";
+        };
+
+        hdmi_ddc: i2c@7000c400 {
+                clock-frequency = <100000>;
+        };
+
+        /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+
+                /* SGTL5000 audio codec */
+                sgtl5000: codec@0a {
+                        compatible = "fsl,sgtl5000";
+                        reg = <0x0a>;
+                        VDDA-supply = <&reg_3v3>;
+                        VDDIO-supply = <&vddio_1v8>;
+                        clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
+                };
+
+                pmic: pmic@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+                        ams,system-power-controller;
+
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+
+                        gpio-controller;
+                        #gpio-cells = <2>;
+
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+
+                        as3722_default: pinmux {
+                                gpio2_7 {
+                                        pins = "gpio2", /* PWR_EN_+V3.3 */
+                                               "gpio7"; /* +V1.6_LPO */
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+
+                                gpio1_3_4_5_6 {
+                                        pins = "gpio1", "gpio3", "gpio4",
+                                               "gpio5", "gpio6";
+                                        bias-high-impedance;
+                                };
+                        };
+
+                        regulators {
+                                vsup-sd2-supply = <&reg_3v3>;
+                                vsup-sd3-supply = <&reg_3v3>;
+                                vsup-sd4-supply = <&reg_3v3>;
+                                vsup-sd5-supply = <&reg_3v3>;
+                                vin-ldo0-supply = <&vddio_ddr_1v35>;
+                                vin-ldo1-6-supply = <&reg_3v3>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
+                                vin-ldo3-4-supply = <&reg_3v3>;
+                                vin-ldo9-10-supply = <&reg_3v3>;
+                                vin-ldo11-supply = <&reg_3v3>;
+
+                                vdd_cpu: sd0 {
+                                        regulator-name = "+VDD_CPU_AP";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <2>;
+                                };
+
+                                sd1 {
+                                        regulator-name = "+VDD_CORE";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <4000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                vddio_ddr_1v35: sd2 {
+                                        regulator-name =
+                                                "+V1.35_VDDIO_DDR(sd2)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                sd3 {
+                                        regulator-name =
+                                                "+V1.35_VDDIO_DDR(sd3)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+
+                                vdd_1v05: sd4 {
+                                        regulator-name = "+V1.05";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+
+                                vddio_1v8: sd5 {
+                                        regulator-name = "+V1.8";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                vdd_gpu: sd6 {
+                                        regulator-name = "+VDD_GPU_AP";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                avdd_1v05: ldo0 {
+                                        regulator-name = "+V1.05_AVDD";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,ext-control = <1>;
+                                };
+
+                                vddio_sdmmc1: ldo1 {
+                                        regulator-name = "VDDIO_SDMMC1";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                ldo2 {
+                                        regulator-name = "+V1.2";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+
+                                ldo3 {
+                                        regulator-name = "+V1.05_RTC";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+
+                                /* 1.8V for LVDS, 3.3V for eDP */
+                                ldo4 {
+                                        regulator-name = "AVDD_LVDS0_PLL";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+
+                                /* LDO5 not used */
+
+                                vddio_sdmmc3: ldo6 {
+                                        regulator-name = "VDDIO_SDMMC3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+
+                                /* LDO7 not used */
+
+                                ldo9 {
+                                        regulator-name = "+V3.3_ETH(ldo9)";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo10 {
+                                        regulator-name = "+V3.3_ETH(ldo10)";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+
+                                ldo11 {
+                                        regulator-name = "+V1.8_VPP_FUSE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+
+                /*
+                 * TMP451 temperature sensor
+                 * Note: THERM_N directly connected to AS3722 PMIC THERM
+                 */
+                temperature-sensor@4c {
+                        compatible = "ti,tmp451";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+
+                        #thermal-sensor-cells = <1>;
+                };
+        };
+
+        /* SPI2: MCU SPI */
+        spi@7000d600 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+        };
+
+        pmc@7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <1>;
+                nvidia,cpu-pwr-good-time = <500>;
+                nvidia,cpu-pwr-off-time = <300>;
+                nvidia,core-pwr-good-time = <641 3845>;
+                nvidia,core-pwr-off-time = <61036>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+
+                /* Set power_off bit in ResetControl register of AS3722 PMIC */
+                i2c-thermtrip {
+                        nvidia,i2c-controller-id = <4>;
+                        nvidia,bus-addr = <0x40>;
+                        nvidia,reg-addr = <0x36>;
+                        nvidia,reg-data = <0x2>;
+                };
+        };
+
+        sata@70020000 {
+                phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
+                phy-names = "sata-0";
+
+                avdd-supply = <&vdd_1v05>;
+                hvdd-supply = <&reg_3v3>;
+                vddio-supply = <&vdd_1v05>;
+        };
+
+        usb@70090000 {
+                /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
+                phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
+                phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
+
+                avddio-pex-supply = <&vdd_1v05>;
+                avdd-pll-erefe-supply = <&avdd_1v05>;
+                avdd-pll-utmip-supply = <&vddio_1v8>;
+                avdd-usb-ss-pll-supply = <&vdd_1v05>;
+                avdd-usb-supply = <&reg_3v3>;
+                dvddio-pex-supply = <&vdd_1v05>;
+                hvdd-usb-ss-pll-e-supply = <&reg_3v3>;
+                hvdd-usb-ss-supply = <&reg_3v3>;
+        };
+
+        padctl@7009f000 {
+                pads {
+                        usb2 {
+                                status = "okay";
+
+                                lanes {
+                                        usb2-0 {
+                                                nvidia,function = "xusb";
+                                                status = "okay";
+                                        };
+
+                                        usb2-1 {
+                                                nvidia,function = "xusb";
+                                                status = "okay";
+                                        };
+
+                                        usb2-2 {
+                                                nvidia,function = "xusb";
+                                                status = "okay";
+                                        };
+                                };
+                        };
+
+                        pcie {
+                                status = "okay";
+
+                                lanes {
+                                        pcie-0 {
+                                                nvidia,function = "usb3-ss";
+                                                status = "okay";
+                                        };
+
+                                        pcie-1 {
+                                                nvidia,function = "usb3-ss";
+                                                status = "okay";
+                                        };
+
+                                        pcie-2 {
+                                                nvidia,function = "pcie";
+                                                status = "okay";
+                                        };
+
+                                        pcie-3 {
+                                                nvidia,function = "pcie";
+                                                status = "okay";
+                                        };
+
+                                        pcie-4 {
+                                                nvidia,function = "pcie";
+                                                status = "okay";
+                                        };
+                                };
+                        };
+
+                        sata {
+                                status = "okay";
+
+                                lanes {
+                                        sata-0 {
+                                                nvidia,function = "sata";
+                                                status = "okay";
+                                        };
+                                };
+                        };
+                };
+
+                ports {
+                        /* USBO1 */
+                        usb2-0 {
+                                status = "okay";
+                                mode = "otg";
+
+                                vbus-supply = <&reg_usbo1_vbus>;
+                        };
+
+                        /* USBH2 */
+                        usb2-1 {
+                                status = "okay";
+                                mode = "host";
+
+                                vbus-supply = <&reg_usbh_vbus>;
+                        };
+
+                        /* USBH4 */
+                        usb2-2 {
+                                status = "okay";
+                                mode = "host";
+
+                                vbus-supply = <&reg_usbh_vbus>;
+                        };
+
+                        usb3-0 {
+                                nvidia,usb2-companion = <2>;
+                                status = "okay";
+                        };
+
+                        usb3-1 {
+                                nvidia,usb2-companion = <0>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        /* eMMC */
+        sdhci@700b0600 {
+                status = "okay";
+                bus-width = <8>;
+                non-removable;
+        };
+
+        /* CPU DFLL clock */
+        clock@70110000 {
+                status = "okay";
+                vdd-cpu-supply = <&vdd_cpu>;
+                nvidia,i2c-fs-rate = <400000>;
+        };
+
+        ahub@70300000 {
+                i2s@70301200 {
+                        status = "okay";
+                };
+        };
+
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+
+        cpus {
+                cpu@0 {
+                        vdd-cpu-supply = <&vdd_cpu>;
+                };
+        };
+
+        reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
+                compatible = "regulator-fixed";
+                regulator-name = "+V1.05_AVDD_HDMI_PLL";
+                regulator-min-microvolt = <1050000>;
+                regulator-max-microvolt = <1050000>;
+                gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                vin-supply = <&vdd_1v05>;
+        };
+
+        reg_3v3_mxm: regulator-3v3-mxm {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_MXM";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+
+        reg_3v3: regulator-3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+                /* PWR_EN_+V3.3 */
+                gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                enable-active-high;
+                vin-supply = <&reg_3v3_mxm>;
+        };
+
+        reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
+                compatible = "regulator-fixed";
+                regulator-name = "+V3.3_AVDD_HDMI";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vdd_1v05>;
+        };
+
+        sound {
+                compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
+                             "nvidia,tegra-audio-sgtl5000";
+                nvidia,model = "Toradex Apalis TK1";
+                nvidia,audio-routing =
+                        "Headphone Jack", "HP_OUT",
+                        "LINE_IN", "Line In Jack",
+                        "MIC_IN", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s2>;
+                nvidia,audio-codec = <&sgtl5000>;
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
+
+        thermal-zones {
+                cpu {
+                        trips {
+                                trip@0 {
+                                        temperature = <101000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                /*
+                                 * There are currently no cooling maps because
+                                 * there are no cooling devices
+                                 */
+                        };
+                };
+
+                mem {
+                        trips {
+                                trip@0 {
+                                        temperature = <101000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                /*
+                                 * There are currently no cooling maps because
+                                 * there are no cooling devices
+                                 */
+                        };
+                };
+
+                gpu {
+                        trips {
+                                trip@0 {
+                                        temperature = <101000>;
+                                        hysteresis = <0>;
+                                        type = "critical";
+                                };
+                        };
+
+                        cooling-maps {
+                                /*
+                                 * There are currently no cooling maps because
+                                 * there are no cooling devices
+                                 */
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
index 2c5cede686dc..accb7055165a 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi
@@ -1,5 +1,5 @@
 / {
-        clock@0,60006000 {
+        clock@60006000 {
                 emc-timings-3 {
                         nvidia,ram-code = <3>;
 
@@ -78,7 +78,7 @@
                 };
         };
 
-        emc@0,7001b000 {
+        emc@7001b000 {
                 emc-timings-3 {
                         nvidia,ram-code = <3>;
 
@@ -2101,7 +2101,7 @@
                 };
         };
 
-        memory-controller@0,70019000 {
+        memory-controller@70019000 {
                 emc-timings-3 {
                         nvidia,ram-code = <3>;
 
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index 941f36263c8f..e52b82449a79 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -10,8 +10,8 @@
         compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
 
         aliases {
-                rtc0 = "/i2c@0,7000d000/pmic@40";
-                rtc1 = "/rtc@0,7000e000";
+                rtc0 = "/i2c@7000d000/pmic@40";
+                rtc1 = "/rtc@7000e000";
 
                 /* This order keeps the mapping DB9 connector <-> ttyS0 */
                 serial0 = &uartd;
@@ -27,7 +27,7 @@
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
-        pcie-controller@0,01003000 {
+        pcie-controller@01003000 {
                 status = "okay";
 
                 avddio-pex-supply = <&vdd_1v05_run>;
@@ -40,21 +40,21 @@
 
                 /* Mini PCIe */
                 pci@1,0 {
-                        phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-4}>;
+                        phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>;
                         phy-names = "pcie-0";
                         status = "okay";
                 };
 
                 /* Gigabit Ethernet */
                 pci@2,0 {
-                        phys = <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-2}>;
+                        phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
                         phy-names = "pcie-0";
                         status = "okay";
                 };
         };
 
-        host1x@0,50000000 {
-                hdmi@0,54280000 {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         hdmi-supply = <&vdd_5v0_hdmi>;
@@ -75,7 +75,7 @@
                 vdd-supply = <&vdd_gpu>;
         };
 
-        pinmux: pinmux@0,70000868 {
+        pinmux: pinmux@70000868 {
                 pinctrl-names = "boot";
                 pinctrl-0 = <&state_boot>;
 
@@ -1356,14 +1356,6 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
                         };
-                        owr {
-                                nvidia,pins = "owr";
-                                nvidia,function = "rsvd2";
-                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
-                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
-                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
-                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
-                        };
                         clk_32k_in {
                                 nvidia,pins = "clk_32k_in";
                                 nvidia,function = "clk";
@@ -1378,6 +1370,10 @@
                                 nvidia,tristate = <TEGRA_PIN_DISABLE>;
                                 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
                         };
+                        dsi_b {
+                                nvidia,pins = "mipi_pad_ctrl_dsi_b";
+                                nvidia,function = "dsi_b";
+                        };
                 };
         };
 
@@ -1404,12 +1400,12 @@
         };
 
         /* DB9 serial port */
-        serial@0,70006300 {
+        serial@70006300 {
                 status = "okay";
         };
 
         /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
-        i2c@0,7000c000 {
+        i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
 
@@ -1437,25 +1433,25 @@
         };
 
         /* Expansion GEN2_I2C_* */
-        i2c@0,7000c400 {
+        i2c@7000c400 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
 
         /* Expansion CAM_I2C_* */
-        i2c@0,7000c500 {
+        i2c@7000c500 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
 
         /* HDMI DDC */
-        hdmi_ddc: i2c@0,7000c700 {
+        hdmi_ddc: i2c@7000c700 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
 
         /* Expansion PWR_I2C_*, on-board components */
-        i2c@0,7000d000 {
+        i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
 
@@ -1646,12 +1642,12 @@
         };
 
         /* Expansion TS_SPI_* */
-        spi@0,7000d400 {
+        spi@7000d400 {
                 status = "okay";
         };
 
         /* Internal SPI */
-        spi@0,7000da00 {
+        spi@7000da00 {
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@0 {
@@ -1661,7 +1657,7 @@
                 };
         };
 
-        pmc@0,7000e400 {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <500>;
@@ -1680,10 +1676,10 @@
         };
 
         /* Serial ATA */
-        sata@0,70020000 {
+        sata@70020000 {
                 status = "okay";
 
-                phys = <&{/padctl@0,7009f000/pads/sata/lanes/sata-0}>;
+                phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
                 phy-names = "sata-0";
 
                 hvdd-supply = <&vdd_3v3_lp0>;
@@ -1694,15 +1690,15 @@
                 target-12v-supply = <&vdd_12v0_sata>;
         };
 
-        hda@0,70030000 {
+        hda@70030000 {
                 status = "okay";
         };
 
-        usb@0,70090000 {
-                phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
-                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
-                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
-                       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
+        usb@70090000 {
+                phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* Micro A/B */
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Mini PCIe */
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* USB3 */
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>; /* USB3 */
                 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0";
 
                 avddio-pex-supply = <&vdd_1v05_run>;
@@ -1717,7 +1713,7 @@
                 status = "okay";
         };
 
-        padctl@0,7009f000 {
+        padctl@7009f000 {
                 status = "okay";
 
                 pads {
@@ -1804,7 +1800,7 @@
         };
 
         /* SD card */
-        sdhci@0,700b0400 {
+        sdhci@700b0400 {
                 status = "okay";
                 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -1814,40 +1810,40 @@
         };
 
         /* eMMC */
-        sdhci@0,700b0600 {
+        sdhci@700b0600 {
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
         };
 
         /* CPU DFLL clock */
-        clock@0,70110000 {
+        clock@70110000 {
                 status = "okay";
                 vdd-cpu-supply = <&vdd_cpu>;
                 nvidia,i2c-fs-rate = <400000>;
         };
 
-        ahub@0,70300000 {
-                i2s@0,70301100 {
+        ahub@70300000 {
+                i2s@70301100 {
                         status = "okay";
                 };
         };
 
         /* mini-PCIe USB */
-        usb@0,7d004000 {
+        usb@7d004000 {
                 status = "okay";
         };
 
-        usb-phy@0,7d004000 {
+        usb-phy@7d004000 {
                 status = "okay";
         };
 
         /* USB A connector */
-        usb@0,7d008000 {
+        usb@7d008000 {
                 status = "okay";
         };
 
-        usb-phy@0,7d008000 {
+        usb-phy@7d008000 {
                 status = "okay";
                 vbus-supply = <&vdd_usb3_vbus>;
         };
@@ -2049,7 +2045,7 @@
         thermal-zones {
                 cpu {
                         trips {
-                                trip@0 {
+                                trip {
                                         temperature = <101000>;
                                         hysteresis = <0>;
                                         type = "critical";
@@ -2063,7 +2059,7 @@
 
                 mem {
                         trips {
-                                trip@0 {
+                                trip {
                                         temperature = <101000>;
                                         hysteresis = <0>;
                                         type = "critical";
@@ -2077,7 +2073,7 @@
 
                 gpu {
                         trips {
-                                trip@0 {
+                                trip {
                                         temperature = <101000>;
                                         hysteresis = <0>;
                                         type = "critical";
diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
index 1a5748d05dda..4458e86b2769 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi
@@ -1,5 +1,5 @@
 / {
-        clock@0,60006000 {
+        clock@60006000 {
                 emc-timings-1 {
                         nvidia,ram-code = <1>;
 
@@ -67,7 +67,7 @@
                 };
         };
 
-        emc@0,7001b000 {
+        emc@7001b000 {
                 emc-timings-1 {
                         nvidia,ram-code = <1>;
 
@@ -1754,7 +1754,7 @@
                 };
         };
 
-        memory-controller@0,70019000 {
+        memory-controller@70019000 {
                 emc-timings-1 {
                         nvidia,ram-code = <1>;
 
diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts
index 2d21253ea4e3..67d7cfb32541 100644
--- a/arch/arm/boot/dts/tegra124-nyan-big.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-big.dts
@@ -15,7 +15,7 @@
                 ddc-i2c-bus = <&dpaux>;
         };
 
-        sdhci@0,700b0400 { /* SD Card on this bus */
+        sdhci@700b0400 { /* SD Card on this bus */
                 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
         };
 
@@ -26,7 +26,7 @@
                 nvidia,model = "GoogleNyanBig";
         };
 
-        pinmux@0,70000868 {
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinmux_default>;
 
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
index 9ecd108f56cf..4e7b59e25728 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi
@@ -1,5 +1,5 @@
 / {
-        clock@0,60006000 {
+        clock@60006000 {
                 emc-timings-1 {
                         nvidia,ram-code = <1>;
 
@@ -67,7 +67,7 @@
                 };
         };
 
-        emc@0,7001b000 {
+        emc@7001b000 {
                 emc-timings-1 {
                         nvidia,ram-code = <1>;
 
@@ -1754,7 +1754,7 @@
                 };
         };
 
-        memory-controller@0,70019000 {
+        memory-controller@70019000 {
                 emc-timings-1 {
                         nvidia,ram-code = <1>;
 
diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
index 0d30c514ffad..c9582361c26e 100644
--- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts
+++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts
@@ -22,7 +22,7 @@
                 nvidia,model = "GoogleNyanBlaze";
         };
 
-        pinmux@0,70000868 {
+        pinmux@70000868 {
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinmux_default>;
 
diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi
index 0710a600cc69..271505e0715f 100644
--- a/arch/arm/boot/dts/tegra124-nyan.dtsi
+++ b/arch/arm/boot/dts/tegra124-nyan.dtsi
@@ -3,8 +3,8 @@
 
 / {
         aliases {
-                rtc0 = "/i2c@0,7000d000/pmic@40";
-                rtc1 = "/rtc@0,7000e000";
+                rtc0 = "/i2c@7000d000/pmic@40";
+                rtc1 = "/rtc@7000e000";
                 serial0 = &uarta;
         };
 
@@ -16,8 +16,8 @@
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
-        host1x@0,50000000 {
-                hdmi@0,54280000 {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&vdd_3v3_hdmi>;
@@ -29,29 +29,29 @@
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
                 };
 
-                sor@0,54540000 {
+                sor@54540000 {
                         status = "okay";
 
                         nvidia,dpaux = <&dpaux>;
                         nvidia,panel = <&panel>;
                 };
 
-                dpaux@0,545c0000 {
+                dpaux@545c0000 {
                         vdd-supply = <&vdd_3v3_panel>;
                         status = "okay";
                 };
         };
 
-        serial@0,70006000 {
+        serial@70006000 {
                 /* Debug connector on the bottom of the board near SD card. */
                 status = "okay";
         };
 
-        pwm@0,7000a000 {
+        pwm@7000a000 {
                 status = "okay";
         };
 
-        i2c@0,7000c000 {
+        i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
 
@@ -72,7 +72,7 @@
                 };
         };
 
-        i2c@0,7000c400 {
+        i2c@7000c400 {
                 status = "okay";
                 clock-frequency = <100000>;
 
@@ -85,7 +85,7 @@
                 };
         };
 
-        i2c@0,7000c500 {
+        i2c@7000c500 {
                 status = "okay";
                 clock-frequency = <400000>;
 
@@ -95,12 +95,12 @@
                 };
         };
 
-        hdmi_ddc: i2c@0,7000c700 {
+        hdmi_ddc: i2c@7000c700 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
 
-        i2c@0,7000d000 {
+        i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
 
@@ -301,7 +301,7 @@
                 };
         };
 
-        spi@0,7000d400 {
+        spi@7000d400 {
                 status = "okay";
 
                 cros_ec: cros-ec@0 {
@@ -342,7 +342,7 @@
                 };
         };
 
-        spi@0,7000da00 {
+        spi@7000da00 {
                 status = "okay";
                 spi-max-frequency = <25000000>;
 
@@ -353,7 +353,7 @@
                 };
         };
 
-        pmc@0,7000e400 {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <0>;
                 nvidia,cpu-pwr-good-time = <500>;
@@ -364,16 +364,16 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        hda@0,70030000 {
+        hda@70030000 {
                 status = "okay";
         };
 
-        usb@0,70090000 {
-                phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
-                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
-                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
-                       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
-                       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
+        usb@70090000 {
+                phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
                 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
 
                 avddio-pex-supply = <&vdd_1v05_run>;
@@ -388,7 +388,7 @@
                 status = "okay";
         };
 
-        padctl@0,7009f000 {
+        padctl@7009f000 {
                 status = "okay";
 
                 pads {
@@ -467,7 +467,7 @@
                 reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
         };
 
-        sdhci@0,700b0000 { /* WiFi/BT on this bus */
+        sdhci@700b0000 { /* WiFi/BT on this bus */
                 status = "okay";
                 bus-width = <4>;
                 no-1-8-v;
@@ -478,7 +478,7 @@
                 keep-power-in-suspend;
         };
 
-        sdhci@0,700b0400 { /* SD Card on this bus */
+        sdhci@700b0400 { /* SD Card on this bus */
                 status = "okay";
                 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
                 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -487,7 +487,7 @@
                 vqmmc-supply = <&vddio_sdmmc3>;
         };
 
-        sdhci@0,700b0600 { /* eMMC on this bus */
+        sdhci@700b0600 { /* eMMC on this bus */
                 status = "okay";
                 bus-width = <8>;
                 no-1-8-v;
@@ -495,14 +495,14 @@
         };
 
         /* CPU DFLL clock */
-        clock@0,70110000 {
+        clock@70110000 {
                 status = "disabled";
                 vdd-cpu-supply = <&vdd_cpu>;
                 nvidia,i2c-fs-rate = <400000>;
         };
 
-        ahub@0,70300000 {
-                i2s@0,70301100 {
+        ahub@70300000 {
+                i2s@70301100 {
                         status = "okay";
                 };
         };
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index 973446d07182..6e59cec0962b 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -8,8 +8,8 @@
         compatible = "nvidia,venice2", "nvidia,tegra124";
 
         aliases {
-                rtc0 = "/i2c@0,7000d000/pmic@40";
-                rtc1 = "/rtc@0,7000e000";
+                rtc0 = "/i2c@7000d000/pmic@40";
+                rtc1 = "/rtc@7000e000";
                 serial0 = &uarta;
         };
 
@@ -21,8 +21,8 @@
                 reg = <0x0 0x80000000 0x0 0x80000000>;
         };
 
-        host1x@0,50000000 {
-                hdmi@0,54280000 {
+        host1x@50000000 {
+                hdmi@54280000 {
                         status = "okay";
 
                         vdd-supply = <&vdd_3v3_hdmi>;
@@ -34,14 +34,14 @@
                                 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
                 };
 
-                sor@0,54540000 {
+                sor@54540000 {
                         status = "okay";
 
                         nvidia,dpaux = <&dpaux>;
                         nvidia,panel = <&panel>;
                 };
 
-                dpaux@0,545c0000 {
+                dpaux@545c0000 {
                         vdd-supply = <&vdd_3v3_panel>;
                         status = "okay";
                 };
@@ -55,7 +55,7 @@
                 vdd-supply = <&vdd_gpu>;
         };
 
-        pinmux: pinmux@0,70000868 {
+        pinmux: pinmux@70000868 {
                 pinctrl-names = "boot";
                 pinctrl-0 = <&pinmux_boot>;
 
@@ -596,15 +596,15 @@
                 };
         };
 
-        serial@0,70006000 {
+        serial@70006000 {
                 status = "okay";
         };
 
-        pwm@0,7000a000 {
+        pwm@7000a000 {
                 status = "okay";
         };
 
-        i2c@0,7000c000 {
+        i2c@7000c000 {
                 status = "okay";
                 clock-frequency = <100000>;
 
@@ -616,7 +616,7 @@
                 };
         };
 
-        i2c@0,7000c400 {
+        i2c@7000c400 {
                 status = "okay";
                 clock-frequency = <100000>;
 
@@ -629,17 +629,17 @@
                 };
         };
 
-        i2c@0,7000c500 {
+        i2c@7000c500 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
 
-        hdmi_ddc: i2c@0,7000c700 {
+        hdmi_ddc: i2c@7000c700 {
                 status = "okay";
                 clock-frequency = <100000>;
         };
 
-        i2c@0,7000d000 {
+        i2c@7000d000 {
                 status = "okay";
                 clock-frequency = <400000>;
 
@@ -834,7 +834,7 @@
                 };
         };
 
-        spi@0,7000d400 {
+        spi@7000d400 {
                 status = "okay";
 
                 cros_ec: cros-ec@0 {
@@ -874,7 +874,7 @@
                 };
         };
 
-        spi@0,7000da00 {
+        spi@7000da00 {
                 status = "okay";
                 spi-max-frequency = <25000000>;
                 spi-flash@0 {
@@ -884,7 +884,7 @@
                 };
         };
 
-        pmc@0,7000e400 {
+        pmc@7000e400 {
                 nvidia,invert-interrupt;
                 nvidia,suspend-mode = <1>;
                 nvidia,cpu-pwr-good-time = <500>;
@@ -895,16 +895,16 @@
                 nvidia,sys-clock-req-active-high;
         };
 
-        hda@0,70030000 {
+        hda@70030000 {
                 status = "okay";
         };
 
-        usb@0,70090000 {
-                phys = <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
-                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
-                       <&{/padctl@0,7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
-                       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
-                       <&{/padctl@0,7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
+        usb@70090000 {
+                phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, /* 1st USB A */
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>, /* Internal USB */
+                       <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>, /* 2nd USB A */
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>, /* 1st USB A */
+                       <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>; /* 2nd USB A */
                 phy-names = "usb2-0", "usb2-1", "usb2-2", "usb3-0", "usb3-1";
 
                 avddio-pex-supply = <&vdd_1v05_run>;
@@ -919,7 +919,7 @@
                 status = "okay";
         };
 
-        padctl@0,7009f000 {
+        padctl@7009f000 {
                 pads {
                         usb2 {
                                 status = "okay";
@@ -998,7 +998,7 @@
                 };
         };
 
-        sdhci@0,700b0400 {
+        sdhci@700b0400 {
                 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
                 wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
@@ -1007,41 +1007,41 @@
                 vqmmc-supply = <&vddio_sdmmc3>;
         };
 
-        sdhci@0,700b0600 {
+        sdhci@700b0600 {
                 status = "okay";
                 bus-width = <8>;
                 non-removable;
         };
 
-        ahub@0,70300000 {
-                i2s@0,70301100 {
+        ahub@70300000 {
+                i2s@70301100 {
                         status = "okay";
                 };
         };
 
-        usb@0,7d000000 {
+        usb@7d000000 {
                 status = "okay";
         };
 
-        usb-phy@0,7d000000 {
+        usb-phy@7d000000 {
                 status = "okay";
                 vbus-supply = <&vdd_usb1_vbus>;
         };
 
-        usb@0,7d004000 {
+        usb@7d004000 {
                 status = "okay";
         };
 
-        usb-phy@0,7d004000 {
+        usb-phy@7d004000 {
                 status = "okay";
                 vbus-supply = <&vdd_run_cam>;
         };
 
-        usb@0,7d008000 {
+        usb@7d008000 {
                 status = "okay";
         };
 
-        usb-phy@0,7d008000 {
+        usb-phy@7d008000 {
                 status = "okay";
                 vbus-supply = <&vdd_usb3_vbus>;
         };
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index ea4811870de2..ea340f9de448 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -14,7 +14,7 @@
         #address-cells = <2>;
         #size-cells = <2>;
 
-        pcie-controller@0,01003000 {
+        pcie-controller@01003000 {
                 compatible = "nvidia,tegra124-pcie";
                 device_type = "pci";
                 reg = <0x0 0x01003000 0x0 0x00000800   /* PADS registers */
@@ -77,7 +77,7 @@
                 };
         };
 
-        host1x@0,50000000 {
+        host1x@50000000 {
                 compatible = "nvidia,tegra124-host1x", "simple-bus";
                 reg = <0x0 0x50000000 0x0 0x00034000>;
                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
@@ -91,7 +91,7 @@
 
                 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>;
 
-                dc@0,54200000 {
+                dc@54200000 {
                         compatible = "nvidia,tegra124-dc";
                         reg = <0x0 0x54200000 0x0 0x00040000>;
                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
@@ -106,7 +106,7 @@
                         nvidia,head = <0>;
                 };
 
-                dc@0,54240000 {
+                dc@54240000 {
                         compatible = "nvidia,tegra124-dc";
                         reg = <0x0 0x54240000 0x0 0x00040000>;
                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
@@ -121,7 +121,7 @@
                         nvidia,head = <1>;
                 };
 
-                hdmi@0,54280000 {
+                hdmi@54280000 {
                         compatible = "nvidia,tegra124-hdmi";
                         reg = <0x0 0x54280000 0x0 0x00040000>;
                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
@@ -133,7 +133,7 @@
                         status = "disabled";
                 };
 
-                sor@0,54540000 {
+                sor@54540000 {
                         compatible = "nvidia,tegra124-sor";
                         reg = <0x0 0x54540000 0x0 0x00040000>;
                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
@@ -147,7 +147,7 @@
                         status = "disabled";
                 };
 
-                dpaux: dpaux@0,545c0000 {
+                dpaux: dpaux@545c0000 {
                         compatible = "nvidia,tegra124-dpaux";
                         reg = <0x0 0x545c0000 0x0 0x00040000>;
                         interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
@@ -160,7 +160,7 @@
                 };
         };
 
-        gic: interrupt-controller@0,50041000 {
+        gic: interrupt-controller@50041000 {
                 compatible = "arm,cortex-a15-gic";
                 #interrupt-cells = <3>;
                 interrupt-controller;
@@ -173,6 +173,11 @@
                 interrupt-parent = <&gic>;
         };
 
+        /*
+         * Please keep the following 0, notation in place as a former mainline
+         * U-Boot version was looking for that particular notation in order to
+         * perform required fix-ups on that GPU node.
+         */
         gpu@0,57000000 {
                 compatible = "nvidia,gk20a";
                 reg = <0x0 0x57000000 0x0 0x01000000>,
@@ -203,7 +208,7 @@
                 interrupt-parent = <&gic>;
         };
 
-        timer@0,60005000 {
+        timer@60005000 {
                 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                 reg = <0x0 0x60005000 0x0 0x400>;
                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
@@ -215,7 +220,7 @@
                 clocks = <&tegra_car TEGRA124_CLK_TIMER>;
         };
 
-        tegra_car: clock@0,60006000 {
+        tegra_car: clock@60006000 {
                 compatible = "nvidia,tegra124-car";
                 reg = <0x0 0x60006000 0x0 0x1000>;
                 #clock-cells = <1>;
@@ -223,12 +228,12 @@
                 nvidia,external-memory-controller = <&emc>;
         };
 
-        flow-controller@0,60007000 {
+        flow-controller@60007000 {
                 compatible = "nvidia,tegra124-flowctrl";
                 reg = <0x0 0x60007000 0x0 0x1000>;
         };
 
-        actmon@0,6000c800 {
+        actmon@6000c800 {
                 compatible = "nvidia,tegra124-actmon";
                 reg = <0x0 0x6000c800 0x0 0x400>;
                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
@@ -239,7 +244,7 @@
                 reset-names = "actmon";
         };
 
-        gpio: gpio@0,6000d000 {
+        gpio: gpio@6000d000 {
                 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
                 reg = <0x0 0x6000d000 0x0 0x1000>;
                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
@@ -259,7 +264,7 @@
                 */
         };
 
-        apbdma: dma@0,60020000 {
+        apbdma: dma@60020000 {
                 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma";
                 reg = <0x0 0x60020000 0x0 0x1400>;
                 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
@@ -300,13 +305,13 @@
                 #dma-cells = <1>;
         };
 
-        apbmisc@0,70000800 {
+        apbmisc@70000800 {
                 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc";
                 reg = <0x0 0x70000800 0x0 0x64>,   /* Chip revision */
                       <0x0 0x7000e864 0x0 0x04>;   /* Strapping options */
         };
 
-        pinmux: pinmux@0,70000868 {
+        pinmux: pinmux@70000868 {
                 compatible = "nvidia,tegra124-pinmux";
                 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */
                       <0x0 0x70003000 0x0 0x434>, /* Mux registers */
@@ -321,7 +326,7 @@
          * the APB DMA based serial driver, the compatible is
          * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
          */
-        uarta: serial@0,70006000 {
+        uarta: serial@70006000 {
                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                 reg = <0x0 0x70006000 0x0 0x40>;
                 reg-shift = <2>;
@@ -334,7 +339,7 @@
                 status = "disabled";
         };
 
-        uartb: serial@0,70006040 {
+        uartb: serial@70006040 {
                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                 reg = <0x0 0x70006040 0x0 0x40>;
                 reg-shift = <2>;
@@ -347,7 +352,7 @@
                 status = "disabled";
         };
 
-        uartc: serial@0,70006200 {
+        uartc: serial@70006200 {
                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                 reg = <0x0 0x70006200 0x0 0x40>;
                 reg-shift = <2>;
@@ -360,7 +365,7 @@
                 status = "disabled";
         };
 
-        uartd: serial@0,70006300 {
+        uartd: serial@70006300 {
                 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart";
                 reg = <0x0 0x70006300 0x0 0x40>;
                 reg-shift = <2>;
@@ -373,7 +378,7 @@
                 status = "disabled";
         };
 
-        pwm: pwm@0,7000a000 {
+        pwm: pwm@7000a000 {
                 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm";
                 reg = <0x0 0x7000a000 0x0 0x100>;
                 #pwm-cells = <2>;
@@ -383,7 +388,7 @@
                 status = "disabled";
         };
 
-        i2c@0,7000c000 {
+        i2c@7000c000 {
                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
                 reg = <0x0 0x7000c000 0x0 0x100>;
                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
@@ -398,7 +403,7 @@
                 status = "disabled";
         };
 
-        i2c@0,7000c400 {
+        i2c@7000c400 {
                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
                 reg = <0x0 0x7000c400 0x0 0x100>;
                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -413,7 +418,7 @@
                 status = "disabled";
         };
 
-        i2c@0,7000c500 {
+        i2c@7000c500 {
                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
                 reg = <0x0 0x7000c500 0x0 0x100>;
                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
@@ -428,7 +433,7 @@
                 status = "disabled";
         };
 
-        i2c@0,7000c700 {
+        i2c@7000c700 {
                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
                 reg = <0x0 0x7000c700 0x0 0x100>;
                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
@@ -443,7 +448,7 @@
                 status = "disabled";
         };
 
-        i2c@0,7000d000 {
+        i2c@7000d000 {
                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
                 reg = <0x0 0x7000d000 0x0 0x100>;
                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
@@ -458,7 +463,7 @@
                 status = "disabled";
         };
 
-        i2c@0,7000d100 {
+        i2c@7000d100 {
                 compatible = "nvidia,tegra124-i2c", "nvidia,tegra114-i2c";
                 reg = <0x0 0x7000d100 0x0 0x100>;
                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
@@ -473,7 +478,7 @@
                 status = "disabled";
         };
 
-        spi@0,7000d400 {
+        spi@7000d400 {
                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                 reg = <0x0 0x7000d400 0x0 0x200>;
                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
@@ -488,7 +493,7 @@
                 status = "disabled";
         };
 
-        spi@0,7000d600 {
+        spi@7000d600 {
                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                 reg = <0x0 0x7000d600 0x0 0x200>;
                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
@@ -503,7 +508,7 @@
                 status = "disabled";
         };
 
-        spi@0,7000d800 {
+        spi@7000d800 {
                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                 reg = <0x0 0x7000d800 0x0 0x200>;
                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -518,7 +523,7 @@
                 status = "disabled";
         };
 
-        spi@0,7000da00 {
+        spi@7000da00 {
                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                 reg = <0x0 0x7000da00 0x0 0x200>;
                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -533,7 +538,7 @@
                 status = "disabled";
         };
 
-        spi@0,7000dc00 {
+        spi@7000dc00 {
                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                 reg = <0x0 0x7000dc00 0x0 0x200>;
                 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
@@ -548,7 +553,7 @@
                 status = "disabled";
         };
 
-        spi@0,7000de00 {
+        spi@7000de00 {
                 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi";
                 reg = <0x0 0x7000de00 0x0 0x200>;
                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
@@ -563,21 +568,21 @@
                 status = "disabled";
         };
 
-        rtc@0,7000e000 {
+        rtc@7000e000 {
                 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc";
                 reg = <0x0 0x7000e000 0x0 0x100>;
                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&tegra_car TEGRA124_CLK_RTC>;
         };
 
-        pmc@0,7000e400 {
+        pmc@7000e400 {
                 compatible = "nvidia,tegra124-pmc";
                 reg = <0x0 0x7000e400 0x0 0x400>;
                 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>;
                 clock-names = "pclk", "clk32k_in";
         };
 
-        fuse@0,7000f800 {
+        fuse@7000f800 {
                 compatible = "nvidia,tegra124-efuse";
                 reg = <0x0 0x7000f800 0x0 0x400>;
                 clocks = <&tegra_car TEGRA124_CLK_FUSE>;
@@ -586,7 +591,7 @@
                 reset-names = "fuse";
         };
 
-        mc: memory-controller@0,70019000 {
+        mc: memory-controller@70019000 {
                 compatible = "nvidia,tegra124-mc";
                 reg = <0x0 0x70019000 0x0 0x1000>;
                 clocks = <&tegra_car TEGRA124_CLK_MC>;
@@ -597,14 +602,14 @@
                 #iommu-cells = <1>;
         };
 
-        emc: emc@0,7001b000 {
+        emc: emc@7001b000 {
                 compatible = "nvidia,tegra124-emc";
                 reg = <0x0 0x7001b000 0x0 0x1000>;
 
                 nvidia,memory-controller = <&mc>;
         };
 
-        sata@0,70020000 {
+        sata@70020000 {
                 compatible = "nvidia,tegra124-ahci";
                 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
                       <0x0 0x70020000 0x0 0x7000>; /* SATA */
@@ -621,7 +626,7 @@
                 status = "disabled";
         };
 
-        hda@0,70030000 {
+        hda@70030000 {
                 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
                 reg = <0x0 0x70030000 0x0 0x10000>;
                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
@@ -636,7 +641,7 @@
                 status = "disabled";
         };
 
-        usb@0,70090000 {
+        usb@70090000 {
                 compatible = "nvidia,tegra124-xusb";
                 reg = <0x0 0x70090000 0x0 0x8000>,
                       <0x0 0x70098000 0x0 0x1000>,
@@ -671,7 +676,7 @@
                 status = "disabled";
         };
 
-        padctl: padctl@0,7009f000 {
+        padctl: padctl@7009f000 {
                 compatible = "nvidia,tegra124-xusb-padctl";
                 reg = <0x0 0x7009f000 0x0 0x1000>;
                 resets = <&tegra_car 142>;
@@ -804,7 +809,7 @@
                 };
         };
 
-        sdhci@0,700b0000 {
+        sdhci@700b0000 {
                 compatible = "nvidia,tegra124-sdhci";
                 reg = <0x0 0x700b0000 0x0 0x200>;
                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
@@ -814,7 +819,7 @@
                 status = "disabled";
         };
 
-        sdhci@0,700b0200 {
+        sdhci@700b0200 {
                 compatible = "nvidia,tegra124-sdhci";
                 reg = <0x0 0x700b0200 0x0 0x200>;
                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -824,7 +829,7 @@
                 status = "disabled";
         };
 
-        sdhci@0,700b0400 {
+        sdhci@700b0400 {
                 compatible = "nvidia,tegra124-sdhci";
                 reg = <0x0 0x700b0400 0x0 0x200>;
                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
@@ -834,7 +839,7 @@
                 status = "disabled";
         };
 
-        sdhci@0,700b0600 {
+        sdhci@700b0600 {
                 compatible = "nvidia,tegra124-sdhci";
                 reg = <0x0 0x700b0600 0x0 0x200>;
                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
@@ -844,7 +849,7 @@
                 status = "disabled";
         };
 
-        soctherm: thermal-sensor@0,700e2000 {
+        soctherm: thermal-sensor@700e2000 {
                 compatible = "nvidia,tegra124-soctherm";
                 reg = <0x0 0x700e2000 0x0 0x1000>;
                 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
@@ -856,7 +861,7 @@
                 #thermal-sensor-cells = <1>;
         };
 
-        dfll: clock@0,70110000 {
+        dfll: clock@70110000 {
                 compatible = "nvidia,tegra124-dfll";
                 reg = <0 0x70110000 0 0x100>, /* DFLL control */
                       <0 0x70110000 0 0x100>, /* I2C output control */
@@ -880,7 +885,7 @@
                 status = "disabled";
         };
 
-        ahub@0,70300000 {
+        ahub@70300000 {
                 compatible = "nvidia,tegra124-ahub";
                 reg = <0x0 0x70300000 0x0 0x200>,
                       <0x0 0x70300800 0x0 0x800>,
@@ -932,7 +937,7 @@
                 #address-cells = <2>;
                 #size-cells = <2>;
 
-                tegra_i2s0: i2s@0,70301000 {
+                tegra_i2s0: i2s@70301000 {
                         compatible = "nvidia,tegra124-i2s";
                         reg = <0x0 0x70301000 0x0 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
@@ -942,7 +947,7 @@
                         status = "disabled";
                 };
 
-                tegra_i2s1: i2s@0,70301100 {
+                tegra_i2s1: i2s@70301100 {
                         compatible = "nvidia,tegra124-i2s";
                         reg = <0x0 0x70301100 0x0 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
@@ -952,7 +957,7 @@
                         status = "disabled";
                 };
 
-                tegra_i2s2: i2s@0,70301200 {
+                tegra_i2s2: i2s@70301200 {
                         compatible = "nvidia,tegra124-i2s";
                         reg = <0x0 0x70301200 0x0 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
@@ -962,7 +967,7 @@
                         status = "disabled";
                 };
 
-                tegra_i2s3: i2s@0,70301300 {
+                tegra_i2s3: i2s@70301300 {
                         compatible = "nvidia,tegra124-i2s";
                         reg = <0x0 0x70301300 0x0 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
@@ -972,7 +977,7 @@
                         status = "disabled";
                 };
 
-                tegra_i2s4: i2s@0,70301400 {
+                tegra_i2s4: i2s@70301400 {
                         compatible = "nvidia,tegra124-i2s";
                         reg = <0x0 0x70301400 0x0 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
@@ -983,7 +988,7 @@
                 };
         };
 
-        usb@0,7d000000 {
+        usb@7d000000 {
                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
                 reg = <0x0 0x7d000000 0x0 0x4000>;
                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
@@ -995,7 +1000,7 @@
                 status = "disabled";
         };
 
-        phy1: usb-phy@0,7d000000 {
+        phy1: usb-phy@7d000000 {
                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
                 reg = <0x0 0x7d000000 0x0 0x4000>,
                       <0x0 0x7d000000 0x0 0x4000>;
@@ -1020,7 +1025,7 @@
                 status = "disabled";
         };
 
-        usb@0,7d004000 {
+        usb@7d004000 {
                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
                 reg = <0x0 0x7d004000 0x0 0x4000>;
                 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -1032,7 +1037,7 @@
                 status = "disabled";
         };
 
-        phy2: usb-phy@0,7d004000 {
+        phy2: usb-phy@7d004000 {
                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
                 reg = <0x0 0x7d004000 0x0 0x4000>,
                       <0x0 0x7d000000 0x0 0x4000>;
@@ -1056,7 +1061,7 @@
                 status = "disabled";
         };
 
-        usb@0,7d008000 {
+        usb@7d008000 {
                 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci", "usb-ehci";
                 reg = <0x0 0x7d008000 0x0 0x4000>;
                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -1068,7 +1073,7 @@
                 status = "disabled";
         };
 
-        phy3: usb-phy@0,7d008000 {
+        phy3: usb-phy@7d008000 {
                 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy";
                 reg = <0x0 0x7d008000 0x0 0x4000>,
                       <0x0 0x7d000000 0x0 0x4000>;
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 8e0066ad9628..1242b841f147 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -478,7 +478,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index d2e960cbc001..d4fb4d39ede7 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -646,7 +646,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 33ed2b23026b..4e361a8c167e 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -512,7 +512,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 94b60a710dd8..2017acacc00c 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -798,7 +798,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index 025e9e8037da..27d2bbbf1eae 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -508,7 +508,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 4a035f74043a..381747f114a9 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -383,7 +383,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index a28c060a839b..8f0aaabf7e28 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -592,7 +592,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index 073806d07b2b..1e06f854c8b4 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -569,7 +569,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
index bf361277fe10..192b95177aac 100644
--- a/arch/arm/boot/dts/tegra30-apalis.dtsi
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -567,7 +567,7 @@
                         blocks = <0x5>;
                         irq-trigger = <0x1>;
 
-                        stmpe_touchscreen {
+                        stmpe_touchscreen@0 {
                                 compatible = "st,stmpe-ts";
                                 reg = <0>;
                                 /* 3.25 MHz ADC clock speed */
@@ -674,13 +674,14 @@
 
                 clk32k_in: clk@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
+
                 clk16m: clk@1 {
                         compatible = "fixed-clock";
-                        reg=<1>;
+                        reg = <1>;
                         #clock-cells = <0>;
                         clock-frequency = <16000000>;
                         clock-output-names = "clk16m";
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index b6da15d823a6..0350002849d5 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1952,7 +1952,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index 4721c1c9c780..f11012bb58cc 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -423,7 +423,7 @@
 
                 clk32k_in: clock@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
index 76875c3160fe..a8c0318743b6 100644
--- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -131,7 +131,7 @@
         clocks {
                 clk16m: clk@1 {
                         compatible = "fixed-clock";
-                        reg=<1>;
+                        reg = <1>;
                         #clock-cells = <0>;
                         clock-frequency = <16000000>;
                         clock-output-names = "clk16m";
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
index 2d8c58fd9357..a265534cd314 100644
--- a/arch/arm/boot/dts/tegra30-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -420,7 +420,7 @@
 
                 clk32k_in: clk@0 {
                         compatible = "fixed-clock";
-                        reg=<0>;
+                        reg = <0>;
                         #clock-cells = <0>;
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
index ce7138c3af1b..f9dc463b9e48 100644
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -16,15 +16,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 3043296345b7..9161cd9889b4 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -21,15 +21,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -99,7 +90,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/uniphier-common32.dtsi b/arch/arm/boot/dts/uniphier-common32.dtsi
index 61a095598206..03f60ec340b5 100644
--- a/arch/arm/boot/dts/uniphier-common32.dtsi
+++ b/arch/arm/boot/dts/uniphier-common32.dtsi
@@ -105,6 +105,8 @@
                         reg = <0x58c00000 0x400>;
                         #address-cells = <2>;
                         #size-cells = <1>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_system_bus>;
                 };
 
                 smpctrl@59800000 {
@@ -134,9 +136,13 @@
                         interrupt-controller;
                 };
 
-                pinctrl: pinctrl@5f801000 {
-                        /* specify compatible in each SoC DTSI */
-                        reg = <0x5f801000 0xe00>;
+                soc-glue@5f800000 {
+                        compatible = "simple-mfd", "syscon";
+                        reg = <0x5f800000 0x2000>;
+
+                        pinctrl: pinctrl {
+                                 /* specify compatible in each SoC DTSI */
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
index dadd86070c98..debad7ffef05 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
@@ -182,5 +182,5 @@
 };
 
 &pinctrl {
-        compatible = "socionext,ph1-ld4-pinctrl", "syscon";
+        compatible = "socionext,uniphier-ld4-pinctrl";
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi
index 532115234025..19c107c66bae 100644
--- a/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-ld6b.dtsi
@@ -63,5 +63,5 @@
  * which makes the pinctrl driver unshareable.
  */
 &pinctrl {
-        compatible = "socionext,ph1-ld6b-pinctrl", "syscon";
+        compatible = "socionext,uniphier-ld6b-pinctrl";
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
index 20f3f2ae7fa4..7b9da0852005 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
@@ -200,5 +200,5 @@
 };
 
 &pinctrl {
-        compatible = "socionext,ph1-pro4-pinctrl", "syscon";
+        compatible = "socionext,uniphier-pro4-pinctrl";
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
index 24f6f664b269..7e4aa2fde719 100644
--- a/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
@@ -194,5 +194,5 @@
 };
 
 &pinctrl {
-        compatible = "socionext,ph1-pro5-pinctrl", "syscon";
+        compatible = "socionext,uniphier-pro5-pinctrl";
 };
diff --git a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
index 6bfd29a05575..467f9d8e9873 100644
--- a/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
@@ -181,5 +181,5 @@
 };
 
 &pinctrl {
-        compatible = "socionext,ph1-sld8-pinctrl", "syscon";
+        compatible = "socionext,uniphier-sld8-pinctrl";
 };
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index f2f3fbe2d517..10a711041b4a 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -78,6 +78,11 @@
                 function = "nand";
         };
 
+        pinctrl_system_bus: system_bus_grp {
+                groups = "system_bus", "system_bus_cs1";
+                function = "system_bus";
+        };
+
         pinctrl_uart0: uart0_grp {
                 groups = "uart0";
                 function = "uart0";
diff --git a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts
index bf2619e4d489..98d895b7af1d 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-proxstream2-gentil.dts
@@ -55,13 +55,13 @@
         };
 
         chosen {
-                stdout-path = "serial2:115200n8";
+                stdout-path = "serial0:115200n8";
         };
 
         aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
+                serial0 = &serial2;
+                serial1 = &serial0;
+                serial2 = &serial1;
                 i2c0 = &i2c0;
                 i2c2 = &i2c2;
                 i2c4 = &i2c4;
diff --git a/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts b/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts
index 498acac3d95d..1fb8bd7bb686 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts
+++ b/arch/arm/boot/dts/uniphier-proxstream2-vodka.dts
@@ -55,13 +55,13 @@
         };
 
         chosen {
-                stdout-path = "serial2:115200n8";
+                stdout-path = "serial0:115200n8";
         };
 
         aliases {
-                serial0 = &serial0;
-                serial1 = &serial1;
-                serial2 = &serial2;
+                serial0 = &serial2;
+                serial1 = &serial0;
+                serial2 = &serial1;
                 i2c0 = &i2c0;
                 i2c4 = &i2c4;
                 i2c5 = &i2c5;
diff --git a/arch/arm/boot/dts/uniphier-proxstream2.dtsi b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
index 4ac484c6ce4e..d00d6f5c2668 100644
--- a/arch/arm/boot/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/boot/dts/uniphier-proxstream2.dtsi
@@ -205,5 +205,5 @@
 };
 
 &pinctrl {
-        compatible = "socionext,proxstream2-pinctrl", "syscon";
+        compatible = "socionext,uniphier-pxs2-pinctrl";
 };
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index 9beea8976584..7514b347cdd2 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -8,15 +8,6 @@
 
 / {
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -90,7 +81,7 @@
                         };
                 };
 
-                usb0: ohci@00500000 {
+                usb0: ohci@500000 {
                         num-ports = <2>;
                         status = "okay";
                 };
@@ -119,7 +110,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 8cc6edb29694..bfc48a272417 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -21,15 +21,6 @@
         };
 
         clocks {
-                #address-cells = <1>;
-                #size-cells = <1>;
-                ranges;
-
-                main_clock: clock@0 {
-                        compatible = "atmel,osc", "fixed-clock";
-                        clock-frequency = <12000000>;
-                };
-
                 slow_xtal {
                         clock-frequency = <32768>;
                 };
@@ -147,7 +138,7 @@
                 };
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 status = "okay";
         };
 };
diff --git a/arch/arm/boot/dts/usb_a9g20_common.dtsi b/arch/arm/boot/dts/usb_a9g20_common.dtsi
index 0b3b36182fe5..088c2c3685ab 100644
--- a/arch/arm/boot/dts/usb_a9g20_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9g20_common.dtsi
@@ -11,14 +11,15 @@
 
 / {
         chosen {
-                bootargs = "mem=64M console=ttyS0,115200 root=/dev/mtdblock5 rw rootfstype=ubifs";
+                bootargs = "mem=64M root=/dev/mtdblock5 rw rootfstype=ubifs";
+                stdout-path = "serial0:115200n8";
         };
 
         memory {
                 reg = <0x20000000 0x4000000>;
         };
 
-        i2c@0 {
+        i2c-gpio-0 {
                 rv3029c2@56 {
                         compatible = "rv3029c2";
                         reg = <0x56>;
diff --git a/arch/arm/mach-bcm/platsmp.c b/arch/arm/mach-bcm/platsmp.c
index 33c4d8349f95..3ac3a9bc663c 100644
--- a/arch/arm/mach-bcm/platsmp.c
+++ b/arch/arm/mach-bcm/platsmp.c
@@ -38,9 +38,6 @@
 #define OF_SECONDARY_BOOT       "secondary-boot-reg"
 #define MPIDR_CPUID_BITMASK     0x3
 
-/* I/O address of register used to coordinate secondary core startup */
-static u32      secondary_boot_addr;
-
 /*
  * Enable the Cortex A9 Snoop Control Unit
  *
@@ -82,20 +79,40 @@ static int __init scu_a9_enable(void)
         return 0;
 }
 
-static int nsp_write_lut(void)
+static u32 secondary_boot_addr_for(unsigned int cpu)
+{
+        u32 secondary_boot_addr = 0;
+        struct device_node *cpu_node = of_get_cpu_node(cpu, NULL);
+
+        if (!cpu_node) {
+                pr_err("Failed to find device tree node for CPU%u\n", cpu);
+                return 0;
+        }
+
+        if (of_property_read_u32(cpu_node,
+                                 OF_SECONDARY_BOOT,
+                                 &secondary_boot_addr))
+                pr_err("required secondary boot register not specified for CPU%u\n",
+                        cpu);
+
+        of_node_put(cpu_node);
+
+        return secondary_boot_addr;
+}
+
+static int nsp_write_lut(unsigned int cpu)
 {
         void __iomem *sku_rom_lut;
         phys_addr_t secondary_startup_phy;
+        const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
 
-        if (!secondary_boot_addr) {
-                pr_warn("required secondary boot register not specified\n");
+        if (!secondary_boot_addr)
                 return -EINVAL;
-        }
 
         sku_rom_lut = ioremap_nocache((phys_addr_t)secondary_boot_addr,
-                                                sizeof(secondary_boot_addr));
+                                      sizeof(phys_addr_t));
         if (!sku_rom_lut) {
-                pr_warn("unable to ioremap SKU-ROM LUT register\n");
+                pr_warn("unable to ioremap SKU-ROM LUT register for cpu %u\n", cpu);
                 return -ENOMEM;
         }
 
@@ -114,70 +131,12 @@ static int nsp_write_lut(void)
 
 static void __init bcm_smp_prepare_cpus(unsigned int max_cpus)
 {
-        static cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
-        struct device_node *cpus_node = NULL;
-        struct device_node *cpu_node = NULL;
-        int ret;
-
-        /*
-         * This function is only called via smp_ops->smp_prepare_cpu().
-         * That only happens if a "/cpus" device tree node exists
-         * and has an "enable-method" property that selects the SMP
-         * operations defined herein.
-         */
-        cpus_node = of_find_node_by_path("/cpus");
-        if (!cpus_node)
-                return;
-
-        for_each_child_of_node(cpus_node, cpu_node) {
-                u32 cpuid;
-
-                if (of_node_cmp(cpu_node->type, "cpu"))
-                        continue;
-
-                if (of_property_read_u32(cpu_node, "reg", &cpuid)) {
-                        pr_debug("%s: missing reg property\n",
-                                     cpu_node->full_name);
-                        ret = -ENOENT;
-                        goto out;
-                }
-
-                /*
-                 * "secondary-boot-reg" property should be defined only
-                 * for secondary cpu
-                 */
-                if ((cpuid & MPIDR_CPUID_BITMASK) == 1) {
-                        /*
-                         * Our secondary enable method requires a
-                         * "secondary-boot-reg" property to specify a register
-                         * address used to request the ROM code boot a secondary
-                         * core. If we have any trouble getting this we fall
-                         * back to uniprocessor mode.
-                         */
-                        if (of_property_read_u32(cpu_node,
-                                                OF_SECONDARY_BOOT,
-                                                &secondary_boot_addr)) {
-                                pr_warn("%s: no" OF_SECONDARY_BOOT "property\n",
-                                        cpu_node->name);
-                                ret = -ENOENT;
-                                goto out;
-                        }
-                }
-        }
-
-        /*
-         * Enable the SCU on Cortex A9 based SoCs. If -ENOENT is
-         * returned, the SoC reported a uniprocessor configuration.
-         * We bail on any other error.
-         */
-        ret = scu_a9_enable();
-out:
-        of_node_put(cpu_node);
-        of_node_put(cpus_node);
+        const cpumask_t only_cpu_0 = { CPU_BITS_CPU0 };
 
-        if (ret) {
+        /* Enable the SCU on Cortex A9 based SoCs */
+        if (scu_a9_enable()) {
                 /* Update the CPU present map to reflect uniprocessor mode */
-                pr_warn("disabling SMP\n");
+                pr_warn("failed to enable A9 SCU - disabling SMP\n");
                 init_cpu_present(&only_cpu_0);
         }
 }
@@ -208,6 +167,7 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
         u32 cpu_id;
         u32 boot_val;
         bool timeout = false;
+        const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
 
         cpu_id = cpu_logical_map(cpu);
         if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
@@ -215,13 +175,11 @@ static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 return -EINVAL;
         }
 
-        if (!secondary_boot_addr) {
-                pr_err("required secondary boot register not specified\n");
+        if (!secondary_boot_addr)
                 return -EINVAL;
-        }
 
-        boot_reg = ioremap_nocache(
-                        (phys_addr_t)secondary_boot_addr, sizeof(u32));
+        boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr,
+                                   sizeof(phys_addr_t));
         if (!boot_reg) {
                 pr_err("unable to map boot register for cpu %u\n", cpu_id);
                 return -ENOMEM;
@@ -315,7 +273,7 @@ static int nsp_boot_secondary(unsigned int cpu, struct task_struct *idle)
          * After wake up, secondary core branches to the startup
          * address programmed at SKU ROM LUT location.
          */
-        ret = nsp_write_lut();
+        ret = nsp_write_lut(cpu);
         if (ret) {
                 pr_err("unable to write startup addr to SKU ROM LUT\n");
                 goto out;
@@ -328,12 +286,12 @@ out:
         return ret;
 }
 
-static const struct smp_operations bcm_smp_ops __initconst = {
+static const struct smp_operations kona_smp_ops __initconst = {
         .smp_prepare_cpus       = bcm_smp_prepare_cpus,
         .smp_boot_secondary     = kona_boot_secondary,
 };
 CPU_METHOD_OF_DECLARE(bcm_smp_bcm281xx, "brcm,bcm11351-cpu-method",
-                        &bcm_smp_ops);
+                        &kona_smp_ops);
 
 static const struct smp_operations bcm23550_smp_ops __initconst = {
         .smp_boot_secondary     = bcm23550_boot_secondary,
diff --git a/drivers/clk/ti/clk-43xx.c b/drivers/clk/ti/clk-43xx.c
index 7255aa818b1f..e816a7500e43 100644
--- a/drivers/clk/ti/clk-43xx.c
+++ b/drivers/clk/ti/clk-43xx.c
@@ -58,6 +58,7 @@ static struct ti_dt_clk am43xx_clks[] = {
         DT_CLK(NULL, "smartreflex1_fck", "smartreflex1_fck"),
         DT_CLK(NULL, "sha0_fck", "sha0_fck"),
         DT_CLK(NULL, "aes0_fck", "aes0_fck"),
+        DT_CLK(NULL, "rng_fck", "rng_fck"),
         DT_CLK(NULL, "timer1_fck", "timer1_fck"),
         DT_CLK(NULL, "timer2_fck", "timer2_fck"),
         DT_CLK(NULL, "timer3_fck", "timer3_fck"),
diff --git a/drivers/spi/spi-st-ssc4.c b/drivers/spi/spi-st-ssc4.c
index d5adf9f31602..a56eca0e95a6 100644
--- a/drivers/spi/spi-st-ssc4.c
+++ b/drivers/spi/spi-st-ssc4.c
@@ -68,32 +68,6 @@ struct spi_st {
         struct completion       done;
 };
 
-static int spi_st_clk_enable(struct spi_st *spi_st)
-{
-        /*
-         * Current platforms use one of the core clocks for SPI and I2C.
-         * If we attempt to disable the clock, the system will hang.
-         *
-         * TODO: Remove this when platform supports power domains.
-         */
-        return 0;
-
-        return clk_prepare_enable(spi_st->clk);
-}
-
-static void spi_st_clk_disable(struct spi_st *spi_st)
-{
-        /*
-         * Current platforms use one of the core clocks for SPI and I2C.
-         * If we attempt to disable the clock, the system will hang.
-         *
-         * TODO: Remove this when platform supports power domains.
-         */
-        return;
-
-        clk_disable_unprepare(spi_st->clk);
-}
-
 /* Load the TX FIFO */
 static void ssc_write_tx_fifo(struct spi_st *spi_st)
 {
@@ -349,7 +323,7 @@ static int spi_st_probe(struct platform_device *pdev)
                 goto put_master;
         }
 
-        ret = spi_st_clk_enable(spi_st);
+        ret = clk_prepare_enable(spi_st->clk);
         if (ret)
                 goto put_master;
 
@@ -408,7 +382,7 @@ static int spi_st_probe(struct platform_device *pdev)
         return 0;
 
 clk_disable:
-        spi_st_clk_disable(spi_st);
+        clk_disable_unprepare(spi_st->clk);
 put_master:
         spi_master_put(master);
         return ret;
@@ -419,7 +393,7 @@ static int spi_st_remove(struct platform_device *pdev)
         struct spi_master *master = platform_get_drvdata(pdev);
         struct spi_st *spi_st = spi_master_get_devdata(master);
 
-        spi_st_clk_disable(spi_st);
+        clk_disable_unprepare(spi_st->clk);
 
         pinctrl_pm_select_sleep_state(&pdev->dev);
 
@@ -435,7 +409,7 @@ static int spi_st_runtime_suspend(struct device *dev)
         writel_relaxed(0, spi_st->base + SSC_IEN);
         pinctrl_pm_select_sleep_state(dev);
 
-        spi_st_clk_disable(spi_st);
+        clk_disable_unprepare(spi_st->clk);
 
         return 0;
 }
@@ -446,7 +420,7 @@ static int spi_st_runtime_resume(struct device *dev)
         struct spi_st *spi_st = spi_master_get_devdata(master);
         int ret;
 
-        ret = spi_st_clk_enable(spi_st);
+        ret = clk_prepare_enable(spi_st->clk);
         pinctrl_pm_select_default_state(dev);
 
         return ret;
diff --git a/include/dt-bindings/clock/r8a7792-clock.h b/include/dt-bindings/clock/r8a7792-clock.h
new file mode 100644
index 000000000000..9a8b392ceb00
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7792-clock.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_R8A7792_H__
+#define __DT_BINDINGS_CLOCK_R8A7792_H__
+
+/* CPG */
+#define R8A7792_CLK_MAIN                0
+#define R8A7792_CLK_PLL0                1
+#define R8A7792_CLK_PLL1                2
+#define R8A7792_CLK_PLL3                3
+#define R8A7792_CLK_LB                  4
+#define R8A7792_CLK_QSPI                5
+#define R8A7792_CLK_Z                   6
+
+/* MSTP0 */
+#define R8A7792_CLK_MSIOF0              0
+
+/* MSTP1 */
+#define R8A7792_CLK_JPU                 6
+#define R8A7792_CLK_TMU1                11
+#define R8A7792_CLK_TMU3                21
+#define R8A7792_CLK_TMU2                22
+#define R8A7792_CLK_CMT0                24
+#define R8A7792_CLK_TMU0                25
+#define R8A7792_CLK_VSP1DU1             27
+#define R8A7792_CLK_VSP1DU0             28
+#define R8A7792_CLK_VSP1_SY             31
+
+/* MSTP2 */
+#define R8A7792_CLK_MSIOF1              8
+#define R8A7792_CLK_SYS_DMAC1           18
+#define R8A7792_CLK_SYS_DMAC0           19
+
+/* MSTP3 */
+#define R8A7792_CLK_TPU0                4
+#define R8A7792_CLK_SDHI0               14
+#define R8A7792_CLK_CMT1                29
+
+/* MSTP4 */
+#define R8A7792_CLK_IRQC                7
+
+/* MSTP5 */
+#define R8A7792_CLK_AUDIO_DMAC0         2
+#define R8A7792_CLK_THERMAL             22
+#define R8A7792_CLK_PWM                 23
+
+/* MSTP7 */
+#define R8A7792_CLK_HSCIF1              16
+#define R8A7792_CLK_HSCIF0              17
+#define R8A7792_CLK_SCIF3               18
+#define R8A7792_CLK_SCIF2               19
+#define R8A7792_CLK_SCIF1               20
+#define R8A7792_CLK_SCIF0               21
+#define R8A7792_CLK_DU1                 23
+#define R8A7792_CLK_DU0                 24
+
+/* MSTP8 */
+#define R8A7792_CLK_VIN5                4
+#define R8A7792_CLK_VIN4                5
+#define R8A7792_CLK_VIN3                8
+#define R8A7792_CLK_VIN2                9
+#define R8A7792_CLK_VIN1                10
+#define R8A7792_CLK_VIN0                11
+#define R8A7792_CLK_ETHERAVB            12
+
+/* MSTP9 */
+#define R8A7792_CLK_GPIO7               4
+#define R8A7792_CLK_GPIO6               5
+#define R8A7792_CLK_GPIO5               7
+#define R8A7792_CLK_GPIO4               8
+#define R8A7792_CLK_GPIO3               9
+#define R8A7792_CLK_GPIO2               10
+#define R8A7792_CLK_GPIO1               11
+#define R8A7792_CLK_GPIO0               12
+#define R8A7792_CLK_GPIO11              13
+#define R8A7792_CLK_GPIO10              14
+#define R8A7792_CLK_CAN1                15
+#define R8A7792_CLK_CAN0                16
+#define R8A7792_CLK_QSPI_MOD            17
+#define R8A7792_CLK_GPIO9               19
+#define R8A7792_CLK_GPIO8               21
+#define R8A7792_CLK_I2C5                25
+#define R8A7792_CLK_IICDVFS             26
+#define R8A7792_CLK_I2C4                27
+#define R8A7792_CLK_I2C3                28
+#define R8A7792_CLK_I2C2                29
+#define R8A7792_CLK_I2C1                30
+#define R8A7792_CLK_I2C0                31
+
+/* MSTP10 */
+#define R8A7792_CLK_SSI_ALL             5
+#define R8A7792_CLK_SSI4                11
+#define R8A7792_CLK_SSI3                12
+
+#endif /* __DT_BINDINGS_CLOCK_R8A7792_H__ */
diff --git a/include/dt-bindings/clock/r8a7794-clock.h b/include/dt-bindings/clock/r8a7794-clock.h
index 4d3ecd626c1f..a3491ba2f6ec 100644
--- a/include/dt-bindings/clock/r8a7794-clock.h
+++ b/include/dt-bindings/clock/r8a7794-clock.h
@@ -67,7 +67,6 @@
 #define R8A7794_CLK_IRQC                7
 
 /* MSTP5 */
-#define R8A7794_CLK_THERMAL             22
 #define R8A7794_CLK_PWM                 23
 
 /* MSTP7 */
diff --git a/include/dt-bindings/clock/stih407-clks.h b/include/dt-bindings/clock/stih407-clks.h
index 7af2b717b3b2..082edd9badfa 100644
--- a/include/dt-bindings/clock/stih407-clks.h
+++ b/include/dt-bindings/clock/stih407-clks.h
@@ -5,6 +5,10 @@
 #ifndef _DT_BINDINGS_CLK_STIH407
 #define _DT_BINDINGS_CLK_STIH407
 
+/* CLOCKGEN A0 */
+#define CLK_IC_LMI0             0
+#define CLK_IC_LMI1             1
+
 /* CLOCKGEN C0 */
 #define CLK_ICN_GPU             0
 #define CLK_FDMA                1
diff --git a/include/dt-bindings/pinctrl/keystone.h b/include/dt-bindings/pinctrl/keystone.h
new file mode 100644
index 000000000000..7f97d776a8ff
--- /dev/null
+++ b/include/dt-bindings/pinctrl/keystone.h
@@ -0,0 +1,39 @@
+/*
+ * This header provides constants for Keystone pinctrl bindings.
+ *
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_KEYSTONE_H
+#define _DT_BINDINGS_PINCTRL_KEYSTONE_H
+
+#define MUX_MODE0       0
+#define MUX_MODE1       1
+#define MUX_MODE2       2
+#define MUX_MODE3       3
+#define MUX_MODE4       4
+#define MUX_MODE5       5
+
+#define BUFFER_CLASS_B  (0 << 19)
+#define BUFFER_CLASS_C  (1 << 19)
+#define BUFFER_CLASS_D  (2 << 19)
+#define BUFFER_CLASS_E  (3 << 19)
+
+#define PULL_DISABLE    (1 << 16)
+#define PIN_PULLUP      (1 << 17)
+#define PIN_PULLDOWN    (0 << 17)
+
+#define KEYSTONE_IOPAD_OFFSET(pa, offset) (((pa) & 0xffff) - (offset))
+
+#define K2G_CORE_IOPAD(pa) KEYSTONE_IOPAD_OFFSET((pa), 0x1000)
+
+#endif
diff --git a/include/dt-bindings/power/r8a7792-sysc.h b/include/dt-bindings/power/r8a7792-sysc.h
new file mode 100644
index 000000000000..74f4a78e29aa
--- /dev/null
+++ b/include/dt-bindings/power/r8a7792-sysc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7792_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7792_PD_CA15_CPU0            0
+#define R8A7792_PD_CA15_CPU1            1
+#define R8A7792_PD_CA15_SCU             12
+#define R8A7792_PD_SGX                  20
+#define R8A7792_PD_IMP                  24
+
+/* Always-on power area */
+#define R8A7792_PD_ALWAYS_ON            32
+
+#endif /* __DT_BINDINGS_POWER_R8A7792_SYSC_H__ */