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author | Jacob Pan <jacob.jun.pan@linux.intel.com> | 2016-06-17 01:28:34 -0400 |
---|---|---|
committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-06-22 21:12:32 -0400 |
commit | 0080d65b7719fc58e60b5595fc61acded330004f (patch) | |
tree | beef0974dd04e5ff3831ee553de0dad947b79016 | |
parent | 02c4fae9ea68fc41ebe871c635408daa2ba37d2e (diff) |
idle_intel: Add Denverton
Denverton is an Intel Atom based micro server which shares the same
Goldmont architecture as Broxton. The available C-states on
Denverton is a subset of Broxton with only C1, C1e, and C6.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Len Brown <len.brown@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-rw-r--r-- | drivers/idle/intel_idle.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index 4c8b23d1a928..170ab8e01075 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c | |||
@@ -826,6 +826,35 @@ static struct cpuidle_state bxt_cstates[] = { | |||
826 | .enter = NULL } | 826 | .enter = NULL } |
827 | }; | 827 | }; |
828 | 828 | ||
829 | static struct cpuidle_state dnv_cstates[] = { | ||
830 | { | ||
831 | .name = "C1-DNV", | ||
832 | .desc = "MWAIT 0x00", | ||
833 | .flags = MWAIT2flg(0x00), | ||
834 | .exit_latency = 2, | ||
835 | .target_residency = 2, | ||
836 | .enter = &intel_idle, | ||
837 | .enter_freeze = intel_idle_freeze, }, | ||
838 | { | ||
839 | .name = "C1E-DNV", | ||
840 | .desc = "MWAIT 0x01", | ||
841 | .flags = MWAIT2flg(0x01), | ||
842 | .exit_latency = 10, | ||
843 | .target_residency = 20, | ||
844 | .enter = &intel_idle, | ||
845 | .enter_freeze = intel_idle_freeze, }, | ||
846 | { | ||
847 | .name = "C6-DNV", | ||
848 | .desc = "MWAIT 0x20", | ||
849 | .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, | ||
850 | .exit_latency = 50, | ||
851 | .target_residency = 500, | ||
852 | .enter = &intel_idle, | ||
853 | .enter_freeze = intel_idle_freeze, }, | ||
854 | { | ||
855 | .enter = NULL } | ||
856 | }; | ||
857 | |||
829 | /** | 858 | /** |
830 | * intel_idle | 859 | * intel_idle |
831 | * @dev: cpuidle_device | 860 | * @dev: cpuidle_device |
@@ -1015,6 +1044,11 @@ static const struct idle_cpu idle_cpu_bxt = { | |||
1015 | .disable_promotion_to_c1e = true, | 1044 | .disable_promotion_to_c1e = true, |
1016 | }; | 1045 | }; |
1017 | 1046 | ||
1047 | static const struct idle_cpu idle_cpu_dnv = { | ||
1048 | .state_table = dnv_cstates, | ||
1049 | .disable_promotion_to_c1e = true, | ||
1050 | }; | ||
1051 | |||
1018 | #define ICPU(model, cpu) \ | 1052 | #define ICPU(model, cpu) \ |
1019 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | 1053 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } |
1020 | 1054 | ||
@@ -1051,6 +1085,7 @@ static const struct x86_cpu_id intel_idle_ids[] __initconst = { | |||
1051 | ICPU(INTEL_FAM6_SKYLAKE_X, idle_cpu_skx), | 1085 | ICPU(INTEL_FAM6_SKYLAKE_X, idle_cpu_skx), |
1052 | ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl), | 1086 | ICPU(INTEL_FAM6_XEON_PHI_KNL, idle_cpu_knl), |
1053 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt), | 1087 | ICPU(INTEL_FAM6_ATOM_GOLDMONT, idle_cpu_bxt), |
1088 | ICPU(INTEL_FAM6_ATOM_DENVERTON, idle_cpu_dnv), | ||
1054 | {} | 1089 | {} |
1055 | }; | 1090 | }; |
1056 | 1091 | ||