refactor: use architecture-specific includes for cycles.h

2 files changed, 46 insertions, 0 deletions

diff --git a/arch/sparc64/include/asm/cycles.h b/arch/sparc64/include/asm/cycles.h
new file mode 100644
index 0000000..ce0e8ce
--- /dev/null
+++ b/arch/sparc64/include/asm/cycles.h
@@ -0,0 +1,16 @@
+#ifndef ASM_CYCLES_H
+#define ASM_CYCLES_H
+
+#define NPT_BIT 63
+
+typedef unsigned long cycles_t;
+
+#define CYCLES_FMT "lu"
+
+static inline cycles_t get_cycles(void) {
+        cycles_t cycles = 0;
+        __asm__ __volatile__("rd %%asr24, %0" : "=r" (cycles));
+        return cycles & ~(1UL << NPT_BIT);
+}
+
+#endif
diff --git a/arch/x86/include/asm/cycles.h b/arch/x86/include/asm/cycles.h
new file mode 100644
index 0000000..00a7593
--- /dev/null
+++ b/arch/x86/include/asm/cycles.h
@@ -0,0 +1,30 @@
+#ifndef ASM_CYCLES_H
+#define ASM_CYCLES_H
+
+#define rdtscll(val) do { \
+        unsigned int __a,__d; \
+        __asm__ __volatile__("rdtsc" : "=a" (__a), "=d" (__d)); \
+        (val) = ((unsigned long long)__a) | (((unsigned long long)__d)<<32); \
+} while(0)
+
+static __inline__ unsigned long long native_read_tsc(void)
+{
+        unsigned long long val;
+
+        __asm__ __volatile__("mfence":::"memory");
+        rdtscll(val);
+        __asm__ __volatile__("mfence":::"memory");
+
+        return val;
+}
+
+#define CYCLES_FMT "llu"
+
+typedef unsigned long long cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+        return native_read_tsc();
+}
+
+#endif