/* * Header file describing the internal (inter-module) DHD interfaces. * * Provides type definitions and function prototypes used to link the * DHD OS, bus, and protocol modules. * * Copyright (C) 1999-2015, Broadcom Corporation * * Unless you and Broadcom execute a separate written software license * agreement governing use of this software, this software is licensed to you * under the terms of the GNU General Public License version 2 (the "GPL"), * available at http://www.broadcom.com/licenses/GPLv2.php, with the * following added to such license: * * As a special exception, the copyright holders of this software give you * permission to link this software with independent modules, and to copy and * distribute the resulting executable under terms of your choice, provided that * you also meet, for each linked independent module, the terms and conditions of * the license of that module. An independent module is a module which is not * derived from this software. The special exception does not apply to any * modifications of the software. * * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. * * $Id: dhd_msgbuf.c 530336 2015-01-29 22:52:35Z $ */ #include #include #include #include #include #include #include #include #include #include #include #include #ifdef PROP_TXSTATUS #include #include #endif #include #include #include #include /* * PCIE D2H DMA Complete Sync Modes * * Firmware may interrupt the host, prior to the D2H Mem2Mem DMA completes into * Host system memory. A WAR using one of 3 approaches is needed: * 1. Dongle places ia modulo-253 seqnum in last word of each D2H message * 2. XOR Checksum, with epoch# in each work item. Dongle builds an XOR checksum * writes in the last word of each work item. Each work item has a seqnum * number = sequence num % 253. * 3. Read Barrier: Dongle does a host memory read access prior to posting an * interrupt. * Host does not participate with option #3, other than reserving a host system * memory location for the dongle to read. */ #define PCIE_D2H_SYNC #define PCIE_D2H_SYNC_WAIT_TRIES 256 #define PCIE_D2H_SYNC_BZERO /* bzero a message before updating the RD offset */ #define RETRIES 2 /* # of retries to retrieve matching ioctl response */ #define IOCTL_HDR_LEN 12 #define DEFAULT_RX_BUFFERS_TO_POST 256 #define RXBUFPOST_THRESHOLD 32 #define RX_BUF_BURST 16 #define DHD_STOP_QUEUE_THRESHOLD 200 #define DHD_START_QUEUE_THRESHOLD 100 #define MODX(x, n) ((x) & ((n) -1)) #define align(x, n) (MODX(x, n) ? ((x) - MODX(x, n) + (n)) : ((x) - MODX(x, n))) #define RX_DMA_OFFSET 8 #define IOCT_RETBUF_SIZE (RX_DMA_OFFSET + WLC_IOCTL_MAXLEN) #define DMA_D2H_SCRATCH_BUF_LEN 8 #define DMA_ALIGN_LEN 4 #define DMA_XFER_LEN_LIMIT 0x400000 #define DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ 8192 #define DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D 1 #define DHD_FLOWRING_MAX_EVENTBUF_POST 8 #define DHD_FLOWRING_MAX_IOCTLRESPBUF_POST 8 #define DHD_PROT_FUNCS 22 typedef struct dhd_mem_map { void *va; dmaaddr_t pa; void *dmah; } dhd_mem_map_t; typedef struct dhd_dmaxfer { dhd_mem_map_t srcmem; dhd_mem_map_t destmem; uint32 len; uint32 srcdelay; uint32 destdelay; } dhd_dmaxfer_t; #define TXP_FLUSH_NITEMS #define TXP_FLUSH_MAX_ITEMS_FLUSH_CNT 48 typedef struct msgbuf_ring { bool inited; uint16 idx; uchar name[24]; dhd_mem_map_t ring_base; #ifdef TXP_FLUSH_NITEMS void* start_addr; uint16 pend_items_count; #endif /* TXP_FLUSH_NITEMS */ ring_mem_t *ringmem; ring_state_t *ringstate; #if defined(PCIE_D2H_SYNC) uint32 seqnum; #endif /* PCIE_D2H_SYNC */ void *secdma; } msgbuf_ring_t; #if defined(PCIE_D2H_SYNC) /* Custom callback attached based upon D2H DMA Sync mode used in dongle. */ typedef uint8 (* d2h_sync_cb_t)(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen); #endif /* PCIE_D2H_SYNC */ typedef struct dhd_prot { osl_t *osh; /* OSL handle */ uint32 reqid; uint32 lastcmd; uint32 pending; uint16 rxbufpost; uint16 max_rxbufpost; uint16 max_eventbufpost; uint16 max_ioctlrespbufpost; uint16 cur_event_bufs_posted; uint16 cur_ioctlresp_bufs_posted; uint16 active_tx_count; uint16 max_tx_count; uint16 txp_threshold; /* Ring info */ msgbuf_ring_t *h2dring_txp_subn; msgbuf_ring_t *h2dring_rxp_subn; msgbuf_ring_t *h2dring_ctrl_subn; /* Cbuf handle for H2D ctrl ring */ msgbuf_ring_t *d2hring_tx_cpln; msgbuf_ring_t *d2hring_rx_cpln; msgbuf_ring_t *d2hring_ctrl_cpln; /* Cbuf handle for D2H ctrl ring */ uint32 rx_dataoffset; dhd_mem_map_t retbuf; dhd_mem_map_t ioctbuf; /* For holding ioct request buf */ dhd_mb_ring_t mb_ring_fn; uint32 d2h_dma_scratch_buf_len; /* For holding ioct request buf */ dhd_mem_map_t d2h_dma_scratch_buf; /* For holding ioct request buf */ uint32 h2d_dma_writeindx_buf_len; /* For holding dma ringupd buf - submission write */ dhd_mem_map_t h2d_dma_writeindx_buf; /* For holding dma ringupd buf - submission write */ uint32 h2d_dma_readindx_buf_len; /* For holding dma ringupd buf - submission read */ dhd_mem_map_t h2d_dma_readindx_buf; /* For holding dma ringupd buf - submission read */ uint32 d2h_dma_writeindx_buf_len; /* For holding dma ringupd buf - completion write */ dhd_mem_map_t d2h_dma_writeindx_buf; /* For holding dma ringupd buf - completion write */ uint32 d2h_dma_readindx_buf_len; /* For holding dma ringupd buf - completion read */ dhd_mem_map_t d2h_dma_readindx_buf; /* For holding dma ringupd buf - completion read */ #if defined(PCIE_D2H_SYNC) d2h_sync_cb_t d2h_sync_cb; /* Sync on D2H DMA done: SEQNUM or XORCSUM */ ulong d2h_sync_wait_max; /* max number of wait loops to receive one msg */ ulong d2h_sync_wait_tot; /* total wait loops */ #endif /* PCIE_D2H_SYNC */ dhd_dmaxfer_t dmaxfer; bool dmaxfer_in_progress; uint16 ioctl_seq_no; uint16 data_seq_no; uint16 ioctl_trans_id; void *pktid_map_handle; uint16 rx_metadata_offset; uint16 tx_metadata_offset; uint16 rx_cpln_early_upd_idx; } dhd_prot_t; static int dhdmsgbuf_query_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action); static int dhd_msgbuf_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf, uint len, uint8 action); static int dhdmsgbuf_cmplt(dhd_pub_t *dhd, uint32 id, uint32 len, void* buf, void* retbuf); static int dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd); static int dhd_prot_rxbufpost(dhd_pub_t *dhd, uint16 count); static void dhd_prot_return_rxbuf(dhd_pub_t *dhd, uint16 rxcnt); static void dhd_prot_rxcmplt_process(dhd_pub_t *dhd, void* buf, uint16 msglen); static void dhd_prot_event_process(dhd_pub_t *dhd, void* buf, uint16 len); static int dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8* buf, uint16 len); static int dhd_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8* buf, uint16 len); static void dhd_prot_noop(dhd_pub_t *dhd, void * buf, uint16 msglen); static void dhd_prot_txstatus_process(dhd_pub_t *dhd, void * buf, uint16 msglen); static void dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void * buf, uint16 msglen); static void dhd_prot_ioctack_process(dhd_pub_t *dhd, void * buf, uint16 msglen); static void dhd_prot_ringstatus_process(dhd_pub_t *dhd, void * buf, uint16 msglen); static void dhd_prot_genstatus_process(dhd_pub_t *dhd, void * buf, uint16 msglen); static void* dhd_alloc_ring_space(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint16 msglen, uint16 *alloced); static int dhd_fillup_ioct_reqst_ptrbased(dhd_pub_t *dhd, uint16 len, uint cmd, void* buf, int ifidx); static INLINE void dhd_prot_packet_free(dhd_pub_t *dhd, uint32 pktid); static INLINE void *dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid); static void dmaxfer_free_dmaaddr(dhd_pub_t *dhd, dhd_dmaxfer_t *dma); static int dmaxfer_prepare_dmaaddr(dhd_pub_t *dhd, uint len, uint srcdelay, uint destdelay, dhd_dmaxfer_t *dma); static void dhdmsgbuf_dmaxfer_compare(dhd_pub_t *dhd, void *buf, uint16 msglen); static void dhd_prot_process_flow_ring_create_response(dhd_pub_t *dhd, void* buf, uint16 msglen); static void dhd_prot_process_flow_ring_delete_response(dhd_pub_t *dhd, void* buf, uint16 msglen); static void dhd_prot_process_flow_ring_flush_response(dhd_pub_t *dhd, void* buf, uint16 msglen); #ifdef DHD_RX_CHAINING #define PKT_CTF_CHAINABLE(dhd, ifidx, evh, prio, h_sa, h_da, h_prio) \ (!ETHER_ISNULLDEST(((struct ether_header *)(evh))->ether_dhost) && \ !ETHER_ISMULTI(((struct ether_header *)(evh))->ether_dhost) && \ !eacmp((h_da), ((struct ether_header *)(evh))->ether_dhost) && \ !eacmp((h_sa), ((struct ether_header *)(evh))->ether_shost) && \ ((h_prio) == (prio)) && (dhd_ctf_hotbrc_check((dhd), (evh), (ifidx))) && \ ((((struct ether_header *)(evh))->ether_type == HTON16(ETHER_TYPE_IP)) || \ (((struct ether_header *)(evh))->ether_type == HTON16(ETHER_TYPE_IPV6)))) static INLINE void BCMFASTPATH dhd_rxchain_reset(rxchain_info_t *rxchain); static void BCMFASTPATH dhd_rxchain_frame(dhd_pub_t *dhd, void *pkt, uint ifidx); static void BCMFASTPATH dhd_rxchain_commit(dhd_pub_t *dhd); #define DHD_PKT_CTF_MAX_CHAIN_LEN 64 #endif /* DHD_RX_CHAINING */ static uint16 dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, bool event_buf, uint32 max_to_post); static int dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *pub); static int dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *pub); static void dhd_prot_ring_detach(dhd_pub_t *dhd, msgbuf_ring_t * ring); static void dhd_ring_init(dhd_pub_t *dhd, msgbuf_ring_t *ring); static msgbuf_ring_t* prot_ring_attach(dhd_prot_t * prot, char* name, uint16 max_item, uint16 len_item, uint16 ringid); static void* prot_get_ring_space(msgbuf_ring_t *ring, uint16 nitems, uint16 * alloced); static void dhd_set_dmaed_index(dhd_pub_t *dhd, uint8 type, uint16 ringid, uint16 new_index); static uint16 dhd_get_dmaed_index(dhd_pub_t *dhd, uint8 type, uint16 ringid); static void prot_ring_write_complete(dhd_pub_t *dhd, msgbuf_ring_t * ring, void* p, uint16 len); static void prot_upd_read_idx(dhd_pub_t *dhd, msgbuf_ring_t * ring); static uint8* prot_get_src_addr(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint16 *available_len); static void prot_store_rxcpln_read_idx(dhd_pub_t *dhd, msgbuf_ring_t *ring); static void prot_early_upd_rxcpln_read_idx(dhd_pub_t *dhd, msgbuf_ring_t * ring); typedef void (*dhd_msgbuf_func_t)(dhd_pub_t *dhd, void * buf, uint16 msglen); static dhd_msgbuf_func_t table_lookup[DHD_PROT_FUNCS] = { dhd_prot_noop, /* 0 is invalid message type */ dhd_prot_genstatus_process, /* MSG_TYPE_GEN_STATUS */ dhd_prot_ringstatus_process, /* MSG_TYPE_RING_STATUS */ NULL, dhd_prot_process_flow_ring_create_response, /* MSG_TYPE_FLOW_RING_CREATE_CMPLT */ NULL, dhd_prot_process_flow_ring_delete_response, /* MSG_TYPE_FLOW_RING_DELETE_CMPLT */ NULL, dhd_prot_process_flow_ring_flush_response, /* MSG_TYPE_FLOW_RING_FLUSH_CMPLT */ NULL, dhd_prot_ioctack_process, /* MSG_TYPE_IOCTLPTR_REQ_ACK */ NULL, dhd_prot_ioctcmplt_process, /* MSG_TYPE_IOCTL_CMPLT */ NULL, dhd_prot_event_process, /* MSG_TYPE_WL_EVENT */ NULL, dhd_prot_txstatus_process, /* MSG_TYPE_TX_STATUS */ NULL, dhd_prot_rxcmplt_process, /* MSG_TYPE_RX_CMPLT */ NULL, dhdmsgbuf_dmaxfer_compare, /* MSG_TYPE_LPBK_DMAXFER_CMPLT */ NULL, }; #if defined(PCIE_D2H_SYNC) /* * D2H DMA to completion callback handlers. Based on the mode advertised by the * dongle through the PCIE shared region, the appropriate callback will be * registered in the proto layer to be invoked prior to precessing any message * from a D2H DMA ring. If the dongle uses a read barrier or another mode that * does not require host participation, then a noop callback handler will be * bound that simply returns the msgtype. */ static void dhd_prot_d2h_sync_livelock(dhd_pub_t *dhd, uint32 seqnum, uint32 tries, uchar *msg, int msglen); static uint8 dhd_prot_d2h_sync_seqnum(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen); static uint8 dhd_prot_d2h_sync_xorcsum(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen); static uint8 dhd_prot_d2h_sync_none(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen); static void dhd_prot_d2h_sync_init(dhd_pub_t *dhd, dhd_prot_t * prot); /* Debug print a livelock avert by dropping a D2H message */ static void dhd_prot_d2h_sync_livelock(dhd_pub_t *dhd, uint32 seqnum, uint32 tries, uchar *msg, int msglen) { DHD_ERROR(("LIVELOCK DHD<%p> seqnum<%u:%u> tries<%u> max<%lu> tot<%lu>\n", dhd, seqnum, seqnum% D2H_EPOCH_MODULO, tries, dhd->prot->d2h_sync_wait_max, dhd->prot->d2h_sync_wait_tot)); prhex("D2H MsgBuf Failure", (uchar *)msg, msglen); } /* Sync on a D2H DMA to complete using SEQNUM mode */ static uint8 BCMFASTPATH dhd_prot_d2h_sync_seqnum(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen) { uint32 tries; uint32 ring_seqnum = ring->seqnum % D2H_EPOCH_MODULO; int num_words = msglen / sizeof(uint32); /* num of 32bit words */ volatile uint32 *marker = (uint32 *)msg + (num_words - 1); /* last word */ dhd_prot_t *prot = dhd->prot; ASSERT(msglen == RING_LEN_ITEMS(ring)); for (tries = 0; tries < PCIE_D2H_SYNC_WAIT_TRIES; tries++) { uint32 msg_seqnum = *marker; if (ltoh32(msg_seqnum) == ring_seqnum) { /* dma upto last word done */ ring->seqnum++; /* next expected sequence number */ goto dma_completed; } if (tries > prot->d2h_sync_wait_max) prot->d2h_sync_wait_max = tries; OSL_CACHE_INV(msg, msglen); /* invalidate and try again */ } /* for PCIE_D2H_SYNC_WAIT_TRIES */ dhd_prot_d2h_sync_livelock(dhd, ring->seqnum, tries, (uchar *)msg, msglen); ring->seqnum++; /* skip this message ... leak of a pktid */ return 0; /* invalid msgtype 0 -> noop callback */ dma_completed: prot->d2h_sync_wait_tot += tries; return msg->msg_type; } /* Sync on a D2H DMA to complete using XORCSUM mode */ static uint8 BCMFASTPATH dhd_prot_d2h_sync_xorcsum(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen) { uint32 tries; uint32 prot_checksum = 0; /* computed checksum */ int num_words = msglen / sizeof(uint32); /* num of 32bit words */ uint8 ring_seqnum = ring->seqnum % D2H_EPOCH_MODULO; dhd_prot_t *prot = dhd->prot; ASSERT(msglen == RING_LEN_ITEMS(ring)); for (tries = 0; tries < PCIE_D2H_SYNC_WAIT_TRIES; tries++) { prot_checksum = bcm_compute_xor32((volatile uint32 *)msg, num_words); if (prot_checksum == 0U) { /* checksum is OK */ if (msg->epoch == ring_seqnum) { ring->seqnum++; /* next expected sequence number */ goto dma_completed; } } if (tries > prot->d2h_sync_wait_max) prot->d2h_sync_wait_max = tries; OSL_CACHE_INV(msg, msglen); /* invalidate and try again */ } /* for PCIE_D2H_SYNC_WAIT_TRIES */ dhd_prot_d2h_sync_livelock(dhd, ring->seqnum, tries, (uchar *)msg, msglen); ring->seqnum++; /* skip this message ... leak of a pktid */ return 0; /* invalid msgtype 0 -> noop callback */ dma_completed: prot->d2h_sync_wait_tot += tries; return msg->msg_type; } /* Do not sync on a D2H DMA */ static uint8 BCMFASTPATH dhd_prot_d2h_sync_none(dhd_pub_t *dhd, msgbuf_ring_t *ring, volatile cmn_msg_hdr_t *msg, int msglen) { return msg->msg_type; } /* Initialize the D2H DMA Sync mode, per D2H ring seqnum and dhd stats */ static void dhd_prot_d2h_sync_init(dhd_pub_t *dhd, dhd_prot_t * prot) { prot->d2h_sync_wait_max = 0UL; prot->d2h_sync_wait_tot = 0UL; prot->d2hring_tx_cpln->seqnum = D2H_EPOCH_INIT_VAL; prot->d2hring_rx_cpln->seqnum = D2H_EPOCH_INIT_VAL; prot->d2hring_ctrl_cpln->seqnum = D2H_EPOCH_INIT_VAL; if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_SEQNUM) prot->d2h_sync_cb = dhd_prot_d2h_sync_seqnum; else if (dhd->d2h_sync_mode & PCIE_SHARED_D2H_SYNC_XORCSUM) prot->d2h_sync_cb = dhd_prot_d2h_sync_xorcsum; else prot->d2h_sync_cb = dhd_prot_d2h_sync_none; } #endif /* PCIE_D2H_SYNC */ /* * +---------------------------------------------------------------------------+ * PktId Map: Provides a native packet pointer to unique 32bit PktId mapping. * The packet id map, also includes storage for some packet parameters that * may be saved. A native packet pointer along with the parameters may be saved * and a unique 32bit pkt id will be returned. Later, the saved packet pointer * and the metadata may be retrieved using the previously allocated packet id. * +---------------------------------------------------------------------------+ */ #define MAX_PKTID_ITEMS (8192) /* Maximum number of pktids supported */ typedef void * dhd_pktid_map_handle_t; /* opaque handle to a pktid map */ /* Construct a packet id mapping table, returing an opaque map handle */ static dhd_pktid_map_handle_t *dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items); /* Destroy a packet id mapping table, freeing all packets active in the table */ static void dhd_pktid_map_fini(dhd_pktid_map_handle_t *map); /* Determine number of pktids that are available */ static INLINE uint32 dhd_pktid_map_avail_cnt(dhd_pktid_map_handle_t *map); /* Allocate a unique pktid against which a pkt and some metadata is saved */ static INLINE uint32 dhd_pktid_map_reserve(dhd_pktid_map_handle_t *handle, void *pkt); static INLINE void dhd_pktid_map_save(dhd_pktid_map_handle_t *handle, void *pkt, uint32 nkey, dmaaddr_t physaddr, uint32 len, uint8 dma, void *secdma); static uint32 dhd_pktid_map_alloc(dhd_pktid_map_handle_t *map, void *pkt, dmaaddr_t physaddr, uint32 len, uint8 dma, void *secdma); /* Return an allocated pktid, retrieving previously saved pkt and metadata */ static void *dhd_pktid_map_free(dhd_pktid_map_handle_t *map, uint32 id, dmaaddr_t *physaddr, uint32 *len, void **secdma); /* Packet metadata saved in packet id mapper */ typedef struct dhd_pktid_item { bool inuse; /* tag an item to be in use */ uint8 dma; /* map direction: flush or invalidate */ uint16 len; /* length of mapped packet's buffer */ void *pkt; /* opaque native pointer to a packet */ dmaaddr_t physaddr; /* physical address of mapped packet's buffer */ void *secdma; } dhd_pktid_item_t; typedef struct dhd_pktid_map { dhd_pub_t *dhd; int items; /* total items in map */ int avail; /* total available items */ int failures; /* lockers unavailable count */ uint32 keys[MAX_PKTID_ITEMS + 1]; /* stack of unique pkt ids */ dhd_pktid_item_t lockers[0]; /* metadata storage */ } dhd_pktid_map_t; /* * PktId (Locker) #0 is never allocated and is considered invalid. * * On request for a pktid, a value DHD_PKTID_INVALID must be treated as a * depleted pktid pool and must not be used by the caller. * * Likewise, a caller must never free a pktid of value DHD_PKTID_INVALID. */ #define DHD_PKTID_INVALID (0U) #define DHD_PKTID_ITEM_SZ (sizeof(dhd_pktid_item_t)) #define DHD_PKTID_MAP_SZ(items) (sizeof(dhd_pktid_map_t) + \ (DHD_PKTID_ITEM_SZ * ((items) + 1))) #define NATIVE_TO_PKTID_INIT(dhd, items) dhd_pktid_map_init((dhd), (items)) #define NATIVE_TO_PKTID_FINI(map) dhd_pktid_map_fini(map) #define NATIVE_TO_PKTID_CLEAR(map) dhd_pktid_map_clear(map) #define NATIVE_TO_PKTID_RSV(map, pkt) dhd_pktid_map_reserve((map), (pkt)) #define NATIVE_TO_PKTID_SAVE(map, pkt, nkey, pa, len, dma, secdma) \ dhd_pktid_map_save((map), (void *)(pkt), (nkey), (pa), (uint32)(len), (uint8)dma, \ (void *)(secdma)) #define NATIVE_TO_PKTID(map, pkt, pa, len, dma, secdma) \ dhd_pktid_map_alloc((map), (void *)(pkt), (pa), (uint32)(len), (uint8)dma, (void *)(secdma)) #define PKTID_TO_NATIVE(map, pktid, pa, len, secdma) \ dhd_pktid_map_free((map), (uint32)(pktid), \ (dmaaddr_t *)&(pa), (uint32 *)&(len), (void **) &secdma) #define PKTID_AVAIL(map) dhd_pktid_map_avail_cnt(map) #if defined(CONFIG_DHD_USE_STATIC_BUF) && defined(DHD_USE_STATIC_FLOWRING) #define FLOWRING_NAME "h2dflr" #define RING_IS_FLOWRING(ring) \ ((strncmp(ring->name, FLOWRING_NAME, sizeof(FLOWRING_NAME))) == (0)) #endif /* CONFIG_DHD_USE_STATIC_BUF && DHD_USE_STATIC_FLOWRING */ /* * +---------------------------------------------------------------------------+ * Packet to Packet Id mapper using a paradigm. * * dhd_pktid_map manages a set of unique Packet Ids range[1..MAX_PKTID_ITEMS]. * * dhd_pktid_map_alloc() may be used to save some packet metadata, and a unique * packet id is returned. This unique packet id may be used to retrieve the * previously saved packet metadata, using dhd_pktid_map_free(). On invocation * of dhd_pktid_map_free(), the unique packet id is essentially freed. A * subsequent call to dhd_pktid_map_alloc() may reuse this packet id. * * Implementation Note: * Convert this into a abstraction and place into bcmutils ! * Locker abstraction should treat contents as opaque storage, and a * callback should be registered to handle inuse lockers on destructor. * * +---------------------------------------------------------------------------+ */ /* Allocate and initialize a mapper of num_items */ static dhd_pktid_map_handle_t * dhd_pktid_map_init(dhd_pub_t *dhd, uint32 num_items) { uint32 nkey; dhd_pktid_map_t *map; uint32 dhd_pktid_map_sz; ASSERT((num_items >= 1) && num_items <= MAX_PKTID_ITEMS); dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(num_items); if ((map = (dhd_pktid_map_t *)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_PKTID_MAP, dhd_pktid_map_sz)) == NULL) { DHD_ERROR(("%s:%d: MALLOC failed for size %d\n", __FUNCTION__, __LINE__, dhd_pktid_map_sz)); return NULL; } bzero(map, dhd_pktid_map_sz); map->dhd = dhd; map->items = num_items; map->avail = num_items; map->lockers[DHD_PKTID_INVALID].inuse = TRUE; /* tag locker #0 as inuse */ for (nkey = 1; nkey <= num_items; nkey++) { /* locker #0 is reserved */ map->keys[nkey] = nkey; /* populate with unique keys */ map->lockers[nkey].inuse = FALSE; } return (dhd_pktid_map_handle_t *)map; /* opaque handle */ } /* * Retrieve all allocated keys and free all . * Freeing implies: unmapping the buffers and freeing the native packet * This could have been a callback registered with the pktid mapper. */ static void dhd_pktid_map_fini(dhd_pktid_map_handle_t *handle) { void *osh; int nkey; dhd_pktid_map_t *map; uint32 dhd_pktid_map_sz; dhd_pktid_item_t *locker; if (handle == NULL) return; map = (dhd_pktid_map_t *)handle; osh = map->dhd->osh; dhd_pktid_map_sz = DHD_PKTID_MAP_SZ(map->items); nkey = 1; /* skip reserved KEY #0, and start from 1 */ locker = &map->lockers[nkey]; for (; nkey <= map->items; nkey++, locker++) { if (locker->inuse == TRUE) { /* numbered key still in use */ locker->inuse = FALSE; /* force open the locker */ { /* This could be a callback registered with dhd_pktid_map */ DMA_UNMAP(osh, locker->physaddr, locker->len, locker->dma, 0, 0); PKTFREE(osh, (ulong*)locker->pkt, FALSE); } } } DHD_OS_PREFREE(map->dhd, handle, dhd_pktid_map_sz); } static void dhd_pktid_map_clear(dhd_pktid_map_handle_t *handle) { void *osh; int nkey; dhd_pktid_map_t *map; dhd_pktid_item_t *locker; DHD_TRACE(("%s\n", __FUNCTION__)); if (handle == NULL) return; map = (dhd_pktid_map_t *)handle; osh = map->dhd->osh; map->failures = 0; nkey = 1; /* skip reserved KEY #0, and start from 1 */ locker = &map->lockers[nkey]; for (; nkey <= map->items; nkey++, locker++) { map->keys[nkey] = nkey; /* populate with unique keys */ if (locker->inuse == TRUE) { /* numbered key still in use */ locker->inuse = FALSE; /* force open the locker */ DHD_TRACE(("%s free id%d\n", __FUNCTION__, nkey)); DMA_UNMAP(osh, locker->physaddr, locker->len, locker->dma, 0, 0); PKTFREE(osh, (ulong*)locker->pkt, FALSE); } } map->avail = map->items; } /* Get the pktid free count */ static INLINE uint32 BCMFASTPATH dhd_pktid_map_avail_cnt(dhd_pktid_map_handle_t *handle) { dhd_pktid_map_t *map; ASSERT(handle != NULL); map = (dhd_pktid_map_t *)handle; return map->avail; } /* * Allocate locker, save pkt contents, and return the locker's numbered key. * dhd_pktid_map_alloc() is not reentrant, and is the caller's responsibility. * Caller must treat a returned value DHD_PKTID_INVALID as a failure case, * implying a depleted pool of pktids. */ static INLINE uint32 dhd_pktid_map_reserve(dhd_pktid_map_handle_t *handle, void *pkt) { uint32 nkey; dhd_pktid_map_t *map; dhd_pktid_item_t *locker; ASSERT(handle != NULL); map = (dhd_pktid_map_t *)handle; if (map->avail <= 0) { /* no more pktids to allocate */ map->failures++; DHD_INFO(("%s:%d: failed, no free keys\n", __FUNCTION__, __LINE__)); return DHD_PKTID_INVALID; /* failed alloc request */ } ASSERT(map->avail <= map->items); nkey = map->keys[map->avail]; /* fetch a free locker, pop stack */ map->avail--; locker = &map->lockers[nkey]; /* save packet metadata in locker */ locker->inuse = TRUE; /* reserve this locker */ locker->pkt = pkt; ASSERT(nkey != DHD_PKTID_INVALID); return nkey; /* return locker's numbered key */ } static INLINE void dhd_pktid_map_save(dhd_pktid_map_handle_t *handle, void *pkt, uint32 nkey, dmaaddr_t physaddr, uint32 len, uint8 dma, void *secdma) { dhd_pktid_map_t *map; dhd_pktid_item_t *locker; ASSERT(handle != NULL); map = (dhd_pktid_map_t *)handle; ASSERT((nkey != DHD_PKTID_INVALID) && (nkey <= (uint32)map->items)); locker = &map->lockers[nkey]; ASSERT(locker->pkt == pkt); locker->dma = dma; /* store contents in locker */ locker->physaddr = physaddr; locker->len = (uint16)len; /* 16bit len */ locker->secdma = secdma; } static uint32 BCMFASTPATH dhd_pktid_map_alloc(dhd_pktid_map_handle_t *handle, void *pkt, dmaaddr_t physaddr, uint32 len, uint8 dma, void *secdma) { uint32 nkey = dhd_pktid_map_reserve(handle, pkt); if (nkey != DHD_PKTID_INVALID) { dhd_pktid_map_save(handle, pkt, nkey, physaddr, len, dma, secdma); } return nkey; } /* * Given a numbered key, return the locker contents. * dhd_pktid_map_free() is not reentrant, and is the caller's responsibility. * Caller may not free a pktid value DHD_PKTID_INVALID or an arbitrary pktid * value. Only a previously allocated pktid may be freed. */ static void * BCMFASTPATH dhd_pktid_map_free(dhd_pktid_map_handle_t *handle, uint32 nkey, dmaaddr_t *physaddr, uint32 *len, void **secdma) { dhd_pktid_map_t *map; dhd_pktid_item_t *locker; ASSERT(handle != NULL); map = (dhd_pktid_map_t *)handle; ASSERT((nkey != DHD_PKTID_INVALID) && (nkey <= (uint32)map->items)); locker = &map->lockers[nkey]; if (locker->inuse == FALSE) { /* Debug check for cloned numbered key */ DHD_ERROR(("%s:%d: Error! freeing invalid pktid<%u>\n", __FUNCTION__, __LINE__, nkey)); ASSERT(locker->inuse != FALSE); return NULL; } map->avail++; map->keys[map->avail] = nkey; /* make this numbered key available */ locker->inuse = FALSE; /* open and free Locker */ *physaddr = locker->physaddr; /* return contents of locker */ *len = (uint32)locker->len; *secdma = locker->secdma; return locker->pkt; } /* Linkage, sets prot link and updates hdrlen in pub */ int dhd_prot_attach(dhd_pub_t *dhd) { uint alloced = 0; dhd_prot_t *prot; /* Allocate prot structure */ if (!(prot = (dhd_prot_t *)DHD_OS_PREALLOC(dhd, DHD_PREALLOC_PROT, sizeof(dhd_prot_t)))) { DHD_ERROR(("%s: kmalloc failed\n", __FUNCTION__)); goto fail; } memset(prot, 0, sizeof(*prot)); prot->osh = dhd->osh; dhd->prot = prot; /* DMAing ring completes supported? FALSE by default */ dhd->dma_d2h_ring_upd_support = FALSE; dhd->dma_h2d_ring_upd_support = FALSE; /* Ring Allocations */ /* 1.0 H2D TXPOST ring */ if (!(prot->h2dring_txp_subn = prot_ring_attach(prot, "h2dtxp", H2DRING_TXPOST_MAX_ITEM, H2DRING_TXPOST_ITEMSIZE, BCMPCIE_H2D_TXFLOWRINGID))) { DHD_ERROR(("%s: kmalloc for H2D TXPOST ring failed\n", __FUNCTION__)); goto fail; } /* 2.0 H2D RXPOST ring */ if (!(prot->h2dring_rxp_subn = prot_ring_attach(prot, "h2drxp", H2DRING_RXPOST_MAX_ITEM, H2DRING_RXPOST_ITEMSIZE, BCMPCIE_H2D_MSGRING_RXPOST_SUBMIT))) { DHD_ERROR(("%s: kmalloc for H2D RXPOST ring failed\n", __FUNCTION__)); goto fail; } /* 3.0 H2D CTRL_SUBMISSION ring */ if (!(prot->h2dring_ctrl_subn = prot_ring_attach(prot, "h2dctrl", H2DRING_CTRL_SUB_MAX_ITEM, H2DRING_CTRL_SUB_ITEMSIZE, BCMPCIE_H2D_MSGRING_CONTROL_SUBMIT))) { DHD_ERROR(("%s: kmalloc for H2D CTRL_SUBMISSION ring failed\n", __FUNCTION__)); goto fail; } /* 4.0 D2H TX_COMPLETION ring */ if (!(prot->d2hring_tx_cpln = prot_ring_attach(prot, "d2htxcpl", D2HRING_TXCMPLT_MAX_ITEM, D2HRING_TXCMPLT_ITEMSIZE, BCMPCIE_D2H_MSGRING_TX_COMPLETE))) { DHD_ERROR(("%s: kmalloc for D2H TX_COMPLETION ring failed\n", __FUNCTION__)); goto fail; } /* 5.0 D2H RX_COMPLETION ring */ if (!(prot->d2hring_rx_cpln = prot_ring_attach(prot, "d2hrxcpl", D2HRING_RXCMPLT_MAX_ITEM, D2HRING_RXCMPLT_ITEMSIZE, BCMPCIE_D2H_MSGRING_RX_COMPLETE))) { DHD_ERROR(("%s: kmalloc for D2H RX_COMPLETION ring failed\n", __FUNCTION__)); goto fail; } /* 6.0 D2H CTRL_COMPLETION ring */ if (!(prot->d2hring_ctrl_cpln = prot_ring_attach(prot, "d2hctrl", D2HRING_CTRL_CMPLT_MAX_ITEM, D2HRING_CTRL_CMPLT_ITEMSIZE, BCMPCIE_D2H_MSGRING_CONTROL_COMPLETE))) { DHD_ERROR(("%s: kmalloc for D2H CTRL_COMPLETION ring failed\n", __FUNCTION__)); goto fail; } /* Return buffer for ioctl */ prot->retbuf.va = DMA_ALLOC_CONSISTENT(dhd->osh, IOCT_RETBUF_SIZE, DMA_ALIGN_LEN, &alloced, &prot->retbuf.pa, &prot->retbuf.dmah); if (prot->retbuf.va == NULL) { ASSERT(0); return BCME_NOMEM; } ASSERT(MODX((unsigned long)prot->retbuf.va, DMA_ALIGN_LEN) == 0); bzero(prot->retbuf.va, IOCT_RETBUF_SIZE); OSL_CACHE_FLUSH((void *) prot->retbuf.va, IOCT_RETBUF_SIZE); /* IOCTL request buffer */ prot->ioctbuf.va = DMA_ALLOC_CONSISTENT(dhd->osh, IOCT_RETBUF_SIZE, DMA_ALIGN_LEN, &alloced, &prot->ioctbuf.pa, &prot->ioctbuf.dmah); if (prot->ioctbuf.va == NULL) { ASSERT(0); return BCME_NOMEM; } ASSERT(MODX((unsigned long)prot->ioctbuf.va, DMA_ALIGN_LEN) == 0); bzero(prot->ioctbuf.va, IOCT_RETBUF_SIZE); OSL_CACHE_FLUSH((void *) prot->ioctbuf.va, IOCT_RETBUF_SIZE); /* Scratch buffer for dma rx offset */ prot->d2h_dma_scratch_buf_len = DMA_D2H_SCRATCH_BUF_LEN; prot->d2h_dma_scratch_buf.va = DMA_ALLOC_CONSISTENT(dhd->osh, DMA_D2H_SCRATCH_BUF_LEN, DMA_ALIGN_LEN, &alloced, &prot->d2h_dma_scratch_buf.pa, &prot->d2h_dma_scratch_buf.dmah); if (prot->d2h_dma_scratch_buf.va == NULL) { ASSERT(0); return BCME_NOMEM; } ASSERT(MODX((unsigned long)prot->d2h_dma_scratch_buf.va, DMA_ALIGN_LEN) == 0); bzero(prot->d2h_dma_scratch_buf.va, DMA_D2H_SCRATCH_BUF_LEN); OSL_CACHE_FLUSH((void *)prot->d2h_dma_scratch_buf.va, DMA_D2H_SCRATCH_BUF_LEN); /* PKTID handle INIT */ prot->pktid_map_handle = NATIVE_TO_PKTID_INIT(dhd, MAX_PKTID_ITEMS); if (prot->pktid_map_handle == NULL) { ASSERT(0); return BCME_NOMEM; } #if defined(PCIE_D2H_SYNC) dhd_prot_d2h_sync_init(dhd, prot); #endif /* PCIE_D2H_SYNC */ prot->dmaxfer.srcmem.va = NULL; prot->dmaxfer.destmem.va = NULL; prot->dmaxfer_in_progress = FALSE; prot->rx_metadata_offset = 0; prot->tx_metadata_offset = 0; #ifdef DHD_RX_CHAINING dhd_rxchain_reset(&prot->rxchain); #endif return 0; fail: #ifndef CONFIG_DHD_USE_STATIC_BUF if (prot != NULL) dhd_prot_detach(dhd); #endif /* CONFIG_DHD_USE_STATIC_BUF */ return BCME_NOMEM; } /* Init memory block on host DMA'ing indices */ int dhd_prot_init_index_dma_block(dhd_pub_t *dhd, uint8 type, uint32 length) { uint alloced = 0; dhd_prot_t *prot = dhd->prot; uint32 dma_block_size = 4 * length; if (prot == NULL) { DHD_ERROR(("prot is not inited\n")); return BCME_ERROR; } switch (type) { case HOST_TO_DNGL_DMA_WRITEINDX_BUFFER: /* ring update dma buffer for submission write */ prot->h2d_dma_writeindx_buf_len = dma_block_size; prot->h2d_dma_writeindx_buf.va = DMA_ALLOC_CONSISTENT(dhd->osh, dma_block_size, DMA_ALIGN_LEN, &alloced, &prot->h2d_dma_writeindx_buf.pa, &prot->h2d_dma_writeindx_buf.dmah); if (prot->h2d_dma_writeindx_buf.va == NULL) { return BCME_NOMEM; } ASSERT(ISALIGNED(prot->h2d_dma_writeindx_buf.va, 4)); bzero(prot->h2d_dma_writeindx_buf.va, dma_block_size); OSL_CACHE_FLUSH((void *)prot->h2d_dma_writeindx_buf.va, dma_block_size); DHD_ERROR(("H2D_WRITEINDX_ARRAY_HOST: %d-bytes " "inited for dma'ing h2d-w indices\n", prot->h2d_dma_writeindx_buf_len)); break; case HOST_TO_DNGL_DMA_READINDX_BUFFER: /* ring update dma buffer for submission read */ prot->h2d_dma_readindx_buf_len = dma_block_size; prot->h2d_dma_readindx_buf.va = DMA_ALLOC_CONSISTENT(dhd->osh, dma_block_size, DMA_ALIGN_LEN, &alloced, &prot->h2d_dma_readindx_buf.pa, &prot->h2d_dma_readindx_buf.dmah); if (prot->h2d_dma_readindx_buf.va == NULL) { return BCME_NOMEM; } ASSERT(ISALIGNED(prot->h2d_dma_readindx_buf.va, 4)); bzero(prot->h2d_dma_readindx_buf.va, dma_block_size); OSL_CACHE_FLUSH((void *)prot->h2d_dma_readindx_buf.va, dma_block_size); DHD_ERROR(("H2D_READINDX_ARRAY_HOST %d-bytes " "inited for dma'ing h2d-r indices\n", prot->h2d_dma_readindx_buf_len)); break; case DNGL_TO_HOST_DMA_WRITEINDX_BUFFER: /* ring update dma buffer for completion write */ prot->d2h_dma_writeindx_buf_len = dma_block_size; prot->d2h_dma_writeindx_buf.va = DMA_ALLOC_CONSISTENT(dhd->osh, dma_block_size, DMA_ALIGN_LEN, &alloced, &prot->d2h_dma_writeindx_buf.pa, &prot->d2h_dma_writeindx_buf.dmah); if (prot->d2h_dma_writeindx_buf.va == NULL) { return BCME_NOMEM; } ASSERT(ISALIGNED(prot->d2h_dma_writeindx_buf.va, 4)); bzero(prot->d2h_dma_writeindx_buf.va, dma_block_size); OSL_CACHE_FLUSH((void *)prot->d2h_dma_writeindx_buf.va, dma_block_size); DHD_ERROR(("D2H_WRITEINDX_ARRAY_HOST %d-bytes " "inited for dma'ing d2h-w indices\n", prot->d2h_dma_writeindx_buf_len)); break; case DNGL_TO_HOST_DMA_READINDX_BUFFER: /* ring update dma buffer for completion read */ prot->d2h_dma_readindx_buf_len = dma_block_size; prot->d2h_dma_readindx_buf.va = DMA_ALLOC_CONSISTENT(dhd->osh, dma_block_size, DMA_ALIGN_LEN, &alloced, &prot->d2h_dma_readindx_buf.pa, &prot->d2h_dma_readindx_buf.dmah); if (prot->d2h_dma_readindx_buf.va == NULL) { return BCME_NOMEM; } ASSERT(ISALIGNED(prot->d2h_dma_readindx_buf.va, 4)); bzero(prot->d2h_dma_readindx_buf.va, dma_block_size); OSL_CACHE_FLUSH((void *)prot->d2h_dma_readindx_buf.va, dma_block_size); DHD_ERROR(("D2H_READINDX_ARRAY_HOST %d-bytes " "inited for dma'ing d2h-r indices\n", prot->d2h_dma_readindx_buf_len)); break; default: DHD_ERROR(("%s: Unexpected option\n", __FUNCTION__)); return BCME_BADOPTION; } return BCME_OK; } /* Unlink, frees allocated protocol memory (including dhd_prot) */ void dhd_prot_detach(dhd_pub_t *dhd) { dhd_prot_t *prot = dhd->prot; /* Stop the protocol module */ if (dhd->prot) { /* free up scratch buffer */ if (prot->d2h_dma_scratch_buf.va) { DMA_FREE_CONSISTENT(dhd->osh, prot->d2h_dma_scratch_buf.va, DMA_D2H_SCRATCH_BUF_LEN, prot->d2h_dma_scratch_buf.pa, prot->d2h_dma_scratch_buf.dmah); prot->d2h_dma_scratch_buf.va = NULL; } /* free up ring upd buffer for submission writes */ if (prot->h2d_dma_writeindx_buf.va) { DMA_FREE_CONSISTENT(dhd->osh, prot->h2d_dma_writeindx_buf.va, prot->h2d_dma_writeindx_buf_len, prot->h2d_dma_writeindx_buf.pa, prot->h2d_dma_writeindx_buf.dmah); prot->h2d_dma_writeindx_buf.va = NULL; } /* free up ring upd buffer for submission reads */ if (prot->h2d_dma_readindx_buf.va) { DMA_FREE_CONSISTENT(dhd->osh, prot->h2d_dma_readindx_buf.va, prot->h2d_dma_readindx_buf_len, prot->h2d_dma_readindx_buf.pa, prot->h2d_dma_readindx_buf.dmah); prot->h2d_dma_readindx_buf.va = NULL; } /* free up ring upd buffer for completion writes */ if (prot->d2h_dma_writeindx_buf.va) { DMA_FREE_CONSISTENT(dhd->osh, prot->d2h_dma_writeindx_buf.va, prot->d2h_dma_writeindx_buf_len, prot->d2h_dma_writeindx_buf.pa, prot->d2h_dma_writeindx_buf.dmah); prot->d2h_dma_writeindx_buf.va = NULL; } /* free up ring upd buffer for completion writes */ if (prot->d2h_dma_readindx_buf.va) { DMA_FREE_CONSISTENT(dhd->osh, prot->d2h_dma_readindx_buf.va, prot->d2h_dma_readindx_buf_len, prot->d2h_dma_readindx_buf.pa, prot->d2h_dma_readindx_buf.dmah); prot->d2h_dma_readindx_buf.va = NULL; } /* ioctl return buffer */ if (prot->retbuf.va) { DMA_FREE_CONSISTENT(dhd->osh, dhd->prot->retbuf.va, IOCT_RETBUF_SIZE, dhd->prot->retbuf.pa, dhd->prot->retbuf.dmah); dhd->prot->retbuf.va = NULL; } /* ioctl request buffer */ if (prot->ioctbuf.va) { DMA_FREE_CONSISTENT(dhd->osh, dhd->prot->ioctbuf.va, IOCT_RETBUF_SIZE, dhd->prot->ioctbuf.pa, dhd->prot->ioctbuf.dmah); dhd->prot->ioctbuf.va = NULL; } /* 1.0 H2D TXPOST ring */ dhd_prot_ring_detach(dhd, prot->h2dring_txp_subn); /* 2.0 H2D RXPOST ring */ dhd_prot_ring_detach(dhd, prot->h2dring_rxp_subn); /* 3.0 H2D CTRL_SUBMISSION ring */ dhd_prot_ring_detach(dhd, prot->h2dring_ctrl_subn); /* 4.0 D2H TX_COMPLETION ring */ dhd_prot_ring_detach(dhd, prot->d2hring_tx_cpln); /* 5.0 D2H RX_COMPLETION ring */ dhd_prot_ring_detach(dhd, prot->d2hring_rx_cpln); /* 6.0 D2H CTRL_COMPLETION ring */ dhd_prot_ring_detach(dhd, prot->d2hring_ctrl_cpln); NATIVE_TO_PKTID_FINI(dhd->prot->pktid_map_handle); #ifndef CONFIG_DHD_USE_STATIC_BUF MFREE(dhd->osh, dhd->prot, sizeof(dhd_prot_t)); #endif /* CONFIG_DHD_USE_STATIC_BUF */ dhd->prot = NULL; } } void dhd_prot_rx_dataoffset(dhd_pub_t *dhd, uint32 rx_offset) { dhd_prot_t *prot = dhd->prot; prot->rx_dataoffset = rx_offset; } /* Initialize protocol: sync w/dongle state. * Sets dongle media info (iswl, drv_version, mac address). */ int dhd_sync_with_dongle(dhd_pub_t *dhd) { int ret = 0; wlc_rev_info_t revinfo; DHD_TRACE(("%s: Enter\n", __FUNCTION__)); /* Post event buffer after shim layer is attached */ ret = dhd_msgbuf_rxbuf_post_event_bufs(dhd); if (ret <= 0) { DHD_ERROR(("%s : Post event buffer fail. ret = %d\n", __FUNCTION__, ret)); return ret; } /* Get the device rev info */ memset(&revinfo, 0, sizeof(revinfo)); ret = dhd_wl_ioctl_cmd(dhd, WLC_GET_REVINFO, &revinfo, sizeof(revinfo), FALSE, 0); if (ret < 0) goto done; dhd_process_cid_mac(dhd, TRUE); ret = dhd_preinit_ioctls(dhd); if (!ret) dhd_process_cid_mac(dhd, FALSE); /* Always assumes wl for now */ dhd->iswl = TRUE; done: return ret; } /* This function does all necessary initialization needed * for IOCTL/IOVAR path */ int dhd_prot_init(dhd_pub_t *dhd) { int ret = 0; dhd_prot_t *prot = dhd->prot; /* Max pkts in ring */ prot->max_tx_count = H2DRING_TXPOST_MAX_ITEM; DHD_INFO(("%s:%d: MAX_TX_COUNT = %d\n", __FUNCTION__, __LINE__, prot->max_tx_count)); /* Read max rx packets supported by dongle */ dhd_bus_cmn_readshared(dhd->bus, &prot->max_rxbufpost, MAX_HOST_RXBUFS, 0); if (prot->max_rxbufpost == 0) { /* This would happen if the dongle firmware is not */ /* using the latest shared structure template */ prot->max_rxbufpost = DEFAULT_RX_BUFFERS_TO_POST; } DHD_INFO(("%s:%d: MAX_RXBUFPOST = %d\n", __FUNCTION__, __LINE__, prot->max_rxbufpost)); prot->max_eventbufpost = DHD_FLOWRING_MAX_EVENTBUF_POST; prot->max_ioctlrespbufpost = DHD_FLOWRING_MAX_IOCTLRESPBUF_POST; prot->active_tx_count = 0; prot->data_seq_no = 0; prot->ioctl_seq_no = 0; prot->txp_threshold = TXP_FLUSH_MAX_ITEMS_FLUSH_CNT; prot->ioctl_trans_id = 1; /* Register the interrupt function upfront */ /* remove corerev checks in data path */ prot->mb_ring_fn = dhd_bus_get_mbintr_fn(dhd->bus); /* Initialise rings */ /* 1.0 H2D TXPOST ring */ if (dhd_bus_is_txmode_push(dhd->bus)) { dhd_ring_init(dhd, prot->h2dring_txp_subn); } /* 2.0 H2D RXPOST ring */ dhd_ring_init(dhd, prot->h2dring_rxp_subn); /* 3.0 H2D CTRL_SUBMISSION ring */ dhd_ring_init(dhd, prot->h2dring_ctrl_subn); /* 4.0 D2H TX_COMPLETION ring */ dhd_ring_init(dhd, prot->d2hring_tx_cpln); /* 5.0 D2H RX_COMPLETION ring */ dhd_ring_init(dhd, prot->d2hring_rx_cpln); /* 6.0 D2H CTRL_COMPLETION ring */ dhd_ring_init(dhd, prot->d2hring_ctrl_cpln); /* init the scratch buffer */ dhd_bus_cmn_writeshared(dhd->bus, &prot->d2h_dma_scratch_buf.pa, sizeof(prot->d2h_dma_scratch_buf.pa), DNGL_TO_HOST_DMA_SCRATCH_BUFFER, 0); dhd_bus_cmn_writeshared(dhd->bus, &prot->d2h_dma_scratch_buf_len, sizeof(prot->d2h_dma_scratch_buf_len), DNGL_TO_HOST_DMA_SCRATCH_BUFFER_LEN, 0); /* If supported by the host, indicate the memory block * for comletion writes / submission reads to shared space */ if (DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support)) { dhd_bus_cmn_writeshared(dhd->bus, &prot->d2h_dma_writeindx_buf.pa, sizeof(prot->d2h_dma_writeindx_buf.pa), DNGL_TO_HOST_DMA_WRITEINDX_BUFFER, 0); dhd_bus_cmn_writeshared(dhd->bus, &prot->h2d_dma_readindx_buf.pa, sizeof(prot->h2d_dma_readindx_buf.pa), HOST_TO_DNGL_DMA_READINDX_BUFFER, 0); } if (DMA_INDX_ENAB(dhd->dma_h2d_ring_upd_support)) { dhd_bus_cmn_writeshared(dhd->bus, &prot->h2d_dma_writeindx_buf.pa, sizeof(prot->h2d_dma_writeindx_buf.pa), HOST_TO_DNGL_DMA_WRITEINDX_BUFFER, 0); dhd_bus_cmn_writeshared(dhd->bus, &prot->d2h_dma_readindx_buf.pa, sizeof(prot->d2h_dma_readindx_buf.pa), DNGL_TO_HOST_DMA_READINDX_BUFFER, 0); } ret = dhd_msgbuf_rxbuf_post(dhd); ret = dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd); return ret; } #define DHD_DBG_SHOW_METADATA 0 #if DHD_DBG_SHOW_METADATA static void BCMFASTPATH dhd_prot_print_metadata(dhd_pub_t *dhd, void *ptr, int len) { uint8 tlv_t; uint8 tlv_l; uint8 *tlv_v = (uint8 *)ptr; if (len <= BCMPCIE_D2H_METADATA_HDRLEN) return; len -= BCMPCIE_D2H_METADATA_HDRLEN; tlv_v += BCMPCIE_D2H_METADATA_HDRLEN; while (len > TLV_HDR_LEN) { tlv_t = tlv_v[TLV_TAG_OFF]; tlv_l = tlv_v[TLV_LEN_OFF]; len -= TLV_HDR_LEN; tlv_v += TLV_HDR_LEN; if (len < tlv_l) break; if ((tlv_t == 0) || (tlv_t == WLFC_CTL_TYPE_FILLER)) break; switch (tlv_t) { case WLFC_CTL_TYPE_TXSTATUS: bcm_print_bytes("METADATA TX_STATUS", tlv_v, tlv_l); break; case WLFC_CTL_TYPE_RSSI: bcm_print_bytes("METADATA RX_RSSI", tlv_v, tlv_l); break; case WLFC_CTL_TYPE_FIFO_CREDITBACK: bcm_print_bytes("METADATA FIFO_CREDITBACK", tlv_v, tlv_l); break; case WLFC_CTL_TYPE_TX_ENTRY_STAMP: bcm_print_bytes("METADATA TX_ENTRY", tlv_v, tlv_l); break; case WLFC_CTL_TYPE_RX_STAMP: bcm_print_bytes("METADATA RX_TIMESTAMP", tlv_v, tlv_l); break; case WLFC_CTL_TYPE_TRANS_ID: bcm_print_bytes("METADATA TRANS_ID", tlv_v, tlv_l); break; case WLFC_CTL_TYPE_COMP_TXSTATUS: bcm_print_bytes("METADATA COMP_TXSTATUS", tlv_v, tlv_l); break; default: bcm_print_bytes("METADATA UNKNOWN", tlv_v, tlv_l); break; } len -= tlv_l; tlv_v += tlv_l; } } #endif /* DHD_DBG_SHOW_METADATA */ static INLINE void BCMFASTPATH dhd_prot_packet_free(dhd_pub_t *dhd, uint32 pktid) { void *PKTBUF; dmaaddr_t pa; uint32 pa_len; void *secdma; PKTBUF = PKTID_TO_NATIVE(dhd->prot->pktid_map_handle, pktid, pa, pa_len, secdma); if (PKTBUF) { { if (SECURE_DMA_ENAB(dhd->osh)) { SECURE_DMA_UNMAP(dhd->osh, pa, (uint) pa_len, DMA_TX, 0, 0, secdma, 0); } else DMA_UNMAP(dhd->osh, pa, (uint) pa_len, DMA_TX, 0, 0); } PKTFREE(dhd->osh, PKTBUF, FALSE); } return; } static INLINE void * BCMFASTPATH dhd_prot_packet_get(dhd_pub_t *dhd, uint32 pktid) { void *PKTBUF; dmaaddr_t pa; uint32 pa_len; void *secdma; PKTBUF = PKTID_TO_NATIVE(dhd->prot->pktid_map_handle, pktid, pa, pa_len, secdma); if (PKTBUF) { if (SECURE_DMA_ENAB(dhd->osh)) SECURE_DMA_UNMAP(dhd->osh, pa, (uint) pa_len, DMA_RX, 0, 0, secdma, 0); else DMA_UNMAP(dhd->osh, pa, (uint) pa_len, DMA_RX, 0, 0); } return PKTBUF; } static int BCMFASTPATH dhd_msgbuf_rxbuf_post(dhd_pub_t *dhd) { dhd_prot_t *prot = dhd->prot; int16 fillbufs; uint16 cnt = 64; int retcount = 0; fillbufs = prot->max_rxbufpost - prot->rxbufpost; while (fillbufs > 0) { cnt--; if (cnt == 0) { /* find a better way to reschedule rx buf post if space not available */ DHD_ERROR(("h2d rx post ring not available to post host buffers \n")); DHD_ERROR(("Current posted host buf count %d \n", prot->rxbufpost)); break; } /* Post in a burst of 8 buffers ata time */ fillbufs = MIN(fillbufs, RX_BUF_BURST); /* Post buffers */ retcount = dhd_prot_rxbufpost(dhd, fillbufs); if (retcount > 0) { prot->rxbufpost += (uint16)retcount; /* how many more to post */ fillbufs = prot->max_rxbufpost - prot->rxbufpost; } else { /* Make sure we don't run loop any further */ fillbufs = 0; } } return 0; } /* Post count no of rx buffers down to dongle */ static int BCMFASTPATH dhd_prot_rxbufpost(dhd_pub_t *dhd, uint16 count) { void *p; uint16 pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ; uint8 *rxbuf_post_tmp; host_rxbuf_post_t *rxbuf_post; void* msg_start; dmaaddr_t physaddr, meta_physaddr; uint32 pktlen; dhd_prot_t *prot = dhd->prot; msgbuf_ring_t * ring = prot->h2dring_rxp_subn; uint8 i = 0; uint16 alloced = 0; unsigned long flags; DHD_GENERAL_LOCK(dhd, flags); /* Claim space for 'count' no of messages */ msg_start = (void *)dhd_alloc_ring_space(dhd, ring, count, &alloced); DHD_GENERAL_UNLOCK(dhd, flags); if (msg_start == NULL) { DHD_INFO(("%s:%d: Rxbufpost Msgbuf Not available\n", __FUNCTION__, __LINE__)); return -1; } /* if msg_start != NULL, we should have alloced space for atleast 1 item */ ASSERT(alloced > 0); rxbuf_post_tmp = (uint8*)msg_start; /* loop through each message */ for (i = 0; i < alloced; i++) { rxbuf_post = (host_rxbuf_post_t *)rxbuf_post_tmp; /* Create a rx buffer */ if ((p = PKTGET(dhd->osh, pktsz, FALSE)) == NULL) { DHD_ERROR(("%s:%d: PKTGET for rxbuf failed\n", __FUNCTION__, __LINE__)); break; } pktlen = PKTLEN(dhd->osh, p); if (SECURE_DMA_ENAB(dhd->osh)) { DHD_GENERAL_LOCK(dhd, flags); physaddr = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0, ring->secdma, 0); DHD_GENERAL_UNLOCK(dhd, flags); } else physaddr = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0); if (PHYSADDRISZERO(physaddr)) { if (SECURE_DMA_ENAB(dhd->osh)) { DHD_GENERAL_LOCK(dhd, flags); SECURE_DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0, ring->secdma, 0); DHD_GENERAL_UNLOCK(dhd, flags); } else DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0); PKTFREE(dhd->osh, p, FALSE); DHD_ERROR(("Invalid phyaddr 0\n")); ASSERT(0); break; } PKTPULL(dhd->osh, p, prot->rx_metadata_offset); pktlen = PKTLEN(dhd->osh, p); /* CMN msg header */ rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_RXBUF_POST; rxbuf_post->cmn_hdr.if_id = 0; /* get the lock before calling NATIVE_TO_PKTID */ DHD_GENERAL_LOCK(dhd, flags); rxbuf_post->cmn_hdr.request_id = htol32(NATIVE_TO_PKTID(dhd->prot->pktid_map_handle, p, physaddr, pktlen, DMA_RX, ring->secdma)); /* free lock */ DHD_GENERAL_UNLOCK(dhd, flags); if (rxbuf_post->cmn_hdr.request_id == DHD_PKTID_INVALID) { if (SECURE_DMA_ENAB(dhd->osh)) { DHD_GENERAL_LOCK(dhd, flags); SECURE_DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0, ring->secdma, 0); DHD_GENERAL_UNLOCK(dhd, flags); } else DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0); PKTFREE(dhd->osh, p, FALSE); DHD_ERROR(("Pktid pool depleted.\n")); break; } rxbuf_post->data_buf_len = htol16((uint16)pktlen); PHYSADDRADDOFFSET(meta_physaddr, physaddr, prot->rx_metadata_offset); rxbuf_post->data_buf_addr.high_addr = htol32(PHYSADDRHI(meta_physaddr)); rxbuf_post->data_buf_addr.low_addr = htol32(PHYSADDRLO(meta_physaddr)); if (prot->rx_metadata_offset) { rxbuf_post->metadata_buf_len = prot->rx_metadata_offset; rxbuf_post->metadata_buf_addr.high_addr = htol32(PHYSADDRHI(physaddr)); rxbuf_post->metadata_buf_addr.low_addr = htol32(PHYSADDRLO(physaddr)); } else { rxbuf_post->metadata_buf_len = 0; rxbuf_post->metadata_buf_addr.high_addr = 0; rxbuf_post->metadata_buf_addr.low_addr = 0; } /* Move rxbuf_post_tmp to next item */ rxbuf_post_tmp = rxbuf_post_tmp + RING_LEN_ITEMS(ring); } if (i < alloced) { if (RING_WRITE_PTR(ring) < (alloced - i)) RING_WRITE_PTR(ring) = RING_MAX_ITEM(ring) - (alloced - i); else RING_WRITE_PTR(ring) -= (alloced - i); alloced = i; } /* Update the write pointer in TCM & ring bell */ if (alloced > 0) prot_ring_write_complete(dhd, prot->h2dring_rxp_subn, msg_start, alloced); return alloced; } static int dhd_prot_rxbufpost_ctrl(dhd_pub_t *dhd, bool event_buf) { void *p; uint16 pktsz; ioctl_resp_evt_buf_post_msg_t *rxbuf_post; dmaaddr_t physaddr; uint32 pktlen; dhd_prot_t *prot = dhd->prot; uint16 alloced = 0; unsigned long flags; if (dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__)); return -1; } if (event_buf) { /* Allocate packet for event buffer post */ pktsz = DHD_FLOWRING_RX_BUFPOST_PKTSZ; } else { /* Allocate packet for ctrl/ioctl buffer post */ pktsz = DHD_FLOWRING_IOCTL_BUFPOST_PKTSZ; } if ((p = PKTGET(dhd->osh, pktsz, FALSE)) == NULL) { DHD_ERROR(("%s:%d: PKTGET for %s rxbuf failed\n", __FUNCTION__, __LINE__, event_buf ? "event" : "ioctl")); return -1; } pktlen = PKTLEN(dhd->osh, p); if (SECURE_DMA_ENAB(dhd->osh)) { DHD_GENERAL_LOCK(dhd, flags); physaddr = SECURE_DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0, prot->h2dring_ctrl_subn->secdma, 0); DHD_GENERAL_UNLOCK(dhd, flags); } else physaddr = DMA_MAP(dhd->osh, PKTDATA(dhd->osh, p), pktlen, DMA_RX, p, 0); if (PHYSADDRISZERO(physaddr)) { DHD_ERROR(("Invalid phyaddr 0\n")); ASSERT(0); goto free_pkt_return; } DHD_GENERAL_LOCK(dhd, flags); rxbuf_post = (ioctl_resp_evt_buf_post_msg_t *)dhd_alloc_ring_space(dhd, prot->h2dring_ctrl_subn, DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D, &alloced); if (rxbuf_post == NULL) { DHD_GENERAL_UNLOCK(dhd, flags); DHD_ERROR(("%s:%d: Ctrl submit Msgbuf Not available to post buffer" " for %s\n", __FUNCTION__, __LINE__, event_buf ? "event" : "ioctl")); if (SECURE_DMA_ENAB(dhd->osh)) { DHD_GENERAL_LOCK(dhd, flags); SECURE_DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0, prot->h2dring_ctrl_subn->secdma, 0); DHD_GENERAL_UNLOCK(dhd, flags); } else DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0); goto free_pkt_return; } /* CMN msg header */ if (event_buf) rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_EVENT_BUF_POST; else rxbuf_post->cmn_hdr.msg_type = MSG_TYPE_IOCTLRESP_BUF_POST; rxbuf_post->cmn_hdr.if_id = 0; rxbuf_post->cmn_hdr.request_id = htol32(NATIVE_TO_PKTID(dhd->prot->pktid_map_handle, p, physaddr, pktlen, DMA_RX, prot->h2dring_ctrl_subn->secdma)); if (rxbuf_post->cmn_hdr.request_id == DHD_PKTID_INVALID) { if (RING_WRITE_PTR(prot->h2dring_ctrl_subn) == 0) RING_WRITE_PTR(prot->h2dring_ctrl_subn) = RING_MAX_ITEM(prot->h2dring_ctrl_subn) - 1; else RING_WRITE_PTR(prot->h2dring_ctrl_subn)--; DHD_GENERAL_UNLOCK(dhd, flags); if (SECURE_DMA_ENAB(dhd->osh)) { DHD_GENERAL_LOCK(dhd, flags); SECURE_DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0, prot->h2dring_ctrl_subn->secdma, 0); DHD_GENERAL_UNLOCK(dhd, flags); } else DMA_UNMAP(dhd->osh, physaddr, pktlen, DMA_RX, 0, 0); goto free_pkt_return; } rxbuf_post->cmn_hdr.flags = 0; rxbuf_post->host_buf_len = htol16((uint16)PKTLEN(dhd->osh, p)); rxbuf_post->host_buf_addr.high_addr = htol32(PHYSADDRHI(physaddr)); rxbuf_post->host_buf_addr.low_addr = htol32(PHYSADDRLO(physaddr)); /* Update the write pointer in TCM & ring bell */ prot_ring_write_complete(dhd, prot->h2dring_ctrl_subn, rxbuf_post, DHD_FLOWRING_DEFAULT_NITEMS_POSTED_H2D); DHD_GENERAL_UNLOCK(dhd, flags); return 1; free_pkt_return: PKTFREE(dhd->osh, p, FALSE); return -1; } static uint16 dhd_msgbuf_rxbuf_post_ctrlpath(dhd_pub_t *dhd, bool event_buf, uint32 max_to_post) { uint32 i = 0; int32 ret_val; DHD_INFO(("max to post %d, event %d \n", max_to_post, event_buf)); if (dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__)); return 0; } while (i < max_to_post) { ret_val = dhd_prot_rxbufpost_ctrl(dhd, event_buf); if (ret_val < 0) break; i++; } DHD_INFO(("posted %d buffers to event_pool/ioctl_resp_pool %d\n", i, event_buf)); return (uint16)i; } static int dhd_msgbuf_rxbuf_post_ioctlresp_bufs(dhd_pub_t *dhd) { dhd_prot_t *prot = dhd->prot; uint16 retcnt = 0; DHD_INFO(("ioctl resp buf post\n")); if (dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__)); return 0; } retcnt = dhd_msgbuf_rxbuf_post_ctrlpath(dhd, FALSE, prot->max_ioctlrespbufpost - prot->cur_ioctlresp_bufs_posted); prot->cur_ioctlresp_bufs_posted += retcnt; return retcnt; } static int dhd_msgbuf_rxbuf_post_event_bufs(dhd_pub_t *dhd) { dhd_prot_t *prot = dhd->prot; uint16 retcnt = 0; if (dhd->busstate == DHD_BUS_DOWN) { DHD_ERROR(("%s: bus is already down.\n", __FUNCTION__)); return 0; } retcnt = dhd_msgbuf_rxbuf_post_ctrlpath(dhd, TRUE, prot->max_eventbufpost - prot->cur_event_bufs_posted); prot->cur_event_bufs_posted += retcnt; return retcnt; } bool BCMFASTPATH dhd_prot_process_msgbuf_rxcpl(dhd_pub_t *dhd, uint bound) { dhd_prot_t *prot = dhd->prot; bool more = TRUE; uint n = 0; /* Process all the messages - DTOH direction */ while (TRUE) { uint8 *src_addr; uint16 src_len; /* Store current read pointer */ /* Read pointer will be updated in prot_early_upd_rxcpln_read_idx */ prot_store_rxcpln_read_idx(dhd, prot->d2hring_rx_cpln); /* Get the message from ring */ src_addr = prot_get_src_addr(dhd, prot->d2hring_rx_cpln, &src_len); if (src_addr == NULL) { more = FALSE; break; } /* Prefetch data to populate the cache */ OSL_PREFETCH(src_addr); if (dhd_prot_process_msgtype(dhd, prot->d2hring_rx_cpln, src_addr, src_len) != BCME_OK) { prot_upd_read_idx(dhd, prot->d2hring_rx_cpln); DHD_ERROR(("%s: Error at process rxpl msgbuf of len %d\n", __FUNCTION__, src_len)); } /* After batch processing, check RX bound */ n += src_len/RING_LEN_ITEMS(prot->d2hring_rx_cpln); if (n >= bound) { break; } } return more; } void dhd_prot_update_txflowring(dhd_pub_t *dhd, uint16 flow_id, void *msgring_info) { uint16 r_index = 0; msgbuf_ring_t *ring = (msgbuf_ring_t *)msgring_info; /* Update read pointer */ if (DMA_INDX_ENAB(dhd->dma_d2h_ring_upd_support)) { r_index = dhd_get_dmaed_index(dhd, H2D_DMA_READINDX, ring->idx); ring->ringstate->r_offset = r_index; } DHD_TRACE(("flow %d, write %d read %d \n\n", flow_id, RING_WRITE_PTR(ring), RING_READ_PTR(ring))); /* Need more logic here, but for now use it directly */ dhd_bus_schedule_queue(dhd->bus, flow_id, TRUE); } bool BCMFASTPATH dhd_prot_process_msgbuf_txcpl(dhd_pub_t *dhd, uint bound) { dhd_prot_t *prot = dhd->prot; bool more = TRUE; uint n = 0; /* Process all the messages - DTOH direction */ while (TRUE) { uint8 *src_addr; uint16 src_len; src_addr = prot_get_src_addr(dhd, prot->d2hring_tx_cpln, &src_len); if (src_addr == NULL) { more = FALSE; break; } /* Prefetch data to populate the cache */ OSL_PREFETCH(src_addr); if (dhd_prot_process_msgtype(dhd, prot->d2hring_tx_cpln, src_addr, src_len) != BCME_OK) { DHD_ERROR(("%s: Error at process txcmpl msgbuf of len %d\n", __FUNCTION__, src_len)); } /* Write to dngl rd ptr */ prot_upd_read_idx(dhd, prot->d2hring_tx_cpln); /* After batch processing, check bound */ n += src_len/RING_LEN_ITEMS(prot->d2hring_tx_cpln); if (n >= bound) { break; } } return more; } int BCMFASTPATH dhd_prot_process_ctrlbuf(dhd_pub_t * dhd) { dhd_prot_t *prot = dhd->prot; /* Process all the messages - DTOH direction */ while (TRUE) { uint8 *src_addr; uint16 src_len; src_addr = prot_get_src_addr(dhd, prot->d2hring_ctrl_cpln, &src_len); if (src_addr == NULL) { break; } /* Prefetch data to populate the cache */ OSL_PREFETCH(src_addr); if (dhd_prot_process_msgtype(dhd, prot->d2hring_ctrl_cpln, src_addr, src_len) != BCME_OK) { DHD_ERROR(("%s: Error at process ctrlmsgbuf of len %d\n", __FUNCTION__, src_len)); } /* Write to dngl rd ptr */ prot_upd_read_idx(dhd, prot->d2hring_ctrl_cpln); } return 0; } static int BCMFASTPATH dhd_prot_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8* buf, uint16 len) { dhd_prot_t *prot = dhd->prot; uint32 cur_dma_len = 0; int ret = BCME_OK; DHD_INFO(("%s: process msgbuf of len %d\n", __FUNCTION__, len)); while (len > 0) { ASSERT(len > (sizeof(cmn_msg_hdr_t) + prot->rx_dataoffset)); if (prot->rx_dataoffset) { cur_dma_len = *(uint32 *) buf; ASSERT(cur_dma_len <= len); buf += prot->rx_dataoffset; len -= (uint16)prot->rx_dataoffset; } else { cur_dma_len = len; } if (dhd_process_msgtype(dhd, ring, buf, (uint16)cur_dma_len) != BCME_OK) { DHD_ERROR(("%s: Error at process msg of dmalen %d\n", __FUNCTION__, cur_dma_len)); ret = BCME_ERROR; } len -= (uint16)cur_dma_len; buf += cur_dma_len; } return ret; } static int BCMFASTPATH dhd_process_msgtype(dhd_pub_t *dhd, msgbuf_ring_t *ring, uint8* buf, uint16 len) { uint16 pktlen = len; uint16 msglen; uint8 msgtype; cmn_msg_hdr_t *msg = NULL; int ret = BCME_OK; #if defined(PCIE_D2H_SYNC_BZERO) uint8 *buf_head = buf; #endif /* PCIE_D2H_SYNC_BZERO */ ASSERT(ring && ring->ringmem); msglen = RING_LEN_ITEMS(ring); if (msglen == 0) { DHD_ERROR(("%s: ringidx %d, msglen is %d, pktlen is %d \n", __FUNCTION__, ring->idx, msglen, pktlen)); return BCME_ERROR; } while (pktlen > 0) { msg = (cmn_msg_hdr_t *)buf; #if defined(PCIE_D2H_SYNC) /* Wait until DMA completes, then fetch msgtype */ msgtype = dhd->prot->d2h_sync_cb(dhd, ring, msg, msglen); #else msgtype = msg->msg_type; #endif /* !PCIE_D2H_SYNC */ DHD_INFO(("msgtype %d, msglen is %d, pktlen is %d \n", msgtype, msglen, pktlen)); if (msgtype == MSG_TYPE_LOOPBACK) { bcm_print_bytes("LPBK RESP: ", (uint8 *)msg, msglen); DHD_ERROR((" MSG_TYPE_LOOPBACK, len %d\n", msglen)); } if (msgtype >= DHD_PROT_FUNCS) { DHD_ERROR(("%s: msgtype %d, msglen is %d, pktlen is %d \n", __FUNCTION__, msgtype, msglen, pktlen)); ret = BCME_ERROR; goto done; } if (table_lookup[msgtype]) { table_lookup[msgtype](dhd, buf, msglen); } if (pktlen < msglen) { ret = BCME_ERROR; goto done; } pktlen = pktlen - msglen; buf = buf + msglen; if (ring->idx == BCMPCIE_D2H_MSGRING_RX_COMPLETE) prot_early_upd_rxcpln_read_idx(dhd, ring); } done: #if defined(PCIE_D2H_SYNC_BZERO) OSL_CACHE_FLUSH(buf_head, len - pktlen); /* Flush the bzeroed msg */ #endif /* PCIE_D2H_SYNC_BZERO */ #ifdef DHD_RX_CHAINING dhd_rxchain_commit(dhd); #endif return ret; } static void dhd_prot_noop(dhd_pub_t *dhd, void * buf, uint16 msglen) { return; } static void dhd_prot_ringstatus_process(dhd_pub_t *dhd, void * buf, uint16 msglen) { pcie_ring_status_t * ring_status = (pcie_ring_status_t *)buf; DHD_ERROR(("ring status: request_id %d, status 0x%04x, flow ring %d, w_offset %d \n", ring_status->cmn_hdr.request_id, ring_status->compl_hdr.status, ring_status->compl_hdr.flow_ring_id, ring_status->write_idx)); /* How do we track this to pair it with ??? */ return; } static void dhd_prot_genstatus_process(dhd_pub_t *dhd, void * buf, uint16 msglen) { pcie_gen_status_t * gen_status = (pcie_gen_status_t *)buf; DHD_ERROR(("gen status: request_id %d, status 0x%04x, flow ring %d \n", gen_status->cmn_hdr.request_id, gen_status->compl_hdr.status, gen_status->compl_hdr.flow_ring_id)); /* How do we track this to pair it with ??? */ return; } static void dhd_prot_ioctack_process(dhd_pub_t *dhd, void * buf, uint16 msglen) { ioctl_req_ack_msg_t * ioct_ack = (ioctl_req_ack_msg_t *)buf; DHD_CTL(("ioctl req ack: request_id %d, status 0x%04x, flow ring %d \n", ioct_ack->cmn_hdr.request_id, ioct_ack->compl_hdr.status, ioct_ack->compl_hdr.flow_ring_id)); if (ioct_ack->compl_hdr.status != 0) { DHD_ERROR(("got an error status for the ioctl request...need to handle that\n")); } #if defined(PCIE_D2H_SYNC_BZERO) memset(buf, 0, msglen); #endif /* PCIE_D2H_SYNC_BZERO */ } static void dhd_prot_ioctcmplt_process(dhd_pub_t *dhd, void * buf, uint16 msglen) { uint16 status; uint32 resp_len = 0; uint32 pkt_id, xt_id; ioctl_comp_resp_msg_t * ioct_resp = (ioctl_comp_resp_msg_t *)buf; resp_len = ltoh16(ioct_resp->resp_len); xt_id = ltoh16(ioct_resp->trans_id); BCM_REFERENCE(xt_id); pkt_id = ltoh32(ioct_resp->cmn_hdr.request_id); status = ioct_resp->compl_hdr.status; #if defined(PCIE_D2H_SYNC_BZERO) memset(buf, 0, msglen); #endif /* PCIE_D2H_SYNC_BZERO */ DHD_CTL(("IOCTL_COMPLETE: pktid %x xtid %d status %x resplen %d\n", pkt_id, xt_id, status, resp_len)); dhd_bus_update_retlen(dhd->bus, sizeof(ioctl_comp_resp_msg_t), pkt_id, status, resp_len); dhd_os_ioctl_resp_wake(dhd); } static void BCMFASTPATH dhd_prot_txstatus_process(dhd_pub_t *dhd, void * buf, uint16 msglen) { dhd_prot_t *prot = dhd->prot; host_txbuf_cmpl_t * txstatus; unsigned long flags; uint32 pktid; void *pkt; dmaaddr_t pa; uint32 pa_len; void *secdma; /* locks required to protect circular buffer accesses */ DHD_GENERAL_LOCK(dhd, flags); txstatus = (host_txbuf_cmpl_t *)buf; pktid = ltoh32(txstatus->cmn_hdr.request_id); DHD_INFO(("txstatus for pktid 0x%04x\n", pktid)); if (prot->active_tx_count) prot->active_tx_count--; else DHD_ERROR(("Extra packets are freed\n")); ASSERT(pktid != 0); pkt = PKTID_TO_NATIVE(dhd->prot->pktid_map_handle, pktid, pa, pa_len, secdma); if (pkt) { if (SECURE_DMA_ENAB(dhd->osh)) { int offset = 0; BCM_REFERENCE(offset); if (dhd->prot->tx_metadata_offset) offset = dhd->prot->tx_metadata_offset + ETHER_HDR_LEN; SECURE_DMA_UNMAP(dhd->osh, (uint) pa, (uint) dhd->prot->tx_metadata_offset, DMA_RX, 0, 0, secdma, offset); } else DMA_UNMAP(dhd->osh, pa, (uint) pa_len, DMA_RX, 0, dmah); #if defined(BCMPCIE) dhd_txcomplete(dhd, pkt, true); #endif #if DHD_DBG_SHOW_METADATA if (dhd->prot->tx_metadata_offset && txstatus->metadata_len) { uchar *ptr; /* The Ethernet header of TX frame was copied and removed. * Here, move the data pointer forward by Ethernet header size. */ PKTPULL(dhd->osh, pkt, ETHER_HDR_LEN); ptr = PKTDATA(dhd->osh, pkt) - (dhd->prot->tx_metadata_offset); bcm_print_bytes("txmetadata", ptr, txstatus->metadata_len); dhd_prot_print_metadata(dhd, ptr, txstatus->metadata_len); } #endif /* DHD_DBG_SHOW_METADATA */ PKTFREE(dhd->osh, pkt, TRUE); } #if defined(PCIE_D2H_SYNC_BZERO) memset(buf, 0, msglen); #endif /* PCIE_D2H_SYNC_BZERO */ DHD_GENERAL_UNLOCK(dhd, flags); return; } static void dhd_prot_event_process(dhd_pub_t *dhd, void* buf, uint16 len) { wlevent_req_msg_t *evnt; uint32 bufid; uint16 buflen; int ifidx = 0; void* pkt; unsigned long flags; dhd_prot_t *prot = dhd->prot; int post_cnt = 0; bool zero_posted = FALSE; /* Event complete header */ evnt = (wlevent_req_msg_t *)buf; bufid = ltoh32(evnt->cmn_hdr.request_id); buflen = ltoh16(evnt->event_data_len); ifidx = BCMMSGBUF_API_IFIDX(&evnt->cmn_hdr); /* Post another rxbuf to the device */ if (prot->cur_event_bufs_posted) prot->cur_event_bufs_posted--; else zero_posted = TRUE; post_cnt = dhd_msgbuf_rxbuf_post_event_bufs(dhd); if (zero_posted && (post_cnt <= 0)) { return; } #if defined(PCIE_D2H_SYNC_BZERO) memset(buf, 0, len); #endif /* PCIE_D2H_SYNC_BZERO */ /* locks required to protect pktid_m