From ee98782e6e5b9dbf2b56b3c933c63056bbf15d15 Mon Sep 17 00:00:00 2001 From: Timo Suoranta Date: Tue, 8 May 2018 14:50:04 +0300 Subject: nvlink: Improve MISRA compliance with U suffix tegra-nvlink-uapi.h is used by nvrm_gpu, and is causing some MISRA violations. A number of MISRA C++ 2008 rules require U suffix for unsigned numbers. 2-13-3 A "U" suffix shall be applied to all octal or hexadecimal integer literals of unsigned type. 5-0-4 An implicit integral conversion shall not change the signedness of the underlying type. 5-0-21 Bitwise operators shall only be applied to operands of unsigned underlying type. Bug 1777616 Change-Id: I02f8b8798b6cc223e0708ff16cef0a18c80856be Signed-off-by: Timo Suoranta Reviewed-on: https://git-master.nvidia.com/r/1710529 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/tegra-nvlink-uapi.h | 222 ++++++++++++++++----------------- 1 file changed, 111 insertions(+), 111 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/tegra-nvlink-uapi.h b/include/uapi/linux/tegra-nvlink-uapi.h index 4511a187c..099ecaeb0 100644 --- a/include/uapi/linux/tegra-nvlink-uapi.h +++ b/include/uapi/linux/tegra-nvlink-uapi.h @@ -35,33 +35,33 @@ /* TEGRA_CTRL_CMD_NVLINK_GET_NVLINK_CAPS */ -#define TEGRA_NVLINK_VERSION_10 0x00000001 -#define TEGRA_NVLINK_VERSION_20 0x00000002 -#define TEGRA_NVLINK_VERSION_22 0x00000004 - -#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000) -#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001) -#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002) -#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004) - -#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000) -#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001) -#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002) -#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004) - -#define TEGRA_CTRL_NVLINK_CAPS_SUPPORTED BIT(0) -#define TEGRA_CTRL_NVLINK_CAPS_P2P_SUPPORTED BIT(1) -#define TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ACCESS BIT(2) -#define TEGRA_CTRL_NVLINK_CAPS_P2P_ATOMICS BIT(3) -#define TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS BIT(4) -#define TEGRA_CTRL_NVLINK_CAPS_PEX_TUNNELING BIT(5) -#define TEGRA_CTRL_NVLINK_CAPS_SLI_BRIDGE BIT(6) -#define TEGRA_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE BIT(7) -#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L0 BIT(8) -#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L1 BIT(9) -#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L2 BIT(10) -#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L3 BIT(11) -#define TEGRA_CTRL_NVLINK_CAPS_VALID BIT(12) +#define TEGRA_NVLINK_VERSION_10 0x00000001U +#define TEGRA_NVLINK_VERSION_20 0x00000002U +#define TEGRA_NVLINK_VERSION_22 0x00000004U + +#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_INVALID (0x00000000U) +#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_1_0 (0x00000001U) +#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_0 (0x00000002U) +#define TEGRA_CTRL_NVLINK_CAPS_NVLINK_VERSION_2_2 (0x00000004U) + +#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U) +#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U) +#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_0 (0x00000002U) +#define TEGRA_CTRL_NVLINK_CAPS_NCI_VERSION_2_2 (0x00000004U) + +#define TEGRA_CTRL_NVLINK_CAPS_SUPPORTED BIT(0U) +#define TEGRA_CTRL_NVLINK_CAPS_P2P_SUPPORTED BIT(1U) +#define TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ACCESS BIT(2U) +#define TEGRA_CTRL_NVLINK_CAPS_P2P_ATOMICS BIT(3U) +#define TEGRA_CTRL_NVLINK_CAPS_SYSMEM_ATOMICS BIT(4U) +#define TEGRA_CTRL_NVLINK_CAPS_PEX_TUNNELING BIT(5U) +#define TEGRA_CTRL_NVLINK_CAPS_SLI_BRIDGE BIT(6U) +#define TEGRA_CTRL_NVLINK_CAPS_SLI_BRIDGE_SENSABLE BIT(7U) +#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L0 BIT(8U) +#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L1 BIT(9U) +#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L2 BIT(10U) +#define TEGRA_CTRL_NVLINK_CAPS_POWER_STATE_L3 BIT(11U) +#define TEGRA_CTRL_NVLINK_CAPS_VALID BIT(12U) struct tegra_nvlink_caps { __u16 nvlink_caps; @@ -78,78 +78,78 @@ struct tegra_nvlink_caps { /* TEGRA_CTRL_CMD_NVLINK_GET_NVLINK_STATUS */ /* NVLink link states */ -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_INIT (0x00000000) -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002) -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003) -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004) -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006) -#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFF) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_INIT (0x00000000U) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_HWCFG (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_SWCFG (0x00000002U) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_ACTIVE (0x00000003U) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_FAULT (0x00000004U) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_RECOVERY (0x00000006U) +#define TEGRA_CTRL_NVLINK_STATUS_LINK_STATE_INVALID (0xFFFFFFFFU) /* NVLink Tx sublink states */ -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_HIGH_SPEED_1 (0x00000000U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SINGLE_LANE (0x00000004U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_TRAINING (0x00000005U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_SAFE_MODE (0x00000006U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_OFF (0x00000007U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_RX_STATE_INVALID (0x000000FFU) /* NVLink Rx sublink states */ -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007) -#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_HIGH_SPEED_1 (0x00000000U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SINGLE_LANE (0x00000004U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_TRAINING (0x00000005U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_SAFE_MODE (0x00000006U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_OFF (0x00000007U) +#define TEGRA_CTRL_NVLINK_STATUS_SUBLINK_TX_STATE_INVALID (0x000000FFU) -#define TEGRA_CTRL_NVLINK_STATUS_PHY_NVHS (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_PHY_GRS (0x00000002) -#define TEGRA_CTRL_NVLINK_STATUS_PHY_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_PHY_NVHS (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_PHY_GRS (0x00000002U) +#define TEGRA_CTRL_NVLINK_STATUS_PHY_INVALID (0x000000FFU) /* Version information */ -#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002) -#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004) -#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_1_0 (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_0 (0x00000002U) +#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_2_2 (0x00000004U) +#define TEGRA_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU) -#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002) -#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004) -#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_1_0 (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_0 (0x00000002U) +#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_2_2 (0x00000004U) +#define TEGRA_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU) -#define TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_1_0 (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_NVHS_VERSION_INVALID (0x000000FFU) -#define TEGRA_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_GRS_VERSION_1_0 (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_GRS_VERSION_INVALID (0x000000FFU) /* Connection properties */ -#define TEGRA_CTRL_NVLINK_STATUS_CONNECTED_TRUE (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_CONNECTED_FALSE (0x00000000) +#define TEGRA_CTRL_NVLINK_STATUS_CONNECTED_TRUE (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_CONNECTED_FALSE (0x00000000U) -#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001) -#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002) -#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000) +#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPBACK (0x00000001U) +#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_LOOPOUT (0x00000002U) +#define TEGRA_CTRL_NVLINK_STATUS_LOOP_PROPERTY_NONE (0x00000000U) -#define TEGRA_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FF) +#define TEGRA_CTRL_NVLINK_STATUS_REMOTE_LINK_NUMBER_INVALID (0x000000FFU) /* NVLink REFCLK types */ -#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00) -#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01) -#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02) +#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U) +#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_NVHS (0x01U) +#define TEGRA_CTRL_NVLINK_REFCLK_TYPE_PEX (0x02U) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FF) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU) -#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFF) +#define TEGRA_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU) struct tegra_nvlink_device_info { /* ID Flags */ @@ -216,30 +216,30 @@ struct tegra_nvlink_status { /* TEGRA_CTRL_CMD_NVLINK_CLEAR_COUNTERS */ /* These are the bitmask definitions for different counter types */ -#define TEGRA_CTRL_NVLINK_COUNTER_INVALID 0x00000000 +#define TEGRA_CTRL_NVLINK_COUNTER_INVALID 0x00000000U -#define TEGRA_CTRL_NVLINK_COUNTER_TL_TX0 0x00000001 -#define TEGRA_CTRL_NVLINK_COUNTER_TL_TX1 0x00000002 -#define TEGRA_CTRL_NVLINK_COUNTER_TL_RX0 0x00000004 -#define TEGRA_CTRL_NVLINK_COUNTER_TL_RX1 0x00000008 +#define TEGRA_CTRL_NVLINK_COUNTER_TL_TX0 0x00000001U +#define TEGRA_CTRL_NVLINK_COUNTER_TL_TX1 0x00000002U +#define TEGRA_CTRL_NVLINK_COUNTER_TL_RX0 0x00000004U +#define TEGRA_CTRL_NVLINK_COUNTER_TL_RX1 0x00000008U -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000 +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_FLIT 0x00010000U -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1 << (i + 17)) -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_SIZE 8 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000 +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L(i) (1U << (i + 17U)) +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_SIZE 8U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L0 0x00020000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L1 0x00040000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L2 0x00080000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L3 0x00100000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L4 0x00200000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L5 0x00400000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L6 0x00800000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_RX_ERR_CRC_LANE_L7 0x01000000U -#define TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000 -#define TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000 +#define TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_REPLAY 0x02000000U +#define TEGRA_CTRL_NVLINK_COUNTER_DL_TX_ERR_RECOVERY 0x04000000U -#define TEGRA_CTRL_NVLINK_COUNTER_MAX_TYPES 32 +#define TEGRA_CTRL_NVLINK_COUNTER_MAX_TYPES 32U /* * Return index of the bit that is set in 'n'. This assumes there is only @@ -247,11 +247,11 @@ struct tegra_nvlink_status { * result is in range of 0-31. */ #define TEGRA_BIT_IDX_32(n) \ - ((((n) & 0xFFFF0000) ? 0x10 : 0) | \ - (((n) & 0xFF00FF00) ? 0x08 : 0) | \ - (((n) & 0xF0F0F0F0) ? 0x04 : 0) | \ - (((n) & 0xCCCCCCCC) ? 0x02 : 0) | \ - (((n) & 0xAAAAAAAA) ? 0x01 : 0)) + ((((n) & 0xFFFF0000U) ? 0x10U : 0U) | \ + (((n) & 0xFF00FF00U) ? 0x08U : 0U) | \ + (((n) & 0xF0F0F0F0U) ? 0x04U : 0U) | \ + (((n) & 0xCCCCCCCCU) ? 0x02U : 0U) | \ + (((n) & 0xAAAAAAAAU) ? 0x01U : 0U)) struct tegra_nvlink_clear_counters { __u32 link_mask; @@ -368,7 +368,7 @@ struct tegra_nvlink_link_state { }; enum tegra_nvlink_conn_train_type { - tegra_nvlink_train_conn_off_to_swcfg = 0, + tegra_nvlink_train_conn_off_to_swcfg = 0U, tegra_nvlink_train_conn_swcfg_to_active, tegra_nvlink_train_conn_to_off, tegra_nvlink_train_conn_active_to_swcfg, @@ -388,12 +388,12 @@ struct tegra_nvlink_train_intranode_conn { }; /* TEGRA_CTRL_CMD_NVLINK_GET_LP_COUNTERS */ -#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0 -#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1 -#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2 -#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3 -#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4 -#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 5 +#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_NVHS 0U +#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_EIGHTH 1U +#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_COUNT_TX_OTHER 2U +#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_ENTER 3U +#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_NUM_TX_LP_EXIT 4U +#define TEGRA_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS 5U struct tegra_nvlink_get_lp_counters { /* input field */ -- cgit v1.2.2