From c1019d0a308875e8f81430dc859ed857e0a0451a Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Tue, 24 May 2016 17:12:12 +0300 Subject: video: tegra: host: pva: Initial Ioctl Added the ioctl header with structure defined in ISS file. Added the code support ioctl for reading the pva characteristics. JIRA PVA-48 Change-Id: Ie19972c6e8586da27ecc89d285a169567e5bd8fe Signed-off-by: Arto Merilainen Reviewed-on: http://git-master/r/1152518 Reviewed-by: Vinod Gopalakrishnakurup Tested-by: Vinod Gopalakrishnakurup GVS: Gerrit_Virtual_Submit --- include/uapi/linux/nvhost_pva_ioctl.h | 75 +++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 include/uapi/linux/nvhost_pva_ioctl.h (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h new file mode 100644 index 000000000..b431445a4 --- /dev/null +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -0,0 +1,75 @@ +/* + * Tegra PVA Driver ioctls + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; If not, see . + */ + +#ifndef __LINUX_NVHOST_PVA_IOCTL_H +#define __LINUX_NVHOST_PVA_IOCTL_H + +#include +#include + +#if !defined(__KERNEL__) +#define __user +#endif + +#define NVHOST_PVA_IOCTL_MAGIC 'P' + +/** + * struct pva_characteristics_req - Request filling of characteristics struct + * + * @characteristics: pointer to be filled with characteristics + * @characteristics_size: size in bytes + * @characteristics_filled: reserved(set to zero) + * + */ +struct pva_characteristics_req { + __u64 characteristics; + __u64 characteristics_size; + __u64 characteristics_filled; +}; + +/** + * struct pva_characteristics - the information of the pva cluster + * + * @num_vpu: number of vpu per pva + * @vpu_generation: vpu hardware generation + * @task_structure_version: highest supported task struct ver + * @reserved: reserved for future use + * @r5_ucode_version: R5 firmware version + * @r5_ucode_earliest: 1st version compatible with current running fw + * @r5_vpu_runtime_earliest: First supported vpu runtime version + * + */ +struct pva_characteristics { + __u8 num_vpu; + __u8 vpu_generation; + __u8 reserved[6]; + __u32 r5_ucode_version; + __u32 r5_ucode_earliest; + __u32 r5_vpu_runtime_earliest; +}; + + +#define PVA_IOCTL_CHARACTERISTICS \ + _IOWR(NVHOST_PVA_IOCTL_MAGIC, 1, struct pva_characteristics_req) + + +#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_CHARACTERISTICS) +#define NVHOST_PVA_IOCTL_MAX_ARG_SIZE sizeof(struct pva_characteristics_req) + +#endif /* __LINUX_NVHOST_PVA_IOCTL_H */ + -- cgit v1.2.2 From c94150df965350cd0759796999eec2b320cf8b66 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Tue, 7 Jun 2016 17:46:04 -0700 Subject: video: tegra: pva: Add Buffer Pin and Unpin Code This patch will pin and unpin the memhandles passed from user side to device iova. A bufferlist is maintained as part of the pva_private struct. Maintainig a reference count to avoid multiple mapping calls for same memory handle JIRA PVA-43 Change-Id: I2023038fa893f32cf8a136857950e0f4bcd67cfe Signed-off-by: Vinod G Reviewed-on: http://git-master/r/1160512 GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- include/uapi/linux/nvhost_pva_ioctl.h | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index b431445a4..1631f5cf8 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -57,18 +57,38 @@ struct pva_characteristics_req { struct pva_characteristics { __u8 num_vpu; __u8 vpu_generation; - __u8 reserved[6]; + __u8 reserved[2]; __u32 r5_ucode_version; __u32 r5_ucode_earliest; __u32 r5_vpu_runtime_earliest; }; +/** + * struct pva_pin_unpin_args - buffer handles to pin or unpin + * + * @buffers: Pointer to the table of u32 + * @num_buffers: elements in the buffer table + * @reserved: reserved + * + * Used to deliver information about the buffer handles that should be + * be pinned into (or unpinned from) the PVA address space. + * + */ +struct pva_pin_unpin_args { + __u64 buffers; + __u32 num_buffers; + __u32 reserved; +}; #define PVA_IOCTL_CHARACTERISTICS \ _IOWR(NVHOST_PVA_IOCTL_MAGIC, 1, struct pva_characteristics_req) +#define PVA_IOCTL_PIN \ + _IOW(NVHOST_PVA_IOCTL_MAGIC, 2, struct pva_pin_unpin_args) +#define PVA_IOCTL_UNPIN \ + _IOW(NVHOST_PVA_IOCTL_MAGIC, 3, struct pva_pin_unpin_args) -#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_CHARACTERISTICS) +#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_UNPIN) #define NVHOST_PVA_IOCTL_MAX_ARG_SIZE sizeof(struct pva_characteristics_req) #endif /* __LINUX_NVHOST_PVA_IOCTL_H */ -- cgit v1.2.2 From 8195e0445f758de6bc1b4f7f03f36e67ee59bd73 Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Sun, 4 Sep 2016 18:12:46 +0300 Subject: video: tegra: host: pva: Implement PVA submit ioctl This patch implements ioctl interface for submitting tasks. Since the hardware support is not yet available, the software simply creates fences that already have been expired and marks the task as failed. JIRA PVA-45 Change-Id: Ied95f7a072b73e771b73a00fd595ff55baca94cb Signed-off-by: Arto Merilainen Reviewed-on: http://git-master/r/1215616 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup --- include/uapi/linux/nvhost_pva_ioctl.h | 167 +++++++++++++++++++++++++++++++++- 1 file changed, 166 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 1631f5cf8..1ffa220e6 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -80,15 +80,180 @@ struct pva_pin_unpin_args { __u32 reserved; }; +/** + * struct pva_ioctl_status_handle - A handle to a status structure + * + * @handle: Handle to a dmabuf that holds the status buffer + * @offset: An offset within the buffer to the status structure. + */ +struct pva_status_handle { + __u32 handle; + __u32 offset; +}; + +/** + * struct pva_ioctl_surface - The surface descriptor + * + * @format: Surface pixel format + * @surface_handle: Memory handle that holds the surface + * @surface_offset: Offset within the surface memory buffer to the surface + * @roi_handle: Memory handle that holds the ROI + * @roi_offset: Offset within the ROI memory buffer to the ROI + * @surface_stride: Offset between planes in bytes + * @line_stride: Offset between two consequent lines in bytes. + * @depth: Number of planes in the surface + * @width: Width of the surface + * @height: Height of the surface + * @layout: Surface layout (pitch linear, block linear) + * + * This structure defines a list of surfaces to be delivered for + * PVA. + */ +struct pva_surface { + __u64 format; + __u32 surface_handle; + __u32 surface_offset; + __u32 roi_handle; + __u32 roi_offset; + __u32 surface_stride; + __u32 line_stride; + __u32 depth; + __u32 width; + __u32 height; + __u32 layout; +}; + +/** + * struct pva_ioct_task_parameter - Parameter structure for a task + * + * @handle: Memory handle including the parameter array. This field shall be + * used in cases where the UMD prepares the data in advance to a + * shared buffer or the input data is prepared by the upstream engine. + * @offset: Offset within the memory handle to the parameter array + * + * The parameter descriptor defines a single parameter array that is + * received. The handle and offset is translated into IOVA by the kernel + * driver and delivered to PVA. + */ +struct pva_task_parameter { + __u32 handle; + __u32 offset; +}; + +/** + * struct pva_ioctl_fence structure for passing fence information + * + * @type: Type of the fence (syncpoint, sync fd or semaphore) + * @syncpoint_index: Syncpoint id + * @syncpoint_value: Value of syncpoint id + * @sync_fd: Linux sync FD handle + * @semaphore_handle: File handle to the semaphore memory buffer + * @semaphore_offset: Offset to the semaphore within the buffer + * @semaphore_value: Value of the semaphore + */ +struct pva_fence { + __u32 type; +#define PVA_FENCE_TYPE_SYNCPT 0 +#define PVA_FENCE_TYPE_SYNC_FD 1 +#define PVA_FENCE_TYPE_SEMAPHORE 2 + __u32 syncpoint_index; + __u32 syncpoint_value; + __u32 sync_fd; + __u32 semaphore_handle; + __u32 semaphore_offset; + __u32 semaphore_value; +}; + +#define PVA_MAX_TASKS 16 +#define PVA_MAX_PREFENCES 8 +#define PVA_MAX_POSTFENCES 8 +#define PVA_MAX_INPUT_STATUS 8 +#define PVA_MAX_OUTPUT_STATUS 8 +#define PVA_MAX_INPUT_SURFACES 4 +#define PVA_MAX_OUTPUT_SURFACES 4 + +/** + * struct pva_ioctl_submit_task - Describe a task for PVA + * + * @num_prefences: Number of pre-fences in this task + * @num_postfences: Number of post-fences in this task + * @num_input_surfaces: Number of input surfaces + * @num_output_surfaces: Number of output surfaces + * @num_input_task_status: Number of input task status structures + * @num_output_task_status: Number of output task status structures + * @reserved: Reserved for future usage. + * @timeout: Latest Unix time when the task must complete. 0 if disabled. + * @prefences: Pointer to pre-fence structures + * @postfences: Pointer to post-fence structures + * @input_surfaces: Pointer to input surfaces + * @input_scalars: Information for input scalars + * @input_2dpoint: Information for input 2d points + * @input_rois: Pointer to input ROIs + * @output_surfaces: Pointer to output surfaces + * @output_scalars: Information for output scalars + * @output_2dpoint: Information for output 2d points + * @output_rois: Pointer to output ROIs + * @input_task_status: Pointer to input status structure + * @output_task_status: Pointer to output status structure + * + * This structure is used for delivering information that is required to + * finish a single task on PVA. + * + */ +struct pva_ioctl_submit_task { + __u8 num_prefences; + __u8 num_postfences; + __u8 num_input_surfaces; + __u8 num_output_surfaces; + __u8 num_input_task_status; + __u8 num_output_task_status; + __u8 reserved[14]; + __u32 operation; + __u64 timeout; + __u64 prefences; + __u64 postfences; + __u64 input_surfaces; + struct pva_task_parameter input_scalars; + struct pva_task_parameter input_2dpoint; + struct pva_task_parameter input_rois; + __u64 output_surfaces; + struct pva_task_parameter output_scalars; + struct pva_task_parameter output_2dpoint; + struct pva_task_parameter output_rois; + __u64 input_task_status; + __u64 output_task_status; +}; + +/** + * struct pva_submit_args - submit tasks to PVA + * + * @tasks: Pointer to a list of tasks structures + * @flags: Flags for the given tasks + * @num_tasks: Number of tasks in the list + * @version: Version of the task structure. + * + * This ioctl is used for submitting tasks to PVA. The given structures + * are modified to include information about post-fences. + * + */ +struct pva_ioctl_submit_args { + __u64 tasks; + __u16 flags; + __u16 num_tasks; + __u32 version; +}; + #define PVA_IOCTL_CHARACTERISTICS \ _IOWR(NVHOST_PVA_IOCTL_MAGIC, 1, struct pva_characteristics_req) #define PVA_IOCTL_PIN \ _IOW(NVHOST_PVA_IOCTL_MAGIC, 2, struct pva_pin_unpin_args) #define PVA_IOCTL_UNPIN \ _IOW(NVHOST_PVA_IOCTL_MAGIC, 3, struct pva_pin_unpin_args) +#define PVA_IOCTL_SUBMIT \ + _IOW(NVHOST_PVA_IOCTL_MAGIC, 4, struct pva_ioctl_submit_args) -#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_UNPIN) +#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_SUBMIT) #define NVHOST_PVA_IOCTL_MAX_ARG_SIZE sizeof(struct pva_characteristics_req) #endif /* __LINUX_NVHOST_PVA_IOCTL_H */ -- cgit v1.2.2 From b3a7b64bc93ad39517d54b6d0dcd4e40cb9a712d Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Wed, 7 Sep 2016 13:31:55 +0300 Subject: video: tegra: host: pva: Add hardware submission This patch implements task construction and submission to PVA. The current version has few restrictions: * Only syncpoint fence type is supported * Only a single task may be submitted at a time * Tasks are not strictly tracked within kernel. This prevents implementing debug dumping through debugfs. * CVSRAM is not supported JIRA PVA-88 Change-Id: I3f22472f658a0493707c5579afa20088c80903cb Signed-off-by: Arto Merilainen Reviewed-on: http://git-master/r/1216373 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup --- include/uapi/linux/nvhost_pva_ioctl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 1ffa220e6..f7311da54 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -164,7 +164,7 @@ struct pva_fence { __u32 semaphore_value; }; -#define PVA_MAX_TASKS 16 +#define PVA_MAX_TASKS 1 #define PVA_MAX_PREFENCES 8 #define PVA_MAX_POSTFENCES 8 #define PVA_MAX_INPUT_STATUS 8 -- cgit v1.2.2 From 39f669d12204389c6aefdef0f3c1c814869c6c7e Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Wed, 21 Dec 2016 09:59:08 +0530 Subject: video: tegra: host: add semaphore with timestamp It adds timestamp place holder with semaphore. It helps debugging blockage of task list. Jira PVA-240 Change-Id: Id7ea4dceb82705a032d2e8fcb43a9d49ef1b4761 Signed-off-by: Puneet Saxena Reviewed-on: http://git-master/r/1274619 Reviewed-by: Sachin Nikam Reviewed-by: Automatic_Commit_Validation_User --- include/uapi/linux/nvhost_pva_ioctl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index f7311da54..9a570bbe3 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -156,6 +156,7 @@ struct pva_fence { #define PVA_FENCE_TYPE_SYNCPT 0 #define PVA_FENCE_TYPE_SYNC_FD 1 #define PVA_FENCE_TYPE_SEMAPHORE 2 +#define PVA_FENCE_TYPE_SEMAPHORE_TS 3 __u32 syncpoint_index; __u32 syncpoint_value; __u32 sync_fd; -- cgit v1.2.2 From a33af42261ce0269e188d7c88dcc643df064e8d3 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 4 Jan 2017 10:39:28 +0200 Subject: video: tegra: host: pva: Add pin/unpin buffer count limit Check buffer count to prevent overflows in byte count calculations. Coverity ID 38903 Bug 200192445 Change-Id: I258fa8592f4c2920e3973454c48a146b3ca29592 Signed-off-by: Mikko Perttunen Reviewed-on: http://git-master/r/1279992 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvhost_pva_ioctl.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 9a570bbe3..d9052539d 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -80,6 +80,8 @@ struct pva_pin_unpin_args { __u32 reserved; }; +#define PVA_MAX_PIN_BUFFERS 256 + /** * struct pva_ioctl_status_handle - A handle to a status structure * -- cgit v1.2.2 From 7381574818378fef1516ee7d74ccf099acb5793d Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Wed, 5 Apr 2017 14:51:19 +0300 Subject: video: tegra: host: Use dmabuf instead of fd The buffer management code is currently using fd as the buffer identifier, however, fds are ambiguous as identifiers: If user closes a dmabuf fd and allocates a new one, the two buffers may share the same fd. If the new dmabuf fd is passed to kernel, kernel incorrectly uses the old memory buffer. This patch reworks buffer management code to use dmabuf pointers as identifier instead of dmabuf fds. Reduce PVA_MAX_PIN_BUFFER from 256 to 64 nvhost_buffer_pin, nvhost_buffer_unpin, nvhost_get_iova_addr, nvhost_buffer_submit_pin and nvhost_buffer_submit_unpin are modified to pass dmabuf pointer instead of fd handle. JIRA PVA-357 Change-Id: I1f736cbcf704d0872a8e97de28308649f0f1586b Signed-off-by: Arto Merilainen Signed-off-by: Vinod G Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1455918 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvhost_pva_ioctl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index d9052539d..183389308 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -80,7 +80,7 @@ struct pva_pin_unpin_args { __u32 reserved; }; -#define PVA_MAX_PIN_BUFFERS 256 +#define PVA_MAX_PIN_BUFFERS 64 /** * struct pva_ioctl_status_handle - A handle to a status structure -- cgit v1.2.2 From 49839fd8c011b513e9807c54d9980765aa90d66f Mon Sep 17 00:00:00 2001 From: Vinod G Date: Thu, 23 Mar 2017 16:05:21 -0700 Subject: video: tegra: pva: BlockLiner support Add block_height_log2 variable to the surface descriptor to pass the block height from user space. To be backward compatible, layout and block_height_log2 are defined as 16bit variables. Set bit 39 for block linear surfaces in the address field. This bit is used for indicating that memory subsystem should convert the block linear format into common block linear format that is used by other engines in Tegra. The bit in itself is dropped before making the address translation in SMMU. JIRA PVA-93 Change-Id: I9b482412dfcbe845951d01e62abd20ff8d53d249 Signed-off-by: Vinod G Reviewed-on: http://git-master/r/1327181 Reviewed-by: Arto Merilainen Tested-by: Arto Merilainen --- include/uapi/linux/nvhost_pva_ioctl.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 183389308..ab68cf79c 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -1,7 +1,7 @@ /* * Tegra PVA Driver ioctls * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -107,6 +107,7 @@ struct pva_status_handle { * @width: Width of the surface * @height: Height of the surface * @layout: Surface layout (pitch linear, block linear) + * @block_height_log2: Block height * * This structure defines a list of surfaces to be delivered for * PVA. @@ -122,7 +123,8 @@ struct pva_surface { __u32 depth; __u32 width; __u32 height; - __u32 layout; + __u16 layout; + __u16 block_height_log2; }; /** -- cgit v1.2.2 From 897a4f33b4508fb255a8a1c09356a20530afc3d6 Mon Sep 17 00:00:00 2001 From: Vinod G Date: Fri, 7 Apr 2017 11:07:15 -0700 Subject: video: tegra: pva: Add num_queues variable Add num_queues variable to the pva characteristics struct to let the user know how many queues be supported per pva. JIRA PVA-335 Change-Id: I069dc4fa1c6b4764628ca3503cc3d2302a455147 Signed-off-by: Vinod G Reviewed-on: http://git-master/r/1458103 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvhost_pva_ioctl.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index ab68cf79c..a239a6f75 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -47,7 +47,7 @@ struct pva_characteristics_req { * * @num_vpu: number of vpu per pva * @vpu_generation: vpu hardware generation - * @task_structure_version: highest supported task struct ver + * @num_queues: number of queues per pva * @reserved: reserved for future use * @r5_ucode_version: R5 firmware version * @r5_ucode_earliest: 1st version compatible with current running fw @@ -57,7 +57,8 @@ struct pva_characteristics_req { struct pva_characteristics { __u8 num_vpu; __u8 vpu_generation; - __u8 reserved[2]; + __u8 num_queues; + __u8 reserved[1]; __u32 r5_ucode_version; __u32 r5_ucode_earliest; __u32 r5_vpu_runtime_earliest; -- cgit v1.2.2 From 29ffc31a01e226944beac43c8a440f4431d177d7 Mon Sep 17 00:00:00 2001 From: Ajay Nandakumar Date: Tue, 31 Jan 2017 11:27:56 +0530 Subject: tegra: host: pva: Support setting queue attributes Adding support to set queue attributes on PVA. JIRA PVA-47 Change-Id: Id3471c5f7b11e14d9f5e6acfe6ca5d981082ff86 Signed-off-by: Ajay Nandakumar Reviewed-on: http://git-master/r/1296362 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvhost_pva_ioctl.h | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index a239a6f75..e577168c1 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -249,6 +249,23 @@ struct pva_ioctl_submit_args { __u32 version; }; +/** + * struct pva_ioctl_queue_attr - set queue attributes + * + * @attr_id: Attribute id which defines the attribute to be set + * @reserved: reserved + * @attr_val: The value to be set for the attribute + * + * This ioctl is used for setting attributes for a queue with id queue_id + * on the R5. + * + */ +struct pva_ioctl_queue_attr { + __u16 id; + __u16 reserved; + __u32 val; +}; + #define PVA_IOCTL_CHARACTERISTICS \ _IOWR(NVHOST_PVA_IOCTL_MAGIC, 1, struct pva_characteristics_req) #define PVA_IOCTL_PIN \ @@ -257,9 +274,11 @@ struct pva_ioctl_submit_args { _IOW(NVHOST_PVA_IOCTL_MAGIC, 3, struct pva_pin_unpin_args) #define PVA_IOCTL_SUBMIT \ _IOW(NVHOST_PVA_IOCTL_MAGIC, 4, struct pva_ioctl_submit_args) +#define PVA_IOCTL_SET_QUEUE_ATTRIBUTES \ + _IOW(NVHOST_PVA_IOCTL_MAGIC, 5, struct pva_ioctl_queue_attr) -#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_SUBMIT) +#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_SET_QUEUE_ATTRIBUTES) #define NVHOST_PVA_IOCTL_MAX_ARG_SIZE sizeof(struct pva_characteristics_req) #endif /* __LINUX_NVHOST_PVA_IOCTL_H */ -- cgit v1.2.2 From d06e385a89ed1025af6af20a0ba10b3bc7e0a386 Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Fri, 9 Jun 2017 15:22:18 +0300 Subject: video: tegra: host: Increase number of surfaces This change increases maximum number of surfaces that are supported by the PVA kernel driver. Change-Id: Ic5b79375f0c8f8efc91e13c59d7972015b09c451 Signed-off-by: Arto Merilainen Reviewed-on: http://git-master/r/1499311 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup --- include/uapi/linux/nvhost_pva_ioctl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index e577168c1..1f917f368 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -175,8 +175,8 @@ struct pva_fence { #define PVA_MAX_POSTFENCES 8 #define PVA_MAX_INPUT_STATUS 8 #define PVA_MAX_OUTPUT_STATUS 8 -#define PVA_MAX_INPUT_SURFACES 4 -#define PVA_MAX_OUTPUT_SURFACES 4 +#define PVA_MAX_INPUT_SURFACES 8 +#define PVA_MAX_OUTPUT_SURFACES 8 /** * struct pva_ioctl_submit_task - Describe a task for PVA -- cgit v1.2.2 From aa6795870e79868828514161397f89de3dade15d Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Sat, 28 Jan 2017 14:13:21 +0200 Subject: video: tegra: host: pva: Use structures for task This change modifies task definition to use structures instead of keeping track of data offsets. This makes the code maintenance easier and allows modifying data within the fields without manually calculating sizes. JIRA PVA-275 JIRA PVA-301 Change-Id: I486ec5f536d9200576d0ef76bec5644d36635547 Signed-off-by: Arto Merilainen Reviewed-on: https://git-master.nvidia.com/r/1513581 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvhost_pva_ioctl.h | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 1f917f368..dc47a2859 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -83,6 +83,17 @@ struct pva_pin_unpin_args { #define PVA_MAX_PIN_BUFFERS 64 +/** + * struct pva_memory_handle - A handle to PVA pointer + * + * @handle: Handle to a dmabuf that holds the data + * @offset: An offset within the buffer to the data within the buffer + */ +struct pva_memory_handle { + __u32 handle; + __u32 offset; +}; + /** * struct pva_ioctl_status_handle - A handle to a status structure * -- cgit v1.2.2 From c073d8a3c41cf78f98752e8afb35067b09ae49ac Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Sat, 28 Jan 2017 14:13:21 +0200 Subject: video: tegra: host: pva: Add pointer type This change adds pointer type support to PVA kernel driver. JIRA PVA-275 JIRA PVA-301 Change-Id: Ifa5d3bc6565418bc075c13ed33a065bab1d759e3 Signed-off-by: Arto Merilainen Reviewed-on: https://git-master.nvidia.com/r/1513582 GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup --- include/uapi/linux/nvhost_pva_ioctl.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index dc47a2859..6088f91d5 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -188,6 +188,7 @@ struct pva_fence { #define PVA_MAX_OUTPUT_STATUS 8 #define PVA_MAX_INPUT_SURFACES 8 #define PVA_MAX_OUTPUT_SURFACES 8 +#define PVA_MAX_POINTERS 128 /** * struct pva_ioctl_submit_task - Describe a task for PVA @@ -224,7 +225,9 @@ struct pva_ioctl_submit_task { __u8 num_output_surfaces; __u8 num_input_task_status; __u8 num_output_task_status; - __u8 reserved[14]; + __u16 num_pointers; + __u64 pointers; + __u8 reserved[4]; __u32 operation; __u64 timeout; __u64 prefences; -- cgit v1.2.2 From 7d3f574690ff81b257e31f935970d913b9955396 Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Fri, 14 Jul 2017 17:57:04 +0530 Subject: t194: cache: l3 cache It adds ioctl to get gpu_cpu_ways, gpu_only_ways. It sets gpu_l3_ways(max) and gpu_l3_only_ways(min) to program l3 cache. It exposes debugfs nodes to set/get - - gpu_cpu_ways - gpu_only_ways It also exposes debugfs node to get - - total_ways - L3 cache size Bug 200324092 Change-Id: Ibef7484be30041825ff2324791c9455e4e70bd4d Signed-off-by: Puneet Saxena Reviewed-on: https://git-master.nvidia.com/r/1520534 Reviewed-by: Sachin Nikam --- include/uapi/linux/t19x_cache.h | 45 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 include/uapi/linux/t19x_cache.h (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/t19x_cache.h b/include/uapi/linux/t19x_cache.h new file mode 100644 index 000000000..98dfd12fa --- /dev/null +++ b/include/uapi/linux/t19x_cache.h @@ -0,0 +1,45 @@ +/* + * t19x_cache.h + * + * declarations for t19x cache + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __T19x_CACHE_H +#define __T19x_CACHE_H + +#include +#include + +#define TEGRA_L3_CACHE_IOC_MAGIC 'C' + +#if !defined(__KERNEL__) +#define __user +#endif + +struct tegra_l3_ioctl_data { + __u32 igpu_cpu_ways; /* integrated gpu */ + __u32 igpu_only_ways; + __u32 total_ways; + __u32 reserved; + __u64 size; +}; + +#define TEGRA_L3_CACHE_GET_IOCTL_DATA \ + _IOWR(TEGRA_L3_CACHE_IOC_MAGIC, 1, struct tegra_l3_ioctl_data) + +#define TEGRA_L3_CACHE_IOCTL_IOC_MAXNR _IOC_NR(TEGRA_L3_CACHE_GET_IOCTL_DATA) +#define TEGRA_L3_CACHE_IOCTL_MAX_ARG_SIZE \ + sizeof(struct tegra_l3_ioctl_data) + +#endif /* __T19x_CACHE_H */ -- cgit v1.2.2 From 2052b38fb1c4be037c946bc57f8cac218b3e1fec Mon Sep 17 00:00:00 2001 From: Puneet Saxena Date: Thu, 7 Sep 2017 11:20:39 +0530 Subject: tegra: l3: cache: rename header file It renames header file "t19x_cache.h" -> "tegra_l3_cache.h" as header file name which exposes ioctl to userspace should be by the ioctl name. The IOCTL prefix is TEGRA_L3_CACHE hence renaming it tegra_l3_cache.h Bug 200324092 Change-Id: I15911073417499f31b51e7d027fdf9d932e039c2 Signed-off-by: Puneet Saxena Reviewed-on: https://git-master.nvidia.com/r/1554241 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/t19x_cache.h | 45 ------------------------------------- include/uapi/linux/tegra_l3_cache.h | 45 +++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 45 deletions(-) delete mode 100644 include/uapi/linux/t19x_cache.h create mode 100644 include/uapi/linux/tegra_l3_cache.h (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/t19x_cache.h b/include/uapi/linux/t19x_cache.h deleted file mode 100644 index 98dfd12fa..000000000 --- a/include/uapi/linux/t19x_cache.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * t19x_cache.h - * - * declarations for t19x cache - * - * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __T19x_CACHE_H -#define __T19x_CACHE_H - -#include -#include - -#define TEGRA_L3_CACHE_IOC_MAGIC 'C' - -#if !defined(__KERNEL__) -#define __user -#endif - -struct tegra_l3_ioctl_data { - __u32 igpu_cpu_ways; /* integrated gpu */ - __u32 igpu_only_ways; - __u32 total_ways; - __u32 reserved; - __u64 size; -}; - -#define TEGRA_L3_CACHE_GET_IOCTL_DATA \ - _IOWR(TEGRA_L3_CACHE_IOC_MAGIC, 1, struct tegra_l3_ioctl_data) - -#define TEGRA_L3_CACHE_IOCTL_IOC_MAXNR _IOC_NR(TEGRA_L3_CACHE_GET_IOCTL_DATA) -#define TEGRA_L3_CACHE_IOCTL_MAX_ARG_SIZE \ - sizeof(struct tegra_l3_ioctl_data) - -#endif /* __T19x_CACHE_H */ diff --git a/include/uapi/linux/tegra_l3_cache.h b/include/uapi/linux/tegra_l3_cache.h new file mode 100644 index 000000000..2ba30ddc6 --- /dev/null +++ b/include/uapi/linux/tegra_l3_cache.h @@ -0,0 +1,45 @@ +/* + * tegra_l3_cache.h + * + * declarations for t19x cache + * + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TEGRA_L3_CACHE_H +#define __TEGRA_L3_CACHE_H + +#include +#include + +#define TEGRA_L3_CACHE_IOC_MAGIC 'C' + +#if !defined(__KERNEL__) +#define __user +#endif + +struct tegra_l3_ioctl_data { + __u32 igpu_cpu_ways; /* integrated gpu */ + __u32 igpu_only_ways; + __u32 total_ways; + __u32 reserved; + __u64 size; +}; + +#define TEGRA_L3_CACHE_GET_IOCTL_DATA \ + _IOWR(TEGRA_L3_CACHE_IOC_MAGIC, 1, struct tegra_l3_ioctl_data) + +#define TEGRA_L3_CACHE_IOCTL_IOC_MAXNR _IOC_NR(TEGRA_L3_CACHE_GET_IOCTL_DATA) +#define TEGRA_L3_CACHE_IOCTL_MAX_ARG_SIZE \ + sizeof(struct tegra_l3_ioctl_data) + +#endif /* __TEGRA_L3_CACHE_H */ -- cgit v1.2.2 From f3a2fe4f44b80bfc11d853c0eb99ba2cea4a4859 Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Fri, 18 Aug 2017 11:13:05 +0300 Subject: video: tegra: host: pva: Remove deprecated types 2d point and ROI data types were never used by userspace or supported by PVA. Therefore, remove these data types in favor of pointers. JIRA PVA-302 JIRA PVA-538 Change-Id: I053a17fe5189fd1b8040408f4733eae8dfdef11b Signed-off-by: Arto Merilainen Reviewed-on: https://git-master.nvidia.com/r/1541231 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: svc-mobile-coverity --- include/uapi/linux/nvhost_pva_ioctl.h | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 6088f91d5..a8aa21c87 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -205,12 +205,8 @@ struct pva_fence { * @postfences: Pointer to post-fence structures * @input_surfaces: Pointer to input surfaces * @input_scalars: Information for input scalars - * @input_2dpoint: Information for input 2d points - * @input_rois: Pointer to input ROIs * @output_surfaces: Pointer to output surfaces * @output_scalars: Information for output scalars - * @output_2dpoint: Information for output 2d points - * @output_rois: Pointer to output ROIs * @input_task_status: Pointer to input status structure * @output_task_status: Pointer to output status structure * @@ -227,19 +223,17 @@ struct pva_ioctl_submit_task { __u8 num_output_task_status; __u16 num_pointers; __u64 pointers; - __u8 reserved[4]; + __u8 reserved0[4]; __u32 operation; __u64 timeout; __u64 prefences; __u64 postfences; __u64 input_surfaces; struct pva_task_parameter input_scalars; - struct pva_task_parameter input_2dpoint; - struct pva_task_parameter input_rois; + u8 reserved1[16]; __u64 output_surfaces; struct pva_task_parameter output_scalars; - struct pva_task_parameter output_2dpoint; - struct pva_task_parameter output_rois; + u8 reserved2[16]; __u64 input_task_status; __u64 output_task_status; }; -- cgit v1.2.2 From 7c5d6f96e5c8f6bb912a62c3249158ed3b892369 Mon Sep 17 00:00:00 2001 From: Arto Merilainen Date: Fri, 18 Aug 2017 14:02:52 +0300 Subject: video: tegra: host: pva: Add opaque type This change adds an opaque data type for passing information from userspace to firmware. The data type replaces the existing "pointer" data type with a new type that supports delivering payload as part of the task. JIRA PVA-302 JIRA PVA-538 Change-Id: If290ae7809cb4603693510a0d0a14b11a1380258 Signed-off-by: Arto Merilainen Reviewed-on: https://git-master.nvidia.com/r/1541232 Reviewed-by: Vinod Gopalakrishnakurup Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker --- include/uapi/linux/nvhost_pva_ioctl.h | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index a8aa21c87..18588cefe 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -181,14 +181,15 @@ struct pva_fence { __u32 semaphore_value; }; -#define PVA_MAX_TASKS 1 -#define PVA_MAX_PREFENCES 8 -#define PVA_MAX_POSTFENCES 8 -#define PVA_MAX_INPUT_STATUS 8 -#define PVA_MAX_OUTPUT_STATUS 8 -#define PVA_MAX_INPUT_SURFACES 8 -#define PVA_MAX_OUTPUT_SURFACES 8 -#define PVA_MAX_POINTERS 128 +#define PVA_MAX_TASKS 1 +#define PVA_MAX_PREFENCES 8 +#define PVA_MAX_POSTFENCES 8 +#define PVA_MAX_INPUT_STATUS 8 +#define PVA_MAX_OUTPUT_STATUS 8 +#define PVA_MAX_INPUT_SURFACES 8 +#define PVA_MAX_OUTPUT_SURFACES 8 +#define PVA_MAX_POINTERS 128 +#define PVA_MAX_PRIMARY_PAYLOAD_SIZE 4096 /** * struct pva_ioctl_submit_task - Describe a task for PVA @@ -223,17 +224,18 @@ struct pva_ioctl_submit_task { __u8 num_output_task_status; __u16 num_pointers; __u64 pointers; - __u8 reserved0[4]; + __u32 primary_payload_size; __u32 operation; __u64 timeout; __u64 prefences; __u64 postfences; __u64 input_surfaces; struct pva_task_parameter input_scalars; - u8 reserved1[16]; + __u64 primary_payload; + u8 reserved0[8]; __u64 output_surfaces; struct pva_task_parameter output_scalars; - u8 reserved2[16]; + u8 reserved1[16]; __u64 input_task_status; __u64 output_task_status; }; -- cgit v1.2.2 From 127bacd08922e10f17d2e805bfd1c4c6b93c3a1b Mon Sep 17 00:00:00 2001 From: Ajay Nandakumar Date: Wed, 25 Oct 2017 06:45:18 -0700 Subject: video: tegra: pva: vpu function table Adding functionality to expose the function table to the userspace. Also adding functionality to expose the function table along with its id. JIRA PVA-144 Change-Id: I930545e06e3954f22c95b5734ed5e13eeef67af3 Signed-off-by: Ajay Nandakumar Reviewed-on: https://git-master.nvidia.com/r/1585418 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/uapi/linux/nvhost_pva_ioctl.h | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) (limited to 'include/uapi/linux') diff --git a/include/uapi/linux/nvhost_pva_ioctl.h b/include/uapi/linux/nvhost_pva_ioctl.h index 18588cefe..233b9eca5 100644 --- a/include/uapi/linux/nvhost_pva_ioctl.h +++ b/include/uapi/linux/nvhost_pva_ioctl.h @@ -276,6 +276,25 @@ struct pva_ioctl_queue_attr { __u32 val; }; +/** + * struct pva_ioctl_vpu_func_table - ioctl vpu function table entries + * + * @addr: Userspace address space to which the function table needs to be copied + * @entries: The number of entries in the vpu table + * @size: Size of the user buffer passed/ Size of the function table + * + * This ioctl is used to fetch the VPU function table available on a PVA, which + * is copied to user space buffer starting at "addr" with size "size". Once the + * function table is copied the the number of entries is updated along with the + * size of the vpu function table. + * + */ +struct pva_ioctl_vpu_func_table { + __u64 addr; + __u32 entries; + __u32 size; +}; + #define PVA_IOCTL_CHARACTERISTICS \ _IOWR(NVHOST_PVA_IOCTL_MAGIC, 1, struct pva_characteristics_req) #define PVA_IOCTL_PIN \ @@ -286,9 +305,11 @@ struct pva_ioctl_queue_attr { _IOW(NVHOST_PVA_IOCTL_MAGIC, 4, struct pva_ioctl_submit_args) #define PVA_IOCTL_SET_QUEUE_ATTRIBUTES \ _IOW(NVHOST_PVA_IOCTL_MAGIC, 5, struct pva_ioctl_queue_attr) +#define PVA_IOCTL_COPY_VPU_FUNCTION_TABLE \ + _IOWR(NVHOST_PVA_IOCTL_MAGIC, 6, struct pva_ioctl_vpu_func_table) -#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_SET_QUEUE_ATTRIBUTES) +#define NVHOST_PVA_IOCTL_LAST _IOC_NR(PVA_IOCTL_COPY_VPU_FUNCTION_TABLE) #define NVHOST_PVA_IOCTL_MAX_ARG_SIZE sizeof(struct pva_characteristics_req) #endif /* __LINUX_NVHOST_PVA_IOCTL_H */ -- cgit v1.2.2