From 1f2fcb56fb9a8b8fc402da57318a7c3fbc17b057 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Fri, 10 Jun 2016 09:38:41 +0530 Subject: video: tegra: host: nvdla: add IOCTL stub - adds basic IOCTL stub for device ctrl node - register newly added fops to ctrl node Jira DLA-20 Change-Id: I87e764f47dc8b5e96c087b84c1baad909bfcfbf7 Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1150326 GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Gaikwad --- include/linux/nvhost_nvdla_ioctl.h | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 include/linux/nvhost_nvdla_ioctl.h (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h new file mode 100644 index 000000000..220ff0e21 --- /dev/null +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -0,0 +1,33 @@ +/* + * include/linux/nvhost_nvdla_ioctl.h + * + * Tegra NvDLA Driver + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, see . + */ + +#ifndef __LINUX_NVHOST_NVDLA_IOCTL_H +#define __LINUX_NVHOST_NVDLA_IOCTL_H + +#include +#include + +#if !defined(__KERNEL__) +#define __user +#endif + +#define NVHOST_NVDLA_IOCTL_MAGIC 'D' + +#endif /* __LINUX_NVHOST_NVDLA_IOCTL_H */ -- cgit v1.2.2 From 45b35f35547473681cb536f6c0ae6988deca30f2 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Thu, 23 Jun 2016 14:02:10 +0530 Subject: video: tegra: host: nvdla: add ping cmd ioctl - this adds first IOCTL for NvDLA for ping cmd - this ping cmd added to make sure that, falcon and memory read/write are working. - Through IOCTL, pass ping number to falcon via KMD - From falcon, for CRC check update mailbox and writeback with multiplier. Jira DLA-20 Change-Id: I9cd1bb57d42d00b03907d7cb45750dcec0b2df7b Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1170198 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Gaikwad --- include/linux/nvhost_nvdla_ioctl.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 220ff0e21..633facb2a 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -28,6 +28,20 @@ #define __user #endif +struct nvdla_ctrl_ping_args { + __u32 in_challenge; + __u32 out_response; +}; + #define NVHOST_NVDLA_IOCTL_MAGIC 'D' +#define NVDLA_IOCTL_CTRL_PING \ + _IOWR(NVHOST_NVDLA_IOCTL_MAGIC, 1, struct nvdla_ctrl_ping_args) + +#define NVDLA_IOCTL_CTRL_LAST \ + _IOC_NR(NVDLA_IOCTL_CTRL_PING) + +#define NVDLA_IOCTL_CTRL_MAX_ARG_SIZE \ + sizeof(struct nvdla_ctrl_ping_args) + #endif /* __LINUX_NVHOST_NVDLA_IOCTL_H */ -- cgit v1.2.2 From 1c7ca4fd69f129b13fb07f655a453af2d5cd12f6 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Fri, 1 Jul 2016 21:18:47 +0530 Subject: video: tegra: host: add buffer pin and unpin for nvdla - Using nvhost buffer management framework API's support Buffer pin and unpin for multiple buffer handles. Jira DLA-21 Change-Id: I029dfae698a699caa6e19ef6e7e3c0641b9de782 Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1174651 Reviewed-by: Prashant Gaikwad --- include/linux/nvhost_nvdla_ioctl.h | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 633facb2a..b5b6c676b 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -33,15 +33,25 @@ struct nvdla_ctrl_ping_args { __u32 out_response; }; +struct nvdla_ctrl_pin_unpin_args { + __u64 buffers; + __u32 num_buffers; + __u32 reserved; +}; + #define NVHOST_NVDLA_IOCTL_MAGIC 'D' #define NVDLA_IOCTL_CTRL_PING \ _IOWR(NVHOST_NVDLA_IOCTL_MAGIC, 1, struct nvdla_ctrl_ping_args) +#define NVDLA_IOCTL_CTRL_PIN \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 2, struct nvdla_ctrl_pin_unpin_args) +#define NVDLA_IOCTL_CTRL_UNPIN \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 3, struct nvdla_ctrl_pin_unpin_args) #define NVDLA_IOCTL_CTRL_LAST \ - _IOC_NR(NVDLA_IOCTL_CTRL_PING) + _IOC_NR(NVDLA_IOCTL_CTRL_UNPIN) #define NVDLA_IOCTL_CTRL_MAX_ARG_SIZE \ - sizeof(struct nvdla_ctrl_ping_args) + sizeof(struct nvdla_ctrl_pin_unpin_args) #endif /* __LINUX_NVHOST_NVDLA_IOCTL_H */ -- cgit v1.2.2 From 99b319a13e559bc8eec488ec35cb50ed23d0e68b Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Mon, 25 Jul 2016 14:58:10 +0530 Subject: video: tegra: host: dla: add submit IOCTL - add initial task submit stub Jira DLA-19 Change-Id: Iea249cfd14cf186b984d1f296373740f80429c3d Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1191493 --- include/linux/nvhost_nvdla_ioctl.h | 62 ++++++++++++++++++++++++++++++++++++-- 1 file changed, 60 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index b5b6c676b..06f4f1011 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -39,6 +39,63 @@ struct nvdla_ctrl_pin_unpin_args { __u32 reserved; }; +struct nvdla_ctrl_submit_args { + __u64 tasks; + __u16 num_tasks; +#define MAX_TASKS_PER_SUBMIT 32 +#define NVDLA_SUBMIT_FLAGS_ATOMIC (1 << 0) + __u16 flags; + __u32 version; +}; + +struct nvdla_ctrl_ioctl_submit_task { + __u8 num_prefences; + __u8 num_postfences; + __u8 num_input_task_status; + __u8 num_output_task_status; + __u16 flags; + __u16 reserved; + + __u64 prefences; + __u64 postfences; + + __u64 input_task_status; + __u64 output_task_status; + + __u32 num_operations; + __u32 num_addresses; + __u64 operation_desc; + + __u64 surface_desc; + __u64 address_list; +}; + +struct nvdla_fence { + __u32 type; +#define NVDLA_FENCE_TYPE_SYNCPT 0 +#define NVDLA_FENCE_TYPE_SYNC_FD 1 + __u32 syncpoint_index; + __u32 syncpoint_value; + __u32 sync_fd; +}; + +struct nvdla_task_surface { + __u64 format; + __u32 handle; + __u32 offset; +}; + +struct nvdla_task_roi { + __u32 handle; + __u32 offset; +}; + +struct nvdla_task_status_handle { + __u32 handle; + __u32 reserved; + __u64 offset; +}; + #define NVHOST_NVDLA_IOCTL_MAGIC 'D' #define NVDLA_IOCTL_CTRL_PING \ @@ -47,9 +104,10 @@ struct nvdla_ctrl_pin_unpin_args { _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 2, struct nvdla_ctrl_pin_unpin_args) #define NVDLA_IOCTL_CTRL_UNPIN \ _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 3, struct nvdla_ctrl_pin_unpin_args) - +#define NVDLA_IOCTL_CTRL_SUBMIT \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 4, struct nvdla_ctrl_submit_args) #define NVDLA_IOCTL_CTRL_LAST \ - _IOC_NR(NVDLA_IOCTL_CTRL_UNPIN) + _IOC_NR(NVDLA_IOCTL_CTRL_SUBMIT) #define NVDLA_IOCTL_CTRL_MAX_ARG_SIZE \ sizeof(struct nvdla_ctrl_pin_unpin_args) -- cgit v1.2.2 From 37febd472a4920976c841fadb37a9a2aae76d0f4 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Wed, 27 Jul 2016 14:19:08 +0530 Subject: video: tegra: host: dla: add basic tasklist support - fix include files path in makefile - fix ioctl include header file path - update comments in doxygen format add support to submit task to engine as per tasklist management protocol - maintain list of tasks under assigned queue with ref counts - allocates task to maintain list of fences and update them - dma alloc task descriptor and action list and update them - submit tasks one by one and send received fence back to application - register for syncpoint notifier with nvhost for completion of fence - on fence completion interrupt handler, cleanup task Jira DLA-52 Change-Id: Ibe385f47dc9f17dda79cca3daf29b89218dc7289 Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1191495 Reviewed-by: Prashant Gaikwad GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- include/linux/nvhost_nvdla_ioctl.h | 69 ++++++++++++++++++++++++++++---------- 1 file changed, 52 insertions(+), 17 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 06f4f1011..1db5d710e 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -28,17 +28,42 @@ #define __user #endif +/** + * struct nvdla_ctrl_ping_args structure for ping data + * + * @in_challenge challenge data to be sent + * @out_response response/CRC on challenge data from engine + * + */ struct nvdla_ctrl_ping_args { __u32 in_challenge; __u32 out_response; }; + +/** + * struct nvdla_ctrl_pin_unpin_args strcture args for buffer pin/unpin + * + * @buffers list of buffers to pin/unpin'ed + * @num_buffers number of buffers count + * @reserved reserved for future use + * + */ struct nvdla_ctrl_pin_unpin_args { __u64 buffers; __u32 num_buffers; __u32 reserved; }; +/** + * struct nvdla_ctrl_submit_args structure for task submit + * + * @tasks pointer to task list + * @num_tasks number of tasks count + * @flags flags for task submit, like atomic + * @version version of task structure + * + */ struct nvdla_ctrl_submit_args { __u64 tasks; __u16 num_tasks; @@ -48,6 +73,25 @@ struct nvdla_ctrl_submit_args { __u32 version; }; +/** + * struct nvdla_ctrl_ioctl_submit_task structure for single task information + * + * @num_prefences number of pre-fences in task + * @num_postfences number of post-fences in task + * @num_input_task_status number of input task status + * @num_output_task_status number of output task status + * @flags flags for bitwise task info embeddeing + * @reserved reserved for future use + * @prefences pointer to pre-fence struct table + * @postfences pointer to post-fence struct table + * @input_task_status pointer to input task status struct table + * @output_task_status pointer to output task status struct table + * @num_operations number of operations for a task + * @num_addresses total number of addressed passed in structure + * @surface_desc pointer to surface descriptor + * @address_list pointer to address list + * + */ struct nvdla_ctrl_ioctl_submit_task { __u8 num_prefences; __u8 num_postfences; @@ -70,6 +114,14 @@ struct nvdla_ctrl_ioctl_submit_task { __u64 address_list; }; +/** + * struct nvdla_fence structure for passing fence information + * + * @type type of fence: syncpoint, Linux Sync Fd + * @syncpoint_index syncpoint id + * @syncpoint_value value of syncpoint id + * @sync_fd Linux sync FD handle + */ struct nvdla_fence { __u32 type; #define NVDLA_FENCE_TYPE_SYNCPT 0 @@ -79,23 +131,6 @@ struct nvdla_fence { __u32 sync_fd; }; -struct nvdla_task_surface { - __u64 format; - __u32 handle; - __u32 offset; -}; - -struct nvdla_task_roi { - __u32 handle; - __u32 offset; -}; - -struct nvdla_task_status_handle { - __u32 handle; - __u32 reserved; - __u64 offset; -}; - #define NVHOST_NVDLA_IOCTL_MAGIC 'D' #define NVDLA_IOCTL_CTRL_PING \ -- cgit v1.2.2 From c4e510fb1451c3af2bea2352725e8d1607e8b5b7 Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Thu, 15 Sep 2016 01:29:18 +0530 Subject: video: tegra: host: nvdla: add offset to memory handles Use offset and memory handle to calculate IOVA address for descriptors. It allows using single buffer in user space for all descriptors. Jira DLA-176 Change-Id: I141efa7fc8662be8aa4b5c3bd2ea7a369a90769a Signed-off-by: Prashant Gaikwad Reviewed-on: http://git-master/r/1220956 --- include/linux/nvhost_nvdla_ioctl.h | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 1db5d710e..b0774d633 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -73,6 +73,18 @@ struct nvdla_ctrl_submit_args { __u32 version; }; +/** + * struct nvdla_ctrl_mem_handle structure for memory handles + * + * @handle handle to buffer allocated in userspace + * @offset offset in buffer + * + */ +struct nvdla_ctrl_mem_handle { + __u32 handle; + __u32 offset; +}; + /** * struct nvdla_ctrl_ioctl_submit_task structure for single task information * @@ -88,7 +100,8 @@ struct nvdla_ctrl_submit_args { * @output_task_status pointer to output task status struct table * @num_operations number of operations for a task * @num_addresses total number of addressed passed in structure - * @surface_desc pointer to surface descriptor + * @operation_desc pointer to operation descriptor list + * @surface_desc pointer to surface descriptor list * @address_list pointer to address list * */ @@ -108,10 +121,9 @@ struct nvdla_ctrl_ioctl_submit_task { __u32 num_operations; __u32 num_addresses; - __u64 operation_desc; - - __u64 surface_desc; - __u64 address_list; + struct nvdla_ctrl_mem_handle operation_desc; + struct nvdla_ctrl_mem_handle surface_desc; + struct nvdla_ctrl_mem_handle address_list; }; /** -- cgit v1.2.2 From d77caf2cba2e02a3fcd8960f41ca8cc4c12bf26d Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Thu, 15 Sep 2016 19:58:01 +0530 Subject: video: tegra: host: nvdla: add more info to task Add below information to task descriptor - Address list - LUT data - Dynamic ROI Jira DLA-176 Change-Id: I067025da34a68a2d81c5e3829ac76c516ed8754b Signed-off-by: Prashant Gaikwad Reviewed-on: http://git-master/r/1221382 --- include/linux/nvhost_nvdla_ioctl.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index b0774d633..aba5ff554 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -120,9 +120,16 @@ struct nvdla_ctrl_ioctl_submit_task { __u64 output_task_status; __u32 num_operations; - __u32 num_addresses; + __u32 num_luts; struct nvdla_ctrl_mem_handle operation_desc; struct nvdla_ctrl_mem_handle surface_desc; + struct nvdla_ctrl_mem_handle lut_data; + + __u8 dynamic_roi; + struct nvdla_ctrl_mem_handle roi_desc_array; + struct nvdla_ctrl_mem_handle surface; + + __u32 num_addresses; struct nvdla_ctrl_mem_handle address_list; }; -- cgit v1.2.2 From 842fb9099d984d12eae833e22cbd4bdcd3fecbf6 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Thu, 1 Dec 2016 16:52:59 +0530 Subject: video: tegra: host: dla: correct IOCTL parameters names - this is cosmetic change to remove _ctrl_ from interface fields and params Change-Id: Ibb2aad75755fea158015f9f756c5b844a8984ded Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1263102 GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Gaikwad --- include/linux/nvhost_nvdla_ioctl.h | 58 +++++++++++++++++++------------------- 1 file changed, 29 insertions(+), 29 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index aba5ff554..41a4918fe 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -29,34 +29,34 @@ #endif /** - * struct nvdla_ctrl_ping_args structure for ping data + * struct nvdla_ping_args structure for ping data * * @in_challenge challenge data to be sent * @out_response response/CRC on challenge data from engine * */ -struct nvdla_ctrl_ping_args { +struct nvdla_ping_args { __u32 in_challenge; __u32 out_response; }; /** - * struct nvdla_ctrl_pin_unpin_args strcture args for buffer pin/unpin + * struct nvdla_pin_unpin_args strcture args for buffer pin/unpin * * @buffers list of buffers to pin/unpin'ed * @num_buffers number of buffers count * @reserved reserved for future use * */ -struct nvdla_ctrl_pin_unpin_args { +struct nvdla_pin_unpin_args { __u64 buffers; __u32 num_buffers; __u32 reserved; }; /** - * struct nvdla_ctrl_submit_args structure for task submit + * struct nvdla_submit_args structure for task submit * * @tasks pointer to task list * @num_tasks number of tasks count @@ -64,7 +64,7 @@ struct nvdla_ctrl_pin_unpin_args { * @version version of task structure * */ -struct nvdla_ctrl_submit_args { +struct nvdla_submit_args { __u64 tasks; __u16 num_tasks; #define MAX_TASKS_PER_SUBMIT 32 @@ -74,19 +74,19 @@ struct nvdla_ctrl_submit_args { }; /** - * struct nvdla_ctrl_mem_handle structure for memory handles + * struct nvdla_mem_handle structure for memory handles * * @handle handle to buffer allocated in userspace * @offset offset in buffer * */ -struct nvdla_ctrl_mem_handle { +struct nvdla_mem_handle { __u32 handle; __u32 offset; }; /** - * struct nvdla_ctrl_ioctl_submit_task structure for single task information + * struct nvdla_ioctl_submit_task structure for single task information * * @num_prefences number of pre-fences in task * @num_postfences number of post-fences in task @@ -105,7 +105,7 @@ struct nvdla_ctrl_mem_handle { * @address_list pointer to address list * */ -struct nvdla_ctrl_ioctl_submit_task { +struct nvdla_ioctl_submit_task { __u8 num_prefences; __u8 num_postfences; __u8 num_input_task_status; @@ -121,16 +121,16 @@ struct nvdla_ctrl_ioctl_submit_task { __u32 num_operations; __u32 num_luts; - struct nvdla_ctrl_mem_handle operation_desc; - struct nvdla_ctrl_mem_handle surface_desc; - struct nvdla_ctrl_mem_handle lut_data; + struct nvdla_mem_handle operation_desc; + struct nvdla_mem_handle surface_desc; + struct nvdla_mem_handle lut_data; __u8 dynamic_roi; - struct nvdla_ctrl_mem_handle roi_desc_array; - struct nvdla_ctrl_mem_handle surface; + struct nvdla_mem_handle roi_desc_array; + struct nvdla_mem_handle surface; __u32 num_addresses; - struct nvdla_ctrl_mem_handle address_list; + struct nvdla_mem_handle address_list; }; /** @@ -152,18 +152,18 @@ struct nvdla_fence { #define NVHOST_NVDLA_IOCTL_MAGIC 'D' -#define NVDLA_IOCTL_CTRL_PING \ - _IOWR(NVHOST_NVDLA_IOCTL_MAGIC, 1, struct nvdla_ctrl_ping_args) -#define NVDLA_IOCTL_CTRL_PIN \ - _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 2, struct nvdla_ctrl_pin_unpin_args) -#define NVDLA_IOCTL_CTRL_UNPIN \ - _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 3, struct nvdla_ctrl_pin_unpin_args) -#define NVDLA_IOCTL_CTRL_SUBMIT \ - _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 4, struct nvdla_ctrl_submit_args) -#define NVDLA_IOCTL_CTRL_LAST \ - _IOC_NR(NVDLA_IOCTL_CTRL_SUBMIT) - -#define NVDLA_IOCTL_CTRL_MAX_ARG_SIZE \ - sizeof(struct nvdla_ctrl_pin_unpin_args) +#define NVDLA_IOCTL_PING \ + _IOWR(NVHOST_NVDLA_IOCTL_MAGIC, 1, struct nvdla_ping_args) +#define NVDLA_IOCTL_PIN \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 2, struct nvdla_pin_unpin_args) +#define NVDLA_IOCTL_UNPIN \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 3, struct nvdla_pin_unpin_args) +#define NVDLA_IOCTL_SUBMIT \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 4, struct nvdla_submit_args) +#define NVDLA_IOCTL_LAST \ + _IOC_NR(NVDLA_IOCTL_SUBMIT) + +#define NVDLA_IOCTL_MAX_ARG_SIZE \ + sizeof(struct nvdla_pin_unpin_args) #endif /* __LINUX_NVHOST_NVDLA_IOCTL_H */ -- cgit v1.2.2 From d56b20c03b25fa0422cd4da0775de69a8016b58b Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Wed, 23 Nov 2016 17:54:20 +0530 Subject: video: tegra: host: nvdla: update task descriptor All network related information is now added to network descriptor which is created by UMD and used by firmware. Remove that information from task descriptor and keep only address list in task descriptor for IOVA translation. Jira DLA-148 Change-Id: Ie25e5297a58cd0320f8ae994c1bd1fa670306594 Signed-off-by: Prashant Gaikwad Reviewed-on: http://git-master/r/1267278 Reviewed-by: Automatic_Commit_Validation_User --- include/linux/nvhost_nvdla_ioctl.h | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 41a4918fe..5e9d82bd1 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -98,10 +98,7 @@ struct nvdla_mem_handle { * @postfences pointer to post-fence struct table * @input_task_status pointer to input task status struct table * @output_task_status pointer to output task status struct table - * @num_operations number of operations for a task * @num_addresses total number of addressed passed in structure - * @operation_desc pointer to operation descriptor list - * @surface_desc pointer to surface descriptor list * @address_list pointer to address list * */ @@ -119,16 +116,6 @@ struct nvdla_ioctl_submit_task { __u64 input_task_status; __u64 output_task_status; - __u32 num_operations; - __u32 num_luts; - struct nvdla_mem_handle operation_desc; - struct nvdla_mem_handle surface_desc; - struct nvdla_mem_handle lut_data; - - __u8 dynamic_roi; - struct nvdla_mem_handle roi_desc_array; - struct nvdla_mem_handle surface; - __u32 num_addresses; struct nvdla_mem_handle address_list; }; -- cgit v1.2.2 From a4ccef286a37ddfcc16b9bb5a11b7fd6bbe3cd10 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Tue, 20 Dec 2016 17:09:24 +0530 Subject: video: tegra: host: dla: add semaphore support for prefences - this adds semaphore/memsignal support in prefences - while updating task descriptor, does pinning of UMD semaphore handle and received dma_addr added as preaction Jira DLA-161 Change-Id: If3695b0cca29d485c04b93a83848d50ad81dd9fd Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1274302 Reviewed-by: Prashant Gaikwad GVS: Gerrit_Virtual_Submit --- include/linux/nvhost_nvdla_ioctl.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 5e9d82bd1..e5eef1554 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -132,9 +132,13 @@ struct nvdla_fence { __u32 type; #define NVDLA_FENCE_TYPE_SYNCPT 0 #define NVDLA_FENCE_TYPE_SYNC_FD 1 +#define NVDLA_FENCE_TYPE_SEMAPHORE 2 __u32 syncpoint_index; __u32 syncpoint_value; __u32 sync_fd; + __u32 sem_handle; + __u32 sem_offset; + __u32 sem_val; }; #define NVHOST_NVDLA_IOCTL_MAGIC 'D' -- cgit v1.2.2 From e478d722d85da23a75d929faf8274cc5c52cbeba Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Wed, 21 Dec 2016 10:17:57 +0530 Subject: video: tegra: host: dla: add TIMESTAMP semaphore - this adds TIMESTAMP semaphore for postactions - TIMESTAMP semaphore is similar to default SEMAPHORE with added field to update timestamp Jira DLA-197 Change-Id: I2e663c7bfcf5e75727c9ac3a1c41ce333e45cf15 Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1274611 Reviewed-by: Prashant Gaikwad GVS: Gerrit_Virtual_Submit --- include/linux/nvhost_nvdla_ioctl.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index e5eef1554..8cb7bfc45 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -133,6 +133,7 @@ struct nvdla_fence { #define NVDLA_FENCE_TYPE_SYNCPT 0 #define NVDLA_FENCE_TYPE_SYNC_FD 1 #define NVDLA_FENCE_TYPE_SEMAPHORE 2 +#define NVDLA_FENCE_TYPE_TS_SEMAPHORE 3 __u32 syncpoint_index; __u32 syncpoint_value; __u32 sync_fd; -- cgit v1.2.2 From bf0d9672c51320ce3066b0112228a5f0480d5603 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Thu, 22 Dec 2016 12:15:13 +0530 Subject: video: tegra: host: dla: add support for input task status - input task status notifier added as preactions and if task status of preaction matches with task status then task can proceed for execution - this adds support adding input status notifier: alloc memory for task and task descriptor, copy and pin user memory, send IOVA of status notifier user memory to engine Jira DLA-62 Change-Id: Ibfa3ea0a15dd173fc279ac58b1ab85d2c2e77d82 Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1275539 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/nvhost_nvdla_ioctl.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 8cb7bfc45..60f823a93 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -142,6 +142,20 @@ struct nvdla_fence { __u32 sem_val; }; +/** + * struct nvdla_status_notify structure for passing status notify information + * + * @handle handle to buffer allocated in userspace + * @offset offset in buffer + * @status status + * + */ +struct nvdla_status_notify { + __u32 handle; + __u32 offset; + __u32 status; +}; + #define NVHOST_NVDLA_IOCTL_MAGIC 'D' #define NVDLA_IOCTL_PING \ -- cgit v1.2.2 From 5a0dfce1b2803937fe6f780fbe6ad1f99ed5bfba Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Thu, 29 Dec 2016 16:43:56 +0530 Subject: video: tegra: host: dla: add queue operations cmd - define and add ioctl to set queue operations like, suspend and resume. - on validating user argument, pass command to engine to suspend and resume. - on receiving this command, firmware just update queue status as sent and doesn't interrupt ongoing task or queue work. Jira DLA-218 Change-Id: I13f5d8822d920961277884c64534daaf64d812be Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1278192 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Prashant Gaikwad GVS: Gerrit_Virtual_Submit --- include/linux/nvhost_nvdla_ioctl.h | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 60f823a93..02926b1fd 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -3,7 +3,7 @@ * * Tegra NvDLA Driver * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -28,6 +28,18 @@ #define __user #endif +/** + * struct nvdla_queue_stat_args strcture + * + * @status queue status flags + * + */ +struct nvdla_queue_status_args { +#define NVDLA_QUEUE_FLAGS_SUSPEND (1 << 0) +#define NVDLA_QUEUE_FLAGS_RESUME (1 << 1) + __u64 status; +}; + /** * struct nvdla_ping_args structure for ping data * @@ -166,8 +178,10 @@ struct nvdla_status_notify { _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 3, struct nvdla_pin_unpin_args) #define NVDLA_IOCTL_SUBMIT \ _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 4, struct nvdla_submit_args) +#define NVDLA_IOCTL_SET_QUEUE_STATUS \ + _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 5, struct nvdla_queue_status_args) #define NVDLA_IOCTL_LAST \ - _IOC_NR(NVDLA_IOCTL_SUBMIT) + _IOC_NR(NVDLA_IOCTL_SET_QUEUE_STATUS) #define NVDLA_IOCTL_MAX_ARG_SIZE \ sizeof(struct nvdla_pin_unpin_args) -- cgit v1.2.2 From ce5b38eb1218f3dd6d4275fc704cbf256af8d159 Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Mon, 2 Jan 2017 11:37:23 +0200 Subject: video: tegra: host: Add device data for NVENC1 Add the device data structure and required class ID and MLOCK ID defines for NVENC1. Jira HOSTX-158 Signed-off-by: Mikko Perttunen Change-Id: Icbd88c93557fe4a34d377a1119f36efbf84e1dca Reviewed-on: http://git-master/r/1287441 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/nvhost_ioctl_t194.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/linux/nvhost_ioctl_t194.h (limited to 'include/linux') diff --git a/include/linux/nvhost_ioctl_t194.h b/include/linux/nvhost_ioctl_t194.h new file mode 100644 index 000000000..0b7ee446f --- /dev/null +++ b/include/linux/nvhost_ioctl_t194.h @@ -0,0 +1,30 @@ +/* + * include/linux/nvhost_ioctl_t194.h + * + * Tegra graphics host driver + * + * Copyright (c) 2017, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __LINUX_NVHOST_IOCTL_T194_H +#define __LINUX_NVHOST_IOCTL_T194_H + +enum nvhost_module_id_t194 { + NVHOST_MODULE_NVENC1 = 12, +}; + +#endif -- cgit v1.2.2 From 616b709f02dd0cda47ae0ba02b1b3eb0ffb1e389 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Tue, 24 Jan 2017 15:42:49 +0530 Subject: video: tegra: host: dla: remove updating user bufffer with IOVA This patch addresses two fixes: [1] Removes updating user buffers with IOVA. - In address translation of address list of a tasks, handle and offset were replaced with actual IOVA into user buffer and same buffer was shared with engine. This approach is error prone. - To fix this issue, kernel keeps IOVA list and shares with engine. - In task submit, mem_handle list from user and updated in kernel copy of task. - and while pinning user buffers, engine shared list updated with actual dma address retrieved from submit pin call. [2] Remove dynamic allocation required in address translation - Required memory of 'kernel copy address list' and 'engine shared address list' both allocated from queue memory pool. - and assigned and released along with task data. DLA-286 Change-Id: I4d5a322adaff25e6e587d3305847540757850c77 Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1293124 Reviewed-by: Prashant Gaikwad GVS: Gerrit_Virtual_Submit --- include/linux/nvhost_nvdla_ioctl.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 02926b1fd..56044c85f 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -119,6 +119,8 @@ struct nvdla_ioctl_submit_task { __u8 num_postfences; __u8 num_input_task_status; __u8 num_output_task_status; +#define NVDLA_MAX_BUFFERS_PER_TASK (256) + __u32 num_addresses; __u16 flags; __u16 reserved; @@ -127,9 +129,7 @@ struct nvdla_ioctl_submit_task { __u64 input_task_status; __u64 output_task_status; - - __u32 num_addresses; - struct nvdla_mem_handle address_list; + __u64 address_list; }; /** -- cgit v1.2.2 From aa9280900f4b3148f807c3f88d21144a655d2f5d Mon Sep 17 00:00:00 2001 From: Mikko Perttunen Date: Wed, 8 Feb 2017 16:55:31 +0200 Subject: video: tegra: host: Add device data for NVDEC1 Add the device data structure and required class ID and MLOCK ID defines for NVDEC1. Jira HOSTX-177 Change-Id: Ib3676ac02e08157d2c88424394810a5dd97400b6 Signed-off-by: Mikko Perttunen Reviewed-on: http://git-master/r/1301453 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/nvhost_ioctl_t194.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include/linux') diff --git a/include/linux/nvhost_ioctl_t194.h b/include/linux/nvhost_ioctl_t194.h index 0b7ee446f..6606c84dd 100644 --- a/include/linux/nvhost_ioctl_t194.h +++ b/include/linux/nvhost_ioctl_t194.h @@ -25,6 +25,7 @@ enum nvhost_module_id_t194 { NVHOST_MODULE_NVENC1 = 12, + NVHOST_MODULE_NVDEC1 = 13, }; #endif -- cgit v1.2.2 From ddcfffcf6a354492fccda77f75ad51667f661a40 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Wed, 4 Jan 2017 16:44:39 -0800 Subject: t19x: mce: add mce driver This patch adds the initial driver for sw interface with the mts/mce in t19x. The driver provides api's and debugfs nodes for interaction with the mts/mce. JIRA TPM-1062 Change-Id: I4a682457a8e28e9b8db2a6a370a756f0d0524830 Signed-off-by: Krishna Sitaraman Reviewed-on: http://git-master/r/1280452 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt --- include/linux/t19x_mce.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 include/linux/t19x_mce.h (limited to 'include/linux') diff --git a/include/linux/t19x_mce.h b/include/linux/t19x_mce.h new file mode 100644 index 000000000..fcd611d94 --- /dev/null +++ b/include/linux/t19x_mce.h @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _LINUX_TEGRA_MCE_H +#define _LINUX_TEGRA_MCE_H + +#define NVG_STAT_MAX_ENTRIES 5 + +int t19x_mce_enter_cstate(u32 state, u32 wake_time); +int t19x_mce_update_cstate_info(u32 cluster, u32 ccplex, + u32 system, u8 force, u32 wake_mask, bool valid); +int t19x_mce_update_crossover_time(u32 type, u32 time); +int t19x_mce_read_cstate_stats(u32 state, u32 *stats); +int t19x_mce_write_cstate_stats(u32 state, u32 stats); +int t19x_mce_is_sc7_allowed(u32 state, u32 wake, u32 *allowed); +int t19x_mce_online_core(int cpu); +int t19x_mce_cc3_ctrl(u32 freq, u32 volt, u8 enable); +int t19x_mce_echo_data(u32 data, int *matched); +int t19x_mce_read_versions(u32 *major, u32 *minor); +int t19x_mce_enum_features(u64 *features); + +#endif -- cgit v1.2.2 From e8b83ca0aeac0d3a0365a69325cc7746fdfa4c62 Mon Sep 17 00:00:00 2001 From: Rohit Khanna Date: Fri, 27 Jan 2017 15:10:12 -0800 Subject: tegra: T194 cpu macro Add a macro to detect if a CPU core is Carmel or not. Bug 1814444 Bug 1827294 Change-Id: I5797f80ff990ffbbb59342a11f68ed22ea2b184c Signed-off-by: Rohit Khanna Reviewed-on: http://git-master/r/1295512 Reviewed-by: Krishna Sitaraman Tested-by: Krishna Sitaraman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt --- include/linux/platform/tegra/tegra-cpu.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 include/linux/platform/tegra/tegra-cpu.h (limited to 'include/linux') diff --git a/include/linux/platform/tegra/tegra-cpu.h b/include/linux/platform/tegra/tegra-cpu.h new file mode 100644 index 000000000..a85c4ab9a --- /dev/null +++ b/include/linux/platform/tegra/tegra-cpu.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#define MIDR_CPU_MASK 0xFF0FFFF0 +#define MIDR_CPU_CARMEL 0x4E0F0040 + +static inline u8 tegra_is_cpu_carmel(u8 cpu) +{ + struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, cpu); + return ((cpuinfo->reg_midr & MIDR_CPU_MASK) == MIDR_CPU_CARMEL); +} -- cgit v1.2.2 From 4685489ab40c27aa5088eb00be3ca27a675374c9 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Wed, 1 Feb 2017 17:45:50 -0800 Subject: t194: mce: Add nvg header file This patch adds the initial nvg header file for use by kernel. The header contains information for communication with the mce in ccplex through nvg interface. JIRA TPM-1062 Change-Id: Ib14685ab1a051e883f6f8183a92cbf48d545f6c1 Signed-off-by: Krishna Sitaraman Reviewed-on: http://git-master/r/1297644 GVS: Gerrit_Virtual_Submit Reviewed-by: svccoveritychecker Reviewed-by: Alexander Van Brunt --- include/linux/t194_nvg.h | 215 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 215 insertions(+) create mode 100644 include/linux/t194_nvg.h (limited to 'include/linux') diff --git a/include/linux/t194_nvg.h b/include/linux/t194_nvg.h new file mode 100644 index 000000000..32fae953d --- /dev/null +++ b/include/linux/t194_nvg.h @@ -0,0 +1,215 @@ +#ifndef T194_NVG_H +#define T194_NVG_H + +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/** + * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). + * Official documentation for this interface is included as part + * of the T194 TRM. + */ + +enum { + TEGRA_NVG_VERSION_MAJOR = 6, + TEGRA_NVG_VERSION_MINOR = 0, +}; + +typedef enum { + TEGRA_NVG_CHANNEL_VERSION = 0, + TEGRA_NVG_CHANNEL_POWER_PERF = 1, + TEGRA_NVG_CHANNEL_POWER_MODES = 2, + TEGRA_NVG_CHANNEL_WAKE_TIME = 3, + TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, + TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, + TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, + /* Value 7 reserved */ + TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, + /* Value 9 reserved */ + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, + TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, + /* Values 12-42 reserved */ + TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, + TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, + TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51, + /* 52 FREQ FEEDBACK */ + TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, + TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_LAST_INDEX, +} tegra_nvg_channel_id_t; + +typedef enum { + /* Value 0 reserved */ + NVG_STAT_QUERY_SC7_ENTRIES = 1, + /* Values 2-5 reserved */ + NVG_STAT_QUERY_CC6_ENTRIES = 6, + NVG_STAT_QUERY_CG7_ENTRIES = 7, + /* Values 8-9 reserved */ + NVG_STAT_QUERY_C6_ENTRIES = 10, + /* Values 11-13 reserved */ + NVG_STAT_QUERY_C7_ENTRIES = 14, + /* Values 15-31 reserved */ + NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, + NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, + NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, + NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51, + NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56, +} tegra_nvg_stat_query_t; + +typedef enum { + TEGRA_NVG_CORE_C0 = 0, + TEGRA_NVG_CORE_C1 = 1, + TEGRA_NVG_CORE_C6 = 6, + TEGRA_NVG_CORE_C7 = 7, + TEGRA_NVG_CORE_WARMRSTREQ = 8, +} tegra_nvg_core_sleep_state_t; + +typedef enum { + TEGRA_NVG_CLUSTER_CC0 = 0, + TEGRA_NVG_CLUSTER_CC6 = 6, +} tegra_nvg_cluster_sleep_state_t; + +typedef enum { + TEGRA_NVG_CCPLEX_CG0 = 0, + TEGRA_NVG_CCPLEX_CG7 = 1, +} tegra_nvg_cluster_group_sleep_state_t; + +typedef enum { + TEGRA_NVG_SYSTEM_SC0 = 0, + TEGRA_NVG_SYSTEM_SC7 = 7, + TEGRA_NVG_SYSTEM_SC8 = 8, +} tegra_nvg_system_sleep_state_t; + +/* ------------------- */ +/* NVG Data subformats */ +/* ------------------- */ + +typedef union { + uint64_t flat; + struct nvg_version_channel_t { + uint64_t minor_version : 32; + uint64_t major_version : 32; + } bits; +} nvg_version_data_t; + +typedef union nvg_channel_1_data_u { + uint64_t flat; + struct nvg_channel_1_data_s { + uint64_t perf_per_watt_mode : 1; + uint64_t reserved_63_1 : 63; + } bits; +} nvg_channel_1_data_t; + +typedef union nvg_channel_2_data_u { + uint64_t flat; + struct nvg_channel_2_data_s { + uint64_t reserved_1_0 : 2; + uint64_t battery_saver_mode : 1; + uint64_t reserved_63_3 : 61; + } bits; +} nvg_channel_2_data_t; + +typedef union { + uint64_t flat; + struct nvg_wake_time_channel_t { + uint64_t wake_time : 32; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_wake_time_channel_t; + +typedef union { + uint64_t flat; + struct nvg_cstate_info_channel_t { + uint64_t cluster_state : 3; + uint64_t reserved_6_3 : 4; + uint64_t update_cluster : 1; + uint64_t cg_cstate : 3; + uint64_t reserved_14_11 : 4; + uint64_t update_cg : 1; + uint64_t system_cstate : 4; + uint64_t reserved_22_20 : 3; + uint64_t update_system : 1; + uint64_t reserved_30_24 : 7; + uint64_t update_wake_mask : 1; + uint64_t wake_mask : 32; + } bits; +} nvg_cstate_info_channel_t; + +typedef union { + uint64_t flat; + struct nvg_lower_bound_channel_t { + uint64_t crossover_value : 32; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_lower_bound_channel_t; + + +typedef union { + uint64_t flat; + struct nvg_cstate_stat_query_channel_t { + uint64_t unit_id : 4; + uint64_t reserved_15_4 : 12; + uint64_t stat_id : 16; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_cstate_stat_query_channel_t; + +typedef union { + uint64_t flat; + struct nvg_is_sc7_allowed_channel_t { + uint64_t is_sc7_allowed : 1; + uint64_t reserved_63_32 : 63; + } bits; +} nvg_is_sc7_allowed_channel_t; + + +typedef union { + uint64_t flat; + struct nvg_core_online_channel_t { + uint64_t core_id : 4; + uint64_t reserved_63_4 : 60; + } bits; +} nvg_core_online_channel_t; + + +typedef union { + uint64_t flat; + struct nvg_cc3_control_channel_t { + uint64_t freq_req : 8; + uint64_t reserved_30_8 : 23; + uint64_t enable : 1; + uint64_t reserved_63_32 : 32; + } bits; +} nvg_cc3_control_channel_t; + +typedef union { + uint64_t flat; + struct nvg_update_gsc_channel_t { + uint64_t gsc_enum : 16; + uint64_t reserved_63_16 : 48; + } bits; +} nvg_update_gsc_channel_t; + +typedef union { + uint64_t flat; + struct nvg_cache_inval_channel_t { + uint64_t cache_clean : 1; + uint64_t cache_clean_inval : 1; + uint64_t cache_clean_inval_tr : 1; + uint64_t reserved_63_3 : 61; + } bits; +} nvg_cache_inval_channel_t; + +#endif /* T194_NVG_H */ -- cgit v1.2.2 From 301048cb839a1310e65240ddb97f94163c5b5459 Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Thu, 23 Mar 2017 08:43:34 +0530 Subject: video: tegra: host: dla: add IOCTL to send fw version and q status - Add IOCTL to send DLA firmware version. - If DLA engine is not powered on before IOCTL call, poweron engine and send version. - Add IOCTL to send queue status, like current fence Jira DLA-316 Jira DLA-336 Change-Id: I2367446f99809253c4b765b751d66712f969442c Signed-off-by: Shridhar Rasal Reviewed-on: http://git-master/r/1326511 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Prashant Gaikwad Reviewed-by: Amit Sharma (SW-TEGRA) --- include/linux/nvhost_nvdla_ioctl.h | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index 56044c85f..aa5fe61de 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -85,6 +85,28 @@ struct nvdla_submit_args { __u32 version; }; +/** + * struct nvdla_get_fw_ver_args strcture + * + * @version Firmware version + * + */ +struct nvdla_get_fw_ver_args { + __u32 version; +}; + +/** + * struct nvdla_get_q_status_args strcture + * + * @id queue id + * @fence fence assigned to queue + * + */ +struct nvdla_get_q_status_args { + __u32 id; + __u64 fence; +}; + /** * struct nvdla_mem_handle structure for memory handles * @@ -180,8 +202,12 @@ struct nvdla_status_notify { _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 4, struct nvdla_submit_args) #define NVDLA_IOCTL_SET_QUEUE_STATUS \ _IOW(NVHOST_NVDLA_IOCTL_MAGIC, 5, struct nvdla_queue_status_args) +#define NVDLA_IOCTL_GET_FIRMWARE_VERSION \ + _IOWR(NVHOST_NVDLA_IOCTL_MAGIC, 6, struct nvdla_get_fw_ver_args) +#define NVDLA_IOCTL_GET_QUEUE_STATUS \ + _IOWR(NVHOST_NVDLA_IOCTL_MAGIC, 7, struct nvdla_get_q_status_args) #define NVDLA_IOCTL_LAST \ - _IOC_NR(NVDLA_IOCTL_SET_QUEUE_STATUS) + _IOC_NR(NVDLA_IOCTL_GET_QUEUE_STATUS) #define NVDLA_IOCTL_MAX_ARG_SIZE \ sizeof(struct nvdla_pin_unpin_args) -- cgit v1.2.2 From 47f00b09b57812008c985ab99803d092c725ad50 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 20 Feb 2017 20:30:27 +0530 Subject: iommu: arm-smmu: add support for bl format -Set 39th bit of pte when IOMMU_USE_BL_FORMAT specified in alloc_pte. -Provide override functions for dma handle marshaling and qualifying ioprot with 39th bit set when IOMMU_USE_BL_FORMAT specified and chip is t19x. Bug 1866465 Change-Id: Id35708364ba6db411d0c819d4ad7a8beeec7a432 Signed-off-by: Pritesh Raithatha Reviewed-on: http://git-master/r/1460454 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/dma-override.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) create mode 100644 include/linux/dma-override.h (limited to 'include/linux') diff --git a/include/linux/dma-override.h b/include/linux/dma-override.h new file mode 100644 index 000000000..63e070874 --- /dev/null +++ b/include/linux/dma-override.h @@ -0,0 +1,16 @@ +#ifndef _LINUX_DMA_MAPPING_OVERRIDE_H +#define _LINUX_DMA_MAPPING_OVERRIDE_H + +#include +#include +#include + +#define IOMMU_USE_BL_FORMAT (1 << 5) + +void dma_qualify_ioprot(enum dma_data_direction dir, unsigned long *ioprot); + +void dma_marshal_handle(enum dma_data_direction dir, dma_addr_t *handle); + +void dma_unmarshal_handle(enum dma_data_direction dir, dma_addr_t *handle); + +#endif -- cgit v1.2.2 From 45e5983944477dbb47e6a7cbf8f0a56833cf33bc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 12 May 2017 12:35:40 +0530 Subject: video: tegra: host: move exported APIs to public header Exported APIs like below are defined in private header file nvhost_syncpt_unit_interface.h nvhost_syncpt_unit_interface_get_aperture() nvhost_syncpt_unit_interface_get_byte_offset() This causes linking problems if these functions are needed by some other driver outside nvhost Hence move these exported APIs into a new public header in include/linux/nvhost_t194.h Change-Id: Ib70177da71c2cc6aee1c6da2668b0a92ea01ccf7 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1480588 Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom --- include/linux/nvhost_t194.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/linux/nvhost_t194.h (limited to 'include/linux') diff --git a/include/linux/nvhost_t194.h b/include/linux/nvhost_t194.h new file mode 100644 index 000000000..f7b7dbdeb --- /dev/null +++ b/include/linux/nvhost_t194.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2017, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __LINUX_NVHOST_T194_H__ +#define __LINUX_NVHOST_T194_H__ + +int nvhost_syncpt_unit_interface_get_aperture( + struct platform_device *host_pdev, + phys_addr_t *base, + size_t *size); + +u32 nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); + +#endif /* __LINUX_NVHOST_T194_H__ */ -- cgit v1.2.2 From 21d2d79170398113d8eb63abb3e931e322cf035d Mon Sep 17 00:00:00 2001 From: Shridhar Rasal Date: Mon, 24 Apr 2017 13:56:20 +0530 Subject: video: tegra: host: nvdla: add task timeout support - pass task timeout parameter from user to engine for book keeping of task runtime - as stack framesize crossing limit of 2048 bytes, reduce number of maximum task can be submitted in one go. Jira DLA-374 Bug 200302518 Change-Id: I99d3706d9d80ac0201529d68c0a959cdd22a1488 Signed-off-by: Shridhar Rasal Signed-off-by: Prashant Gaikwad Reviewed-on: http://git-master/r/1468355 Reviewed-by: Amit Sharma (SW-TEGRA) Reviewed-by: Inamdar Sharif Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- include/linux/nvhost_nvdla_ioctl.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/nvhost_nvdla_ioctl.h b/include/linux/nvhost_nvdla_ioctl.h index aa5fe61de..60893e813 100644 --- a/include/linux/nvhost_nvdla_ioctl.h +++ b/include/linux/nvhost_nvdla_ioctl.h @@ -79,7 +79,7 @@ struct nvdla_pin_unpin_args { struct nvdla_submit_args { __u64 tasks; __u16 num_tasks; -#define MAX_TASKS_PER_SUBMIT 32 +#define MAX_TASKS_PER_SUBMIT 24 #define NVDLA_SUBMIT_FLAGS_ATOMIC (1 << 0) __u16 flags; __u32 version; @@ -134,6 +134,7 @@ struct nvdla_mem_handle { * @output_task_status pointer to output task status struct table * @num_addresses total number of addressed passed in structure * @address_list pointer to address list + * @timeout task timeout * */ struct nvdla_ioctl_submit_task { @@ -152,6 +153,7 @@ struct nvdla_ioctl_submit_task { __u64 input_task_status; __u64 output_task_status; __u64 address_list; + __u64 timeout; }; /** -- cgit v1.2.2 From fe14354d56c1f95a76d7e104d513b451178b6546 Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Wed, 17 May 2017 16:08:15 +0530 Subject: iommu: arm-smmu: remove bl format support Hw team confirm that 39-bit needs to set before SMMU, that is in iova address and client can do that directly. No changes required from SMMU/DMA side. Removing the support that we added. Bug 1866465 Change-Id: Ifcde76c50e0086ce65c94757681eeac534e3460a Signed-off-by: Pritesh Raithatha Reviewed-on: http://git-master/r/1483859 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy --- include/linux/dma-override.h | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 include/linux/dma-override.h (limited to 'include/linux') diff --git a/include/linux/dma-override.h b/include/linux/dma-override.h deleted file mode 100644 index 63e070874..000000000 --- a/include/linux/dma-override.h +++ /dev/null @@ -1,16 +0,0 @@ -#ifndef _LINUX_DMA_MAPPING_OVERRIDE_H -#define _LINUX_DMA_MAPPING_OVERRIDE_H - -#include -#include -#include - -#define IOMMU_USE_BL_FORMAT (1 << 5) - -void dma_qualify_ioprot(enum dma_data_direction dir, unsigned long *ioprot); - -void dma_marshal_handle(enum dma_data_direction dir, dma_addr_t *handle); - -void dma_unmarshal_handle(enum dma_data_direction dir, dma_addr_t *handle); - -#endif -- cgit v1.2.2 From c43a867573f81e1ce8f92a1a66e3a9da1d1aabe9 Mon Sep 17 00:00:00 2001 From: Krishna Reddy Date: Mon, 8 May 2017 15:17:24 -0700 Subject: platform: tegra: mcerr: add mcerror handling for t19x TMM-31 Change-Id: I68b3e2009704e0f890cff9f8ac08717aa1398b76 Signed-off-by: Krishna Reddy Reviewed-on: http://git-master/r/1477689 Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit --- include/linux/platform/tegra/mc-regs-t19x.h | 2071 +++++++++++++++++++++++++++ 1 file changed, 2071 insertions(+) create mode 100644 include/linux/platform/tegra/mc-regs-t19x.h (limited to 'include/linux') diff --git a/include/linux/platform/tegra/mc-regs-t19x.h b/include/linux/platform/tegra/mc-regs-t19x.h new file mode 100644 index 000000000..17ad19801 --- /dev/null +++ b/include/linux/platform/tegra/mc-regs-t19x.h @@ -0,0 +1,2071 @@ +/* + * Copyright (c) 2017, NVIDIA Corporation. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __MACH_TEGRA_MC_REGS_T19X_H__ +#define __MACH_TEGRA_MC_REGS_T19X_H__ + +/* Auto generated. Do not edit. */ +#define MC_MCF_ORSPX_RDRSP 0x8004 +#define MC_MCF_ORSPX_WRRSP 0x8008 +#define MC_MCF_IRSPX_RDRSP_OPT 0x800c +#define MC_MCF_ORSPX_CLKEN_OVERRIDE 0x8010 +#define MC_MCF_IRSPX_CLKEN_OVERRIDE 0x8014 +#define MC_MCF_ORSPX_PM_FIFO_SRC_MATCH 0x8018 +#define MC_MCF_ORSPX_PM_FIFO_CONFIG 0x801c +#define MC_MCF_IRSPX_PM_FIFO_SRC_MATCH 0x8020 +#define MC_MCF_IREQX_VCARB_CONFIG 0x8100 +#define MC_MCF_OREQX_VCARB_CONFIG 0x8104 +#define MC_MCF_OREQX_LLARB_CONFIG 0x8108 +#define MC_MCF_IREQX_SRC_WEIGHT_0 0x810c +#define MC_MCF_IREQX_SRC_WEIGHT_1 0x8110 +#define MC_MCF_IREQX_CLKEN_OVERRIDE 0x8114 +#define MC_MCF_OREQX_CLKEN_OVERRIDE 0x8118 +#define MC_MCF_IREQX_PM_FIFO_SRC_MATCH0 0x8130 +#define MC_MCF_IREQX_PM_FIFO_SRC_MATCH1 0x8134 +#define MC_MCF_IREQX_PM_FIFO_SUM_MSK 0x8138 +#define MC_MCF_IREQX_PM_FIFO_SRC_MISC 0x813c +#define MC_MCF_OREQX_PM_FIFO_SRC_MATCH0 0x8140 +#define MC_MCF_OREQX_PM_FIFO_SRC_MATCH1 0x8144 +#define MC_MCF_OREQX_PM_FIFO_SUM_MSK 0x8148 +#define MC_MCF_OREQX_PM_FIFO_SRC_MISC 0x814c +#define MC_MCF_IREQX_HUB_FIFO_NISO 0x8200 +#define MC_MCF_IREQX_HUB_FIFO_SISO 0x8204 +#define MC_MCF_IREQX_HUB_FIFO_ISO 0x8208 +#define MC_MCF_IREQX_HUB_FIFO_TRANS_DONE 0x820c +#define MC_MCF_IREQX_HUB_FIFO_ORD_1 0x8214 +#define MC_MCF_IREQX_HUB_FIFO_ORD_2 0x8218 +#define MC_MCF_IREQX_HUB_FIFO_ORD_3 0x821c +#define MC_MCF_IREQX_HUB_FIFO_SHARED 0x8220 +#define MC_MCF_IREQX_NVL_FIFO_NISO 0x8224 +#define MC_MCF_IREQX_NVL_FIFO_SISO 0x8228 +#define MC_MCF_IREQX_NVL_FIFO_ISO 0x822c +#define MC_MCF_IREQX_NVL_FIFO_TRANS_DONE 0x8230 +#define MC_MCF_IREQX_NVL_FIFO_ORD_1 0x8238 +#define MC_MCF_IREQX_NVL_FIFO_ORD_2 0x823c +#define MC_MCF_IREQX_NVL_FIFO_ORD_3 0x8240 +#define MC_MCF_IREQX_NVL_FIFO_SHARED 0x8244 +#define MC_MCF_OREQX_MCF_FIFO_NISO 0x8248 +#define MC_MCF_OREQX_MCF_FIFO_SISO 0x824c +#define MC_MCF_OREQX_MCF_FIFO_ISO 0x8250 +#define MC_MCF_OREQX_MCF_FIFO_CPU_LL 0x8254 +#define MC_MCF_OREQX_MCF_FIFO_NISO_REMOTE 0x8258 +#define MC_MCF_OREQX_MCF_FIFO_SHARED 0x825c +#define MC_MCF_OREQX_SCF_FIFO_NISO 0x8260 +#define MC_MCF_OREQX_SCF_FIFO_SISO 0x8264 +#define MC_MCF_OREQX_SCF_FIFO_ISO 0x8268 +#define MC_MCF_OREQX_SCF_FIFO_CPU_LL 0x826c +#define MC_MCF_OREQX_SCF_FIFO_NISO_REMOTE 0x8270 +#define MC_MCF_OREQX_SCF_FIFO_SHARED 0x8274 +#define MC_MCF_OREQX_SCF_LLFIFO_CPU_LL 0x8278 +#define MC_MCF_SLICE_CFG 0x8300 +#define MC_MCF_SLICE_FL_NISO_LIMIT 0x8304 +#define MC_MCF_SLICE_FL_SISO_LIMIT 0x8308 +#define MC_MCF_SLICE_FL_ISO_LIMIT 0x830c +#define MC_MCF_SLICE_FL_TRANSDONE_LIMIT 0x8310 +#define MC_MCF_SLICE_FL_NISO_REMOTE_LIMIT 0x8314 +#define MC_MCF_SLICE_FL_ORD1_LIMIT 0x8318 +#define MC_MCF_SLICE_FL_ORD2_LIMIT 0x831c +#define MC_MCF_SLICE_FL_ORD3_LIMIT 0x8320 +#define MC_MCF_SLICE_CLKEN_OVERRIDE 0x8324 +#define MC_MSS_SYSRAM_INIT 0x8c00 +#define MC_MSS_SYSRAM_CLKEN_OVERRIDE 0x8c04 +#define MC_MSS_SBS_ASYNC 0x8f00 +#define MC_MSS_SBS_ARB 0x8f04 +#define MC_MSS_SBS_INTSTATUS 0x8f08 +#define MC_MSS_SBS_INTMASK 0x8f0c +#define MC_MSS_SBS_CLKEN_OVERRIDE 0x8f10 +#define MC_MSS_SBS_VC_LIMIT 0x8f14 +#define MC_REGIF_CONFIG 0xf80 +#define MC_REGIF_CONFIG_1 0xf8c +#define MC_REGIF_CONFIG_2 0x3700 +#define MC_REGIF_BROADCAST 0xf84 +#define MC_REGIF_BROADCAST_1 0xf88 +#define MC_REGIF_BROADCAST_2 0x3704 +#define MC_REGIF_UNICAST0 0xf90 +#define MC_REGIF_UNICAST0_1 0x1134 +#define MC_REGIF_UNICAST0_2 0x370c +#define MC_REGIF_UNICAST1 0xf94 +#define MC_REGIF_UNICAST1_1 0x1140 +#define MC_REGIF_UNICAST1_2 0x3710 +#define MC_REGIF_UNICAST2 0xf98 +#define MC_REGIF_UNICAST2_1 0x1144 +#define MC_REGIF_UNICAST2_2 0x3714 +#define MC_REGIF_UNICAST3 0xf9c +#define MC_REGIF_UNICAST3_1 0x1148 +#define MC_REGIF_UNICAST3_2 0x3718 +#define MC_REGIF_UNICAST4 0x1164 +#define MC_REGIF_UNICAST4_1 0x114c +#define MC_REGIF_UNICAST4_2 0x371c +#define MC_REGIF_UNICAST5 0x1168 +#define MC_REGIF_UNICAST5_1 0x1150 +#define MC_REGIF_UNICAST5_2 0x3720 +#define MC_REGIF_UNICAST6 0x116c +#define MC_REGIF_UNICAST6_1 0x1154 +#define MC_REGIF_UNICAST6_2 0x3724 +#define MC_REGIF_UNICAST7 0x1170 +#define MC_REGIF_UNICAST7_1 0x1160 +#define MC_REGIF_UNICAST7_2 0x3728 +#define MC_REGIF_UNICAST8 0x372c +#define MC_REGIF_UNICAST8_1 0x374c +#define MC_REGIF_UNICAST8_2 0x376c +#define MC_REGIF_UNICAST9 0x3730 +#define MC_REGIF_UNICAST9_1 0x3750 +#define MC_REGIF_UNICAST9_2 0x3770 +#define MC_REGIF_UNICAST10 0x3734 +#define MC_REGIF_UNICAST10_1 0x3754 +#define MC_REGIF_UNICAST10_2 0x3774 +#define MC_REGIF_UNICAST11 0x3738 +#define MC_REGIF_UNICAST11_1 0x3758 +#define MC_REGIF_UNICAST11_2 0x3778 +#define MC_REGIF_UNICAST12 0x373c +#define MC_REGIF_UNICAST12_1 0x375c +#define MC_REGIF_UNICAST12_2 0x377c +#define MC_REGIF_UNICAST13 0x3740 +#define MC_REGIF_UNICAST13_1 0x3760 +#define MC_REGIF_UNICAST13_2 0x3780 +#define MC_REGIF_UNICAST14 0x3744 +#define MC_REGIF_UNICAST14_1 0x3764 +#define MC_REGIF_UNICAST14_2 0x3784 +#define MC_REGIF_UNICAST15 0x3748 +#define MC_REGIF_UNICAST15_1 0x3768 +#define MC_REGIF_UNICAST15_2 0x3788 +#define MC_INTSTATUS 0x0 +#define MC_INTMASK 0x4 +#define MC_INTPRIORITY 0xec4 +#define MC_HUBC_INTSTATUS 0xf2c +#define MC_HUB_INTMASK 0xf50 +#define MC_HUB_INTPRIORITY 0xf54 +#define MC_HUB_INTSTATUS 0xf58 +#define MC_GLOBAL_INTSTATUS 0xf24 +#define MC_GLOBAL_CRITICAL_INTSTATUS 0xf28 +#define MC_GLOBAL_INTSTATUS_1 0x37e0 +#define MC_GLOBAL_CRITICAL_INTSTATUS_1 0x37e4 +#define MC_ERR_STATUS 0x8 +#define MC_ERR_ADR 0xc +#define MC_ERR_ADR_HI 0x11fc +#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0 +#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4 +#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8 +#define MC_PCFIFO_CLIENT_CONFIG3 0xddc +#define MC_PCFIFO_CLIENT_CONFIG4 0xde0 +#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4 +#define MC_PCFIFO_CLIENT_CONFIG6 0xb90 +#define MC_PCFIFO_CLIENT_CONFIG7 0xacc +#define MC_EMEM_CFG 0x50 +#define MC_EMEM_ADR_CFG 0x54 +#define MC_EMEM_ADR_CFG_DEV0 0x58 +#define MC_EMEM_ADR_CFG_DEV1 0x5c +#define MC_EMEM_ADR_CFG_CHANNEL_ENABLE 0xdf8 +#define MC_EMEM_ADR_CFG_CHANNEL_MASK 0x60 +#define MC_EMEM_ADR_CFG_CHANNEL_MASK_1 0xdfc +#define MC_EMEM_ADR_CFG_CHANNEL_MASK_2 0xdf4 +#define MC_EMEM_ADR_CFG_CHANNEL_MASK_3 0xdf0 +#define MC_EMEM_ADR_CFG_BANK_MASK_0 0x64 +#define MC_EMEM_ADR_CFG_BANK_MASK_1 0x68 +#define MC_EMEM_ADR_CFG_BANK_MASK_2 0x6c +#define MC_SECURITY_CFG0 0x70 +#define MC_SECURITY_CFG1 0x74 +#define MC_SECURITY_CFG_REG_CTRL 0x154 +#define MC_SECURITY_CFG3 0x9bc +#define MC_SECURITY_RSV 0x7c +#define MC_EMEM_ARB_CFG 0x90 +#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 +#define MC_EMEM_ARB_TIMING_RCD 0x98 +#define MC_EMEM_ARB_TIMING_RP 0x9c +#define MC_EMEM_ARB_TIMING_RC 0xa0 +#define MC_EMEM_ARB_TIMING_RAS 0xa4 +#define MC_EMEM_ARB_TIMING_FAW 0xa8 +#define MC_EMEM_ARB_TIMING_RRD 0xac +#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 +#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 +#define MC_EMEM_ARB_TIMING_R2R 0xb8 +#define MC_EMEM_ARB_TIMING_W2W 0xbc +#define MC_EMEM_ARB_TIMING_R2W 0xc0 +#define MC_EMEM_ARB_TIMING_W2R 0xc4 +#define MC_EMEM_ARB_TIMING_RFCPB 0x6c0 +#define MC_EMEM_ARB_TIMING_CCDMW 0x6c4 +#define MC_EMEM_ARB_TIMING_PBR2PBR 0x6c8 +#define MC_EMEM_ARB_TIMING_PDEX 0x6cc +#define MC_EMEM_ARB_TIMING_SREX 0x6d0 +#define MC_EMEM_ARB_REFPB_HP_CTRL 0x6f0 +#define MC_EMEM_ARB_REFPB_BANK_CTRL 0x6f4 +#define MC_EMEM_ARB_DA_TURNS 0xd0 +#define MC_EMEM_ARB_DA_COVERS 0xd4 +#define MC_EMEM_ARB_DA_HYSTERESIS 0x9fc +#define MC_EMEM_ARB_MISC0 0xd8 +#define MC_EMEM_ARB_MISC1 0xdc +#define MC_EMEM_ARB_MISC2 0xc8 +#define MC_EMEM_ARB_MISC3 0x23c +#define MC_EMEM_ARB_MISC4 0x240 +#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 +#define MC_EMEM_ARB_RING3_THROTTLE 0xe4 +#define MC_EMEM_ARB_NISO_THROTTLE 0x6b0 +#define MC_EMEM_ARB_OVERRIDE 0xe8 +#define MC_EMEM_ARB_RSV 0xec +#define MC_CLKEN_OVERRIDE 0xf4 +#define MC_HUB_CLKEN_OVERRIDE 0xfa0 +#define MC_HUB_VCTHROTTLE_OVERRIDE 0xfa4 +#define MC_CLKEN_A1_OVERRIDE 0xcc +#define MC_TIMING_CONTROL_DBG 0xf8 +#define MC_TIMING_CONTROL 0xfc +#define MC_STAT_CONTROL 0x100 +#define MC_STAT_STATUS 0x104 +#define MC_STAT_EMC_CLOCK_LIMIT 0x108 +#define MC_STAT_EMC_CLOCK_LIMIT_MSBS 0x10c +#define MC_STAT_EMC_CLOCKS 0x110 +#define MC_STAT_EMC_CLOCKS_MSBS 0x114 +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_LO 0x118 +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_LO 0x158 +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_HI 0x11c +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_HI 0x15c +#define MC_STAT_EMC_FILTER_SET0_ADR_LIMIT_UPPER 0xa20 +#define MC_STAT_EMC_FILTER_SET1_ADR_LIMIT_UPPER 0xa24 +#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_LO 0x198 +#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_LO 0x1a8 +#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_HI 0x19c +#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_HI 0x1ac +#define MC_STAT_EMC_FILTER_SET0_VIRTUAL_ADR_LIMIT_UPPER 0xa28 +#define MC_STAT_EMC_FILTER_SET1_VIRTUAL_ADR_LIMIT_UPPER 0xa2c +#define MC_STAT_EMC_FILTER_SET0_ASID 0x1a0 +#define MC_STAT_EMC_FILTER_SET1_ASID 0x1b0 +#define MC_STAT_EMC_FILTER_SET0_SLACK_LIMIT 0x120 +#define MC_STAT_EMC_FILTER_SET1_SLACK_LIMIT 0x160 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_0 0x128 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_0 0x168 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_1 0x12c +#define MC_STAT_EMC_FILTER_SET1_CLIENT_1 0x16c +#define MC_STAT_EMC_FILTER_SET0_CLIENT_2 0x130 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_2 0x170 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_3 0x134 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_4 0xb88 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_5 0xbc4 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_6 0xac4 +#define MC_STAT_EMC_FILTER_SET0_CLIENT_7 0xac8 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_3 0x174 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_4 0xb8c +#define MC_STAT_EMC_FILTER_SET1_CLIENT_5 0xbc8 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_6 0xec8 +#define MC_STAT_EMC_FILTER_SET1_CLIENT_7 0xecc +#define MC_STAT_EMC_SET0_COUNT 0x138 +#define MC_STAT_EMC_SET0_COUNT_MSBS 0x13c +#define MC_STAT_EMC_SET1_COUNT 0x178 +#define MC_STAT_EMC_SET1_COUNT_MSBS 0x17c +#define MC_STAT_EMC_SET0_SLACK_ACCUM 0x140 +#define MC_STAT_EMC_SET0_SLACK_ACCUM_MSBS 0x144 +#define MC_STAT_EMC_SET1_SLACK_ACCUM 0x180 +#define MC_STAT_EMC_SET1_SLACK_ACCUM_MSBS 0x184 +#define MC_STAT_EMC_SET0_HISTO_COUNT 0x148 +#define MC_STAT_EMC_SET0_HISTO_COUNT_MSBS 0x14c +#define MC_STAT_EMC_SET1_HISTO_COUNT 0x188 +#define MC_STAT_EMC_SET1_HISTO_COUNT_MSBS 0x18c +#define MC_STAT_EMC_SET0_MINIMUM_SLACK_OBSERVED 0x150 +#define MC_STAT_EMC_SET1_MINIMUM_SLACK_OBSERVED 0x190 +#define MC_STAT_EMC_SET0_IDLE_CYCLE_COUNT 0x1b8 +#define MC_STAT_EMC_SET0_IDLE_CYCL_COUNT_MSBS 0x1bc +#define MC_STAT_EMC_SET1_IDLE_CYCLE_COUNT 0x1c8 +#define MC_STAT_EMC_SET1_IDLE_CYCL_COUNT_MSBS 0x1cc +#define MC_STAT_EMC_SET0_IDLE_CYCLE_PARTITION_SELECT 0x1c0 +#define MC_STAT_EMC_SET1_IDLE_CYCLE_PARTITION_SELECT 0x1d0 +#define MC_CIFLL_MISC0 0xf60 +#define MC_CIFLL_REDEADLINE0 0xf64 +#define MC_CIFLL_REDEADLINE1 0xf68 +#define MC_CIFLL_REQ_MT_FIFO_CREDITS 0xf6c +#define MC_CIFLL_WRDAT_MT_FIFO_CREDITS 0xf70 +#define MC_CLIENT_HOTRESET_CTRL 0x200 +#define MC_CLIENT_HOTRESET_CTRL_1 0x970 +#define MC_CLIENT_HOTRESET_CTRL_2 0x97c +#define MC_CLIENT_HOTRESET_STATUS 0x204 +#define MC_CLIENT_HOTRESET_STATUS_1 0x974 +#define MC_EMEM_ARB_ISOCHRONOUS_0 0x208 +#define MC_EMEM_ARB_ISOCHRONOUS_1 0x20c +#define MC_EMEM_ARB_ISOCHRONOUS_2 0x210 +#define MC_EMEM_ARB_ISOCHRONOUS_3 0x214 +#define MC_EMEM_ARB_ISOCHRONOUS_4 0xb94 +#define MC_EMEM_ARB_ISOCHRONOUS_5 0xba8 +#define MC_EMEM_ARB_ISOCHRONOUS_6 0xaac +#define MC_EMEM_ARB_ISOCHRONOUS_7 0xab0 +#define MC_EMEM_ARB_HYSTERESIS_0 0x218 +#define MC_EMEM_ARB_HYSTERESIS_1 0x21c +#define MC_EMEM_ARB_HYSTERESIS_2 0x220 +#define MC_EMEM_ARB_HYSTERESIS_3 0x224 +#define MC_EMEM_ARB_HYSTERESIS_4 0xb84 +#define MC_EMEM_ARB_HYSTERESIS_5 0xba4 +#define MC_EMEM_ARB_HYSTERESIS_6 0xef4 +#define MC_EMEM_ARB_HYSTERESIS_7 0xef8 +#define MC_EMEM_ARB_DHYSTERESIS_0 0xbb0 +#define MC_EMEM_ARB_DHYSTERESIS_1 0xbb4 +#define MC_EMEM_ARB_DHYSTERESIS_2 0xbb8 +#define MC_EMEM_ARB_DHYSTERESIS_3 0xbbc +#define MC_EMEM_ARB_DHYSTERESIS_4 0xbc0 +#define MC_EMEM_ARB_DHYSTERESIS_5 0xbf0 +#define MC_EMEM_ARB_DHYSTERESIS_6 0x1d00 +#define MC_EMEM_ARB_DHYSTERESIS_7 0x1d04 +#define MC_EMEM_ARB_DHYST_CTRL 0xbcc +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0 0xbd0 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1 0xbd4 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2 0xbd8 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3 0xbdc +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4 0xbe0 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5 0xbe4 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6 0xbe8 +#define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7 0xbec +#define MC_RESERVED_RSV 0x3fc +#define MC_UFSHCPC2_EXTRA_SNAP_LEVELS 0x4844 +#define MC_BPMPPC_EXTRA_SNAP_LEVELS 0xa60 +#define MC_PVA1XA3_EXTRA_SNAP_LEVELS 0x4818 +#define MC_FTOP_EXTRA_SNAP_LEVELS 0x2bc +#define MC_MIU4_EXTRA_SNAP_LEVELS 0x4924 +#define MC_MIU6_EXTRA_SNAP_LEVELS 0x492c +#define MC_VICPC3_EXTRA_SNAP_LEVELS 0xa80 +#define MC_ISP2PC_EXTRA_SNAP_LEVELS 0x4910 +#define MC_USBD2_EXTRA_SNAP_LEVELS 0x484c +#define MC_PVA1XB_EXTRA_SNAP_LEVELS 0x481c +#define MC_PVA0XB3_EXTRA_SNAP_LEVELS 0x4810 +#define MC_VICPC_EXTRA_SNAP_LEVELS 0xa1c +#define MC_UFSHCPC_EXTRA_SNAP_LEVELS 0xa58 +#define MC_MSEA_EXTRA_SNAP_LEVELS 0x4900 +#define MC_USBX_EXTRA_SNAP_LEVELS 0x404 +#define MC_PCIE4XA_EXTRA_SNAP_LEVELS 0x4800 +#define MC_MSE2_EXTRA_SNAP_LEVELS 0xe08 +#define MC_PVA0XA3_EXTRA_SNAP_LEVELS 0x4808 +#define MC_PCIE4X_EXTRA_SNAP_LEVELS 0x4104 +#define MC_DLA1XA2_EXTRA_SNAP_LEVELS 0x482c +#define MC_MIU3_EXTRA_SNAP_LEVELS 0x3260 +#define MC_NVD2_EXTRA_SNAP_LEVELS 0xe00 +#define MC_USBD_EXTRA_SNAP_LEVELS 0xa18 +#define MC_PVA0XB2_EXTRA_SNAP_LEVELS 0x4834 +#define MC_RCEPC_EXTRA_SNAP_LEVELS 0xe20 +#define MC_MSE_EXTRA_SNAP_LEVELS 0x40c +#define MC_AUD_EXTRA_SNAP_LEVELS 0xa10 +#define MC_DLA0XA_EXTRA_SNAP_LEVELS 0xe10 +#define MC_PCIE0X2_EXTRA_SNAP_LEVELS 0x4914 +#define MC_DLA0XA2_EXTRA_SNAP_LEVELS 0x4828 +#define MC_PCIE0XA_EXTRA_SNAP_LEVELS 0x4118 +#define MC_PCIE1X_EXTRA_SNAP_LEVELS 0x3270 +#define MC_EQOSPC_EXTRA_SNAP_LEVELS 0xa5c +#define MC_MIU7_EXTRA_SNAP_LEVELS 0x4930 +#define MC_MIU1_EXTRA_SNAP_LEVELS 0x3258 +#define MC_HDAPC_EXTRA_SNAP_LEVELS 0xa48 +#define MC_DLA0FALPC_EXTRA_SNAP_LEVELS 0x3264 +#define MC_PVA1XB2_EXTRA_SNAP_LEVELS 0x483c +#define MC_PVA1XA_EXTRA_SNAP_LEVELS 0xe1c +#define MC_AONPC_EXTRA_SNAP_LEVELS 0xa68 +#define MC_SD_EXTRA_SNAP_LEVELS 0xa04 +#define MC_VE_EXTRA_SNAP_LEVELS 0x2d8 +#define MC_SCEPC_EXTRA_SNAP_LEVELS 0xa70 +#define MC_HOST_EXTRA_SNAP_LEVELS 0xa14 +#define MC_JPG_EXTRA_SNAP_LEVELS 0xa3c +#define MC_DLA0XA3_EXTRA_SNAP_LEVELS 0x4110 +#define MC_DIS_EXTRA_SNAP_LEVELS 0x2ac +#define MC_DLA1XA_EXTRA_SNAP_LEVELS 0xe14 +#define MC_PCIE0X_EXTRA_SNAP_LEVELS 0x326c +#define MC_PCIE5X_EXTRA_SNAP_LEVELS 0x4108 +#define MC_PVA0XC_EXTRA_SNAP_LEVELS 0x4814 +#define MC_MSE3_EXTRA_SNAP_LEVELS 0x3250 +#define MC_USBX2_EXTRA_SNAP_LEVELS 0x4848 +#define MC_PVA0XA_EXTRA_SNAP_LEVELS 0xe18 +#define MC_DLA1FALPC_EXTRA_SNAP_LEVELS 0x3268 +#define MC_DLA1XA3_EXTRA_SNAP_LEVELS 0x4114 +#define MC_PCIE5XA_EXTRA_SNAP_LEVELS 0x4804 +#define MC_MIU5_EXTRA_SNAP_LEVELS 0x4928 +#define MC_VICPC2_EXTRA_SNAP_LEVELS 0xa7c +#define MC_ISPPC_EXTRA_SNAP_LEVELS 0x490c +#define MC_PCIE1XA_EXTRA_SNAP_LEVELS 0x411c +#define MC_NVD6_EXTRA_SNAP_LEVELS 0x4920 +#define MC_SDM_EXTRA_SNAP_LEVELS 0xa44 +#define MC_APB_EXTRA_SNAP_LEVELS 0x2a4 +#define MC_ISP_EXTRA_SNAP_LEVELS 0xa08 +#define MC_MIU0_EXTRA_SNAP_LEVELS 0x3254 +#define MC_PCIE5X2_EXTRA_SNAP_LEVELS 0x4840 +#define MC_NIC_EXTRA_SNAP_LEVELS 0xa54 +#define MC_MIU2_EXTRA_SNAP_LEVELS 0x325c +#define MC_PVA0XB_EXTRA_SNAP_LEVELS 0x480c +#define MC_PVA1XB3_EXTRA_SNAP_LEVELS 0x4820 +#define MC_NVD3_EXTRA_SNAP_LEVELS 0xe04 +#define MC_SAX_EXTRA_SNAP_LEVELS 0x2c0 +#define MC_MSEB1_EXTRA_SNAP_LEVELS 0x4908 +#define MC_MSEB_EXTRA_SNAP_LEVELS 0x4904 +#define MC_NVD4_EXTRA_SNAP_LEVELS 0x4918 +#define MC_PVA1XC_EXTRA_SNAP_LEVELS 0x4824 +#define MC_NVD_EXTRA_SNAP_LEVELS 0xa38 +#define MC_PVA1XA2_EXTRA_SNAP_LEVELS 0x4838 +#define MC_PVA0XA2_EXTRA_SNAP_LEVELS 0x4830 +#define MC_NVD5_EXTRA_SNAP_LEVELS 0x491c +#define MC_DIS2_EXTRA_SNAP_LEVELS 0xa84 +#define MC_VIDEO_PROTECT_BOM 0x648 +#define MC_VIDEO_PROTECT_SIZE_MB 0x64c +#define MC_VIDEO_PROTECT_BOM_ADR_HI 0x978 +#define MC_VIDEO_PROTECT_REG_CTRL 0x650 +#define MC_ERR_VPR_STATUS 0x654 +#define MC_ERR_VPR_ADR 0x658 +#define MC_VIDEO_PROTECT_VPR_OVERRIDE 0x418 +#define MC_VIDEO_PROTECT_VPR_OVERRIDE1 0x590 +#define MC_VIDEO_PROTECT_VPR_OVERRIDE2 0x594 +#define MC_EMEM_CFG_ACCESS_CTRL 0x664 +#define MC_TZ_SECURITY_CTRL 0x668 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS2 0x1988 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS6 0x1998 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS3 0x198c +#define MC_TZ_CARVEOUT_CLIENT_ACCESS5 0x1994 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS0 0x1980 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS4 0x1990 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS1 0x1984 +#define MC_TZ_CARVEOUT_CLIENT_ACCESS7 0x199c +#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3 0x66c +#define MC_EMEM_ARB_OUTSTANDING_REQ_NISO 0x6b4 +#define MC_EMEM_ARB_RING0_THROTTLE_MASK 0x6bc +#define MC_EMEM_ARB_NISO_THROTTLE_MASK_3 0x3b00 +#define MC_EMEM_ARB_NISO_THROTTLE_MASK 0x6b8 +#define MC_EMEM_ARB_NISO_THROTTLE_MASK_1 0xb80 +#define MC_EMEM_ARB_NISO_THROTTLE_MASK_2 0x3200 +#define MC_SEC_CARVEOUT_BOM 0x670 +#define MC_SEC_CARVEOUT_SIZE_MB 0x674 +#define MC_SEC_CARVEOUT_ADR_HI 0x9d4 +#define MC_SEC_CARVEOUT_REG_CTRL 0x678 +#define MC_ERR_SEC_STATUS 0x67c +#define MC_ERR_SEC_ADR 0x680 +#define MC_PC_IDLE_CLOCK_GATE_CONFIG 0x684 +#define MC_STUTTER_CONTROL 0x688 +#define MC_RESERVED_RSV_1 0x958 +#define MC_DVFS_PIPE_SELECT 0x95c +#define MC_SCEPC_PTSA_MIN 0x790 +#define MC_AUD_PTSA_MIN 0x54c +#define MC_MLL_MPCORER_PTSA_RATE 0x44c +#define MC_RING2_PTSA_RATE 0x440 +#define MC_USBD_PTSA_RATE 0x530 +#define MC_PCIE5X_PTSA_MAX 0x3350 +#define MC_ISPPC_PTSA_MIN 0x3a70 +#define MC_JPG_PTSA_RATE 0x584 +#define MC_APB_PTSA_MAX 0x4f0 +#define MC_PVA1XC_PTSA_RATE 0x3924 +#define MC_MIU7_PTSA_MAX 0x4b68 +#define MC_PVA0XB_PTSA_MIN 0x3558 +#define MC_DIS_PTSA_MIN 0x420 +#define MC_NVD2_PTSA_MIN 0x3a1c +#define MC_SD_PTSA_MAX 0x4d8 +#define MC_MSE_PTSA_RATE 0x4c4 +#define MC_MSE3_PTSA_MIN 0x3134 +#define MC_DLA0XA_PTSA_MIN 0x7e4 +#define MC_ISP_PTSA_RATE 0x4a0 +#define MC_MIU6_PTSA_MAX 0x4b5c +#define MC_UFSHCPC2_PTSA_RATE 0x3a24 +#define MC_PCIE5X2_PTSA_RATE 0x3a00 +#define MC_PVA0XB2_PTSA_MIN 0x3958 +#define MC_HOST_PTSA_MIN 0x51c +#define MC_DLA1XA3_PTSA_MIN 0x3370 +#define MC_MLL_MPCORER_PTSA_MAX 0x454 +#define MC_SD_PTSA_MIN 0x4d4 +#define MC_PVA1XB2_PTSA_MAX 0x3974 +#define MC_DLA0XA_PTSA_MAX 0x7e8 +#define MC_RING1_PTSA_RATE 0x47c +#define MC_NVD2_PTSA_RATE 0x3a18 +#define MC_PVA1XC_PTSA_MAX 0x392c +#define MC_DLA1FALPC_PTSA_MIN 0x3304 +#define MC_PCIE1XA_PTSA_MIN 0x3510 +#define MC_MIU1_PTSA_MAX 0x3150 +#define MC_MIU0_PTSA_RATE 0x313c +#define MC_JPG_PTSA_MAX 0x58c +#define MC_UFSHCPC_PTSA_MAX 0x74c +#define MC_NVD5_PTSA_MAX 0x4b2c +#define MC_VICPC2_PTSA_MIN 0x3a10 +#define MC_VICPC_PTSA_MAX 0x55c +#define MC_DLA1FALPC_PTSA_MAX 0x3308 +#define MC_NVD2_PTSA_MAX 0x3a20 +#define MC_NVD_PTSA_RATE 0x578 +#define MC_MIU1_PTSA_RATE 0x3148 +#define MC_SCEPC_PTSA_RATE 0x78c +#define MC_MIU3_PTSA_MIN 0x3164 +#define MC_EQOSPC_PTSA_MIN 0x754 +#define MC_PVA1XB3_PTSA_MAX 0x3920 +#define MC_PVA0XA2_PTSA_RATE 0x3948 +#define MC_EQOSPC_PTSA_RATE 0x750 +#define MC_USBX2_PTSA_MAX 0x3a38 +#define MC_VICPC3_PTSA_MIN 0x7b4 +#define MC_MLL_MPCORER_PTSA_MIN 0x450 +#define MC_ISP_PTSA_MAX 0x4a8 +#define MC_PCIE4XA_PTSA_MAX 0x3538 +#define MC_UFSHCPC_PTSA_MIN 0x748 +#define MC_PVA0XC_PTSA_MIN 0x3570 +#define MC_FTOP_PTSA_RATE 0x50c +#define MC_VICPC2_PTSA_MAX 0x3a14 +#define MC_PCIE4XA_PTSA_RATE 0x3530 +#define MC_DLA0XA2_PTSA_RATE 0x3930 +#define MC_NVD3_PTSA_MIN 0x7c0 +#define MC_PCIE5X2_PTSA_MIN 0x3a04 +#define MC_DLA0FALPC_PTSA_MAX 0x3174 +#define MC_MIU0_PTSA_MIN 0x3140 +#define MC_MIU2_PTSA_MAX 0x315c +#define MC_ISP2PC_PTSA_MIN 0x4b04 +#define MC_USBX_PTSA_MAX 0x52c +#define MC_USBD_PTSA_MAX 0x538 +#define MC_MIU5_PTSA_MIN 0x4b4c +#define MC_USBX_PTSA_RATE 0x524 +#define MC_PCIE0X_PTSA_MAX 0x3314 +#define MC_MSEA_PTSA_MIN 0x3a4c +#define MC_FTOP_PTSA_MAX 0x514 +#define MC_PVA0XA3_PTSA_MAX 0x3550 +#define MC_ISP2PC_PTSA_MAX 0x4b08 +#define MC_HDAPC_PTSA_MAX 0x630 +#define MC_SD_PTSA_RATE 0x4d0 +#define MC_MSEA_PTSA_MAX 0x3a50 +#define MC_PCIE1X_PTSA_MAX 0x3320 +#define MC_PCIE0X2_PTSA_MAX 0x4b14 +#define MC_PCIE5XA_PTSA_RATE 0x353c +#define MC_PVA0XA_PTSA_MIN 0x3104 +#define MC_FTOP_PTSA_MIN 0x510 +#define MC_DLA1XA3_PTSA_RATE 0x336c +#define MC_BPMPPC_PTSA_MAX 0x764 +#define MC_MSE_PTSA_MIN 0x4c8 +#define MC_PCIE0X2_PTSA_MIN 0x4b10 +#define MC_PVA0XB3_PTSA_RATE 0x3560 +#define MC_PVA0XA_PTSA_RATE 0x3100 +#define MC_NVD5_PTSA_MIN 0x4b28 +#define MC_VE_PTSA_RATE 0x434 +#define MC_DLA1XA2_PTSA_RATE 0x393c +#define MC_AONPC_PTSA_RATE 0x774 +#define MC_DLA0FALPC_PTSA_MIN 0x3170 +#define MC_MIU4_PTSA_RATE 0x4b3c +#define MC_MIU4_PTSA_MAX 0x4b44 +#define MC_SAX_PTSA_MIN 0x4bc +#define MC_PVA0XB2_PTSA_MAX 0x395c +#define MC_PVA0XA3_PTSA_MIN 0x354c +#define MC_ISP_PTSA_MIN 0x4a4 +#define MC_HOST_PTSA_MAX 0x520 +#define MC_BPMPPC_PTSA_MIN 0x760 +#define MC_PCIE1X_PTSA_RATE 0x3318 +#define MC_NVD6_PTSA_RATE 0x4b30 +#define MC_DLA0XA2_PTSA_MIN 0x3934 +#define MC_ISP2PC_PTSA_RATE 0x4b00 +#define MC_PVA0XB3_PTSA_MIN 0x3564 +#define MC_MSE3_PTSA_MAX 0x3138 +#define MC_NVD5_PTSA_RATE 0x4b24 +#define MC_MSEB1_PTSA_MIN 0x3a64 +#define MC_PVA0XB2_PTSA_RATE 0x3954 +#define MC_EQOSPC_PTSA_MAX 0x758 +#define MC_MSEB_PTSA_RATE 0x3a54 +#define MC_USBX_PTSA_MIN 0x528 +#define MC_PCIE4X_PTSA_RATE 0x333c +#define MC_USBD_PTSA_MIN 0x534 +#define MC_PCIE5X_PTSA_MIN 0x334c +#define MC_MIU3_PTSA_MAX 0x3168 +#define MC_DLA1FALPC_PTSA_RATE 0x3300 +#define MC_PVA1XB3_PTSA_RATE 0x3918 +#define MC_DLA1XA3_PTSA_MAX 0x3374 +#define MC_MIU1_PTSA_MIN 0x314c +#define MC_PCIE5XA_PTSA_MAX 0x3544 +#define MC_DLA0XA3_PTSA_MIN 0x3364 +#define MC_DIS_PTSA_MAX 0x424 +#define MC_RING1_PTSA_MIN 0x480 +#define MC_UFSHCPC2_PTSA_MAX 0x3a2c +#define MC_VICPC_PTSA_MIN 0x558 +#define MC_MSEB_PTSA_MAX 0x3a5c +#define MC_PVA0XB_PTSA_MAX 0x355c +#define MC_USBX2_PTSA_MIN 0x3a34 +#define MC_RING2_PTSA_MAX 0x448 +#define MC_AUD_PTSA_RATE 0x548 +#define MC_PCIE0XA_PTSA_MIN 0x3504 +#define MC_PCIE0XA_PTSA_RATE 0x3500 +#define MC_DLA1XA2_PTSA_MIN 0x3940 +#define MC_PVA1XB2_PTSA_RATE 0x396c +#define MC_RCEPC_PTSA_MIN 0x311c +#define MC_PVA1XA_PTSA_MIN 0x3110 +#define MC_DLA0XA3_PTSA_RATE 0x3360 +#define MC_NIC_PTSA_MAX 0x740 +#define MC_NVD_PTSA_MAX 0x580 +#define MC_MIU6_PTSA_MIN 0x4b58 +#define MC_PCIE0X_PTSA_RATE 0x330c +#define MC_AONPC_PTSA_MAX 0x77c +#define MC_JPG_PTSA_MIN 0x588 +#define MC_UFSHCPC2_PTSA_MIN 0x3a28 +#define MC_HDAPC_PTSA_MIN 0x62c +#define MC_DLA1XA_PTSA_MAX 0x7f4 +#define MC_MSE2_PTSA_MAX 0x7d0 +#define MC_NVD4_PTSA_MAX 0x4b20 +#define MC_PVA1XA_PTSA_MAX 0x3114 +#define MC_VE_PTSA_MAX 0x43c +#define MC_DLA0XA2_PTSA_MAX 0x3938 +#define MC_PVA0XB_PTSA_RATE 0x3554 +#define MC_MSEB1_PTSA_RATE 0x3a60 +#define MC_PVA0XC_PTSA_MAX 0x3574 +#define MC_VICPC_PTSA_RATE 0x554 +#define MC_BPMPPC_PTSA_RATE 0x75c +#define MC_ISPPC_PTSA_MAX 0x3a74 +#define MC_SCEPC_PTSA_MAX 0x794 +#define MC_DLA0XA_PTSA_RATE 0x7e0 +#define MC_DLA0XA3_PTSA_MAX 0x3368 +#define MC_MIU7_PTSA_RATE 0x4b60 +#define MC_PCIE4X_PTSA_MIN 0x3340 +#define MC_PCIE5X_PTSA_RATE 0x3348 +#define MC_SDM_PTSA_MAX 0x624 +#define MC_VICPC2_PTSA_RATE 0x3a0c +#define MC_PCIE5XA_PTSA_MIN 0x3540 +#define MC_NVD4_PTSA_RATE 0x4b18 +#define MC_PVA0XA_PTSA_MAX 0x3108 +#define MC_MSE2_PTSA_MIN 0x7cc +#define MC_USBD2_PTSA_MAX 0x3a44 +#define MC_SAX_PTSA_RATE 0x4b8 +#define MC_APB_PTSA_MIN 0x4ec +#define MC_ISPPC_PTSA_RATE 0x3a6c +#define MC_PVA1XA2_PTSA_RATE 0x3960 +#define MC_PCIE5X2_PTSA_MAX 0x3a08 +#define MC_PCIE4XA_PTSA_MIN 0x3534 +#define MC_RCEPC_PTSA_MAX 0x3120 +#define MC_PVA0XA3_PTSA_RATE 0x3548 +#define MC_AONPC_PTSA_MIN 0x778 +#define MC_PCIE0X2_PTSA_RATE 0x4b0c +#define MC_MSE3_PTSA_RATE 0x3130 +#define MC_RCEPC_PTSA_RATE 0x3118 +#define MC_RING1_PTSA_MAX 0x484 +#define MC_HDAPC_PTSA_RATE 0x628 +#define MC_MIU0_PTSA_MAX 0x3144 +#define MC_PVA1XB2_PTSA_MIN 0x3970 +#define MC_VICPC3_PTSA_RATE 0x7b0 +#define MC_AUD_PTSA_MAX 0x550 +#define MC_MIU2_PTSA_MIN 0x3158 +#define MC_NVD3_PTSA_MAX 0x7c4 +#define MC_MIU6_PTSA_RATE 0x4b54 +#define MC_NVD_PTSA_MIN 0x57c +#define MC_PVA0XA2_PTSA_MIN 0x394c +#define MC_VICPC3_PTSA_MAX 0x7b8 +#define MC_PVA1XA2_PTSA_MIN 0x3964 +#define MC_PVA0XB3_PTSA_MAX 0x3568 +#define MC_PVA1XA3_PTSA_RATE 0x3900 +#define MC_PCIE0X_PTSA_MIN 0x3310 +#define MC_PCIE1XA_PTSA_RATE 0x350c +#define MC_DIS_PTSA_RATE 0x41c +#define MC_USBX2_PTSA_RATE 0x3a30 +#define MC_DLA1XA_PTSA_MIN 0x7f0 +#define MC_PVA1XA3_PTSA_MAX 0x3908 +#define MC_PVA1XB_PTSA_RATE 0x390c +#define MC_DLA1XA2_PTSA_MAX 0x3944 +#define MC_MSEA_PTSA_RATE 0x3a48 +#define MC_MIU2_PTSA_RATE 0x3154 +#define MC_NVD6_PTSA_MAX 0x4b38 +#define MC_PCIE1XA_PTSA_MAX 0x3514 +#define MC_MIU3_PTSA_RATE 0x3160 +#define MC_MIU5_PTSA_MAX 0x4b50 +#define MC_SDM_PTSA_RATE 0x61c +#define MC_SDM_PTSA_MIN 0x620 +#define MC_APB_PTSA_RATE 0x4e8 +#define MC_RING2_PTSA_MIN 0x444 +#define MC_UFSHCPC_PTSA_RATE 0x744 +#define MC_PVA0XC_PTSA_RATE 0x356c +#define MC_MSE2_PTSA_RATE 0x7c8 +#define MC_PCIE0XA_PTSA_MAX 0x3508 +#define MC_MSEB_PTSA_MIN 0x3a58 +#define MC_PVA1XB_PTSA_MAX 0x3914 +#define MC_HOST_PTSA_RATE 0x518 +#define MC_NVD3_PTSA_RATE 0x7bc +#define MC_NVD6_PTSA_MIN 0x4b34 +#define MC_MIU5_PTSA_RATE 0x4b48 +#define MC_PVA1XB_PTSA_MIN 0x3910 +#define MC_PVA1XA_PTSA_RATE 0x310c +#define MC_MIU4_PTSA_MIN 0x4b40 +#define MC_NIC_PTSA_RATE 0x738 +#define MC_PVA1XB3_PTSA_MIN 0x391c +#define MC_NVD4_PTSA_MIN 0x4b1c +#define MC_SAX_PTSA_MAX 0x4c0 +#define MC_MIU7_PTSA_MIN 0x4b64 +#define MC_PVA1XA3_PTSA_MIN 0x3904 +#define MC_VE_PTSA_MIN 0x438 +#define MC_USBD2_PTSA_RATE 0x3a3c +#define MC_DLA1XA_PTSA_RATE 0x7ec +#define MC_PVA0XA2_PTSA_MAX 0x3950 +#define MC_DLA0FALPC_PTSA_RATE 0x316c +#define MC_MSE_PTSA_MAX 0x4cc +#define MC_PCIE4X_PTSA_MAX 0x3344 +#define MC_MSEB1_PTSA_MAX 0x3a68 +#define MC_USBD2_PTSA_MIN 0x3a40 +#define MC_PVA1XA2_PTSA_MAX 0x3968 +#define MC_PCIE1X_PTSA_MIN 0x331c +#define MC_NIC_PTSA_MIN 0x73c +#define MC_PVA1XC_PTSA_MIN 0x3928 +#define MC_PTSA_GRANT_DECREMENT 0x960 +#define MC_LATENCY_ALLOWANCE_AON_0 0x714 +#define MC_LATENCY_ALLOWANCE_NVENC_1 0x1050 +#define MC_LATENCY_ALLOWANCE_BPMP_0 0x70c +#define MC_LATENCY_ALLOWANCE_MIU0_0 0x1054 +#define MC_LATENCY_ALLOWANCE_NVDEC_1 0x72c +#define MC_LATENCY_ALLOWANCE_XUSB_1 0x380 +#define MC_LATENCY_ALLOWANCE_NVENC_2 0x1a28 +#define MC_LATENCY_ALLOWANCE_SE_0 0x3e0 +#define MC_LATENCY_ALLOWANCE_PCIE2_0 0x1a04 +#define MC_LATENCY_ALLOWANCE_PCIE1_0 0x1a00 +#define MC_LATENCY_ALLOWANCE_DLA1_0 0x1028 +#define MC_LATENCY_ALLOWANCE_APEDMA_0 0x724 +#define MC_LATENCY_ALLOWANCE_NVDEC_0 0x3d8 +#define MC_LATENCY_ALLOWANCE_ISP3_0 0x1a14 +#define MC_LATENCY_ALLOWANCE_MIU2_0 0x105c +#define MC_LATENCY_ALLOWANCE_MIU5_0 0x1a38 +#define MC_LATENCY_ALLOWANCE_DLA0_2 0x1a18 +#define MC_LATENCY_ALLOWANCE_PCIE0_0 0x1064 +#define MC_LATENCY_ALLOWANCE_PVA0_2 0x1038 +#define MC_LATENCY_ALLOWANCE_MIU3_0 0x1060 +#define MC_LATENCY_ALLOWANCE_MIU1_0 0x1058 +#define MC_LATENCY_ALLOWANCE_DLA1_1 0x102c +#define MC_LATENCY_ALLOWANCE_PVA1_0 0x103c +#define MC_LATENCY_ALLOWANCE_SDMMC_0 0x3c0 +#define MC_LATENCY_ALLOWANCE_DLA0_1 0x1024 +#define MC_LATENCY_ALLOWANCE_DLA0_0 0x1020 +#define MC_LATENCY_ALLOWANCE_NVJPG_0 0x3e4 +#define MC_LATENCY_ALLOWANCE_MPCORE_0 0x320 +#define MC_LATENCY_ALLOWANCE_VI2_0 0x398 +#define MC_LATENCY_ALLOWANCE_MIU7_0 0x1a40 +#define MC_LATENCY_ALLOWANCE_SCEDMA_0 0x720 +#define MC_LATENCY_ALLOWANCE_PVA1_1 0x1040 +#define MC_LATENCY_ALLOWANCE_SATA_0 0x350 +#define MC_LATENCY_ALLOWANCE_AONDMA_0 0x718 +#define MC_LATENCY_ALLOWANCE_HC_0 0x310 +#define MC_LATENCY_ALLOWANCE_UFSHC_0 0x704 +#define MC_LATENCY_ALLOWANCE_NVDEC_2 0x1a30 +#define MC_LATENCY_ALLOWANCE_VIC_1 0x728 +#define MC_LATENCY_ALLOWANCE_SDMMCAB_0 0x3c4 +#define MC_LATENCY_ALLOWANCE_RCEDMA_0 0x104c +#define MC_LATENCY_ALLOWANCE_HDA_0 0x318 +#define MC_LATENCY_ALLOWANCE_BPMPDMA_0 0x710 +#define MC_LATENCY_ALLOWANCE_PCIE3_0 0x1a08 +#define MC_LATENCY_ALLOWANCE_AXIAP_0 0x3a0 +#define MC_LATENCY_ALLOWANCE_SDMMCA_0 0x3b8 +#define MC_LATENCY_ALLOWANCE_PVA0_3 0x1a1c +#define MC_LATENCY_ALLOWANCE_ISP2_0 0x370 +#define MC_LATENCY_ALLOWANCE_NVDISPLAY_0 0x708 +#define MC_LATENCY_ALLOWANCE_ISP2_1 0x374 +#define MC_LATENCY_ALLOWANCE_PVA1_3 0x1a20 +#define MC_LATENCY_ALLOWANCE_VIC_0 0x394 +#define MC_LATENCY_ALLOWANCE_PCIE4_0 0x1a0c +#define MC_LATENCY_ALLOWANCE_PVA1_2 0x1044 +#define MC_LATENCY_ALLOWANCE_EQOS_0 0x700 +#define MC_LATENCY_ALLOWANCE_TSEC_0 0x390 +#define MC_LATENCY_ALLOWANCE_VIFAL_0 0x101c +#define MC_LATENCY_ALLOWANCE_PVA0_1 0x1034 +#define MC_LATENCY_ALLOWANCE_XUSB_0 0x37c +#define MC_LATENCY_ALLOWANCE_MIU4_0 0x1a34 +#define MC_LATENCY_ALLOWANCE_TSECB_0 0x3f0 +#define MC_LATENCY_ALLOWANCE_SCE_0 0x71c +#define MC_LATENCY_ALLOWANCE_APE_0 0x3dc +#define MC_LATENCY_ALLOWANCE_RCE_0 0x1048 +#define MC_LATENCY_ALLOWANCE_PVA0_0 0x1030 +#define MC_LATENCY_ALLOWANCE_PTC_0 0x34c +#define MC_LATENCY_ALLOWANCE_ETR_0 0x3ec +#define MC_LATENCY_ALLOWANCE_PCIE5_0 0x1a10 +#define MC_LATENCY_ALLOWANCE_AXIS_0 0x3f8 +#define MC_LATENCY_ALLOWANCE_NVENC_0 0x328 +#define MC_LATENCY_ALLOWANCE_MIU6_0 0x1a3c +#define MC_LATENCY_ALLOWANCE_PCIE5_1 0x1a24 +#define MC_EMEM_ARB_OVERRIDE_1 0x968 +#define MC_VIDEO_PROTECT_GPU_OVERRIDE_0 0x984 +#define MC_VIDEO_PROTECT_GPU_OVERRIDE_1 0x988 +#define MC_EMEM_ARB_STATS_0 0x990 +#define MC_EMEM_ARB_STATS_1 0x994 +#define MC_MTS_CARVEOUT_BOM 0x9a0 +#define MC_MTS_CARVEOUT_SIZE_MB 0x9a4 +#define MC_MTS_CARVEOUT_ADR_HI 0x9a8 +#define MC_MTS_CARVEOUT_REG_CTRL 0x9ac +#define MC_ERR_MTS_STATUS 0x9b0 +#define MC_ERR_MTS_ADR 0x9b4 +#define MC_MTS_CARVEOUT_CLIENT_ACCESS6 0x1918 +#define MC_MTS_CARVEOUT_CLIENT_ACCESS4 0x1910 +#define MC_MTS_CARVEOUT_CLIENT_ACCESS1 0x1904 +#define MC_MTS_CARVEOUT_CLIENT_ACCESS5 0x1914 +#define MC_MTS_CARVEOUT_CLIENT_ACCESS0 0x1900 +#define MC_MTS_CARVEOUT_CLIENT_ACCESS7 0x191c +#define MC_MTS_CARVEOUT_CLIENT_ACCESS3 0x190c +#define MC_MTS_CARVEOUT_CLIENT_ACCESS2 0x1908 +#define MC_ERR_ROUTE_SANITY_STATUS 0x9c0 +#define MC_ERR_ROUTE_SANITY_ADR 0x9c4 +#define MC_IGPU_ACCESSIBLE_CARVEOUT_REG_CTRL 0x9c8 +#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT_REG_CTRL 0x9cc +#define MC_IGPU_WPR_ACCESS_CTRL 0x9d8 +#define MC_IGPU_ACCESSIBLE_CARVEOUT1_BOM 0x560 +#define MC_IGPU_ACCESSIBLE_CARVEOUT1_SIZE 0x564 +#define MC_IGPU_ACCESSIBLE_CARVEOUT2_BOM 0x568 +#define MC_IGPU_ACCESSIBLE_CARVEOUT2_SIZE 0x56c +#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT1_BOM 0x5a0 +#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT1_SIZE 0x5a4 +#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT2_BOM 0x5a8 +#define MC_REMOTE_DEV_ACCESSIBLE_CARVEOUT2_SIZE 0x5ac +#define MC_ECC_REGION0_SIZE 0x2b0c +#define MC_ECC_REGION0_CFG0 0x2b00 +#define MC_ECC_REGION3_BOM 0x2b34 +#define MC_ECC_REGION2_BOM 0x2b24 +#define MC_ECC_REGION1_SIZE 0x2b1c +#define MC_ECC_REGION1_BOM 0x2b14 +#define MC_ECC_REGION2_CFG0 0x2b20 +#define MC_ECC_REGION3_BOM_HI 0x2b38 +#define MC_ECC_REGION1_BOM_HI 0x2b18 +#define MC_ECC_REGION1_CFG0 0x2b10 +#define MC_ECC_REGION0_BOM_HI 0x2b08 +#define MC_ECC_REGION2_SIZE 0x2b2c +#define MC_ECC_REGION3_CFG0 0x2b30 +#define MC_ECC_REGION2_BOM_HI 0x2b28 +#define MC_ECC_REGION0_BOM 0x2b04 +#define MC_ECC_REGION3_SIZE 0x2b3c +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS_1 0xbfc +#define MC_ERR_GENERALIZED_CARVEOUT_STATUS 0xc00 +#define MC_ERR_GENERALIZED_CARVEOUT_ADR 0xc04 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2 0xd78 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS6 0xc48 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS5 0xc44 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS7 0xca4 +#define MC_SECURITY_CARVEOUT4_CFG0 0xcf8 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS6 0xd90 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2 0xd10 +#define MC_SECURITY_CARVEOUT4_SIZE_128KB 0xd04 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4 0xc28 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1 0xc34 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4 0xc90 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0 0xd20 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1 0xd74 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS5 0xc2c +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0 0xc30 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS7 0xd8c +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4 0xd80 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS5 0xccc +#define MC_SECURITY_CARVEOUT3_SIZE_128KB 0xcb4 +#define MC_SECURITY_CARVEOUT2_CFG0 0xc58 +#define MC_SECURITY_CARVEOUT1_CFG0 0xc08 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2 0xc88 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0 0xc68 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS7 0xc4c +#define MC_SECURITY_CARVEOUT3_BOM 0xcac +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2 0xc70 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS5 0xd84 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS6 0xd40 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3 0xd7c +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0 0xc80 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4 0xd18 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS6 0xcf0 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS6 0xce8 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS5 0xd1c +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1 0xcbc +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3 0xc3c +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2 0xc38 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2 0xcc0 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2 0xd60 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS6 0xca0 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS7 0xc54 +#define MC_SECURITY_CARVEOUT3_CFG0 0xca8 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0 0xcb8 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3 0xc8c +#define MC_SECURITY_CARVEOUT2_SIZE_128KB 0xc64 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS7 0xcec +#define MC_SECURITY_CARVEOUT5_BOM_HI 0xd50 +#define MC_SECURITY_CARVEOUT1_SIZE_128KB 0xc14 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3 0xd14 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS7 0xd94 +#define MC_SECURITY_CARVEOUT1_BOM 0xc0c +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS7 0xd3c +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4 0xd30 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS7 0xd44 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4 0xd68 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS6 0xd38 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0 0xd58 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4 0xcc8 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS5 0xce4 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2 0xd28 +#define MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3 0xcc4 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4 0xc78 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS7 0xc9c +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS7 0xcf4 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1 0xc1c +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS6 0xd88 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0 0xc18 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1 0xd5c +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3 0xd2c +#define MC_SECURITY_CARVEOUT3_BOM_HI 0xcb0 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3 0xcdc +#define MC_SECURITY_CARVEOUT2_BOM_HI 0xc60 +#define MC_SECURITY_CARVEOUT4_BOM_HI 0xd00 +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3 0xd64 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4 0xce0 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1 0xc84 +#define MC_SECURITY_CARVEOUT5_SIZE_128KB 0xd54 +#define MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS5 0xc94 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1 0xd24 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2 0xcd8 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1 0xd0c +#define MC_SECURITY_CARVEOUT5_CLIENT_ACCESS5 0xd6c +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3 0xc74 +#define MC_SECURITY_CARVEOUT5_CFG0 0xd48 +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0 0xcd0 +#define MC_SECURITY_CARVEOUT4_BOM 0xcfc +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS6 0xc50 +#define MC_SECURITY_CARVEOUT2_BOM 0xc5c +#define MC_SECURITY_CARVEOUT5_BOM 0xd4c +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3 0xc24 +#define MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0 0xd70 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS5 0xc7c +#define MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1 0xcd4 +#define MC_SECURITY_CARVEOUT1_BOM_HI 0xc10 +#define MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS5 0xd34 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS6 0xc98 +#define MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2 0xc20 +#define MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4 0xc40 +#define MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0 0xd08 +#define MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1 0xc6c +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS1 0x225c +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS3 0x21c4 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS1 0x252c +#define MC_SECURITY_CARVEOUT12_CFG0 0x21e0 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS7 0x26d4 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS5 0x208c +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS3 0x265c +#define MC_SECURITY_CARVEOUT9_BOM_HI 0x20f8 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS6 0x24a0 +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS6 0x2090 +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS6 0x2770 +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS2 0x2170 +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS0 0x2208 +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS4 0x2678 +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS0 0x2488 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS5 0x24ec +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS7 0x2184 +#define MC_SECURITY_CARVEOUT15_CFG0 0x22d0 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS1 0x23d4 +#define MC_SECURITY_CARVEOUT7_SIZE_128KB 0x205c +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS7 0x26dc +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS2 0x2490 +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS0 0x2380 +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS5 0x23ac +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS4 0x20c0 +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS2 0x22e8 +#define MC_SECURITY_CARVEOUT16_CFG0 0x2320 +#define MC_SECURITY_CARVEOUT9_BOM 0x20f4 +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS3 0x22b4 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS5 0x2254 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS0 0x2078 +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS1 0x25cc +#define MC_SECURITY_CARVEOUT22_BOM_HI 0x2508 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS3 0x2354 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS5 0x2484 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS3 0x23dc +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS2 0x2210 +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS0 0x2438 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS6 0x2720 +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS0 0x2290 +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS6 0x2138 +#define MC_SECURITY_CARVEOUT8_SIZE_128KB 0x20ac +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS3 0x260c +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS1 0x25b4 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS3 0x2534 +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS0 0x2668 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS2 0x2798 +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS3 0x206c +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS2 0x26a8 +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS3 0x26c4 +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS4 0x2430 +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS7 0x218c +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS4 0x2020 +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS5 0x2394 +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS6 0x2180 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS5 0x20dc +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS5 0x23fc +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS6 0x25e8 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS3 0x21ac +#define MC_SECURITY_CARVEOUT7_BOM 0x2054 +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS3 0x2714 +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS0 0x2060 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS3 0x2624 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS0 0x20c8 +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS3 0x24cc +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS2 0x2300 +#define MC_SECURITY_CARVEOUT17_CFG0 0x2370 +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS5 0x22a4 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS4 0x2088 +#define MC_SECURITY_CARVEOUT29_SIZE_128KB 0x273c +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS3 0x274c +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS3 0x2674 +#define MC_SECURITY_CARVEOUT27_CFG0 0x2690 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS7 0x263c +#define MC_SECURITY_CARVEOUT16_SIZE_128KB 0x232c +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS6 0x2810 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS1 0x207c +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS7 0x27cc +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS3 0x22ec +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS1 0x261c +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS0 0x25b0 +#define MC_SECURITY_CARVEOUT18_BOM 0x23c4 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS0 0x2528 +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS1 0x248c +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS6 0x23b8 +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS0 0x2510 +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS3 0x2214 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS2 0x21a8 +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS1 0x2604 +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS4 0x2340 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS7 0x2274 +#define MC_SECURITY_CARVEOUT29_CFG0 0x2730 +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS0 0x27a8 +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS6 0x2048 +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS4 0x22b8 +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS3 0x21fc +#define MC_SECURITY_CARVEOUT11_CFG0 0x2190 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS3 0x2764 +#define MC_SECURITY_CARVEOUT8_CFG0 0x20a0 +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS2 0x2580 +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS5 0x2164 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS4 0x2480 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS4 0x2538 +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS5 0x2434 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS2 0x2350 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS4 0x24e8 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS5 0x21b4 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS4 0x23e0 +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS1 0x2334 +#define MC_SECURITY_CARVEOUT28_BOM 0x26e4 +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS6 0x2630 +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS1 0x20b4 +#define MC_SECURITY_CARVEOUT15_BOM 0x22d4 +#define MC_SECURITY_CARVEOUT6_BOM 0x2004 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS3 0x26ac +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS2 0x26c0 +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS3 0x201c +#define MC_SECURITY_CARVEOUT10_BOM 0x2144 +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS2 0x2710 +#define MC_SECURITY_CARVEOUT29_BOM_HI 0x2738 +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS0 0x2150 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS7 0x2724 +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS7 0x2594 +#define MC_SECURITY_CARVEOUT7_BOM_HI 0x2058 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS6 0x2818 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS4 0x2110 +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS5 0x2524 +#define MC_SECURITY_CARVEOUT19_SIZE_128KB 0x241c +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS6 0x2040 +#define MC_SECURITY_CARVEOUT18_SIZE_128KB 0x23cc +#define MC_SECURITY_CARVEOUT10_CFG0 0x2140 +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS1 0x21bc +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS0 0x2168 +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS4 0x2308 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS6 0x2638 +#define MC_SECURITY_CARVEOUT6_BOM_HI 0x2008 +#define MC_SECURITY_CARVEOUT15_SIZE_128KB 0x22dc +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS2 0x2670 +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS4 0x24d0 +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS2 0x24c8 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS2 0x2478 +#define MC_SECURITY_CARVEOUT19_CFG0 0x2410 +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS1 0x2014 +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS3 0x25bc +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS1 0x21f4 +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS2 0x2018 +#define MC_SECURITY_CARVEOUT20_SIZE_128KB 0x246c +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS5 0x217c +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS1 0x2654 +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS0 0x2740 +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS1 0x22ac +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS3 0x23f4 +#define MC_SECURITY_CARVEOUT27_BOM 0x2694 +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS6 0x22c0 +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS7 0x2224 +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS2 0x21c0 +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS7 0x222c +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS1 0x26bc +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS3 0x20d4 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS1 0x234c +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS6 0x2450 +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS4 0x2390 +#define MC_SECURITY_CARVEOUT19_BOM_HI 0x2418 +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS0 0x27e0 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS4 0x26b0 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS1 0x2794 +#define MC_SECURITY_CARVEOUT11_BOM_HI 0x2198 +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS0 0x25c8 +#define MC_SECURITY_CARVEOUT23_BOM 0x2554 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS3 0x247c +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS0 0x2028 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS0 0x2240 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS0 0x2618 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS3 0x24e4 +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS1 0x202c +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS7 0x2544 +#define MC_SECURITY_CARVEOUT21_BOM_HI 0x24b8 +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS0 0x23e8 +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS4 0x2588 +#define MC_SECURITY_CARVEOUT25_SIZE_128KB 0x25fc +#define MC_SECURITY_CARVEOUT30_CFG0 0x2780 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS7 0x209c +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS2 0x2338 +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS2 0x2030 +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS6 0x22c8 +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS0 0x2420 +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS4 0x2128 +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS5 0x2074 +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS5 0x2344 +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS1 0x22e4 +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS4 0x27f0 +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS0 0x22f8 +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS0 0x2650 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS7 0x281c +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS6 0x23b0 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS4 0x21b0 +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS2 0x2260 +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS5 0x2754 +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS6 0x2188 +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS4 0x2160 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS5 0x2114 +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS1 0x266c +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS0 0x21b8 +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS2 0x20b8 +#define MC_SECURITY_CARVEOUT28_BOM_HI 0x26e8 +#define MC_SECURITY_CARVEOUT8_BOM_HI 0x20a8 +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS5 0x27f4 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS2 0x2530 +#define MC_SECURITY_CARVEOUT10_BOM_HI 0x2148 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS6 0x2098 +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS5 0x24d4 +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS7 0x2044 +#define MC_SECURITY_CARVEOUT23_BOM_HI 0x2558 +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS2 0x25b8 +#define MC_SECURITY_CARVEOUT26_BOM_HI 0x2648 +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS0 0x2010 +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS2 0x2440 +#define MC_SECURITY_CARVEOUT30_BOM 0x2784 +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS7 0x21dc +#define MC_SECURITY_CARVEOUT18_CFG0 0x23c0 +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS7 0x2454 +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS5 0x2664 +#define MC_SECURITY_CARVEOUT27_BOM_HI 0x2698 +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS1 0x24c4 +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS0 0x21f0 +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS4 0x23f8 +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS5 0x271c +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS2 0x22b0 +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS0 0x2560 +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS1 0x220c +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS6 0x2368 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS4 0x2768 +#define MC_SECURITY_CARVEOUT14_BOM 0x2284 +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS6 0x2408 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS0 0x2790 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS0 0x2348 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS3 0x279c +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS6 0x2688 +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS3 0x238c +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS4 0x2610 +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS1 0x2424 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS1 0x2474 +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS7 0x227c +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS7 0x23b4 +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS5 0x27bc +#define MC_SECURITY_CARVEOUT17_BOM 0x2374 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS6 0x20e8 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS2 0x23d8 +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS3 0x229c +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS6 0x2540 +#define MC_SECURITY_CARVEOUT20_BOM_HI 0x2468 +#define MC_SECURITY_CARVEOUT21_SIZE_128KB 0x24bc +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS3 0x2584 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS7 0x21d4 +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS3 0x2124 +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS3 0x2034 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS5 0x262c +#define MC_SECURITY_CARVEOUT25_BOM 0x25f4 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS6 0x2130 +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS6 0x27c8 +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS5 0x203c +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS3 0x233c +#define MC_SECURITY_CARVEOUT7_CFG0 0x2050 +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS1 0x243c +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS3 0x215c +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS5 0x25c4 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS0 0x2758 +#define MC_SECURITY_CARVEOUT15_BOM_HI 0x22d8 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS2 0x2248 +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS5 0x221c +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS0 0x22e0 +#define MC_SECURITY_CARVEOUT22_BOM 0x2504 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS3 0x210c +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS6 0x24f0 +#define MC_SECURITY_CARVEOUT9_CFG0 0x20f0 +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS2 0x2120 +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS1 0x2384 +#define MC_SECURITY_CARVEOUT17_BOM_HI 0x2378 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS4 0x2358 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS4 0x2808 +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS0 0x24c0 +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS2 0x23a0 +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS6 0x2598 +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS1 0x239c +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS3 0x25d4 +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS5 0x267c +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS1 0x2064 +#define MC_SECURITY_CARVEOUT27_SIZE_128KB 0x269c +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS0 0x26b8 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS5 0x276c +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS4 0x2250 +#define MC_SECURITY_CARVEOUT12_BOM_HI 0x21e8 +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS4 0x2718 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS0 0x2470 +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS2 0x27e8 +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS6 0x24a8 +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS6 0x2220 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS4 0x2628 +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS4 0x22a0 +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS4 0x2448 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS1 0x20cc +#define MC_SECURITY_CARVEOUT11_BOM 0x2194 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS1 0x26f4 +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS6 0x2228 +#define MC_SECURITY_CARVEOUT28_SIZE_128KB 0x26ec +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS7 0x213c +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS3 0x251c +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS4 0x2570 +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS4 0x2200 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS5 0x253c +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS1 0x2744 +#define MC_SECURITY_CARVEOUT13_SIZE_128KB 0x223c +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS0 0x2330 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS2 0x24e0 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS7 0x27c4 +#define MC_SECURITY_CARVEOUT19_BOM 0x2414 +#define MC_SECURITY_CARVEOUT23_SIZE_128KB 0x255c +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS0 0x2398 +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS5 0x20c4 +#define MC_SECURITY_CARVEOUT23_CFG0 0x2550 +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS2 0x2568 +#define MC_SECURITY_CARVEOUT12_SIZE_128KB 0x21ec +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS3 0x2444 +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS7 0x2684 +#define MC_SECURITY_CARVEOUT30_BOM_HI 0x2788 +#define MC_SECURITY_CARVEOUT13_BOM 0x2234 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS1 0x2244 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS5 0x26b4 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS6 0x21d0 +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS7 0x24ac +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS3 0x2304 +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS7 0x245c +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS1 0x211c +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS3 0x27b4 +#define MC_SECURITY_CARVEOUT24_BOM_HI 0x25a8 +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS2 0x25d0 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS7 0x2404 +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS5 0x22f4 +#define MC_SECURITY_CARVEOUT31_CFG0 0x27d0 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS2 0x2108 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS7 0x236c +#define MC_SECURITY_CARVEOUT31_BOM 0x27d4 +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS0 0x2708 +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS5 0x258c +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS2 0x23f0 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS4 0x20d8 +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS4 0x25c0 +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS5 0x226c +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS7 0x2634 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS5 0x280c +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS0 0x20b0 +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS0 0x2600 +#define MC_SECURITY_CARVEOUT24_CFG0 0x25a0 +#define MC_SECURITY_CARVEOUT28_CFG0 0x26e0 +#define MC_SECURITY_CARVEOUT24_SIZE_128KB 0x25ac +#define MC_SECURITY_CARVEOUT6_CFG0 0x2000 +#define MC_SECURITY_CARVEOUT21_BOM 0x24b4 +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS7 0x22cc +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS5 0x249c +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS7 0x272c +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS7 0x2774 +#define MC_SECURITY_CARVEOUT14_BOM_HI 0x2288 +#define MC_SECURITY_CARVEOUT9_SIZE_128KB 0x20fc +#define MC_SECURITY_CARVEOUT21_CLIENT_ACCESS7 0x24f4 +#define MC_SECURITY_CARVEOUT20_BOM 0x2464 +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS5 0x21cc +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS1 0x2294 +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS2 0x2748 +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS4 0x2520 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS7 0x2134 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS6 0x2778 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS1 0x21a4 +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS3 0x2174 +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS3 0x27ec +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS0 0x2258 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS0 0x23d0 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS0 0x26f0 +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS1 0x27ac +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS2 0x2760 +#define MC_SECURITY_CARVEOUT30_SIZE_128KB 0x278c +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS2 0x2428 +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS1 0x22fc +#define MC_SECURITY_CARVEOUT26_CFG0 0x2640 +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS1 0x270c +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS6 0x2458 +#define MC_SECURITY_CARVEOUT31_SIZE_128KB 0x27dc +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS4 0x2660 +#define MC_SECURITY_CARVEOUT14_SIZE_128KB 0x228c +#define MC_SECURITY_CARVEOUT6_SIZE_128KB 0x200c +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS5 0x25dc +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS6 0x20e0 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS6 0x2270 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS2 0x2800 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS7 0x20ec +#define MC_SECURITY_CARVEOUT26_CLIENT_FORCE_INTERNAL_ACCESS7 0x268c +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS5 0x26cc +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS4 0x27b8 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS4 0x2700 +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS4 0x2498 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS7 0x24fc +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS1 0x2564 +#define MC_SECURITY_CARVEOUT13_CLIENT_ACCESS3 0x224c +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS1 0x2104 +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS1 0x2514 +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS7 0x25e4 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS7 0x277c +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS4 0x2070 +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS1 0x2154 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS5 0x23e4 +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS2 0x2608 +#define MC_SECURITY_CARVEOUT11_CLIENT_ACCESS0 0x21a0 +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS3 0x256c +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS6 0x26d8 +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS7 0x2364 +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS4 0x2268 +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS4 0x22f0 +#define MC_SECURITY_CARVEOUT24_BOM 0x25a4 +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS5 0x212c +#define MC_SECURITY_CARVEOUT12_CLIENT_FORCE_INTERNAL_ACCESS4 0x2218 +#define MC_SECURITY_CARVEOUT30_CLIENT_FORCE_INTERNAL_ACCESS2 0x27b0 +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS5 0x22bc +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS7 0x240c +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS2 0x21f8 +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS4 0x21c8 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS3 0x26fc +#define MC_SECURITY_CARVEOUT16_BOM 0x2324 +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS4 0x2178 +#define MC_SECURITY_CARVEOUT8_CLIENT_FORCE_INTERNAL_ACCESS2 0x20d0 +#define MC_SECURITY_CARVEOUT18_BOM_HI 0x23c8 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS3 0x2084 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS0 0x24d8 +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS5 0x230c +#define MC_SECURITY_CARVEOUT28_CLIENT_FORCE_INTERNAL_ACCESS6 0x2728 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS4 0x27a0 +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS7 0x2314 +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS2 0x2658 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS6 0x26d0 +#define MC_SECURITY_CARVEOUT16_CLIENT_FORCE_INTERNAL_ACCESS5 0x235c +#define MC_SECURITY_CARVEOUT19_CLIENT_ACCESS3 0x242c +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS6 0x24f8 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS5 0x27a4 +#define MC_SECURITY_CARVEOUT29_BOM 0x2734 +#define MC_SECURITY_CARVEOUT11_CLIENT_FORCE_INTERNAL_ACCESS6 0x21d8 +#define MC_SECURITY_CARVEOUT25_CLIENT_ACCESS5 0x2614 +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS7 0x231c +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS1 0x257c +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS7 0x25ec +#define MC_SECURITY_CARVEOUT24_CLIENT_ACCESS6 0x25e0 +#define MC_SECURITY_CARVEOUT13_BOM_HI 0x2238 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS7 0x254c +#define MC_SECURITY_CARVEOUT9_CLIENT_FORCE_INTERNAL_ACCESS0 0x2118 +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS2 0x26f8 +#define MC_SECURITY_CARVEOUT17_CLIENT_ACCESS2 0x2388 +#define MC_SECURITY_CARVEOUT21_CFG0 0x24b0 +#define MC_SECURITY_CARVEOUT12_BOM 0x21e4 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS0 0x26a0 +#define MC_SECURITY_CARVEOUT6_CLIENT_ACCESS5 0x2024 +#define MC_SECURITY_CARVEOUT27_CLIENT_FORCE_INTERNAL_ACCESS4 0x26c8 +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS3 0x23a4 +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS1 0x27e4 +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS2 0x2298 +#define MC_SECURITY_CARVEOUT10_SIZE_128KB 0x214c +#define MC_SECURITY_CARVEOUT22_CLIENT_ACCESS2 0x2518 +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS6 0x2278 +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS7 0x259c +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS4 0x2038 +#define MC_SECURITY_CARVEOUT20_CLIENT_ACCESS7 0x24a4 +#define MC_SECURITY_CARVEOUT9_CLIENT_ACCESS0 0x2100 +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS7 0x23bc +#define MC_SECURITY_CARVEOUT31_CLIENT_ACCESS7 0x2814 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS3 0x2804 +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS6 0x2590 +#define MC_SECURITY_CARVEOUT23_CLIENT_FORCE_INTERNAL_ACCESS0 0x2578 +#define MC_SECURITY_CARVEOUT22_SIZE_128KB 0x250c +#define MC_SECURITY_CARVEOUT24_CLIENT_FORCE_INTERNAL_ACCESS4 0x25d8 +#define MC_SECURITY_CARVEOUT27_CLIENT_ACCESS1 0x26a4 +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS7 0x2094 +#define MC_SECURITY_CARVEOUT10_CLIENT_ACCESS2 0x2158 +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS0 0x27f8 +#define MC_SECURITY_CARVEOUT7_CLIENT_ACCESS2 0x2068 +#define MC_SECURITY_CARVEOUT23_CLIENT_ACCESS5 0x2574 +#define MC_SECURITY_CARVEOUT6_CLIENT_FORCE_INTERNAL_ACCESS7 0x204c +#define MC_SECURITY_CARVEOUT28_CLIENT_ACCESS5 0x2704 +#define MC_SECURITY_CARVEOUT7_CLIENT_FORCE_INTERNAL_ACCESS2 0x2080 +#define MC_SECURITY_CARVEOUT11_SIZE_128KB 0x219c +#define MC_SECURITY_CARVEOUT31_CLIENT_FORCE_INTERNAL_ACCESS1 0x27fc +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS7 0x20e4 +#define MC_SECURITY_CARVEOUT25_BOM_HI 0x25f8 +#define MC_SECURITY_CARVEOUT16_CLIENT_ACCESS6 0x2360 +#define MC_SECURITY_CARVEOUT31_BOM_HI 0x27d8 +#define MC_SECURITY_CARVEOUT18_CLIENT_FORCE_INTERNAL_ACCESS1 0x23ec +#define MC_SECURITY_CARVEOUT16_BOM_HI 0x2328 +#define MC_SECURITY_CARVEOUT20_CFG0 0x2460 +#define MC_SECURITY_CARVEOUT20_CLIENT_FORCE_INTERNAL_ACCESS3 0x2494 +#define MC_SECURITY_CARVEOUT21_CLIENT_FORCE_INTERNAL_ACCESS1 0x24dc +#define MC_SECURITY_CARVEOUT14_CLIENT_FORCE_INTERNAL_ACCESS0 0x22a8 +#define MC_SECURITY_CARVEOUT17_CLIENT_FORCE_INTERNAL_ACCESS4 0x23a8 +#define MC_SECURITY_CARVEOUT25_CLIENT_FORCE_INTERNAL_ACCESS2 0x2620 +#define MC_SECURITY_CARVEOUT25_CFG0 0x25f0 +#define MC_SECURITY_CARVEOUT8_CLIENT_ACCESS3 0x20bc +#define MC_SECURITY_CARVEOUT13_CLIENT_FORCE_INTERNAL_ACCESS3 0x2264 +#define MC_SECURITY_CARVEOUT10_CLIENT_FORCE_INTERNAL_ACCESS1 0x216c +#define MC_SECURITY_CARVEOUT14_CFG0 0x2280 +#define MC_SECURITY_CARVEOUT8_BOM 0x20a4 +#define MC_SECURITY_CARVEOUT22_CFG0 0x2500 +#define MC_SECURITY_CARVEOUT29_CLIENT_ACCESS4 0x2750 +#define MC_SECURITY_CARVEOUT26_SIZE_128KB 0x264c +#define MC_SECURITY_CARVEOUT13_CFG0 0x2230 +#define MC_SECURITY_CARVEOUT22_CLIENT_FORCE_INTERNAL_ACCESS6 0x2548 +#define MC_SECURITY_CARVEOUT26_BOM 0x2644 +#define MC_SECURITY_CARVEOUT29_CLIENT_FORCE_INTERNAL_ACCESS1 0x275c +#define MC_SECURITY_CARVEOUT26_CLIENT_ACCESS6 0x2680 +#define MC_SECURITY_CARVEOUT30_CLIENT_ACCESS6 0x27c0 +#define MC_SECURITY_CARVEOUT12_CLIENT_ACCESS5 0x2204 +#define MC_SECURITY_CARVEOUT17_SIZE_128KB 0x237c +#define MC_SECURITY_CARVEOUT19_CLIENT_FORCE_INTERNAL_ACCESS5 0x244c +#define MC_SECURITY_CARVEOUT14_CLIENT_ACCESS7 0x22c4 +#define MC_SECURITY_CARVEOUT18_CLIENT_ACCESS6 0x2400 +#define MC_SECURITY_CARVEOUT15_CLIENT_ACCESS6 0x2310 +#define MC_SECURITY_CARVEOUT15_CLIENT_FORCE_INTERNAL_ACCESS6 0x2318 +#define MC_ERR_APB_ASID_UPDATE_STATUS 0x9d0 +#define MC_DA_CONFIG0 0x9dc +#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8 +#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624 +#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16dc +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644 +#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000 +#define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAW 0x1504 +#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRA 0x1680 +#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8 +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162c +#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA1 0x1750 +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654 +#define MC_TXN_OVERRIDE_CONFIG_MIU6R 0x17f4 +#define MC_TXN_OVERRIDE_CONFIG_MIU5R 0x17e4 +#define MC_TBU_CLIENT_STEERING_CONFIG_RCEW 0x16a0 +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16c4 +#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470 +#define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALR 0x122c +#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0 +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178c +#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVW 0x126c +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774 +#define MC_TBU_CLIENT_STEERING_CONFIG_AXISR 0x1464 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0WRA 0x1608 +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16bc +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU1W 0x154c +#define MC_TBU_CLIENT_STEERING_CONFIG_SATAW 0x11ec +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3W 0x1700 +#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510 +#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTR 0x1254 +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8 +#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390 +#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAW 0x14b4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB 0x1670 +#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468 +#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_HOSTW 0x125c +#define MC_TXN_OVERRIDE_CONFIG_MIU6W 0x17fc +#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU6R 0x17f8 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179c +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764 +#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8 +#define MC_TXN_OVERRIDE_CONFIG_MIU7R 0x1008 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AW 0x16f0 +#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258 +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15f4 +#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438 +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17dc +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R 0x16c8 +#define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAR 0x16a8 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD1 0x1790 +#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRD 0x12a4 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176c +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166c +#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0 +#define MC_TBU_CLIENT_STEERING_CONFIG_ISPWA 0x1234 +#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0 +#define MC_TBU_CLIENT_STEERING_CONFIG_RCEDMAW 0x16b0 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE2AR 0x16e8 +#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420 +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16ec +#define MC_TBU_CLIENT_STEERING_CONFIG_VIW 0x1394 +#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPR 0x149c +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD 0x13c4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16d4 +#define MC_TBU_CLIENT_STEERING_CONFIG_EQOSR 0x1474 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDC 0x1648 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674 +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164c +#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCR 0x1314 +#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430 +#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548 +#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16cc +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU3R 0x1584 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU6W 0x4c00 +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17cc +#define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCW 0x148c +#define MC_TBU_CLIENT_STEERING_CONFIG_AONR 0x14bc +#define MC_TXN_OVERRIDE_CONFIG_MIU7W 0x1010 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU4W 0x15a0 +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDC 0x1678 +#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580 +#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158c +#define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAW 0x14d4 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU2R 0x1574 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU5R 0x17e8 +#define MC_TBU_CLIENT_STEERING_CONFIG_SATAR 0x10fc +#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400 +#define MC_TBU_CLIENT_STEERING_CONFIG_SESRD 0x1404 +#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWAB 0x133c +#define MC_TBU_CLIENT_STEERING_CONFIG_AXISW 0x146c +#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA 0x1618 +#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWRB 0x143c +#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE3R 0x16f8 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU3W 0x1590 +#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8 +#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4R 0x1708 +#define MC_TBU_CLIENT_STEERING_CONFIG_PTCR 0x1004 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1RDA1 0x1758 +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSWR 0x13cc +#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALWRB 0x1630 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338 +#define MC_TXN_OVERRIDE_CONFIG_ISPFALR 0x1228 +#define MC_TBU_CLIENT_STEERING_CONFIG_SCEW 0x14e4 +#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCWA 0x1324 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1W 0x16e0 +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175c +#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16b4 +#define MC_TBU_CLIENT_STEERING_CONFIG_HDAR 0x10ac +#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPW 0x14a4 +#define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPW 0x141c +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508 +#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664 +#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174c +#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE1R 0x16d8 +#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8 +#define MC_TXN_OVERRIDE_CONFIG_AXIAPR 0x1410 +#define MC_TBU_CLIENT_STEERING_CONFIG_ETRW 0x142c +#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16e4 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1FALRDB 0x1620 +#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310 +#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALRDB 0x1600 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU7W 0x1014 +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0FALWRB 0x1610 +#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694 +#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170c +#define MC_TBU_CLIENT_STEERING_CONFIG_VIFALR 0x15e8 +#define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD 0x1364 +#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0 +#define MC_TBU_CLIENT_STEERING_CONFIG_AONDMAR 0x14cc +#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA 0x1638 +#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220 +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA1 0x1770 +#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU5W 0x17f0 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDECSRD1 0x151c +#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17d4 +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614 +#define MC_TBU_CLIENT_STEERING_CONFIG_VICSRD1 0x1514 +#define MC_TBU_CLIENT_STEERING_CONFIG_BPMPDMAR 0x14ac +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0 +#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330 +#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161c +#define MC_TBU_CLIENT_STEERING_CONFIG_SESWR 0x140c +#define MC_TBU_CLIENT_STEERING_CONFIG_EQOSW 0x147c +#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8 +#define MC_TBU_CLIENT_STEERING_CONFIG_ETRR 0x1424 +#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169c +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318 +#define MC_TBU_CLIENT_STEERING_CONFIG_MPCORER 0x113c +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU0R 0x1534 +#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604 +#define MC_TBU_CLIENT_STEERING_CONFIG_XUSB_DEVR 0x1264 +#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15e4 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSRD 0x13f4 +#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16f4 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SWR 0x16c0 +#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171c +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R1 0x1780 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5W 0x1720 +#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCW 0x1334 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260 +#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538 +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160c +#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15ec +#define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA1 0x1798 +#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15fc +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA0RDA 0x15f8 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB1 0x1768 +#define MC_TBU_CLIENT_STEERING_CONFIG_APER 0x13d4 +#define MC_TBU_CLIENT_STEERING_CONFIG_ISPRA 0x1224 +#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16fc +#define MC_TBU_CLIENT_STEERING_CONFIG_DLA1WRA 0x1628 +#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRC 0x1690 +#define MC_TBU_CLIENT_STEERING_CONFIG_VICSWR 0x136c +#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165c +#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8 +#define MC_TBU_CLIENT_STEERING_CONFIG_AONW 0x14c4 +#define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAR 0x14ec +#define MC_TBU_CLIENT_STEERING_CONFIG_AXIAPR 0x1414 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDA 0x1668 +#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU4R 0x1598 +#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0 +#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408 +#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRA 0x1304 +#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSWR 0x12ac +#define MC_TXN_OVERRIDE_CONFIG_AXIAPW 0x1418 +#define MC_TBU_CLIENT_STEERING_CONFIG_TSECSRDB 0x1434 +#define MC_TXN_OVERRIDE_CONFIG_MIU4R 0x1594 +#define MC_TXN_OVERRIDE_CONFIG_MIU4W 0x159c +#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRB 0x1658 +#define MC_TBU_CLIENT_STEERING_CONFIG_RCER 0x1698 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1RDB1 0x1778 +#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0 +#define MC_TBU_CLIENT_STEERING_CONFIG_APEDMAR 0x14fc +#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0 +#define MC_TBU_CLIENT_STEERING_CONFIG_UFSHCR 0x1484 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU7R 0x100c +#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0 +#define MC_TBU_CLIENT_STEERING_CONFIG_MPCOREW 0x11cc +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE4W 0x1710 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0R1 0x17a0 +#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD1 0x1788 +#define MC_TBU_CLIENT_STEERING_CONFIG_HOST1XDMAR 0x10b4 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU2W 0x157c +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD1 0x17d8 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA1WRB 0x1688 +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE0W 0x16d0 +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684 +#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRA 0x1650 +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168c +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16a4 +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU1R 0x1544 +#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794 +#define MC_TBU_CLIENT_STEERING_CONFIG_ISPWB 0x123c +#define MC_TBU_CLIENT_STEERING_CONFIG_MIU0W 0x153c +#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8 +#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16ac +#define MC_TBU_CLIENT_STEERING_CONFIG_PCIE5R 0x1718 +#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488 +#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428 +#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8 +#define MC_TBU_CLIENT_STEERING_CONFIG_SDMMCRAB 0x131c +#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368 +#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158 +#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177c +#define MC_TBU_CLIENT_STEERING_CONFIG_SCER 0x14dc +#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163c +#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR1 0x150c +#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSWR 0x115c +#define MC_TBU_CLIENT_STEERING_CONFIG_NVJPGSWR 0x13fc +#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167c +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDA1 0x1760 +#define MC_TXN_OVERRIDE_CONFIG_MIU5W 0x17ec +#define MC_TBU_CLIENT_STEERING_CONFIG_VIFALW 0x15f0 +#define MC_TBU_CLIENT_STEERING_CONFIG_SCEDMAW 0x14f4 +#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SRD 0x17d0 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDEC1SWR 0x17e0 +#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVDISPLAYR 0x1494 +#define MC_TBU_CLIENT_STEERING_CONFIG_HDAW 0x11ac +#define MC_TBU_CLIENT_STEERING_CONFIG_NVENCSRD 0x10e4 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0RDB 0x1640 +#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268 +#define MC_TBU_CLIENT_STEERING_CONFIG_NVENC1SRD 0x16b8 +#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0 +#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704 +#define MC_TBU_CLIENT_STEERING_CONFIG_APEW 0x13dc +#define MC_TBU_CLIENT_STEERING_CONFIG_ISPFALW 0x1728 +#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0 +#define MC_TBU_CLIENT_STEERING_CONFIG_PVA0WRC 0x1660 +#define MC_TBU_ADR_MASK_0 0x1800 +#define MC_TBU_ADR_MASK_1 0x1804 +#define MC_TBU_ADR_MASK_2 0x18bc +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_0 0x1808 +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_1 0x180c +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_2 0x1810 +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_3 0x1814 +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_4 0x1818 +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_5 0x181c +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_6 0x18b0 +#define MC_CLIENT_TRAFFIC_TYPE_CONFIG_7 0x18b4 +#define MC_MC_TBU_TRANSACTION_ATTR_CTRL 0x18b8 +#define MC_CLIENT_ORDER_ID_27 0x2a6c +#define MC_CLIENT_ORDER_ID_13 0x2a34 +#define MC_CLIENT_ORDER_ID_9 0x2a24 +#define MC_CLIENT_ORDER_ID_4 0x2a10 +#define MC_CLIENT_ORDER_ID_10 0x2a28 +#define MC_CLIENT_ORDER_ID_21 0x2a54 +#define MC_CLIENT_ORDER_ID_26 0x2a68 +#define MC_CLIENT_ORDER_ID_17 0x2a44 +#define MC_CLIENT_ORDER_ID_15 0x2a3c +#define MC_CLIENT_ORDER_ID_6 0x2a18 +#define MC_CLIENT_ORDER_ID_30 0x2d00 +#define MC_CLIENT_ORDER_ID_18 0x2a48 +#define MC_CLIENT_ORDER_ID_5 0x2a14 +#define MC_CLIENT_ORDER_ID_23 0x2a5c +#define MC_CLIENT_ORDER_ID_29 0x2a74 +#define MC_CLIENT_ORDER_ID_14 0x2a38 +#define MC_CLIENT_ORDER_ID_24 0x2a60 +#define MC_CLIENT_ORDER_ID_3 0x2a0c +#define MC_CLIENT_ORDER_ID_19 0x2a4c +#define MC_CLIENT_ORDER_ID_7 0x2a1c +#define MC_CLIENT_ORDER_ID_0 0x2a00 +#define MC_CLIENT_ORDER_ID_2 0x2a08 +#define MC_CLIENT_ORDER_ID_16 0x2a40 +#define MC_CLIENT_ORDER_ID_22 0x2a58 +#define MC_CLIENT_ORDER_ID_12 0x2a30 +#define MC_CLIENT_ORDER_ID_28 0x2a70 +#define MC_CLIENT_ORDER_ID_31 0x2d04 +#define MC_CLIENT_ORDER_ID_25 0x2a64 +#define MC_CLIENT_ORDER_ID_20 0x2a50 +#define MC_CLIENT_ORDER_ID_8 0x2a20 +#define MC_HUB_PC_VC_ID_11 0x2aa4 +#define MC_HUB_PC_VC_ID_12 0x2aa8 +#define MC_HUB_PC_VC_ID_2 0x2a80 +#define MC_HUB_PC_VC_ID_10 0x2aa0 +#define MC_HUB_PC_VC_ID_6 0x2a90 +#define MC_HUB_PC_VC_ID_13 0x2d78 +#define MC_HUB_PC_VC_ID_1 0x2a7c +#define MC_HUB_PC_VC_ID_7 0x2a94 +#define MC_HUB_PC_VC_ID_0 0x2a78 +#define MC_HUB_PC_VC_ID_9 0x2a9c +#define MC_HUB_PC_VC_ID_5 0x2a8c +#define MC_HUB_PC_VC_ID_3 0x2a84 +#define MC_HUB_PC_VC_ID_8 0x2a98 +#define MC_HUB_PC_VC_ID_14 0x2d7c +#define MC_HUB_PC_VC_ID_4 0x2a88 +#define MC_COALESCE_CTRL 0x2930 +#define MC_CLIENT_COALESCE_CONFIG_0 0x2934 +#define MC_CLIENT_COALESCE_CONFIG_1 0x2938 +#define MC_CLIENT_COALESCE_CONFIG_2 0x293c +#define MC_CLIENT_COALESCE_CONFIG_3 0x2940 +#define MC_CLIENT_COALESCE_CONFIG_4 0x2944 +#define MC_CLIENT_COALESCE_CONFIG_5 0x2948 +#define MC_CLIENT_COALESCE_CONFIG_6 0x294c +#define MC_CLIENT_COALESCE_CONFIG_7 0x2950 +#define MC_HUB_VC_ARB_SEL 0x2954 +#define MC_MC_SMMU_ARB_MAX_OUTSTANDING_NISO 0x2958 +#define MC_MC_SMMU_ARB_MAX_OUTSTANDING_SISO 0x295c +#define MC_MC_SMMU_ARB_MAX_OUTSTANDING_ISO 0x2960 +#define MC_MC_SMMU_ARB_MAX_THROTTLE 0x2964 +#define MC_MC_SMMU_PTC2H_REQ_MAPPING_OVERRIDE 0x296c +#define MC_MC_SMMU_PTC2H_REQ_MAPPING 0x2970 +#define MC_COALESCE_ERR_STATUS 0x3000 +#define MC_COALESCE_ERR_ADR_HI 0x3004 +#define MC_COALESCE_ERR_ADR 0x3008 +#define MC_CLIENT_CCI_CAPABLE_0 0x1824 +#define MC_CLIENT_CCI_CAPABLE_1 0x1828 +#define MC_CLIENT_CCI_CAPABLE_2 0x182c +#define MC_CLIENT_CCI_CAPABLE_3 0x1830 +#define MC_CLIENT_CCI_CAPABLE_4 0x1834 +#define MC_CLIENT_CCI_CAPABLE_5 0x1838 +#define MC_CLIENT_CCI_CAPABLE_6 0x183c +#define MC_CLIENT_CCI_CAPABLE_8 0x1c34 +#define MC_CLIENT_CCI_CAPABLE_7 0x193c +#define MC_MAX_OUTSTANDING_CCI 0x1840 +#define MC_NV_CACHE_CONFIG 0x1844 +#define MC_NV_CACHE_HUB_MASK 0x184c +#define MC_SYSRAM_BOM 0x1850 +#define MC_SYSRAM_TOM 0x1854 +#define MC_SYSRAM_ADR_HI 0x1588 +#define MC_SYSRAM_REG_CTRL 0x185c +#define MC_MSSNVLINK_BOM 0x1860 +#define MC_MSSNVLINK_TOM 0x1864 +#define MC_MSSNVLINK_REG_CTRL 0x186c +#define MC_SYNCPOINT_BOM 0x1870 +#define MC_SYNCPOINT_TOM 0x1874 +#define MC_SYNCPOINT_REG_CTRL 0x187c +#define MC_ECC_CONTROL 0x1880 +#define MC_MSSNVLINK_IGPU_LATENCY_ALLOWANCE 0x1890 +#define MC_MSSNVLINK_DGPU_LATENCY_ALLOWANCE 0x1894 +#define MC_CIFLL_NVLRHP_LATENCY_ALLOWANCE 0x189c +#define MC_CLIENT_HOTRESET_STATUS_2 0x1898 +#define MC_CFG_WCAM_GOB_REMAP 0xed4 +#define MC_ECC_RAW_MODE_CONTROL 0xed8 +#define MC_ECC_CFG 0x1884 +#define MC_TR_BIT_CTL 0xed0 +#define MC_CH_INTSTATUS 0xe54 +#define MC_LATENCY_ALLOWANCE_WCAM 0xe5c +#define MC_CFG_WCAM 0xe60 +#define MC_WCAM_ENCR_KEY_STATUS 0xe64 +#define MC_WCAM_STATE 0xeb0 +#define MC_WCAM_IRQ_TEST 0xedc +#define MC_WCAM_IRQ_P0_STATUS0 0xee0 +#define MC_WCAM_IRQ_P0_STATUS1 0xee4 +#define MC_WCAM_IRQ_P1_STATUS0 0xee8 +#define MC_WCAM_IRQ_P1_STATUS1 0xeec +#define MC_ROC_DMA_R_PTSA_MIN 0xe68 +#define MC_ROC_DMA_R_PTSA_MAX 0xe6c +#define MC_ROC_DMA_R_PTSA_RATE 0xe70 +#define MC_RING1_WR_B_PTSA_MIN 0xe74 +#define MC_RING1_WR_B_PTSA_MAX 0xe78 +#define MC_RING1_WR_B_PTSA_RATE 0xe7c +#define MC_RING1_WR_NB_PTSA_MIN 0xe80 +#define MC_RING1_WR_NB_PTSA_MAX 0xe84 +#define MC_RING1_WR_NB_PTSA_RATE 0xe88 +#define MC_RING1_RD_B_PTSA_MIN 0xe8c +#define MC_RING1_RD_B_PTSA_MAX 0xe90 +#define MC_RING1_RD_B_PTSA_RATE 0xe94 +#define MC_RING1_RD_NB_PTSA_MIN 0xe98 +#define MC_RING1_RD_NB_PTSA_MAX 0xe9c +#define MC_RING1_RD_NB_PTSA_RATE 0xea0 +#define MC_FREE_BANK_QUEUES 0xea4 +#define MC_RING0_MT_FIFO_CREDITS 0xea8 +#define MC_LATENCY_ALLOWANCE_ROC_DMA_R_0 0xeac +#define MC_LATENCY_ALLOWANCE_CIFLL_WR_0 0x1100 +#define MC_CIFLL_NISO_PTSA_MIN 0x1104 +#define MC_CIFLL_NISO_PTSA_MAX 0x1108 +#define MC_CIFLL_NISO_PTSA_RATE 0x110c +#define MC_CIFLL_SISO_PTSA_MIN 0x1110 +#define MC_CIFLL_SISO_PTSA_MAX 0x1114 +#define MC_CIFLL_SISO_PTSA_RATE 0x1118 +#define MC_CIFLL_ISO_PTSA_MIN 0x111c +#define MC_CIFLL_ISO_PTSA_MAX 0x1120 +#define MC_CIFLL_ISO_PTSA_RATE 0x1124 +#define MC_CIFLL_RING0X_PTSA_MIN 0x1128 +#define MC_CIFLL_RING0X_PTSA_MAX 0x112c +#define MC_CIFLL_RING0X_PTSA_RATE 0x1130 +#define MC_CIFLL_CPU_RD_PRI_CTRL 0x1174 +#define MC_MEM_SCRUBBER_ECC_ADDR 0xf18 +#define MC_MEM_SCRUBBER_ECC_ADDR_HI 0xf1c +#define MC_MEM_SCRUBBER_ECC_REG_CTRL 0xf20 +#define MC_CONFIG_TSA_SINGLE_ARB_ENABLE 0xfe8 +#define MC_DBB_RINGFENCE_CTRL 0xfec +#define MC_DBB_RINGFENCE_STATUS 0xff0 +#define MC_CCITRX_ENABLE_CONFIG 0xf3c +#define MC_CCI_WR_LATENCY_ALLOWANCE_CONFIG 0xf40 +#define MC_EMEM_ARB_THROTTLE_CFG 0xf44 +#define MC_MSS_SYSRAM_EC_FEATURE 0x9000 +#define MC_MSS_SYSRAM_EC_SWRESET 0x9004 +#define MC_MSS_SYSRAM_EC_MISSIONERR_TYPE 0x9008 +#define MC_MSS_SYSRAM_EC_CURRENT_COUNTER_VALUE 0x900c +#define MC_MSS_SYSRAM_EC_MISSIONERR_USERVALUE 0x9010 +#define MC_MSS_SYSRAM_EC_MISSIONERR_INDEX 0x9014 +#define MC_MSS_SYSRAM_EC_CORRECTABLE_THRESHOLD 0x9018 +#define MC_MSS_SYSRAM_EC_MISSIONERR_INJECT_UNLOCK 0x901c +#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9030 +#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_FORCE 0x9034 +#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_STATUS 0x9038 +#define MC_MSS_SYSRAM_EC_ERRSLICE0_MISSIONERR_INJECT 0x903c +#define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_ENABLE 0x9040 +#define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_FORCE 0x9044 +#define MC_MSS_SYSRAM_EC_ERRSLICE0_LATENTERR_STATUS 0x9048 +#define MC_MSS_SYSRAM_EC_ERRSLICE0_COUNTER_RELOAD 0x9050 +#define MC_TCU_WRAP_EC_FEATURE 0x9100 +#define MC_TCU_WRAP_EC_SWRESET 0x9104 +#define MC_TCU_WRAP_EC_MISSIONERR_TYPE 0x9108 +#define MC_TCU_WRAP_EC_CURRENT_COUNTER_VALUE 0x910c +#define MC_TCU_WRAP_EC_MISSIONERR_USERVALUE 0x9110 +#define MC_TCU_WRAP_EC_MISSIONERR_INDEX 0x9114 +#define MC_TCU_WRAP_EC_CORRECTABLE_THRESHOLD 0x9118 +#define MC_TCU_WRAP_EC_MISSIONERR_INJECT_UNLOCK 0x911c +#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9130 +#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_FORCE 0x9134 +#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_STATUS 0x9138 +#define MC_TCU_WRAP_EC_ERRSLICE0_MISSIONERR_INJECT 0x913c +#define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_ENABLE 0x9140 +#define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_FORCE 0x9144 +#define MC_TCU_WRAP_EC_ERRSLICE0_LATENTERR_STATUS 0x9148 +#define MC_TCU_WRAP_EC_ERRSLICE0_COUNTER_RELOAD 0x9150 +#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9160 +#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_FORCE 0x9164 +#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_STATUS 0x9168 +#define MC_TCU_WRAP_EC_ERRSLICE1_MISSIONERR_INJECT 0x916c +#define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_ENABLE 0x9170 +#define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_FORCE 0x9174 +#define MC_TCU_WRAP_EC_ERRSLICE1_LATENTERR_STATUS 0x9178 +#define MC_TCU_WRAP_EC_ERRSLICE1_COUNTER_RELOAD 0x9180 +#define MC_MSS_SBS_EC_FEATURE 0x9200 +#define MC_MSS_SBS_EC_SWRESET 0x9204 +#define MC_MSS_SBS_EC_MISSIONERR_TYPE 0x9208 +#define MC_MSS_SBS_EC_CURRENT_COUNTER_VALUE 0x920c +#define MC_MSS_SBS_EC_MISSIONERR_USERVALUE 0x9210 +#define MC_MSS_SBS_EC_MISSIONERR_INDEX 0x9214 +#define MC_MSS_SBS_EC_CORRECTABLE_THRESHOLD 0x9218 +#define MC_MSS_SBS_EC_MISSIONERR_INJECT_UNLOCK 0x921c +#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9230 +#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_FORCE 0x9234 +#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_STATUS 0x9238 +#define MC_MSS_SBS_EC_ERRSLICE0_MISSIONERR_INJECT 0x923c +#define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_ENABLE 0x9240 +#define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_FORCE 0x9244 +#define MC_MSS_SBS_EC_ERRSLICE0_LATENTERR_STATUS 0x9248 +#define MC_MSS_SBS_EC_ERRSLICE0_COUNTER_RELOAD 0x9250 +#define MC_MCF_SLICE_EC_FEATURE 0x9300 +#define MC_MCF_SLICE_EC_SWRESET 0x9304 +#define MC_MCF_SLICE_EC_MISSIONERR_TYPE 0x9308 +#define MC_MCF_SLICE_EC_CURRENT_COUNTER_VALUE 0x930c +#define MC_MCF_SLICE_EC_MISSIONERR_USERVALUE 0x9310 +#define MC_MCF_SLICE_EC_MISSIONERR_INDEX 0x9314 +#define MC_MCF_SLICE_EC_CORRECTABLE_THRESHOLD 0x9318 +#define MC_MCF_SLICE_EC_MISSIONERR_INJECT_UNLOCK 0x931c +#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9330 +#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_FORCE 0x9334 +#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_STATUS 0x9338 +#define MC_MCF_SLICE_EC_ERRSLICE0_MISSIONERR_INJECT 0x933c +#define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_ENABLE 0x9340 +#define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_FORCE 0x9344 +#define MC_MCF_SLICE_EC_ERRSLICE0_LATENTERR_STATUS 0x9348 +#define MC_MCF_SLICE_EC_ERRSLICE0_COUNTER_RELOAD 0x9350 +#define MC_MCF_IREQX_EC_FEATURE 0x9400 +#define MC_MCF_IREQX_EC_SWRESET 0x9404 +#define MC_MCF_IREQX_EC_MISSIONERR_TYPE 0x9408 +#define MC_MCF_IREQX_EC_CURRENT_COUNTER_VALUE 0x940c +#define MC_MCF_IREQX_EC_MISSIONERR_INDEX 0x9414 +#define MC_MCF_IREQX_EC_CORRECTABLE_THRESHOLD 0x9418 +#define MC_MCF_IREQX_EC_MISSIONERR_INJECT_UNLOCK 0x941c +#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9430 +#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9434 +#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9438 +#define MC_MCF_IREQX_EC_ERRSLICE0_MISSIONERR_INJECT 0x943c +#define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9440 +#define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_FORCE 0x9444 +#define MC_MCF_IREQX_EC_ERRSLICE0_LATENTERR_STATUS 0x9448 +#define MC_MCF_IREQX_EC_ERRSLICE0_COUNTER_RELOAD 0x9450 +#define MC_MCF_IRSPX_EC_FEATURE 0x9500 +#define MC_MCF_IRSPX_EC_SWRESET 0x9504 +#define MC_MCF_IRSPX_EC_MISSIONERR_TYPE 0x9508 +#define MC_MCF_IRSPX_EC_CURRENT_COUNTER_VALUE 0x950c +#define MC_MCF_IRSPX_EC_MISSIONERR_USERVALUE 0x9510 +#define MC_MCF_IRSPX_EC_MISSIONERR_INDEX 0x9514 +#define MC_MCF_IRSPX_EC_CORRECTABLE_THRESHOLD 0x9518 +#define MC_MCF_IRSPX_EC_MISSIONERR_INJECT_UNLOCK 0x951c +#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9530 +#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9534 +#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9538 +#define MC_MCF_IRSPX_EC_ERRSLICE0_MISSIONERR_INJECT 0x953c +#define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9540 +#define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_FORCE 0x9544 +#define MC_MCF_IRSPX_EC_ERRSLICE0_LATENTERR_STATUS 0x9548 +#define MC_MCF_IRSPX_EC_ERRSLICE0_COUNTER_RELOAD 0x9550 +#define MC_MCF_OREQX_EC_FEATURE 0x9600 +#define MC_MCF_OREQX_EC_SWRESET 0x9604 +#define MC_MCF_OREQX_EC_MISSIONERR_TYPE 0x9608 +#define MC_MCF_OREQX_EC_CURRENT_COUNTER_VALUE 0x960c +#define MC_MCF_OREQX_EC_MISSIONERR_USERVALUE 0x9610 +#define MC_MCF_OREQX_EC_MISSIONERR_INDEX 0x9614 +#define MC_MCF_OREQX_EC_CORRECTABLE_THRESHOLD 0x9618 +#define MC_MCF_OREQX_EC_MISSIONERR_INJECT_UNLOCK 0x961c +#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9630 +#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9634 +#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9638 +#define MC_MCF_OREQX_EC_ERRSLICE0_MISSIONERR_INJECT 0x963c +#define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9640 +#define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_FORCE 0x9644 +#define MC_MCF_OREQX_EC_ERRSLICE0_LATENTERR_STATUS 0x9648 +#define MC_MCF_OREQX_EC_ERRSLICE0_COUNTER_RELOAD 0x9650 +#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9660 +#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_FORCE 0x9664 +#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_STATUS 0x9668 +#define MC_MCF_OREQX_EC_ERRSLICE1_MISSIONERR_INJECT 0x966c +#define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_ENABLE 0x9670 +#define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_FORCE 0x9674 +#define MC_MCF_OREQX_EC_ERRSLICE1_LATENTERR_STATUS 0x9678 +#define MC_MCF_OREQX_EC_ERRSLICE1_COUNTER_RELOAD 0x9680 +#define MC_MCF_ORSPX_EC_FEATURE 0x9700 +#define MC_MCF_ORSPX_EC_SWRESET 0x9704 +#define MC_MCF_ORSPX_EC_MISSIONERR_TYPE 0x9708 +#define MC_MCF_ORSPX_EC_CURRENT_COUNTER_VALUE 0x970c +#define MC_MCF_ORSPX_EC_MISSIONERR_INDEX 0x9714 +#define MC_MCF_ORSPX_EC_CORRECTABLE_THRESHOLD 0x9718 +#define MC_MCF_ORSPX_EC_MISSIONERR_INJECT_UNLOCK 0x971c +#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9730 +#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_FORCE 0x9734 +#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_STATUS 0x9738 +#define MC_MCF_ORSPX_EC_ERRSLICE0_MISSIONERR_INJECT 0x973c +#define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_ENABLE 0x9740 +#define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_FORCE 0x9744 +#define MC_MCF_ORSPX_EC_ERRSLICE0_LATENTERR_STATUS 0x9748 +#define MC_MCF_ORSPX_EC_ERRSLICE0_COUNTER_RELOAD 0x9750 +#define MC_CHANNEL_EC_FEATURE 0x9800 +#define MC_CHANNEL_EC_SWRESET 0x9804 +#define MC_CHANNEL_EC_MISSIONERR_TYPE 0x9808 +#define MC_CHANNEL_EC_CURRENT_COUNTER_VALUE 0x980c +#define MC_CHANNEL_EC_MISSIONERR_USERVALUE 0x9810 +#define MC_CHANNEL_EC_MISSIONERR_INDEX 0x9814 +#define MC_CHANNEL_EC_CORRECTABLE_THRESHOLD 0x9818 +#define MC_CHANNEL_EC_MISSIONERR_INJECT_UNLOCK 0x981c +#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9830 +#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_FORCE 0x9834 +#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_STATUS 0x9838 +#define MC_CHANNEL_EC_ERRSLICE0_MISSIONERR_INJECT 0x983c +#define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_ENABLE 0x9840 +#define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_FORCE 0x9844 +#define MC_CHANNEL_EC_ERRSLICE0_LATENTERR_STATUS 0x9848 +#define MC_CHANNEL_EC_ERRSLICE0_COUNTER_RELOAD 0x9850 +#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_ENABLE 0x9860 +#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_FORCE 0x9864 +#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_STATUS 0x9868 +#define MC_CHANNEL_EC_ERRSLICE1_MISSIONERR_INJECT 0x986c +#define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_ENABLE 0x9870 +#define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_FORCE 0x9874 +#define MC_CHANNEL_EC_ERRSLICE1_LATENTERR_STATUS 0x9878 +#define MC_CHANNEL_EC_ERRSLICE1_COUNTER_RELOAD 0x9880 +#define MC_HUB_EC_FEATURE 0x9900 +#define MC_HUB_EC_SWRESET 0x9904 +#define MC_HUB_EC_MISSIONERR_TYPE 0x9908 +#define MC_HUB_EC_CURRENT_COUNTER_VALUE 0x990c +#define MC_HUB_EC_MISSIONERR_USERVALUE 0x9910 +#define MC_HUB_EC_MISSIONERR_INDEX 0x9914 +#define MC_HUB_EC_CORRECTABLE_THRESHOLD 0x9918 +#define MC_HUB_EC_MISSIONERR_INJECT_UNLOCK 0x991c +#define MC_HUB_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9930 +#define MC_HUB_EC_ERRSLICE0_MISSIONERR_FORCE 0x9934 +#define MC_HUB_EC_ERRSLICE0_MISSIONERR_STATUS 0x9938 +#define MC_HUB_EC_ERRSLICE0_MISSIONERR_INJECT 0x993c +#define MC_HUB_EC_ERRSLICE0_LATENTERR_ENABLE 0x9940 +#define MC_HUB_EC_ERRSLICE0_LATENTERR_FORCE 0x9944 +#define MC_HUB_EC_ERRSLICE0_LATENTERR_STATUS 0x9948 +#define MC_HUB_EC_ERRSLICE0_COUNTER_RELOAD 0x9950 +#define MC_HUBC_EC_FEATURE 0x9a00 +#define MC_HUBC_EC_SWRESET 0x9a04 +#define MC_HUBC_EC_MISSIONERR_TYPE 0x9a08 +#define MC_HUBC_EC_CURRENT_COUNTER_VALUE 0x9a0c +#define MC_HUBC_EC_MISSIONERR_USERVALUE 0x9a10 +#define MC_HUBC_EC_MISSIONERR_INDEX 0x9a14 +#define MC_HUBC_EC_CORRECTABLE_THRESHOLD 0x9a18 +#define MC_HUBC_EC_MISSIONERR_INJECT_UNLOCK 0x9a1c +#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_ENABLE 0x9a30 +#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_FORCE 0x9a34 +#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_STATUS 0x9a38 +#define MC_HUBC_EC_ERRSLICE0_MISSIONERR_INJECT 0x9a3c +#define MC_HUBC_EC_ERRSLICE0_LATENTERR_ENABLE 0x9a40 +#define MC_HUBC_EC_ERRSLICE0_LATENTERR_FORCE 0x9a44 +#define MC_HUBC_EC_ERRSLICE0_LATENTERR_STATUS 0x9a48 +#define MC_HUBC_EC_ERRSLICE0_COUNTER_RELOAD 0x9a50 + +#endif -- cgit v1.2.2 From 996735a71af96a8e37ac32e1a5a83b8b682644e8 Mon Sep 17 00:00:00 2001 From: Hoang Pham Date: Tue, 16 May 2017 13:40:50 -0700 Subject: t19x: mce: Update mce_cc3_ctrl API This patch updates API for cc3 control. T19x does not require voltage parameter. JIRA TPM-1062 Change-Id: Ie38cf383efe190904330f4cead00237e4ad86414 Signed-off-by: Hoang Pham Reviewed-on: http://git-master/r/1483382 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Sitaraman Reviewed-by: svccoveritychecker GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt --- include/linux/t19x_mce.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/t19x_mce.h b/include/linux/t19x_mce.h index fcd611d94..e999bc9a7 100644 --- a/include/linux/t19x_mce.h +++ b/include/linux/t19x_mce.h @@ -27,7 +27,7 @@ int t19x_mce_read_cstate_stats(u32 state, u32 *stats); int t19x_mce_write_cstate_stats(u32 state, u32 stats); int t19x_mce_is_sc7_allowed(u32 state, u32 wake, u32 *allowed); int t19x_mce_online_core(int cpu); -int t19x_mce_cc3_ctrl(u32 freq, u32 volt, u8 enable); +int t19x_mce_cc3_ctrl(u32 ndiv, u8 enable); int t19x_mce_echo_data(u32 data, int *matched); int t19x_mce_read_versions(u32 *major, u32 *minor); int t19x_mce_enum_features(u64 *features); -- cgit v1.2.2 From 070123b6fdd34ce13739e22b8692e2971d3a7557 Mon Sep 17 00:00:00 2001 From: Sri Krishna chowdary Date: Wed, 1 Jun 2016 13:59:12 +0530 Subject: video: tegra: nvmap: support cvsram carveout cvram carveout should not be accessed by cpu and also should not be dma mapped. bug 1763257 Change-Id: Ib8908e735165b2b5d6d7a9cc8290a28c81ce97c6 Signed-off-by: Sri Krishna chowdary Reviewed-on: http://git-master/r/1156663 GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy --- include/linux/nvmap_t19x.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/linux/nvmap_t19x.h (limited to 'include/linux') diff --git a/include/linux/nvmap_t19x.h b/include/linux/nvmap_t19x.h new file mode 100644 index 000000000..44cd6c7b3 --- /dev/null +++ b/include/linux/nvmap_t19x.h @@ -0,0 +1,28 @@ +/* + * include/linux/nvmap_t19x.h + * + * structure declarations for nvmem and nvmap user-space ioctls + * + * Copyright (c) 2009-2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _LINUX_NVMAP_T19x_H +#define _LINUX_NVMAP_T19x_H + +#define NVMAP_HEAP_CARVEOUT_CVSRAM (1ul<<25) + +#endif /* _LINUX_NVMAP_T19x_H */ -- cgit v1.2.2 From 994e15b8b45cd7c209435a266537f8acda42d44e Mon Sep 17 00:00:00 2001 From: Sri Krishna chowdary Date: Thu, 23 Jun 2016 10:00:56 +0530 Subject: linux: nvmap_t19x: declare nvmap_register_cvsram_carveout This is needed for sanity testing cvsram carveout. bug 1763257 Change-Id: I5c22d6c9663598679f2e0d8000f3760337b05b3c Signed-off-by: Sri Krishna chowdary Reviewed-on: http://git-master/r/1170006 GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy --- include/linux/nvmap_t19x.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvmap_t19x.h b/include/linux/nvmap_t19x.h index 44cd6c7b3..bfe6cec5f 100644 --- a/include/linux/nvmap_t19x.h +++ b/include/linux/nvmap_t19x.h @@ -20,9 +20,15 @@ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ +#include +#include + #ifndef _LINUX_NVMAP_T19x_H #define _LINUX_NVMAP_T19x_H #define NVMAP_HEAP_CARVEOUT_CVSRAM (1ul<<25) +int nvmap_register_cvsram_carveout(struct device *dma_dev, + phys_addr_t base, size_t size); + #endif /* _LINUX_NVMAP_T19x_H */ -- cgit v1.2.2 From b93e5aefa726929278a8cac4a76dc6c9d93a8b28 Mon Sep 17 00:00:00 2001 From: Sri Krishna chowdary Date: Tue, 26 Jul 2016 09:15:20 +0530 Subject: video: tegra: nvmap: support gosmem initialization Also add nvmap_gosmem_fetch_cvdev_info() so that the cv components can fetch the information they need about the grid of semaphore memory. bug 200209819 Change-Id: I8ac5384a4240d118de54fb12913b61833e66a0bc Signed-off-by: Sri Krishna chowdary Reviewed-on: http://git-master/r/1190541 Reviewed-by: Prashant Gaikwad GVS: Gerrit_Virtual_Submit --- include/linux/nvmap_t19x.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvmap_t19x.h b/include/linux/nvmap_t19x.h index bfe6cec5f..59638aaf6 100644 --- a/include/linux/nvmap_t19x.h +++ b/include/linux/nvmap_t19x.h @@ -27,8 +27,18 @@ #define _LINUX_NVMAP_T19x_H #define NVMAP_HEAP_CARVEOUT_CVSRAM (1ul<<25) +#define NVMAP_HEAP_CARVEOUT_GOS (1ul<<24) int nvmap_register_cvsram_carveout(struct device *dma_dev, phys_addr_t base, size_t size); +struct cv_dev_info { + struct device_node *np; + struct sg_table *sgt; + int idx; /* index to use by firmware to identify the client */ + int count; /* number of sgt */ +}; + +struct cv_dev_info *nvmap_fetch_cv_dev_info(struct device *dev); + #endif /* _LINUX_NVMAP_T19x_H */ -- cgit v1.2.2 From 7c96a5d9539309f3f9a93040f1f492036486690c Mon Sep 17 00:00:00 2001 From: Sri Krishna chowdary Date: Tue, 25 Oct 2016 21:19:05 +0530 Subject: video: tegra: nvmap: Consider client coherency for cache ops Track the number of outstanding dma maps from non IO coherent clients of dmabuf and do cache maintenance only if the count is non zero. This patch assumes that the following sequence is followed for all clients is 1. dma_buf_map_attachment 2. cache maintenance for device 3. device does some oepration 4. cache maintenance for cpu 5. dma_buf_unmap_attachment Although this patch would work with dmabuf deferred unmapping feature, disabling deferred unmapping for non IO coherent clients will help avoid unnecessary cache maintenance. Add "nvidia,tegra194-carveouts" to compatible property of nvmap DT node to enable this feature. JIRA TMM-80 Change-Id: Ic06b4ae110b48f69705d535cbfd90a13313b170f Signed-off-by: Sri Krishna chowdary Reviewed-on: http://git-master/r/1242227 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- include/linux/nvmap_t19x.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvmap_t19x.h b/include/linux/nvmap_t19x.h index 59638aaf6..cf6b24fa1 100644 --- a/include/linux/nvmap_t19x.h +++ b/include/linux/nvmap_t19x.h @@ -41,4 +41,10 @@ struct cv_dev_info { struct cv_dev_info *nvmap_fetch_cv_dev_info(struct device *dev); +struct nvmap_handle_t19x { + atomic_t nc_pin; /* no. of pins from non io coherent devices */ +}; + +extern bool nvmap_version_t19x; + #endif /* _LINUX_NVMAP_T19x_H */ -- cgit v1.2.2 From 1cff492553513ed0e0b099a646a3bf2fde78929a Mon Sep 17 00:00:00 2001 From: Sri Krishna chowdary Date: Thu, 29 Dec 2016 17:17:24 +0530 Subject: video: tegra: nvmap: Support Gosmem initialization Add support for gosmem offset_dev. This can be used for allocating the individual semaphores from GoS. Also fix the following issues 1. Use rmem->phandle to retrieve DT node of gosmem as name is not reliable. 2. alloc sgt before setting buf as it leads to NULL dereference otherwise 3. Use same API to get cv_dev_info of a particular device. This improves code coverage and also fixes the incorrect sgt mapping. bug 200209819 Change-Id: I66f83a71c4a44350fea662da22d08308099df58c Signed-off-by: Sri Krishna chowdary Reviewed-on: http://git-master/r/1278215 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/nvmap_t19x.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/nvmap_t19x.h b/include/linux/nvmap_t19x.h index cf6b24fa1..0f1348b42 100644 --- a/include/linux/nvmap_t19x.h +++ b/include/linux/nvmap_t19x.h @@ -3,7 +3,7 @@ * * structure declarations for nvmem and nvmap user-space ioctls * - * Copyright (c) 2009-2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,6 +35,7 @@ int nvmap_register_cvsram_carveout(struct device *dma_dev, struct cv_dev_info { struct device_node *np; struct sg_table *sgt; + struct device offset_dev; /* used to alloc/free semaphore offsets within GoS */ int idx; /* index to use by firmware to identify the client */ int count; /* number of sgt */ }; -- cgit v1.2.2 From 592bc947bb088720081c12639836b326e0f377e2 Mon Sep 17 00:00:00 2001 From: Sri Krishna chowdary Date: Tue, 25 Apr 2017 19:39:34 +0530 Subject: video: tegra: nvmap: update copyright text Update copyright text as recommended by GPLv2 bug 200302395 Change-Id: I18d720ba152df43532ef16bb7bb0e95f00f683ea Signed-off-by: Sri Krishna chowdary Reviewed-on: http://git-master/r/1469581 Reviewed-by: Krishna Reddy Reviewed-by: Sachin Nikam --- include/linux/nvmap_t19x.h | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) (limited to 'include/linux') diff --git a/include/linux/nvmap_t19x.h b/include/linux/nvmap_t19x.h index 0f1348b42..5fa9bbcd8 100644 --- a/include/linux/nvmap_t19x.h +++ b/include/linux/nvmap_t19x.h @@ -5,19 +5,14 @@ * * Copyright (c) 2009-2017, NVIDIA CORPORATION. All rights reserved. * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. * - * This program is distributed in the hope that it will be useful, but WITHOUT + * This program is distributed in the hope it will be useful, but WITHOUT * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ #include -- cgit v1.2.2 From e555573dd7f8321817e9e7861cfb26591d63c6f1 Mon Sep 17 00:00:00 2001 From: Krishna Sitaraman Date: Tue, 30 May 2017 16:33:20 -0700 Subject: t194: mce: update cstats api This patch updates the cstats api to properly read the cpu power state statistics for t194. It also updates the cstats debugfs node to read and show all cpu power state statistics. JIRA: TPM-1059 Change-Id: I708dc9a22f9ee8765517cfd64aaab57385f98e05 Signed-off-by: Krishna Sitaraman Reviewed-on: https://git-master.nvidia.com/r/1492473 Reviewed-by: svccoveritychecker Reviewed-by: Alexander Van Brunt GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza --- include/linux/t19x_mce.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'include/linux') diff --git a/include/linux/t19x_mce.h b/include/linux/t19x_mce.h index e999bc9a7..b289a9f97 100644 --- a/include/linux/t19x_mce.h +++ b/include/linux/t19x_mce.h @@ -17,7 +17,14 @@ #ifndef _LINUX_TEGRA_MCE_H #define _LINUX_TEGRA_MCE_H -#define NVG_STAT_MAX_ENTRIES 5 +#define NVG_STAT_MAX_ENTRIES 10 +#define MCE_STAT_ID_SHIFT 16UL + +struct cstats_info { + char *name; /* name of the cstats */ + int id; /* NVG id */ + int units;/* No of cores/clusters/cluster groups */ +}; int t19x_mce_enter_cstate(u32 state, u32 wake_time); int t19x_mce_update_cstate_info(u32 cluster, u32 ccplex, -- cgit v1.2.2 From 2503f1a541e270b47ccc77ce2617d5ecd793566c Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 21 Aug 2017 22:49:39 +0530 Subject: iommu: arm-smmu: add support for NVLINK All physical address > 128 GB are treated as NVLINK addresses. Whenever user specify DMA attribute with NVLINK, we will set bit-37 of physical address so that it will be treated as NVLINK. Bug 1964471 Change-Id: I781ef6350e0b7ae3d793bd3592667f96e6a48cfe Signed-off-by: Pritesh Raithatha Reviewed-on: https://git-master.nvidia.com/r/1542855 Reviewed-by: svccoveritychecker Reviewed-by: Sachin Nikam GVS: Gerrit_Virtual_Submit --- include/linux/dma-override.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 include/linux/dma-override.h (limited to 'include/linux') diff --git a/include/linux/dma-override.h b/include/linux/dma-override.h new file mode 100644 index 000000000..ccc4b1a6c --- /dev/null +++ b/include/linux/dma-override.h @@ -0,0 +1,19 @@ +#ifndef _LINUX_DMA_MAPPING_OVERRIDE_H +#define _LINUX_DMA_MAPPING_OVERRIDE_H + +#include +#include +#include + +#define DMA_FOR_NVLINK (1 << 5) + +#define NVLINK_PHY_BIT 37 + +void dma_qualify_ioprot(enum dma_data_direction dir, unsigned long *ioprot); + +void dma_marshal_handle(enum dma_data_direction dir, dma_addr_t *handle); + +void dma_unmarshal_handle(enum dma_data_direction dir, dma_addr_t *handle); + +#endif + -- cgit v1.2.2 From 2d13da728797044bbd60b935fac156e6c73ab589 Mon Sep 17 00:00:00 2001 From: Sai Gurrappadi Date: Wed, 23 Aug 2017 17:43:45 -0700 Subject: video: tegra: host: Map buffers over NVLINK This patch adds a new relocation buffer type NVHOST_RELOC_TYPE_NVLINK. NVLINK reloc buffers will use DMA_FOR_NVLINK for the mapping direction so that the dma buf api knows that the buffer is being accessed over NVLINK. JIRA HOSTX-265 Change-Id: Ie8c388eb5fadae925c6c710b9854d2e74bf5f8f5 Signed-off-by: Sai Gurrappadi Reviewed-on: https://git-master.nvidia.com/r/1544522 Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/nvhost_ioctl_t194.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include/linux') diff --git a/include/linux/nvhost_ioctl_t194.h b/include/linux/nvhost_ioctl_t194.h index 6606c84dd..25bf0d205 100644 --- a/include/linux/nvhost_ioctl_t194.h +++ b/include/linux/nvhost_ioctl_t194.h @@ -28,4 +28,6 @@ enum nvhost_module_id_t194 { NVHOST_MODULE_NVDEC1 = 13, }; +#define NVHOST_RELOC_TYPE_NVLINK 3 + #endif -- cgit v1.2.2 From 2111b5f11d2115ed5876ba2ed552af6025a53299 Mon Sep 17 00:00:00 2001 From: Rohit Khanna Date: Wed, 6 Sep 2017 17:35:49 -0700 Subject: t194: mce: update nvg header to v6.1 This patch updates t194_nvg.h to v6.1 Bug 1987411 Change-Id: I3066a8d4ad461d17c3ed03bf8bbd29cd45631676 Signed-off-by: Rohit Khanna Reviewed-on: https://git-master.nvidia.com/r/1554072 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt --- include/linux/t194_nvg.h | 209 ++++++++++++++++++++++++++++++++++------------- 1 file changed, 150 insertions(+), 59 deletions(-) (limited to 'include/linux') diff --git a/include/linux/t194_nvg.h b/include/linux/t194_nvg.h index 32fae953d..23fb6c9bf 100644 --- a/include/linux/t194_nvg.h +++ b/include/linux/t194_nvg.h @@ -12,17 +12,25 @@ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -/** +/* * t194_nvg.h - Header for the NVIDIA Generic interface (NVG). * Official documentation for this interface is included as part * of the T194 TRM. */ +/* + * Current version - Major version increments may break backwards + * compatibility and binary compatibility. Minor version increments + * occur when there is only new functionality. + */ enum { TEGRA_NVG_VERSION_MAJOR = 6, - TEGRA_NVG_VERSION_MINOR = 0, + TEGRA_NVG_VERSION_MINOR = 1, }; typedef enum { @@ -33,34 +41,43 @@ typedef enum { TEGRA_NVG_CHANNEL_CSTATE_INFO = 4, TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5, TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6, - /* Value 7 reserved */ TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8, - /* Value 9 reserved */ TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10, TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11, - /* Values 12-42 reserved */ + TEGRA_NVG_CHANNEL_SHUTDOWN = 42, TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43, TEGRA_NVG_CHANNEL_ONLINE_CORE = 44, TEGRA_NVG_CHANNEL_CC3_CTRL = 45, + TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51, - /* 52 FREQ FEEDBACK */ + /* Above needs to be removed - Not supported */ TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, + TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, + TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58, + TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 60, + TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 61, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 62, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 63, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 64, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 65, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 66, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 67, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 68, + TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 69, TEGRA_NVG_CHANNEL_LAST_INDEX, } tegra_nvg_channel_id_t; typedef enum { - /* Value 0 reserved */ NVG_STAT_QUERY_SC7_ENTRIES = 1, - /* Values 2-5 reserved */ NVG_STAT_QUERY_CC6_ENTRIES = 6, NVG_STAT_QUERY_CG7_ENTRIES = 7, - /* Values 8-9 reserved */ NVG_STAT_QUERY_C6_ENTRIES = 10, - /* Values 11-13 reserved */ NVG_STAT_QUERY_C7_ENTRIES = 14, - /* Values 15-31 reserved */ NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32, NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41, NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46, @@ -92,124 +109,198 @@ typedef enum { TEGRA_NVG_SYSTEM_SC8 = 8, } tegra_nvg_system_sleep_state_t; -/* ------------------- */ -/* NVG Data subformats */ -/* ------------------- */ +/* --------------------------------------------------------------------------- + * NVG Data subformats + * --------------------------------------------------------------------------- + */ typedef union { uint64_t flat; struct nvg_version_channel_t { - uint64_t minor_version : 32; - uint64_t major_version : 32; + uint32_t minor_version : 32; + uint32_t major_version : 32; } bits; } nvg_version_data_t; typedef union nvg_channel_1_data_u { uint64_t flat; struct nvg_channel_1_data_s { - uint64_t perf_per_watt_mode : 1; - uint64_t reserved_63_1 : 63; + uint32_t perf_per_watt_mode : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; } bits; } nvg_channel_1_data_t; +typedef union { + uint64_t flat; + struct nvg_ccplex_cache_control_channel_t { + uint32_t gpu_ways : 5; + uint32_t reserved_7_5 : 3; + uint32_t gpu_only_ways : 5; + uint32_t reserved_31_13 : 19; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_ccplex_cache_control_channel_t; + typedef union nvg_channel_2_data_u { uint64_t flat; struct nvg_channel_2_data_s { - uint64_t reserved_1_0 : 2; - uint64_t battery_saver_mode : 1; - uint64_t reserved_63_3 : 61; + uint32_t reserved_1_0 : 2; + uint32_t battery_saver_mode : 1; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; } bits; } nvg_channel_2_data_t; typedef union { uint64_t flat; struct nvg_wake_time_channel_t { - uint64_t wake_time : 32; - uint64_t reserved_63_32 : 32; + uint32_t wake_time : 32; + uint32_t reserved_63_32 : 32; } bits; } nvg_wake_time_channel_t; typedef union { uint64_t flat; struct nvg_cstate_info_channel_t { - uint64_t cluster_state : 3; - uint64_t reserved_6_3 : 4; - uint64_t update_cluster : 1; - uint64_t cg_cstate : 3; - uint64_t reserved_14_11 : 4; - uint64_t update_cg : 1; - uint64_t system_cstate : 4; - uint64_t reserved_22_20 : 3; - uint64_t update_system : 1; - uint64_t reserved_30_24 : 7; - uint64_t update_wake_mask : 1; - uint64_t wake_mask : 32; + uint32_t cluster_state : 3; + uint32_t reserved_6_3 : 4; + uint32_t update_cluster : 1; + uint32_t cg_cstate : 3; + uint32_t reserved_14_11 : 4; + uint32_t update_cg : 1; + uint32_t system_cstate : 4; + uint32_t reserved_22_20 : 3; + uint32_t update_system : 1; + uint32_t reserved_30_24 : 7; + uint32_t update_wake_mask : 1; + uint32_t wake_mask : 32; } bits; } nvg_cstate_info_channel_t; typedef union { uint64_t flat; struct nvg_lower_bound_channel_t { - uint64_t crossover_value : 32; - uint64_t reserved_63_32 : 32; + uint32_t crossover_value : 32; + uint32_t reserved_63_32 : 32; } bits; } nvg_lower_bound_channel_t; - typedef union { uint64_t flat; struct nvg_cstate_stat_query_channel_t { - uint64_t unit_id : 4; - uint64_t reserved_15_4 : 12; - uint64_t stat_id : 16; - uint64_t reserved_63_32 : 32; + uint32_t unit_id : 4; + uint32_t reserved_15_4 : 12; + uint32_t stat_id : 16; + uint32_t reserved_63_32 : 32; } bits; } nvg_cstate_stat_query_channel_t; typedef union { uint64_t flat; struct nvg_is_sc7_allowed_channel_t { - uint64_t is_sc7_allowed : 1; - uint64_t reserved_63_32 : 63; + uint32_t is_sc7_allowed : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; } bits; } nvg_is_sc7_allowed_channel_t; - typedef union { uint64_t flat; struct nvg_core_online_channel_t { - uint64_t core_id : 4; - uint64_t reserved_63_4 : 60; + uint32_t core_id : 4; + uint32_t reserved_31_4 : 28; + uint32_t reserved_63_32 : 32; } bits; } nvg_core_online_channel_t; - typedef union { uint64_t flat; struct nvg_cc3_control_channel_t { - uint64_t freq_req : 8; - uint64_t reserved_30_8 : 23; - uint64_t enable : 1; - uint64_t reserved_63_32 : 32; + uint32_t freq_req : 8; + uint32_t reserved_30_8 : 23; + uint32_t enable : 1; + uint32_t reserved_63_32 : 32; } bits; } nvg_cc3_control_channel_t; +typedef enum { + TEGRA_NVG_CHANNEL_UPDATE_GSC_GSC_ALL = 0, + TEGRA_NVG_CHANNEL_UPDATE_GSC_GSC_1 = 1, + TEGRA_NVG_CHANNEL_UPDATE_GSC_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX, +} tegra_nvg_channel_update_gsc_gsc_enum_t; + typedef union { uint64_t flat; struct nvg_update_gsc_channel_t { - uint64_t gsc_enum : 16; - uint64_t reserved_63_16 : 48; + uint32_t gsc_enum : 16; + uint32_t reserved_31_16 : 16; + uint32_t reserved_63_32 : 32; } bits; } nvg_update_gsc_channel_t; typedef union { uint64_t flat; struct nvg_cache_inval_channel_t { - uint64_t cache_clean : 1; - uint64_t cache_clean_inval : 1; - uint64_t cache_clean_inval_tr : 1; - uint64_t reserved_63_3 : 61; + uint32_t cache_clean : 1; + uint32_t cache_clean_inval : 1; + uint32_t cache_clean_inval_tr : 1; + uint32_t reserved_31_3 : 29; + uint32_t reserved_63_32 : 32; } bits; } nvg_cache_inval_channel_t; -#endif /* T194_NVG_H */ +/* GSC type define */ +typedef enum { + TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2, + TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, + TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_DMCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_DMCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR_RESIZE = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BO_MTS_PACKAGE = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BO_MCE_PREBOOT = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM_IDX = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR_IDX = 35, +} tegra_nvg_gsc_index_t; + +typedef enum { + TEGRA_NVG_CROSSOVER_C6 = 0, + TEGRA_NVG_CROSSOVER_CC6 = 1, + TEGRA_NVG_CROSSOVER_CG7 = 2, +} tegra_nvg_crossover_index_t; + +typedef union { + uint64_t flat; + struct nvg_security_config_channel_t { + uint32_t strict_checking_enabled : 1; + uint32_t strict_checking_locked : 1; + uint32_t reserved_31_2 : 30; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_security_config_t; + +#endif + -- cgit v1.2.2 From 3432dcc91b4d238b9d76c8069a848ffe6c1fb5a2 Mon Sep 17 00:00:00 2001 From: Mika Liljeberg Date: Tue, 12 Sep 2017 17:24:08 +0300 Subject: platform: tegra: rce: remove vi5 dependency Remove dependency to vi5 driver. Provide an API to map RCE RM scratch area for a device that is not part of the same IO address domain. Check that the scratch area gets mapped to the correct base address (requires DT change). Bug 1975059 Signed-off-by: Mika Liljeberg Change-Id: I55158f880ff15e29776c8dfc5bc8c44aa4767ac5 Reviewed-on: https://git-master.nvidia.com/r/1558236 Reviewed-by: svc-mobile-coverity Reviewed-by: Ajith Kumar Reviewed-by: svccoveritychecker Reviewed-by: Jihoon Bang GVS: Gerrit_Virtual_Submit --- include/linux/tegra-rce-rm.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) create mode 100644 include/linux/tegra-rce-rm.h (limited to 'include/linux') diff --git a/include/linux/tegra-rce-rm.h b/include/linux/tegra-rce-rm.h new file mode 100644 index 000000000..a4c6fbb67 --- /dev/null +++ b/include/linux/tegra-rce-rm.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2017 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _LINUX_TEGRA_RCE_RM_H_ +#define _LINUX_TEGRA_RCE_RM_H_ + +#include +#include + +int rce_rm_map_carveout_for_device(struct platform_device *pdev, + struct device *dev, struct sg_table *sgt); + +#endif -- cgit v1.2.2 From 7f5a5487628dfca54a0135626551228e02deef24 Mon Sep 17 00:00:00 2001 From: Rohit Khanna Date: Wed, 4 Oct 2017 13:42:17 -0700 Subject: t194: mce: update nvg header to v6.1 This patch updates t194_nvg.h to v6.1 Bug 1987411 Bug 200351851 Change-Id: I454d1b4c34888388e876e1b29b017d06b4e7b3be Signed-off-by: Rohit Khanna Reviewed-on: https://git-master.nvidia.com/r/1573224 Reviewed-by: Krishna Sitaraman GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt --- include/linux/t194_nvg.h | 91 +++++++++++++++++++++--------------------------- 1 file changed, 39 insertions(+), 52 deletions(-) (limited to 'include/linux') diff --git a/include/linux/t194_nvg.h b/include/linux/t194_nvg.h index 23fb6c9bf..3cae5422e 100644 --- a/include/linux/t194_nvg.h +++ b/include/linux/t194_nvg.h @@ -50,8 +50,6 @@ typedef enum { TEGRA_NVG_CHANNEL_CC3_CTRL = 45, TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49, TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50, - TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51, - /* Above needs to be removed - Not supported */ TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53, TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54, TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55, @@ -99,8 +97,8 @@ typedef enum { } tegra_nvg_cluster_sleep_state_t; typedef enum { - TEGRA_NVG_CCPLEX_CG0 = 0, - TEGRA_NVG_CCPLEX_CG7 = 1, + TEGRA_NVG_CG_CG0 = 0, + TEGRA_NVG_CG_CG7 = 1, } tegra_nvg_cluster_group_sleep_state_t; typedef enum { @@ -224,38 +222,6 @@ typedef union { } bits; } nvg_cc3_control_channel_t; -typedef enum { - TEGRA_NVG_CHANNEL_UPDATE_GSC_GSC_ALL = 0, - TEGRA_NVG_CHANNEL_UPDATE_GSC_GSC_1 = 1, - TEGRA_NVG_CHANNEL_UPDATE_GSC_GSC_31 = 31, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, - TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, - TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX, -} tegra_nvg_channel_update_gsc_gsc_enum_t; - -typedef union { - uint64_t flat; - struct nvg_update_gsc_channel_t { - uint32_t gsc_enum : 16; - uint32_t reserved_31_16 : 16; - uint32_t reserved_63_32 : 32; - } bits; -} nvg_update_gsc_channel_t; - -typedef union { - uint64_t flat; - struct nvg_cache_inval_channel_t { - uint32_t cache_clean : 1; - uint32_t cache_clean_inval : 1; - uint32_t cache_clean_inval_tr : 1; - uint32_t reserved_31_3 : 29; - uint32_t reserved_63_32 : 32; - } bits; -} nvg_cache_inval_channel_t; - -/* GSC type define */ typedef enum { TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0, TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1, @@ -269,28 +235,41 @@ typedef enum { TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9, TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10, TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11, - TEGRA_NVG_CHANNEL_UPDATE_GSC_SE = 12, - TEGRA_NVG_CHANNEL_UPDATE_GSC_DMCE = 13, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_DMCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13, + TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15, TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16, + TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17, TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19, TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20, + TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21, TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22, TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR_RESIZE = 24, - TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 25, + TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24, + TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25, TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BO_MTS_PACKAGE = 28, - TEGRA_NVG_CHANNEL_UPDATE_GSC_BO_MCE_PREBOOT = 29, - TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM_IDX = 34, - TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR_IDX = 35, -} tegra_nvg_gsc_index_t; + TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27, + TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29, + TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30, + TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31, + TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32, + TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33, + TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34, + TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35, + TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX, +} tegra_nvg_channel_update_gsc_gsc_enum_t; -typedef enum { - TEGRA_NVG_CROSSOVER_C6 = 0, - TEGRA_NVG_CROSSOVER_CC6 = 1, - TEGRA_NVG_CROSSOVER_CG7 = 2, -} tegra_nvg_crossover_index_t; +typedef union { + uint64_t flat; + struct nvg_update_ccplex_gsc_channel_t { + uint32_t gsc_enum : 16; + uint32_t reserved_31_16 : 16; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_update_ccplex_gsc_channel_t; typedef union { uint64_t flat; @@ -302,5 +281,13 @@ typedef union { } bits; } nvg_security_config_t; -#endif +typedef union { + uint64_t flat; + struct nvg_shutdown_channel_t { + uint32_t reboot : 1; + uint32_t reserved_31_1 : 31; + uint32_t reserved_63_32 : 32; + } bits; +} nvg_shutdown_t; +#endif -- cgit v1.2.2 From 09153e17a136ca2842b637b8b49629241144ef5d Mon Sep 17 00:00:00 2001 From: Rohit Khanna Date: Wed, 22 Feb 2017 13:42:07 -0800 Subject: ras: add arm64_ras driver Add a driver to handle MCA/RAS errors. The driver allows you to handle Correctable errors using FHI or Fault Handling Interrupt. The driver provides an API for CPU sepcific RAS drivers to register callbacks in case of FHI. When FHI occurs, the FHI ISR goes through the list of registered callbacks and executes them. Bug 1814444 Bug 200319716 Change-Id: I9cd14466ae9e3672807e1a21637503800ab2b657 Signed-off-by: Rohit Khanna Reviewed-on: https://git-master.nvidia.com/r/1258400 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/arm64_ras.h | 90 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 include/linux/arm64_ras.h (limited to 'include/linux') diff --git a/include/linux/arm64_ras.h b/include/linux/arm64_ras.h new file mode 100644 index 000000000..7acc506a1 --- /dev/null +++ b/include/linux/arm64_ras.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +struct ras_error { + char *name; + u16 error_code; +}; + +struct error_record { + struct list_head node; + char *name; + u64 errx; + u8 processed; + u64 err_ctrl; + struct ras_error *errors; +}; + +#define RAS_BIT(_bit_) (1ULL << (_bit_)) +#define RAS_MASK(_msb_, _lsb_) \ + ((RAS_BIT(_msb_+1) - 1ULL) & ~(RAS_BIT(_lsb_) - 1ULL)) +#define RAS_EXTRACT(_x_, _msb_, _lsb_) \ + ((_x_ & RAS_MASK(_msb_, _lsb_)) >> _lsb_) + +#define RAS_CTL_CFI RAS_BIT(8) +#define RAS_CTL_UE RAS_BIT(4) +#define RAS_CTL_ED RAS_BIT(0) + +#define ERRi_STATUS_UET ((RAS_BIT(20)) | (RAS_BIT(21))) +#define ERRi_STATUS_CE ((RAS_BIT(24)) | (RAS_BIT(25))) +#define ERRi_STATUS_MV RAS_BIT(26) +#define ERRi_STATUS_OF RAS_BIT(27) +#define ERRi_STATUS_UE RAS_BIT(29) +#define ERRi_STATUS_VALID RAS_BIT(30) +#define ERRi_STATUS_AV RAS_BIT(31) + +#define ERRi_PFGCTL_CDNEN RAS_BIT(31) +#define ERRi_PFGCTL_R RAS_BIT(30) +#define ERRi_PFGCTL_CE RAS_BIT(6) +#define ERRi_PFGCTL_UC RAS_BIT(1) + +#define ERRi_PFGCDN_CDN_1 0x1 + +#define get_error_status_ce(_x_) RAS_EXTRACT(_x_, 25, 24) +#define get_error_status_ierr(_x_) RAS_EXTRACT(_x_, 15, 8) +#define get_error_status_serr(_x_) RAS_EXTRACT(_x_, 7, 0) + +struct ras_fhi_callback { + struct list_head node; + void (*fn)(void); +}; + +/* Macros for reading ID_PFR0 - RAS Version field */ +#define PFR0_RAS_SHIFT 28 +#define PFR0_RAS_MASK (0xf << PFR0_RAS_SHIFT) +#define PFR0_RAS(pfr0) \ + (((pfr0) & PFR0_RAS_MASK) >> PFR0_RAS_SHIFT) +#define PFR0_RAS_VERSION_1 0x1 + +/* RAS functions needed by ras_carmel driver */ +int is_ras_ready(void); +int is_this_ras_cpu(void); +int is_ras_cpu(int cpu); +u64 ras_read_error_status(void); +u64 ras_read_errselr(void); +u64 ras_read_pfg_control(void); +u64 ras_read_pfg_cdn(void); +u64 ras_read_error_control(void); +void ras_write_error_control(u64 err_ctl); +void ras_write_error_status(u64 status); +void ras_write_error_addr(u64 addr); +void ras_write_error_misc0(u64 misc0); +void ras_write_error_misc1(u64 misc1); +void ras_write_error_statustrigger(u64 status); +void ras_write_pfg_control(u64 pfg_ctl); +void ras_write_pfg_cdn(u64 pfg_cdn); +void ras_write_errselr(u64 errx); +void print_error_record(struct error_record *record, u64 status); +void register_fhi_callback(struct ras_fhi_callback *callback); +void unregister_fhi_callback(struct ras_fhi_callback *callback); + -- cgit v1.2.2 From 6431ad3e99f4bcb0ff3b130049306cb16ff9fab8 Mon Sep 17 00:00:00 2001 From: Rohit Khanna Date: Tue, 21 Feb 2017 15:41:45 -0800 Subject: tegra: add RAS support for Carmel Add a driver to handle Carmel RAS errors per core, per core cluster and per CCPLEX. Carmel supports two kinds of errors : Correctable and Uncorrectable Correctable errors are handled using Fault Handling Interrupt (FHI) and Uncorrectable errors using SERROR. For FHI, the driver registers and defines callbacks that interface with arm64_ras driver. For SError, driver registers callbacks and defines callbacks that interface with arm64_traps driver. Driver also provides support for triggering RAS errors for SW testing via debugfs nodes. Bug 1814444 Bug 200319716 Change-Id: Id543bf62d8d00317cc1aaea9fd8c65dd03c29822 Signed-off-by: Rohit Khanna Reviewed-on: https://git-master.nvidia.com/r/1309006 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/platform/tegra/carmel_ras.h | 159 ++++++++++++++++++++++++++++++ 1 file changed, 159 insertions(+) create mode 100644 include/linux/platform/tegra/carmel_ras.h (limited to 'include/linux') diff --git a/include/linux/platform/tegra/carmel_ras.h b/include/linux/platform/tegra/carmel_ras.h new file mode 100644 index 000000000..66176252e --- /dev/null +++ b/include/linux/platform/tegra/carmel_ras.h @@ -0,0 +1,159 @@ +/* + * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +/* Error Records Per Core */ +/* ERR_CTLR bits for IFU */ +#define RAS_IFU_CTL_ITLB_SNP_ERR RAS_BIT(43) +#define RAS_IFU_CTL_MITGRP_ERR RAS_BIT(42) +#define RAS_IFU_CTL_IMQDP_ERR RAS_BIT(41) +#define RAS_IFU_CTL_L2UC_ERR RAS_BIT(40) +#define RAS_IFU_CTL_ICTPSNP_ERR RAS_BIT(38) +#define RAS_IFU_CTL_ICMHSNP_ERR RAS_BIT(37) +#define RAS_IFU_CTL_ITLBP_ERR RAS_BIT(36) +#define RAS_IFU_CTL_THERR_ERR RAS_BIT(35) +#define RAS_IFU_CTL_ICDP_ERR RAS_BIT(34) +#define RAS_IFU_CTL_ICTP_ERR RAS_BIT(33) +#define RAS_IFU_CTL_ICMH_ERR RAS_BIT(32) + +/* ERR_CTLR bits for RET_JSR */ +#define ERR_CTL_RET_JSR_FRFP_ERR RAS_BIT(35) +#define ERR_CTL_RET_JSR_IRFP_ERR RAS_BIT(34) +#define ERR_CTL_RET_JSR_GB_ERR RAS_BIT(33) +#define ERR_CTL_RET_JSR_TO_ERR RAS_BIT(32) + +/* ERR_CTLR bits for MTS_JSR */ +#define ERR_CTL_MTS_JSR_ERRUC_ERR RAS_BIT(32) +#define ERR_CTL_MTS_JSR_ERRC_ERR RAS_BIT(33) +#define ERR_CTL_MTS_JSR_NAFLL_ERR RAS_BIT(34) +#define ERR_CTL_MTS_JSR_CARVE_ERR RAS_BIT(35) +#define ERR_CTL_MTS_JSR_CRAB_ERR RAS_BIT(36) +#define ERR_CTL_MTS_JSR_MMIO_ERR RAS_BIT(37) + +/* ERR_CTLR bits for LSD_1 */ +#define ERR_CTL_LSD1_CCTP_ERR RAS_BIT(32) +#define ERR_CTL_LSD1_MCMH_ERR RAS_BIT(33) +#define ERR_CTL_LSD1_CCMH_ERR RAS_BIT(34) +#define ERR_CTL_LSD1_MCDLP_ERR RAS_BIT(35) +#define ERR_CTL_LSD1_CCDLECC_S_ERR RAS_BIT(36) +#define ERR_CTL_LSD1_CCDLECC_D_ERR RAS_BIT(37) +#define ERR_CTL_LSD1_CCDSECC_S_ERR RAS_BIT(38) +#define ERR_CTL_LSD1_CCDSECC_D_ERR RAS_BIT(39) +#define ERR_CTL_LSD1_CCDEMLECC_ERR RAS_BIT(40) + +/* ERR_CTLR bits for LSD_2 */ +#define ERR_CTL_LSD2_BTCCVPP_ERR RAS_BIT(32) +#define ERR_CTL_LSD2_BTCCPPP_ERR RAS_BIT(33) +#define ERR_CTL_LSD2_BTCCMH_ERR RAS_BIT(34) +#define ERR_CTL_LSD2_VRCDECC_S_ERR RAS_BIT(35) +#define ERR_CTL_LSD2_VRCDECC_D_ERR RAS_BIT(36) +#define ERR_CTL_LSD2_VRCDP_ERR RAS_BIT(37) +#define ERR_CTL_LSD2_MCDEP_ERR RAS_BIT(38) +#define ERR_CTL_LSD2_CCDEECC_S_ERR RAS_BIT(39) +#define ERR_CTL_LSD2_CCDEECC_D_ERR RAS_BIT(40) +#define ERR_CTL_LSD2_L2REQ_UNCORR_ERR RAS_BIT(41) + +/* ERR_CTLR bits for LSD_3 */ +#define ERR_CTL_LSD3_L2TLBP_ERR RAS_BIT(32) +#define ERR_CTL_LSD3_LATENT_ERR RAS_BIT(63) + +/* Error records per CCPLEX */ +/* ERR_CTLR bits for CMU:CCPMU or DPMU*/ +#define ERR_CTL_DPMU_DMCE_CRAB_ACC_ERR RAS_BIT(32) +#define ERR_CTL_DPMU_CRAB_ACC_ERR RAS_BIT(33) +#define ERR_CTL_DPMU_DMCE_UCODE_ERR RAS_BIT(35) + +/* ERR_CTLR bits for SCF:IOB*/ +#define ERR_CTL_SCFIOB_REQ_PAR_ERR RAS_BIT(41) +#define ERR_CTL_SCFIOB_PUT_PAR_ERR RAS_BIT(40) +#define ERR_CTL_SCFIOB_PUT_CECC_ERR RAS_BIT(32) +#define ERR_CTL_SCFIOB_PUT_UECC_ERR RAS_BIT(39) +#define ERR_CTL_SCFIOB_EVP_ERR RAS_BIT(33) +#define ERR_CTL_SCFIOB_TBX_ERR RAS_BIT(34) +#define ERR_CTL_SCFIOB_CRI_ERR RAS_BIT(35) +#define ERR_CTL_SCFIOB_MMCRAB_ERR RAS_BIT(37) +#define ERR_CTL_SCFIOB_IHI_ERR RAS_BIT(36) +#define ERR_CTL_SCFIOB_CBB_ERR RAS_BIT(38) + +/* ERR_CTLR bits for SCF:SNOC*/ +#define ERR_CTL_SCFSNOC_CPE_TO_ERR RAS_BIT(34) +#define ERR_CTL_SCFSNOC_CPE_RSP_ERR RAS_BIT(35) +#define ERR_CTL_SCFSNOC_CPE_REQ_ERR RAS_BIT(36) +#define ERR_CTL_SCFSNOC_DVMU_TO_ERR RAS_BIT(37) +#define ERR_CTL_SCFSNOC_DVMU_PAR_ERR RAS_BIT(38) +#define ERR_CTL_SCFSNOC_MISC_CECC_ERR RAS_BIT(32) +#define ERR_CTL_SCFSNOC_MISC_UECC_ERR RAS_BIT(39) +#define ERR_CTL_SCFSNOC_MISC_PAR_ERR RAS_BIT(40) +#define ERR_CTL_SCFSNOC_MISC_RSP_ERR RAS_BIT(41) +#define ERR_CTL_SCFSNOC_CARVEOUT_ERR RAS_BIT(33) + +/* ERR_CTLR bits for CMU:CTU*/ +#define ERR_CTL_CMUCTU_TRCDMA_PAR_ERR RAS_BIT(32) +#define ERR_CTL_CMUCTU_MCF_PAR_ERR RAS_BIT(33) +#define ERR_CTL_CMUCTU_TRL_PAR_ERR RAS_BIT(34) +#define ERR_CTL_CMUCTU_CTU_DATA_PAR_ERR RAS_BIT(35) +#define ERR_CTL_CMUCTU_TAG_PAR_ERR RAS_BIT(36) +#define ERR_CTL_CMUCTU_CTU_SNP_ERR RAS_BIT(37) +#define ERR_CTL_CMUCTU_TRCDMA_REQ_ERR RAS_BIT(38) + +/* ERR_CTLR bits for SCF:L3_* */ +#define ERR_CTL_SCFL3_ADR_ERR RAS_BIT(38) +#define ERR_CTL_SCFL3_PERR_ERR RAS_BIT(40) +#define ERR_CTL_SCFL3_UECC_ERR RAS_BIT(39) +#define ERR_CTL_SCFL3_CECC_ERR RAS_BIT(41) +#define ERR_CTL_SCFL3_MH_CAM_ERR RAS_BIT(37) +#define ERR_CTL_SCFL3_MH_TAG_ERR RAS_BIT(36) +#define ERR_CTL_SCFL3_UNSUPP_REQ_ERR RAS_BIT(35) +#define ERR_CTL_SCFL3_PROT_ERR RAS_BIT(34) +#define ERR_CTL_SCFL3_TO_ERR RAS_BIT(33) + +/* ERR_CTLR bits for SCFCMU_CLOCKS */ +#define ERR_CTL_SCFCMU_LUT0_PAR_ERR RAS_BIT(32) +#define ERR_CTL_SCFCMU_LUT1_PAR_ERR RAS_BIT(33) +#define ERR_CTL_SCFCMU_ADC0_MON_ERR RAS_BIT(34) +#define ERR_CTL_SCFCMU_ADC1_MON_ERR RAS_BIT(35) + +/* Error records per Core Cluster */ +/* ERR_CTLR bits for L2 */ +#define ERR_CTL_L2_MLD_ECCC_ERR RAS_BIT(32) +#define ERR_CTL_L2_URD_ECCC_ERR RAS_BIT(33) +#define ERR_CTL_L2_MLD_ECCUD_ERR RAS_BIT(34) +#define ERR_CTL_L2_MLD_ECCUC_ERR RAS_BIT(36) +#define ERR_CTL_L2_URD_ECCUC_ERR RAS_BIT(37) +#define ERR_CTL_L2_NTDP_ERR RAS_BIT(38) +#define ERR_CTL_L2_URDP RAS_BIT(39) +#define ERR_CTL_L2_MLTP_ERR RAS_BIT(40) +#define ERR_CTL_L2_NTTP_ERR RAS_BIT(41) +#define ERR_CTL_L2_URTP_ERR RAS_BIT(42) +#define ERR_CTL_L2_L2MH_ERR RAS_BIT(43) +#define ERR_CTL_L2_CORE02L2CP_ERR RAS_BIT(44) +#define ERR_CTL_L2_CORE12L2CP_ERR RAS_BIT(45) +#define ERR_CTL_L2_SCF2L2C_ECCC_ERR RAS_BIT(46) +#define ERR_CTL_L2_SCF2L2C_ECCU_ERR RAS_BIT(47) +#define ERR_CTL_L2_SCF2L2C_FILLDATAP_ERR RAS_BIT(48) +#define ERR_CTL_L2_SCF2L2C_ADVNOTP_ERR RAS_BIT(49) +#define ERR_CTL_L2_SCF2L2C_REQRSPP_ERR RAS_BIT(50) +#define ERR_CTL_L2_SCF2L2C_DECWTERR_ERR RAS_BIT(51) +#define ERR_CTL_L2_SCF2L2C_DECRDERR_ERR RAS_BIT(52) +#define ERR_CTL_L2_SCF2L2C_SLVWTERR_ERR RAS_BIT(53) +#define ERR_CTL_L2_SCF2L2C_SLVRDERR_ERR RAS_BIT(54) +#define ERR_CTL_L2_L2PCL_ERR RAS_BIT(55) +#define ERR_CTL_L2_URTTO_ERR RAS_BIT(56) + +/* ERR_CTLR bits for MMU */ +#define ERR_CTL_MMU_ACPERR_ERR RAS_BIT(32) +#define ERR_CTL_MMU_WCPERR_ERR RAS_BIT(34) + +/* ERR_CTLR bits for CLUSTER_CLOCKS */ +#define ERR_CTL_CC_FREQ_MON_ERR RAS_BIT(32) -- cgit v1.2.2 From 3f2f968721c70f9b7a43e6b945d5f4c6ea1ff21a Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Fri, 29 Sep 2017 11:43:10 +0530 Subject: tegra: t19x: add CBB driver support This driver adds support for handling SError's from Control Backbone(CBB). In case of SError from a bridge within CBB, the driver checks ErrVld status of all three Error Logger's of CBB. It then prints debug information like Error Code, Error Description, Master, Address, AXI ID etc for failed transaction using ErrLog registers of CBB's error logger having ErrVld status set. Bug 200340783 Change-Id: I4e4d079e9853ba0c4cdc5d9c0eb8854478862b75 Signed-off-by: Sumit Gupta Reviewed-on: https://git-master.nvidia.com/r/1570826 GVS: Gerrit_Virtual_Submit Reviewed-by: Rohit Khanna Reviewed-by: Alexander Van Brunt Reviewed-by: mobile promotions Tested-by: mobile promotions --- include/linux/platform/tegra/tegra_cbb.h | 344 +++++++++++++++++++++++++++++++ 1 file changed, 344 insertions(+) create mode 100644 include/linux/platform/tegra/tegra_cbb.h (limited to 'include/linux') diff --git a/include/linux/platform/tegra/tegra_cbb.h b/include/linux/platform/tegra/tegra_cbb.h new file mode 100644 index 000000000..d2c0072ee --- /dev/null +++ b/include/linux/platform/tegra/tegra_cbb.h @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#define OFF_ERRLOGGER_0_ID_COREID_0 0x00000000 +#define OFF_ERRLOGGER_0_ID_REVISIONID_0 0x00000004 +#define OFF_ERRLOGGER_0_FAULTEN_0 0x00000008 +#define OFF_ERRLOGGER_0_ERRVLD_0 0x0000000c +#define OFF_ERRLOGGER_0_ERRCLR_0 0x00000010 +#define OFF_ERRLOGGER_0_ERRLOG0_0 0x00000014 +#define OFF_ERRLOGGER_0_ERRLOG1_0 0x00000018 +#define OFF_ERRLOGGER_0_RESERVED_00_0 0x0000001c +#define OFF_ERRLOGGER_0_ERRLOG3_0 0x00000020 +#define OFF_ERRLOGGER_0_ERRLOG4_0 0x00000024 +#define OFF_ERRLOGGER_0_ERRLOG5_0 0x00000028 +#define OFF_ERRLOGGER_0_STALLEN_0 0x00000038 + +#define OFF_ERRLOGGER_1_ID_COREID_0 0x00000080 +#define OFF_ERRLOGGER_1_ID_REVISIONID_0 0x00000084 +#define OFF_ERRLOGGER_1_FAULTEN_0 0x00000088 +#define OFF_ERRLOGGER_1_ERRVLD_0 0x0000008c +#define OFF_ERRLOGGER_1_ERRCLR_0 0x00000090 +#define OFF_ERRLOGGER_1_ERRLOG0_0 0x00000094 +#define OFF_ERRLOGGER_1_ERRLOG1_0 0x00000098 +#define OFF_ERRLOGGER_1_RESERVED_00_0 0x0000009c +#define OFF_ERRLOGGER_1_ERRLOG3_0 0x000000A0 +#define OFF_ERRLOGGER_1_ERRLOG4_0 0x000000A4 +#define OFF_ERRLOGGER_1_ERRLOG5_0 0x000000A8 +#define OFF_ERRLOGGER_1_STALLEN_0 0x000000b8 + +#define OFF_ERRLOGGER_2_ID_COREID_0 0x00000100 +#define OFF_ERRLOGGER_2_ID_REVISIONID_0 0x00000104 +#define OFF_ERRLOGGER_2_FAULTEN_0 0x00000108 +#define OFF_ERRLOGGER_2_ERRVLD_0 0x0000010c +#define OFF_ERRLOGGER_2_ERRCLR_0 0x00000110 +#define OFF_ERRLOGGER_2_ERRLOG0_0 0x00000114 +#define OFF_ERRLOGGER_2_ERRLOG1_0 0x00000118 +#define OFF_ERRLOGGER_2_RESERVED_00_0 0x0000011c +#define OFF_ERRLOGGER_2_ERRLOG3_0 0x00000120 +#define OFF_ERRLOGGER_2_ERRLOG4_0 0x00000124 +#define OFF_ERRLOGGER_2_ERRLOG5_0 0x00000128 +#define OFF_ERRLOGGER_2_STALLEN_0 0x00000138 + + +#define CBBNOC_BIT(_bit_) (1ULL << (_bit_)) +#define CBBNOC_MASK(_msb_, _lsb_) \ + ((CBBNOC_BIT(_msb_+1) - 1) & ~(CBBNOC_BIT(_lsb_) - 1)) +#define CBBNOC_EXTRACT(_x_, _msb_, _lsb_) \ + ((_x_ & CBBNOC_MASK(_msb_, _lsb_)) >> _lsb_) + + +#define get_cbb_errlog0_trans_opc(_x_) CBBNOC_EXTRACT(_x_, 4, 1) +#define get_cbb_errlog0_code(_x_) CBBNOC_EXTRACT(_x_, 10, 8) +#define get_cbb_errlog0_src(_x_) CBBNOC_EXTRACT(_x_, 27, 16) + +#define get_cbb_errlog5_axi_id(_x_) CBBNOC_EXTRACT(_x_, 30, 23) +#define get_cbb_errlog5_mstr_id(_x_) CBBNOC_EXTRACT(_x_, 22, 19) +#define get_cbb_errlog5_vqc(_x_) CBBNOC_EXTRACT(_x_, 18, 17) +#define get_cbb_errlog5_grpsec(_x_) CBBNOC_EXTRACT(_x_, 16, 10) +#define get_cbb_errlog5_falconsec(_x_) CBBNOC_EXTRACT(_x_, 9, 8) +#define get_cbb_errlog5_axprot(_x_) CBBNOC_EXTRACT(_x_, 7, 5) +#define get_cbb_errlog5_non_modify(_x_) CBBNOC_EXTRACT(_x_, 4, 4) +#define get_cbb_errlog5_axcache(_x_) CBBNOC_EXTRACT(_x_, 3, 0) + +#define get_cbb_routeid_initflow(_x_) CBBNOC_EXTRACT(_x_, 23, 20) +#define get_cbb_routeid_targflow(_x_) CBBNOC_EXTRACT(_x_, 19, 16) +#define get_cbb_routeid_targsubrange(_x_) CBBNOC_EXTRACT(_x_, 15, 9) +#define get_cbb_routeid_seqid(_x_) CBBNOC_EXTRACT(_x_, 8, 0) + + +struct tegra_cbbnoc_errors { + char *errcode; + char *src; + char *type; +}; + +struct tegra_noc_packet_header { + bool lock; // [0] + u8 opc; // [4:1] + u8 errcode;// [10:8]= RD, RDW, RDL, RDX, WR, WRW, WRC, PRE, URG + u16 len1; // [27:16] + bool format; // [31] = 1 -> FlexNoC versions 2.7 & above +}; + +struct tegra_cbb_routeid { + u8 initflow; // [23:20] + u16 targflow; // [19:16] + u8 targ_subrange; // [15:09] + u16 seqid; // [08:00] +}; + + +struct tegra_cbb_errlog_record { + struct list_head node; + struct serr_hook *callback; + char *name; + phys_addr_t start; + void __iomem *vaddr; + u32 errlog0; + u32 errlog1; + u32 errlog2; + u32 errlog3; + u32 errlog4; + u32 errlog5; + u32 errlog6; //RESERVED + u32 errlog7; //RESERVED + u32 errlog8; //RESERVED + unsigned int (*errvld)(void __iomem *addr); + void (*errclr)(void __iomem *addr); + void (*faulten)(void __iomem *addr); + void (*stallen)(void __iomem *addr); + struct tegra_cbbnoc_errors *errors; + struct tegra_lookup_noc_aperture *noc_aperture; + int max_noc_aperture; +}; + +struct tegra_lookup_noc_aperture { + u8 initflow; + u8 targflow; + u8 targ_subrange; + u8 init_mapping; + u32 init_localaddress; + u8 targ_mapping; + u32 targ_localaddress; +}; + +struct tegra_cbb_bridge_data { + char *name; + unsigned int (*errvld)(void __iomem *addr); + void (*errclr)(void __iomem *addr); + void (*faulten)(void __iomem *addr); + void (*stallen)(void __iomem *addr); + struct tegra_cbbnoc_errors *errors; + struct tegra_lookup_noc_aperture *noc_aperture; + int max_error; + int max_noc_aperture; +}; + + +/* + * NOC aperture lookup table as per file "cbb_central_noc_Structure.info". + * Fields: + * Init flow, Targ flow, Targ subrange, Init mapping, Init localAddress, Targ mapping, Targ localAddress + * ----------------------------------------------------------------------------------------------------- + */ + +static struct tegra_lookup_noc_aperture t194_lookup_noc_aperture[] = { + { 0x0, 0x0, 0x00, 0x0, 0x02300000, 0, 0x0 }, + { 0x0, 0x1, 0x00, 0x0, 0x02003000, 0, 0x02003000 }, + { 0x0, 0x1, 0x01, 0x0, 0x02006000, 2, 0x02006000 }, + { 0x0, 0x1, 0x02, 0x0, 0x02016000, 3, 0x02016000 }, + { 0x0, 0x1, 0x03, 0x0, 0x0201d000, 4, 0x0201d000 }, + { 0x0, 0x1, 0x04, 0x0, 0x0202b000, 6, 0x0202b000 }, + { 0x0, 0x1, 0x05, 0x0, 0x02434000, 20, 0x02434000 }, + { 0x0, 0x1, 0x06, 0x0, 0x02436000, 21, 0x02436000 }, + { 0x0, 0x1, 0x07, 0x0, 0x02438000, 22, 0x02438000 }, + { 0x0, 0x1, 0x08, 0x0, 0x02445000, 24, 0x02445000 }, + { 0x0, 0x1, 0x09, 0x0, 0x02446000, 25, 0x02446000 }, + { 0x0, 0x1, 0x0a, 0x0, 0x02004000, 1, 0x02004000 }, + { 0x0, 0x1, 0x0b, 0x0, 0x0201e000, 5, 0x0201e000 }, + { 0x0, 0x1, 0x0c, 0x0, 0x0202c000, 7, 0x0202c000 }, + { 0x0, 0x1, 0x0d, 0x0, 0x02204000, 8, 0x02204000 }, + { 0x0, 0x1, 0x0e, 0x0, 0x02214000, 9, 0x02214000 }, + { 0x0, 0x1, 0x0f, 0x0, 0x02224000, 10, 0x02224000 }, + { 0x0, 0x1, 0x10, 0x0, 0x02234000, 11, 0x02234000 }, + { 0x0, 0x1, 0x11, 0x0, 0x02244000, 12, 0x02244000 }, + { 0x0, 0x1, 0x12, 0x0, 0x02254000, 13, 0x02254000 }, + { 0x0, 0x1, 0x13, 0x0, 0x02264000, 14, 0x02264000 }, + { 0x0, 0x1, 0x14, 0x0, 0x02274000, 15, 0x02274000 }, + { 0x0, 0x1, 0x15, 0x0, 0x02284000, 16, 0x02284000 }, + { 0x0, 0x1, 0x16, 0x0, 0x0243a000, 23, 0x0243a000 }, + { 0x0, 0x1, 0x17, 0x0, 0x02370000, 17, 0x02370000 }, + { 0x0, 0x1, 0x18, 0x0, 0x023d0000, 18, 0x023d0000 }, + { 0x0, 0x1, 0x19, 0x0, 0x023e0000, 19, 0x023e0000 }, + { 0x0, 0x1, 0x1a, 0x0, 0x02450000, 26, 0x02450000 }, + { 0x0, 0x1, 0x1b, 0x0, 0x02460000, 27, 0x02460000 }, + { 0x0, 0x1, 0x1c, 0x0, 0x02490000, 28, 0x02490000 }, + { 0x0, 0x1, 0x1d, 0x0, 0x03130000, 31, 0x03130000 }, + { 0x0, 0x1, 0x1e, 0x0, 0x03160000, 32, 0x03160000 }, + { 0x0, 0x1, 0x1f, 0x0, 0x03270000, 33, 0x03270000 }, + { 0x0, 0x1, 0x20, 0x0, 0x032e0000, 35, 0x032e0000 }, + { 0x0, 0x1, 0x21, 0x0, 0x03300000, 36, 0x03300000 }, + { 0x0, 0x1, 0x22, 0x0, 0x13090000, 40, 0x13090000 }, + { 0x0, 0x1, 0x23, 0x0, 0x20120000, 43, 0x20120000 }, + { 0x0, 0x1, 0x24, 0x0, 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}, + { 0x0, 0x9, 0x00, 0x0, 0x10000000, 0, 0x10000000 }, + { 0x0, 0xA, 0x00, 0x0, 0x22000000, 0, 0x22000000 } +}; + -- cgit v1.2.2