From b375771412149a259fe3ea8cea017b7f5f59b9ca Mon Sep 17 00:00:00 2001 From: Jay Bhukhanwala Date: Wed, 18 Oct 2017 09:56:13 -0700 Subject: video: tegra: dp: Add pc2-disabled binding Since the support for post-cursor2 programming is optional as per the Display Port 1.2 standard, we derive a platform's willingness to support it via a device tree property TDS-2806 Change-Id: Ibab71287c398db8b8700f0e2d480c5234e5a79f0 Signed-off-by: Jay Bhukhanwala Reviewed-on: https://git-master.nvidia.com/r/1581311 Reviewed-by: Shu Zhong Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ujwal Patel --- include/linux/platform/tegra/cpu-tegra.h | 109 +++++++++++++++++++++++++++++++ include/linux/platform/tegra/cpu_emc.h | 25 +++++++ 2 files changed, 134 insertions(+) create mode 100644 include/linux/platform/tegra/cpu-tegra.h create mode 100644 include/linux/platform/tegra/cpu_emc.h (limited to 'include/linux') diff --git a/include/linux/platform/tegra/cpu-tegra.h b/include/linux/platform/tegra/cpu-tegra.h new file mode 100644 index 000000000..4a21ec288 --- /dev/null +++ b/include/linux/platform/tegra/cpu-tegra.h @@ -0,0 +1,109 @@ +/* + * linux/platform/tegra/cpu-tegra.h + * + * Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef __MACH_TEGRA_CPU_TEGRA_H +#define __MACH_TEGRA_CPU_TEGRA_H + +#include +#include + +unsigned int tegra_getspeed(unsigned int cpu); +int tegra_update_cpu_speed(unsigned long rate); +int tegra_cpu_set_speed_cap(unsigned int *speed_cap); +int tegra_cpu_set_speed_cap_locked(unsigned int *speed_cap); +void tegra_cpu_set_volt_cap(unsigned int cap); + +#if defined(CONFIG_TEGRA_CPUQUIET) && defined(CONFIG_TEGRA_CLUSTER_CONTROL) +int tegra_auto_hotplug_init(struct mutex *cpulock); +void tegra_auto_hotplug_exit(void); +void tegra_auto_hotplug_governor(unsigned int cpu_freq, bool suspend); +#else +static inline int tegra_auto_hotplug_init(struct mutex *cpu_lock) +{ return 0; } +static inline void tegra_auto_hotplug_exit(void) +{ } +static inline void tegra_auto_hotplug_governor(unsigned int cpu_freq, + bool suspend) +{ } +#endif + +#ifdef CONFIG_CPU_FREQ +struct cpufreq_frequency_table; + +/** + * freq_table: List of frequencies allowed for cpu. + * throttle_lowest_index: Lowest throttling frequency index. + * throttle_highest_index: Highest throttling frequency index. + * suspend_index: Suspend frequency index. + * preserve_across_suspend: Preserve cpu frequency even after suspend + * for restoring during resume. + */ +struct tegra_cpufreq_table_data { + struct cpufreq_frequency_table *freq_table; + int throttle_lowest_index; + int throttle_highest_index; + int suspend_index; + bool preserve_across_suspend; +}; +struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void); +unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate); +int tegra_update_mselect_rate(unsigned long cpu_rate); +#if defined(CONFIG_ARCH_TEGRA_210_SOC) +unsigned long tegra_emc_cpu_limit(unsigned long cpu_rate); +#else +static inline unsigned long tegra_emc_cpu_limit(unsigned long cpu_rate) +{ return 0; } +#endif +int tegra_suspended_target(unsigned int target_freq); +#else +static inline unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate) +{ return 0; } +static inline int tegra_suspended_target(unsigned int target_freq) +{ return -ENOSYS; } +#endif + +#if defined(CONFIG_CPU_FREQ) && defined(CONFIG_TEGRA_EDP_LIMITS) +int tegra_update_cpu_edp_limits(void); +int tegra_cpu_reg_mode_force_normal(bool force); +#else +static inline int tegra_update_cpu_edp_limits(void) +{ return 0; } +static inline int tegra_cpu_reg_mode_force_normal(bool force) +{ return 0; } +#endif + +#ifdef CONFIG_TEGRA_CPU_VOLT_CAP +struct tegra_cooling_device *tegra_vc_get_cdev(void); +#else +static inline struct tegra_cooling_device *tegra_vc_get_cdev(void) +{ return NULL; } +#endif + +#ifdef CONFIG_TEGRA_HMP_CLUSTER_CONTROL +unsigned long lp_to_virtual_gfreq(unsigned long lp_freq); +int tegra_cpu_volt_cap_apply(int *cap_idx, int new_idx, int level); +#else +static inline unsigned long lp_to_virtual_gfreq(unsigned long freq) +{ return freq; } +static inline int tegra_cpu_volt_cap_apply(int *cap_idx, int new_idx, int level) +{ return -ENOSYS; } +#endif + +#endif /* __MACH_TEGRA_CPU_TEGRA_H */ diff --git a/include/linux/platform/tegra/cpu_emc.h b/include/linux/platform/tegra/cpu_emc.h new file mode 100644 index 000000000..004578939 --- /dev/null +++ b/include/linux/platform/tegra/cpu_emc.h @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _LINUX_TEGRA_CPU_EMC_H +#define _LINUX_TEGRA_CPU_EMC_H + +struct device_node *of_get_scaling_node(const char *name); +int enable_cpu_emc_clk(void); +void disable_cpu_emc_clk(void); +void set_cpu_to_emc_freq(u32 cpu_freq); + +#endif -- cgit v1.2.2