From 2ecc028edf2c7c4d7c038aeaf0ee861b6c2b8305 Mon Sep 17 00:00:00 2001 From: Ken Adams Date: Fri, 25 Jul 2014 16:47:24 -0400 Subject: gpu: nvgpu: gp10b headers first cut. just to get started... Change-Id: I3682909f9ac0a5395ec834046789356f53d0c47d Signed-off-by: Ken Adams Reviewed-on: http://git-master/r/447753 --- drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h | 105 + drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h | 109 + drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h | 85 + drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 181 ++ drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 221 ++ drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 509 ++++ drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h | 141 + drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 57 + drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 1153 +++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 3173 ++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 281 ++ drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 217 ++ drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 469 +++ drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h | 145 + .../gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h | 69 + drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h | 141 + drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 805 +++++ drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 385 +++ drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 217 ++ drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h | 101 + drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 137 + drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 289 ++ 22 files changed, 8990 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h new file mode 100644 index 000000000..e443738fd --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_bus_gp10b_h_ +#define _hw_bus_gp10b_h_ + +static inline u32 bus_bar1_block_r(void) +{ + return 0x00001704; +} +static inline u32 bus_bar1_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar1_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar1_block_mode_virtual_f(void) +{ + return 0x80000000; +} +static inline u32 bus_bar1_block_ptr_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 bus_intr_0_r(void) +{ + return 0x00001100; +} +static inline u32 bus_intr_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +static inline u32 bus_intr_en_0_r(void) +{ + return 0x00001140; +} +static inline u32 bus_intr_en_0_pri_squash_m(void) +{ + return 0x1 << 1; +} +static inline u32 bus_intr_en_0_pri_fecserr_m(void) +{ + return 0x1 << 2; +} +static inline u32 bus_intr_en_0_pri_timeout_m(void) +{ + return 0x1 << 3; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h new file mode 100644 index 000000000..cd5265b33 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ccsr_gp10b_h_ +#define _hw_ccsr_gp10b_h_ + +static inline u32 ccsr_channel_inst_r(u32 i) +{ + return 0x00800000 + i*8; +} +static inline u32 ccsr_channel_inst__size_1_v(void) +{ + return 0x00000200; +} +static inline u32 ccsr_channel_inst_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 ccsr_channel_inst_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_false_f(void) +{ + return 0x0; +} +static inline u32 ccsr_channel_inst_bind_true_f(void) +{ + return 0x80000000; +} +static inline u32 ccsr_channel_r(u32 i) +{ + return 0x00800004 + i*8; +} +static inline u32 ccsr_channel__size_1_v(void) +{ + return 0x00000200; +} +static inline u32 ccsr_channel_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ccsr_channel_enable_set_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 ccsr_channel_enable_set_true_f(void) +{ + return 0x400; +} +static inline u32 ccsr_channel_enable_clr_true_f(void) +{ + return 0x800; +} +static inline u32 ccsr_channel_status_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ccsr_channel_busy_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h new file mode 100644 index 000000000..640453ceb --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_chiplet_pwr_gp10b_h_ +#define _hw_chiplet_pwr_gp10b_h_ + +static inline u32 chiplet_pwr_gpcs_weight_6_r(void) +{ + return 0x0010e018; +} +static inline u32 chiplet_pwr_gpcs_weight_7_r(void) +{ + return 0x0010e01c; +} +static inline u32 chiplet_pwr_gpcs_config_1_r(void) +{ + return 0x0010e03c; +} +static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void) +{ + return 0x1; +} +static inline u32 chiplet_pwr_fbps_weight_0_r(void) +{ + return 0x0010e100; +} +static inline u32 chiplet_pwr_fbps_weight_1_r(void) +{ + return 0x0010e104; +} +static inline u32 chiplet_pwr_fbps_config_1_r(void) +{ + return 0x0010e13c; +} +static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void) +{ + return 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h new file mode 100644 index 000000000..6339cf5b6 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ctxsw_prog_gp10b_h_ +#define _hw_ctxsw_prog_gp10b_h_ + +static inline u32 ctxsw_prog_fecs_header_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_main_image_patch_count_o(void) +{ + return 0x00000010; +} +static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) +{ + return 0x00000014; +} +static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_main_image_zcull_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_main_image_pm_o(void) +{ + return 0x00000028; +} +static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) +{ + return 0x0000002c; +} +static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_main_image_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) +{ + return 0x600dc0de; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_o(void) +{ + return 0x000000f4; +} +static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) +{ + return 0x000000f8; +} +static inline u32 ctxsw_prog_local_magic_value_o(void) +{ + return 0x000000fc; +} +static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) +{ + return 0xad0becab; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) +{ + return 0x000000ec; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) +{ + return 0x00000100; +} +static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) +{ + return 0x00000002; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h new file mode 100644 index 000000000..9dacabce5 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h @@ -0,0 +1,221 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fb_gp10b_h_ +#define _hw_fb_gp10b_h_ + +static inline u32 fb_fbhub_num_active_ltcs_r(void) +{ + return 0x00100800; +} +static inline u32 fb_mmu_ctrl_r(void) +{ + return 0x00100c80; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 fb_mmu_invalidate_pdb_r(void) +{ + return 0x00100cb8; +} +static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 fb_mmu_invalidate_r(void) +{ + return 0x00100cbc; +} +static inline u32 fb_mmu_invalidate_all_va_true_f(void) +{ + return 0x1; +} +static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) +{ + return 0x2; +} +static inline u32 fb_mmu_invalidate_trigger_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_trigger_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 fb_mmu_invalidate_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 fb_mmu_invalidate_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fb_mmu_invalidate_trigger_true_f(void) +{ + return 0x80000000; +} +static inline u32 fb_mmu_debug_wr_r(void) +{ + return 0x00100cc8; +} +static inline u32 fb_mmu_debug_wr_aperture_s(void) +{ + return 2; +} +static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_m(void) +{ + return 0x3 << 0; +} +static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_wr_vol_true_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_debug_wr_vol_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_debug_wr_addr_v(u32 r) +{ + return (r >> 4) & 0xfffffff; +} +static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_rd_r(void) +{ + return 0x00100ccc; +} +static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_vol_false_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_debug_rd_addr_v(u32 r) +{ + return (r >> 4) & 0xfffffff; +} +static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) +{ + return 0x0000000c; +} +static inline u32 fb_mmu_debug_ctrl_r(void) +{ + return 0x00100cc4; +} +static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 fb_mmu_vpr_info_r(void) +{ + return 0x00100cd0; +} +static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_vpr_info_fetch_false_v(void) +{ + return 0x00000000; +} +static inline u32 fb_mmu_vpr_info_fetch_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h new file mode 100644 index 000000000..764c1b6c6 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -0,0 +1,509 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fifo_gp10b_h_ +#define _hw_fifo_gp10b_h_ + +static inline u32 fifo_bar1_base_r(void) +{ + return 0x00002254; +} +static inline u32 fifo_bar1_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_bar1_base_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_bar1_base_valid_false_f(void) +{ + return 0x0; +} +static inline u32 fifo_bar1_base_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_runlist_base_r(void) +{ + return 0x00002270; +} +static inline u32 fifo_runlist_base_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 fifo_runlist_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 fifo_runlist_r(void) +{ + return 0x00002274; +} +static inline u32 fifo_runlist_engine_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 fifo_eng_runlist_base_r(u32 i) +{ + return 0x00002280 + i*8; +} +static inline u32 fifo_eng_runlist_base__size_1_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_eng_runlist_r(u32 i) +{ + return 0x00002284 + i*8; +} +static inline u32 fifo_eng_runlist__size_1_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_eng_runlist_length_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_eng_runlist_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_pb_timeslice_r(u32 i) +{ + return 0x00002350 + i*4; +} +static inline u32 fifo_pb_timeslice_timeout_16_f(void) +{ + return 0x10; +} +static inline u32 fifo_pb_timeslice_timescale_0_f(void) +{ + return 0x0; +} +static inline u32 fifo_pb_timeslice_enable_true_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_pbdma_map_r(u32 i) +{ + return 0x00002390 + i*4; +} +static inline u32 fifo_intr_0_r(void) +{ + return 0x00002100; +} +static inline u32 fifo_intr_0_bind_error_pending_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_bind_error_reset_f(void) +{ + return 0x1; +} +static inline u32 fifo_intr_0_sched_error_pending_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_sched_error_reset_f(void) +{ + return 0x100; +} +static inline u32 fifo_intr_0_chsw_error_pending_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_chsw_error_reset_f(void) +{ + return 0x10000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) +{ + return 0x800000; +} +static inline u32 fifo_intr_0_lb_error_pending_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_lb_error_reset_f(void) +{ + return 0x1000000; +} +static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) +{ + return 0x8000000; +} +static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) +{ + return 0x8000000; +} +static inline u32 fifo_intr_0_mmu_fault_pending_f(void) +{ + return 0x10000000; +} +static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) +{ + return 0x20000000; +} +static inline u32 fifo_intr_0_runlist_event_pending_f(void) +{ + return 0x40000000; +} +static inline u32 fifo_intr_0_channel_intr_pending_f(void) +{ + return 0x80000000; +} +static inline u32 fifo_intr_en_0_r(void) +{ + return 0x00002140; +} +static inline u32 fifo_intr_en_1_r(void) +{ + return 0x00002528; +} +static inline u32 fifo_intr_bind_error_r(void) +{ + return 0x0000252c; +} +static inline u32 fifo_intr_sched_error_r(void) +{ + return 0x0000254c; +} +static inline u32 fifo_intr_sched_error_code_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) +{ + return 0x0000000a; +} +static inline u32 fifo_intr_chsw_error_r(void) +{ + return 0x0000256c; +} +static inline u32 fifo_intr_mmu_fault_id_r(void) +{ + return 0x0000259c; +} +static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) +{ + return 0x0; +} +static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) +{ + return 0x00002800 + i*16; +} +static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) +{ + return 0x00002804 + i*16; +} +static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) +{ + return 0x00002808 + i*16; +} +static inline u32 fifo_intr_mmu_fault_info_r(u32 i) +{ + return 0x0000280c + i*16; +} +static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) +{ + return (r >> 8) & 0x3f; +} +static inline u32 fifo_intr_pbdma_id_r(void) +{ + return 0x000025a0; +} +static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_intr_runlist_r(void) +{ + return 0x00002a00; +} +static inline u32 fifo_fb_timeout_r(void) +{ + return 0x00002a04; +} +static inline u32 fifo_fb_timeout_period_m(void) +{ + return 0x3fffffff << 0; +} +static inline u32 fifo_fb_timeout_period_max_f(void) +{ + return 0x3fffffff; +} +static inline u32 fifo_error_sched_disable_r(void) +{ + return 0x0000262c; +} +static inline u32 fifo_sched_disable_r(void) +{ + return 0x00002630; +} +static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +static inline u32 fifo_sched_disable_runlist_m(u32 i) +{ + return 0x1 << (0 + i*1); +} +static inline u32 fifo_sched_disable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_preempt_r(void) +{ + return 0x00002634; +} +static inline u32 fifo_preempt_pending_true_f(void) +{ + return 0x100000; +} +static inline u32 fifo_preempt_type_channel_f(void) +{ + return 0x0; +} +static inline u32 fifo_preempt_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 fifo_trigger_mmu_fault_r(u32 i) +{ + return 0x00002a30 + i*4; +} +static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 fifo_engine_status_r(u32 i) +{ + return 0x00002640 + i*8; +} +static inline u32 fifo_engine_status__size_1_v(void) +{ + return 0x00000002; +} +static inline u32 fifo_engine_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_engine_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_engine_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_ctx_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_engine_status_ctx_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_engine_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_engine_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_engine_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_faulted_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 fifo_engine_status_faulted_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_engine_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 fifo_engine_status_engine_idle_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_engine_status_engine_busy_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) +{ + return 0x8000; +} +static inline u32 fifo_pbdma_status_r(u32 i) +{ + return 0x00003080 + i*4; +} +static inline u32 fifo_pbdma_status__size_1_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_id_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 fifo_pbdma_status_id_type_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 fifo_pbdma_status_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chan_status_v(u32 r) +{ + return (r >> 13) & 0x7; +} +static inline u32 fifo_pbdma_status_chan_status_valid_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) +{ + return 0x00000005; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) +{ + return 0x00000006; +} +static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) +{ + return 0x00000007; +} +static inline u32 fifo_pbdma_status_next_id_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_pbdma_status_chsw_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h new file mode 100644 index 000000000..b8e236b8f --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_flush_gp10b_h_ +#define _hw_flush_gp10b_h_ + +static inline u32 flush_l2_system_invalidate_r(void) +{ + return 0x00070004; +} +static inline u32 flush_l2_system_invalidate_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_system_invalidate_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_system_invalidate_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_r(void) +{ + return 0x00070010; +} +static inline u32 flush_l2_flush_dirty_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_l2_flush_dirty_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_l2_flush_dirty_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_r(void) +{ + return 0x00070000; +} +static inline u32 flush_fb_flush_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_fb_flush_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_fb_flush_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_fb_flush_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_fb_flush_outstanding_true_v(void) +{ + return 0x00000001; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h new file mode 100644 index 000000000..00291d301 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_fuse_gp10b_h_ +#define _hw_fuse_gp10b_h_ + +static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) +{ + return 0x00021c38 + i*4; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h new file mode 100644 index 000000000..161c1ce0c --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -0,0 +1,1153 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gmmu_gp10b_h_ +#define _hw_gmmu_gp10b_h_ + +static inline u32 gmmu_pde_aperture_big_w(void) +{ + return 0; +} +static inline u32 gmmu_pde_aperture_big_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_aperture_big_video_memory_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pde_size_w(void) +{ + return 0; +} +static inline u32 gmmu_pde_size_full_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_address_big_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_pde_address_big_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_pde_aperture_small_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_aperture_small_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_aperture_small_video_memory_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pde_vol_small_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_vol_small_true_f(void) +{ + return 0x4; +} +static inline u32 gmmu_pde_vol_small_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_vol_big_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_vol_big_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_pde_vol_big_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pde_address_small_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_pde_address_small_sys_w(void) +{ + return 1; +} +static inline u32 gmmu_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_valid_w(void) +{ + return 0; +} +static inline u32 gmmu_pte_valid_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pte_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pte_address_sys_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 gmmu_pte_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_pte_vol_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_vol_true_f(void) +{ + return 0x1; +} +static inline u32 gmmu_pte_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pte_aperture_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_aperture_video_memory_f(void) +{ + return 0x0; +} +static inline u32 gmmu_pte_read_only_w(void) +{ + return 0; +} +static inline u32 gmmu_pte_read_only_true_f(void) +{ + return 0x4; +} +static inline u32 gmmu_pte_write_disable_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_write_disable_true_f(void) +{ + return 0x80000000; +} +static inline u32 gmmu_pte_read_disable_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_read_disable_true_f(void) +{ + return 0x40000000; +} +static inline u32 gmmu_pte_comptagline_f(u32 v) +{ + return (v & 0x1ffff) << 12; +} +static inline u32 gmmu_pte_comptagline_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_f(u32 v) +{ + return (v & 0xff) << 4; +} +static inline u32 gmmu_pte_kind_w(void) +{ + return 1; +} +static inline u32 gmmu_pte_kind_invalid_v(void) +{ + return 0x000000ff; +} +static inline u32 gmmu_pte_kind_pitch_v(void) +{ + return 0x00000000; +} +static inline u32 gmmu_pte_kind_z16_v(void) +{ + return 0x00000001; +} +static inline u32 gmmu_pte_kind_z16_2c_v(void) +{ + return 0x00000002; +} +static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) +{ + return 0x00000003; +} +static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) +{ + return 0x00000004; +} +static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) +{ + return 0x00000005; +} +static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) +{ + return 0x00000006; +} +static inline u32 gmmu_pte_kind_z16_2z_v(void) +{ + return 0x00000007; +} +static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) +{ + return 0x00000009; +} +static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) +{ + return 0x0000000a; +} +static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) +{ + return 0x0000000b; +} +static inline u32 gmmu_pte_kind_z16_4cz_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) +{ + return 0x0000000d; +} +static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) +{ + return 0x0000000e; +} +static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) +{ + return 0x0000000f; +} +static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_pte_kind_s8z24_v(void) +{ + return 0x00000011; +} +static inline u32 gmmu_pte_kind_s8z24_1z_v(void) +{ + return 0x00000012; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) +{ + return 0x00000013; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) +{ + return 0x00000014; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) +{ + return 0x00000015; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) +{ + return 0x00000016; +} +static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) +{ + return 0x00000017; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) +{ + return 0x00000018; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) +{ + return 0x00000019; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) +{ + return 0x0000001a; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) +{ + return 0x0000001b; +} +static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) +{ + return 0x0000001c; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) +{ + return 0x0000001d; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) +{ + return 0x0000001e; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) +{ + return 0x0000001f; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) +{ + return 0x00000020; +} +static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) +{ + return 0x00000021; +} +static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) +{ + return 0x00000022; +} +static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) +{ + return 0x00000023; +} +static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) +{ + return 0x00000024; +} +static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) +{ + return 0x00000025; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) +{ + return 0x00000026; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) +{ + return 0x00000027; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) +{ + return 0x00000028; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) +{ + return 0x00000029; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) +{ + return 0x0000002e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) +{ + return 0x0000002f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) +{ + return 0x00000030; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) +{ + return 0x00000031; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) +{ + return 0x00000032; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) +{ + return 0x00000033; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) +{ + return 0x00000034; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) +{ + return 0x00000035; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) +{ + return 0x0000003a; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) +{ + return 0x0000003b; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) +{ + return 0x0000003c; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) +{ + return 0x0000003d; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) +{ + return 0x0000003e; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) +{ + return 0x0000003f; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) +{ + return 0x00000040; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) +{ + return 0x00000041; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) +{ + return 0x00000042; +} +static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) +{ + return 0x00000043; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) +{ + return 0x00000044; +} +static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) +{ + return 0x00000045; +} +static inline u32 gmmu_pte_kind_z24s8_v(void) +{ + return 0x00000046; +} +static inline u32 gmmu_pte_kind_z24s8_1z_v(void) +{ + return 0x00000047; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) +{ + return 0x00000048; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) +{ + return 0x00000049; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) +{ + return 0x0000004a; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) +{ + return 0x0000004b; +} +static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) +{ + return 0x0000004c; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) +{ + return 0x0000004d; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) +{ + return 0x0000004e; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) +{ + return 0x0000004f; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) +{ + return 0x00000050; +} +static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) +{ + return 0x00000051; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) +{ + return 0x00000052; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) +{ + return 0x00000053; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) +{ + return 0x00000054; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) +{ + return 0x00000055; +} +static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) +{ + return 0x00000056; +} +static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) +{ + return 0x00000057; +} +static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) +{ + return 0x00000058; +} +static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) +{ + return 0x00000059; +} +static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) +{ + return 0x0000005a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) +{ + return 0x0000005b; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) +{ + return 0x0000005c; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) +{ + return 0x0000005d; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) +{ + return 0x0000005e; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) +{ + return 0x00000063; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) +{ + return 0x00000064; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) +{ + return 0x00000065; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) +{ + return 0x00000066; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) +{ + return 0x00000067; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) +{ + return 0x00000068; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) +{ + return 0x00000069; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) +{ + return 0x0000006a; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) +{ + return 0x0000006f; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) +{ + return 0x00000070; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) +{ + return 0x00000071; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) +{ + return 0x00000072; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) +{ + return 0x00000073; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) +{ + return 0x00000074; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) +{ + return 0x00000075; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) +{ + return 0x00000076; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) +{ + return 0x00000077; +} +static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) +{ + return 0x00000078; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) +{ + return 0x00000079; +} +static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) +{ + return 0x0000007a; +} +static inline u32 gmmu_pte_kind_zf32_v(void) +{ + return 0x0000007b; +} +static inline u32 gmmu_pte_kind_zf32_1z_v(void) +{ + return 0x0000007c; +} +static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) +{ + return 0x0000007d; +} +static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) +{ + return 0x0000007e; +} +static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) +{ + return 0x0000007f; +} +static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) +{ + return 0x00000080; +} +static inline u32 gmmu_pte_kind_zf32_2cs_v(void) +{ + return 0x00000081; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) +{ + return 0x00000082; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) +{ + return 0x00000083; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) +{ + return 0x00000084; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) +{ + return 0x00000085; +} +static inline u32 gmmu_pte_kind_zf32_2cz_v(void) +{ + return 0x00000086; +} +static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) +{ + return 0x00000087; +} +static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) +{ + return 0x00000088; +} +static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) +{ + return 0x00000089; +} +static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) +{ + return 0x0000008a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) +{ + return 0x0000008b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) +{ + return 0x0000008c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) +{ + return 0x0000008d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) +{ + return 0x0000008e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x0000008f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x00000090; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x00000091; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x00000092; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x00000097; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x00000098; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x00000099; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x0000009a; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x0000009b; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x0000009c; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x0000009d; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x0000009e; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x0000009f; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000a0; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000a1; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000a2; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000a3; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000a4; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000a5; +} +static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000a6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) +{ + return 0x000000a7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) +{ + return 0x000000a8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) +{ + return 0x000000a9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) +{ + return 0x000000aa; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) +{ + return 0x000000ab; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) +{ + return 0x000000ac; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) +{ + return 0x000000ad; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) +{ + return 0x000000ae; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) +{ + return 0x000000b3; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) +{ + return 0x000000b4; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) +{ + return 0x000000b5; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) +{ + return 0x000000b6; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) +{ + return 0x000000b7; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) +{ + return 0x000000b8; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) +{ + return 0x000000b9; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) +{ + return 0x000000ba; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) +{ + return 0x000000bb; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) +{ + return 0x000000bc; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) +{ + return 0x000000bd; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) +{ + return 0x000000be; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) +{ + return 0x000000bf; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) +{ + return 0x000000c0; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) +{ + return 0x000000c1; +} +static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) +{ + return 0x000000c2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) +{ + return 0x000000c3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) +{ + return 0x000000c4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) +{ + return 0x000000c5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) +{ + return 0x000000c6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) +{ + return 0x000000c7; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) +{ + return 0x000000c8; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) +{ + return 0x000000ce; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) +{ + return 0x000000cf; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) +{ + return 0x000000d0; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) +{ + return 0x000000d1; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) +{ + return 0x000000d2; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) +{ + return 0x000000d3; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) +{ + return 0x000000d4; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) +{ + return 0x000000d5; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) +{ + return 0x000000d6; +} +static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) +{ + return 0x000000d7; +} +static inline u32 gmmu_pte_kind_generic_16bx2_v(void) +{ + return 0x000000fe; +} +static inline u32 gmmu_pte_kind_c32_2c_v(void) +{ + return 0x000000d8; +} +static inline u32 gmmu_pte_kind_c32_2cbr_v(void) +{ + return 0x000000d9; +} +static inline u32 gmmu_pte_kind_c32_2cba_v(void) +{ + return 0x000000da; +} +static inline u32 gmmu_pte_kind_c32_2cra_v(void) +{ + return 0x000000db; +} +static inline u32 gmmu_pte_kind_c32_2bra_v(void) +{ + return 0x000000dc; +} +static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) +{ + return 0x000000dd; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) +{ + return 0x000000de; +} +static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) +{ + return 0x000000cc; +} +static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) +{ + return 0x000000df; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) +{ + return 0x000000e0; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) +{ + return 0x000000e1; +} +static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) +{ + return 0x000000e2; +} +static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) +{ + return 0x000000e3; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) +{ + return 0x000000e4; +} +static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) +{ + return 0x000000e5; +} +static inline u32 gmmu_pte_kind_c64_2c_v(void) +{ + return 0x000000e6; +} +static inline u32 gmmu_pte_kind_c64_2cbr_v(void) +{ + return 0x000000e7; +} +static inline u32 gmmu_pte_kind_c64_2cba_v(void) +{ + return 0x000000e8; +} +static inline u32 gmmu_pte_kind_c64_2cra_v(void) +{ + return 0x000000e9; +} +static inline u32 gmmu_pte_kind_c64_2bra_v(void) +{ + return 0x000000ea; +} +static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) +{ + return 0x000000eb; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) +{ + return 0x000000ec; +} +static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) +{ + return 0x000000cd; +} +static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) +{ + return 0x000000ed; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) +{ + return 0x000000ee; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) +{ + return 0x000000ef; +} +static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) +{ + return 0x000000f0; +} +static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) +{ + return 0x000000f1; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) +{ + return 0x000000f2; +} +static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) +{ + return 0x000000f3; +} +static inline u32 gmmu_pte_kind_c128_2c_v(void) +{ + return 0x000000f4; +} +static inline u32 gmmu_pte_kind_c128_2cr_v(void) +{ + return 0x000000f5; +} +static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) +{ + return 0x000000f6; +} +static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) +{ + return 0x000000f7; +} +static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) +{ + return 0x000000f8; +} +static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) +{ + return 0x000000f9; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) +{ + return 0x000000fa; +} +static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) +{ + return 0x000000fb; +} +static inline u32 gmmu_pte_kind_x8c24_v(void) +{ + return 0x000000fc; +} +static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) +{ + return 0x000000fd; +} +static inline u32 gmmu_pte_kind_smsked_message_v(void) +{ + return 0x000000ca; +} +static inline u32 gmmu_pte_kind_smhost_message_v(void) +{ + return 0x000000cb; +} +static inline u32 gmmu_pte_kind_s8_v(void) +{ + return 0x0000002a; +} +static inline u32 gmmu_pte_kind_s8_2s_v(void) +{ + return 0x0000002b; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h new file mode 100644 index 000000000..7a4761d6b --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -0,0 +1,3173 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_gr_gp10b_h_ +#define _hw_gr_gp10b_h_ + +static inline u32 gr_intr_r(void) +{ + return 0x00400100; +} +static inline u32 gr_intr_notify_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_notify_reset_f(void) +{ + return 0x1; +} +static inline u32 gr_intr_semaphore_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_semaphore_reset_f(void) +{ + return 0x2; +} +static inline u32 gr_intr_illegal_method_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_method_reset_f(void) +{ + return 0x10; +} +static inline u32 gr_intr_illegal_class_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_illegal_class_reset_f(void) +{ + return 0x20; +} +static inline u32 gr_intr_class_error_pending_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_class_error_reset_f(void) +{ + return 0x100000; +} +static inline u32 gr_intr_exception_pending_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_exception_reset_f(void) +{ + return 0x200000; +} +static inline u32 gr_intr_en_r(void) +{ + return 0x0040013c; +} +static inline u32 gr_exception_r(void) +{ + return 0x00400108; +} +static inline u32 gr_exception_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception_gpc_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_exception1_r(void) +{ + return 0x00400118; +} +static inline u32 gr_exception1_gpc_0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_exception2_r(void) +{ + return 0x0040011c; +} +static inline u32 gr_exception_en_r(void) +{ + return 0x00400138; +} +static inline u32 gr_exception_en_fe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_exception1_en_r(void) +{ + return 0x00400130; +} +static inline u32 gr_exception2_en_r(void) +{ + return 0x00400134; +} +static inline u32 gr_gpfifo_ctl_r(void) +{ + return 0x00400500; +} +static inline u32 gr_gpfifo_ctl_access_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpfifo_ctl_access_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpfifo_ctl_access_enabled_f(void) +{ + return 0x1; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_trapped_addr_r(void) +{ + return 0x00400704; +} +static inline u32 gr_trapped_addr_mthd_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 gr_trapped_addr_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 gr_trapped_data_lo_r(void) +{ + return 0x00400708; +} +static inline u32 gr_trapped_data_hi_r(void) +{ + return 0x0040070c; +} +static inline u32 gr_status_r(void) +{ + return 0x00400700; +} +static inline u32 gr_status_fe_method_lower_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_status_fe_method_lower_idle_v(void) +{ + return 0x00000000; +} +static inline u32 gr_status_mask_r(void) +{ + return 0x00400610; +} +static inline u32 gr_engine_status_r(void) +{ + return 0x0040060c; +} +static inline u32 gr_engine_status_value_busy_f(void) +{ + return 0x1; +} +static inline u32 gr_pipe_bundle_address_r(void) +{ + return 0x00400200; +} +static inline u32 gr_pipe_bundle_address_value_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pipe_bundle_data_r(void) +{ + return 0x00400204; +} +static inline u32 gr_pipe_bundle_config_r(void) +{ + return 0x00400208; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_hww_esr_r(void) +{ + return 0x00404000; +} +static inline u32 gr_fe_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_fe_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fe_go_idle_timeout_r(void) +{ + return 0x00404154; +} +static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_object_table_r(u32 i) +{ + return 0x00404200 + i*4; +} +static inline u32 gr_fe_object_table_nvclass_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_fe_tpc_fs_r(void) +{ + return 0x004041c4; +} +static inline u32 gr_pri_mme_shadow_raw_index_r(void) +{ + return 0x00404488; +} +static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pri_mme_shadow_raw_data_r(void) +{ + return 0x0040448c; +} +static inline u32 gr_mme_hww_esr_r(void) +{ + return 0x00404490; +} +static inline u32 gr_mme_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_mme_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_memfmt_hww_esr_r(void) +{ + return 0x00404600; +} +static inline u32 gr_memfmt_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_memfmt_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_fecs_cpuctl_r(void) +{ + return 0x00409100; +} +static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_cpuctl_alias_r(void) +{ + return 0x00409130; +} +static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_dmactl_r(void) +{ + return 0x0040910c; +} +static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_fecs_os_r(void) +{ + return 0x00409080; +} +static inline u32 gr_fecs_idlestate_r(void) +{ + return 0x0040904c; +} +static inline u32 gr_fecs_mailbox0_r(void) +{ + return 0x00409040; +} +static inline u32 gr_fecs_mailbox1_r(void) +{ + return 0x00409044; +} +static inline u32 gr_fecs_irqstat_r(void) +{ + return 0x00409008; +} +static inline u32 gr_fecs_irqmode_r(void) +{ + return 0x0040900c; +} +static inline u32 gr_fecs_irqmask_r(void) +{ + return 0x00409018; +} +static inline u32 gr_fecs_irqdest_r(void) +{ + return 0x0040901c; +} +static inline u32 gr_fecs_curctx_r(void) +{ + return 0x00409050; +} +static inline u32 gr_fecs_nxtctx_r(void) +{ + return 0x00409054; +} +static inline u32 gr_fecs_engctl_r(void) +{ + return 0x004090a4; +} +static inline u32 gr_fecs_debug1_r(void) +{ + return 0x00409090; +} +static inline u32 gr_fecs_debuginfo_r(void) +{ + return 0x00409094; +} +static inline u32 gr_fecs_icd_cmd_r(void) +{ + return 0x00409200; +} +static inline u32 gr_fecs_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 gr_fecs_icd_rdata_r(void) +{ + return 0x0040920c; +} +static inline u32 gr_fecs_imemc_r(u32 i) +{ + return 0x00409180 + i*16; +} +static inline u32 gr_fecs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_imemd_r(u32 i) +{ + return 0x00409184 + i*16; +} +static inline u32 gr_fecs_imemt_r(u32 i) +{ + return 0x00409188 + i*16; +} +static inline u32 gr_fecs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_fecs_dmemc_r(u32 i) +{ + return 0x004091c0 + i*8; +} +static inline u32 gr_fecs_dmemc_offs_s(void) +{ + return 6; +} +static inline u32 gr_fecs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_fecs_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 gr_fecs_dmemc_offs_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +static inline u32 gr_fecs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_fecs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_fecs_dmemd_r(u32 i) +{ + return 0x004091c4 + i*8; +} +static inline u32 gr_fecs_dmatrfbase_r(void) +{ + return 0x00409110; +} +static inline u32 gr_fecs_dmatrfmoffs_r(void) +{ + return 0x00409114; +} +static inline u32 gr_fecs_dmatrffboffs_r(void) +{ + return 0x0040911c; +} +static inline u32 gr_fecs_dmatrfcmd_r(void) +{ + return 0x00409118; +} +static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_fecs_bootvec_r(void) +{ + return 0x00409104; +} +static inline u32 gr_fecs_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_falcon_hwcfg_r(void) +{ + return 0x00409108; +} +static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) +{ + return 0x0041a108; +} +static inline u32 gr_fecs_falcon_rm_r(void) +{ + return 0x00409084; +} +static inline u32 gr_fecs_current_ctx_r(void) +{ + return 0x00409b00; +} +static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_current_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_current_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_current_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_current_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_current_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_current_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_current_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_current_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_current_ctx_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_method_data_r(void) +{ + return 0x00409500; +} +static inline u32 gr_fecs_method_push_r(void) +{ + return 0x00409504; +} +static inline u32 gr_fecs_method_push_adr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) +{ + return 0x00000003; +} +static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) +{ + return 0x3; +} +static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) +{ + return 0x00000009; +} +static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) +{ + return 0x00000015; +} +static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) +{ + return 0x00000016; +} +static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) +{ + return 0x00000025; +} +static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) +{ + return 0x00000030; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) +{ + return 0x00000031; +} +static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) +{ + return 0x00000032; +} +static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) +{ + return 0x00000038; +} +static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) +{ + return 0x00000039; +} +static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) +{ + return 0x21; +} +static inline u32 gr_fecs_host_int_enable_r(void) +{ + return 0x00409c24; +} +static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) +{ + return 0x10000; +} +static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) +{ + return 0x20000; +} +static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) +{ + return 0x40000; +} +static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) +{ + return 0x80000; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) +{ + return 0x00409614; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) +{ + return 0x10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) +{ + return 0x20; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) +{ + return 0x40; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) +{ + return 0x100; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) +{ + return 0x200; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) +{ + return (v & 0x1) << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) +{ + return 0x1 << 10; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) +{ + return (r >> 10) & 0x1; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) +{ + return 0x0; +} +static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) +{ + return 0x400; +} +static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) +{ + return 0x0040960c; +} +static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) +{ + return 0x00409800 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) +{ + return 0x00000001; +} +static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) +{ + return 0x00000002; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) +{ + return 0x004098c0 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) +{ + return 0x00409840 + i*4; +} +static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fecs_fs_r(void) +{ + return 0x00409604; +} +static inline u32 gr_fecs_fs_num_available_gpcs_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_fecs_fs_num_available_fbps_s(void) +{ + return 5; +} +static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_m(void) +{ + return 0x1f << 16; +} +static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_fecs_cfg_r(void) +{ + return 0x00409620; +} +static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_fecs_rc_lanes_r(void) +{ + return 0x00409880; +} +static inline u32 gr_fecs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_fecs_ctxsw_status_1_r(void) +{ + return 0x00409400; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) +{ + return 1; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) +{ + return (v & 0x1) << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) +{ + return 0x1 << 12; +} +static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) +{ + return (r >> 12) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_adr_r(void) +{ + return 0x00409a24; +} +static inline u32 gr_fecs_new_ctx_r(void) +{ + return 0x00409b04; +} +static inline u32 gr_fecs_new_ctx_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_new_ctx_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_new_ctx_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_new_ctx_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_new_ctx_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_new_ctx_valid_s(void) +{ + return 1; +} +static inline u32 gr_fecs_new_ctx_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_fecs_new_ctx_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_fecs_new_ctx_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_fecs_arb_ctx_ptr_r(void) +{ + return 0x00409a0c; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) +{ + return 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) +{ + return (r >> 0) & 0xfffffff; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) +{ + return 2; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 gr_fecs_arb_ctx_cmd_r(void) +{ + return 0x00409a10; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) +{ + return 5; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) +{ + return 0x1f << 0; +} +static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_rstr2d_gpc_map0_r(void) +{ + return 0x0040780c; +} +static inline u32 gr_rstr2d_gpc_map1_r(void) +{ + return 0x00407810; +} +static inline u32 gr_rstr2d_gpc_map2_r(void) +{ + return 0x00407814; +} +static inline u32 gr_rstr2d_gpc_map3_r(void) +{ + return 0x00407818; +} +static inline u32 gr_rstr2d_gpc_map4_r(void) +{ + return 0x0040781c; +} +static inline u32 gr_rstr2d_gpc_map5_r(void) +{ + return 0x00407820; +} +static inline u32 gr_rstr2d_map_table_cfg_r(void) +{ + return 0x004078bc; +} +static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_hww_esr_r(void) +{ + return 0x00406018; +} +static inline u32 gr_pd_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_pd_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) +{ + return 0x00406028 + i*4; +} +static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) +{ + return (v & 0xf) << 4; +} +static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) +{ + return (v & 0xf) << 12; +} +static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) +{ + return (v & 0xf) << 24; +} +static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) +{ + return (v & 0xf) << 28; +} +static inline u32 gr_pd_ab_dist_cfg0_r(void) +{ + return 0x004064c0; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) +{ + return 0x0; +} +static inline u32 gr_pd_ab_dist_cfg1_r(void) +{ + return 0x004064c4; +} +static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) +{ + return 0xffff; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) +{ + return (v & 0xffff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) +{ + return 0x00000080; +} +static inline u32 gr_pd_ab_dist_cfg2_r(void) +{ + return 0x004064c8; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) +{ + return (v & 0x1fff) << 0; +} +static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) +{ + return 0x000001c0; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) +{ + return (v & 0x1fff) << 16; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) +{ + return 0x00000182; +} +static inline u32 gr_pd_pagepool_r(void) +{ + return 0x004064cc; +} +static inline u32 gr_pd_pagepool_total_pages_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_pd_dist_skip_table_r(u32 i) +{ + return 0x004064d0 + i*4; +} +static inline u32 gr_pd_dist_skip_table__size_1_v(void) +{ + return 0x00000008; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 gr_ds_debug_r(void) +{ + return 0x00405800; +} +static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) +{ + return 0x8000000; +} +static inline u32 gr_ds_zbc_color_r_r(void) +{ + return 0x00405804; +} +static inline u32 gr_ds_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_g_r(void) +{ + return 0x00405808; +} +static inline u32 gr_ds_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_b_r(void) +{ + return 0x0040580c; +} +static inline u32 gr_ds_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_a_r(void) +{ + return 0x00405810; +} +static inline u32 gr_ds_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_r(void) +{ + return 0x00405814; +} +static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) +{ + return (v & 0x7f) << 0; +} +static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) +{ + return 0x00000002; +} +static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) +{ + return 0x00000004; +} +static inline u32 gr_ds_zbc_z_r(void) +{ + return 0x00405818; +} +static inline u32 gr_ds_zbc_z_val_s(void) +{ + return 32; +} +static inline u32 gr_ds_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_ds_zbc_z_val_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_ds_zbc_z_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_ds_zbc_z_val__init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_ds_zbc_z_val__init_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_r(void) +{ + return 0x0040581c; +} +static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_zbc_tbl_index_r(void) +{ + return 0x00405820; +} +static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_ds_zbc_tbl_ld_r(void) +{ + return 0x00405824; +} +static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) +{ + return 0x0; +} +static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_esr_r(void) +{ + return 0x00405840; +} +static inline u32 gr_ds_hww_esr_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_esr_2_r(void) +{ + return 0x00405848; +} +static inline u32 gr_ds_hww_esr_2_reset_s(void) +{ + return 1; +} +static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_ds_hww_esr_2_reset_task_v(void) +{ + return 0x00000001; +} +static inline u32 gr_ds_hww_esr_2_reset_task_f(void) +{ + return 0x40000000; +} +static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 gr_ds_hww_report_mask_r(void) +{ + return 0x00405844; +} +static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) +{ + return 0x2; +} +static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) +{ + return 0x4; +} +static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) +{ + return 0x8; +} +static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) +{ + return 0x10; +} +static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) +{ + return 0x20; +} +static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) +{ + return 0x40; +} +static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) +{ + return 0x80; +} +static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) +{ + return 0x100; +} +static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) +{ + return 0x200; +} +static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) +{ + return 0x400; +} +static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) +{ + return 0x800; +} +static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) +{ + return 0x200000; +} +static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_ds_hww_report_mask_2_r(void) +{ + return 0x0040584c; +} +static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) +{ + return 0x1; +} +static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) +{ + return 0x00405870 + i*4; +} +static inline u32 gr_scc_bundle_cb_base_r(void) +{ + return 0x00408004; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_bundle_cb_size_r(void) +{ + return 0x00408008; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) +{ + return 0x00000018; +} +static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_pagepool_base_r(void) +{ + return 0x0040800c; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_scc_pagepool_r(void) +{ + return 0x00408010; +} +static inline u32 gr_scc_pagepool_total_pages_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) +{ + return 0x00000000; +} +static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) +{ + return 0x00000080; +} +static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) +{ + return 0x00000100; +} +static inline u32 gr_scc_pagepool_max_valid_pages_s(void) +{ + return 8; +} +static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_scc_pagepool_max_valid_pages_m(void) +{ + return 0xff << 8; +} +static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) +{ + return (r >> 8) & 0xff; +} +static inline u32 gr_scc_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_scc_init_r(void) +{ + return 0x0040802c; +} +static inline u32 gr_scc_init_ram_trigger_f(void) +{ + return 0x1; +} +static inline u32 gr_scc_hww_esr_r(void) +{ + return 0x00408030; +} +static inline u32 gr_scc_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_scc_hww_esr_en_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_sked_hww_esr_r(void) +{ + return 0x00407020; +} +static inline u32 gr_sked_hww_esr_reset_active_f(void) +{ + return 0x40000000; +} +static inline u32 gr_cwd_fs_r(void) +{ + return 0x00405b00; +} +static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) +{ + return 0x00405b60 + i*4; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_cwd_sm_id_r(u32 i) +{ + return 0x00405ba0 + i*4; +} +static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpc0_fs_gpc_r(void) +{ + return 0x00502608; +} +static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) +{ + return (r >> 16) & 0x1f; +} +static inline u32 gr_gpc0_cfg_r(void) +{ + return 0x00502620; +} +static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpccs_rc_lanes_r(void) +{ + return 0x00502880; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpc0_zcull_fs_r(void) +{ + return 0x00500910; +} +static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 gr_gpc0_zcull_ram_addr_r(void) +{ + return 0x00500914; +} +static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) +{ + return (v & 0xf) << 8; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) +{ + return 0x00500918; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) +{ + return 0x00800000; +} +static inline u32 gr_gpc0_zcull_total_ram_size_r(void) +{ + return 0x00500920; +} +static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) +{ + return 0x00500a04 + i*32; +} +static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) +{ + return 0x00000040; +} +static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) +{ + return 0x00000010; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) +{ + return 0x00500c10 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) +{ + return 0x00500c30 + i*4; +} +static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) +{ + return 0x00504088; +} +static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) +{ + return 0x00504698; +} +static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) +{ + return 0x00503018; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) +{ + return 0x005030c0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) +{ + return 0x00100000; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) +{ + return 0x005030f4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) +{ + return 0x005030e4; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) +{ + return 0x00000800; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) +{ + return 0x00000020; +} +static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) +{ + return 0x005030f8; +} +static inline u32 gr_gpccs_falcon_addr_r(void) +{ + return 0x0041a0ac; +} +static inline u32 gr_gpccs_falcon_addr_lsb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_m(void) +{ + return 0x3f << 0; +} +static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_msb_s(void) +{ + return 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_m(void) +{ + return 0x3f << 6; +} +static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) +{ + return (r >> 6) & 0x3f; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpccs_falcon_addr_ext_s(void) +{ + return 12; +} +static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_m(void) +{ + return 0xfff << 0; +} +static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +static inline u32 gr_gpccs_cpuctl_r(void) +{ + return 0x0041a100; +} +static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_gpccs_dmactl_r(void) +{ + return 0x0041a10c; +} +static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpccs_imemc_r(u32 i) +{ + return 0x0041a180 + i*16; +} +static inline u32 gr_gpccs_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_imemd_r(u32 i) +{ + return 0x0041a184 + i*16; +} +static inline u32 gr_gpccs_imemt_r(u32 i) +{ + return 0x0041a188 + i*16; +} +static inline u32 gr_gpccs_imemt__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 gr_gpccs_imemt_tag_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpccs_dmemc_r(u32 i) +{ + return 0x0041a1c0 + i*8; +} +static inline u32 gr_gpccs_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 gr_gpccs_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 gr_gpccs_dmemd_r(u32 i) +{ + return 0x0041a1c4 + i*8; +} +static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) +{ + return 0x0041a800 + i*4; +} +static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) +{ + return 0x00418e24; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) +{ + return 32; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) +{ + return 0x00418e28; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) +{ + return 11; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) +{ + return (v & 0x7ff) << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) +{ + return 0x7ff << 0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) +{ + return (r >> 0) & 0x7ff; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) +{ + return 0x00000018; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) +{ + return 0x18; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) +{ + return 0x00418ea0 + i*4; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) +{ + return 0x3fffff << 0; +} +static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) +{ + return 0x00418e30; +} +static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) +{ + return 0x00418810; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) +{ + return 0x0000000c; +} +static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 gr_crstr_gpc_map0_r(void) +{ + return 0x00418b08; +} +static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map1_r(void) +{ + return 0x00418b0c; +} +static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map2_r(void) +{ + return 0x00418b10; +} +static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map3_r(void) +{ + return 0x00418b14; +} +static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map4_r(void) +{ + return 0x00418b18; +} +static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_gpc_map5_r(void) +{ + return 0x00418b1c; +} +static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) +{ + return (v & 0x7) << 5; +} +static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) +{ + return (v & 0x7) << 10; +} +static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) +{ + return (v & 0x7) << 15; +} +static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) +{ + return (v & 0x7) << 25; +} +static inline u32 gr_crstr_map_table_cfg_r(void) +{ + return 0x00418bb8; +} +static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) +{ + return 0x00418980; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) +{ + return 0x00418984; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) +{ + return 0x00418988; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) +{ + return 3; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) +{ + return 0x7 << 28; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) +{ + return (r >> 28) & 0x7; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) +{ + return 0x0041898c; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) +{ + return (v & 0x7) << 4; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) +{ + return (v & 0x7) << 16; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) +{ + return (v & 0x7) << 20; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) +{ + return (v & 0x7) << 28; +} +static inline u32 gr_gpcs_gpm_pd_cfg_r(void) +{ + return 0x00418c6c; +} +static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_gcc_pagepool_base_r(void) +{ + return 0x00419004; +} +static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_gcc_pagepool_r(void) +{ + return 0x00419008; +} +static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) +{ + return 0x0041980c; +} +static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) +{ + return 0x00419848; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) +{ + return 0x00419c00; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) +{ + return 0x00419c2c; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) +{ + return 0x10000000; +} +static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) +{ + return 0x00419e00; +} +static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) +{ + return 0x1 << 7; +} +static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) +{ + return 0x1 << 15; +} +static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) +{ + return 0x00419e44; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) +{ + return 0x100; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) +{ + return 0x200; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) +{ + return 0x400; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) +{ + return 0x800; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) +{ + return 0x1000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) +{ + return 0x2000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) +{ + return 0x4000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) +{ + return 0x8000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) +{ + return 0x20000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) +{ + return 0x40000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) +{ + return 0x800000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) +{ + return 0x400000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) +{ + return 0x80000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) +{ + return 0x100000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) +{ + return 0x00419e4c; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) +{ + return 0x10000; +} +static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) +{ + return 0x0041ac90; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) +{ + return 0x00419d08; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) +{ + return 0x00504610; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) +{ + return 0x0050460c; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) +{ + return 0x00504650; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) +{ + return 0x00504648; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) +{ + return 0x00504770; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) +{ + return 0x00419f70; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) +{ + return 0x1 << 4; +} +static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) +{ + return 0x0050477c; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) +{ + return 0x00419f7c; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) +{ + return 0x00419ed8; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) +{ + return 0x0041be08; +} +static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) +{ + return 0x4; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) +{ + return 0x0041bf00; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) +{ + return 0x0041bf04; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) +{ + return 0x0041bf08; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) +{ + return 0x0041bf0c; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) +{ + return 0x0041bf10; +} +static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) +{ + return 0x0041bf14; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) +{ + return 0x0041bfd0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) +{ + return (v & 0x7) << 21; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) +{ + return (v & 0x1f) << 24; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) +{ + return 0x0041bfd4; +} +static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) +{ + return 0x0041bfe4; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) +{ + return (v & 0x1f) << 0; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) +{ + return (v & 0x1f) << 5; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) +{ + return (v & 0x1f) << 10; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) +{ + return (v & 0x1f) << 20; +} +static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) +{ + return (v & 0x1f) << 25; +} +static inline u32 gr_bes_zrop_settings_r(void) +{ + return 0x00408850; +} +static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_be0_crop_debug3_r(void) +{ + return 0x00410108; +} +static inline u32 gr_bes_crop_debug3_r(void) +{ + return 0x00408908; +} +static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_bes_crop_settings_r(void) +{ + return 0x00408958; +} +static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) +{ + return 0x00000020; +} +static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) +{ + return 0x000000c0; +} +static inline u32 gr_zcull_subregion_qty_v(void) +{ + return 0x00000010; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) +{ + return 0x00504604; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) +{ + return 0x00504608; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) +{ + return 0x0050465c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) +{ + return 0x00504660; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) +{ + return 0x00504664; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) +{ + return 0x00504668; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) +{ + return 0x0050466c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) +{ + return 0x00504658; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) +{ + return 0x00504730; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) +{ + return 0x00504734; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) +{ + return 0x00504738; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) +{ + return 0x0050473c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) +{ + return 0x00504740; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) +{ + return 0x00504744; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) +{ + return 0x00504748; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) +{ + return 0x0050474c; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) +{ + return 0x00504678; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) +{ + return 0x00504694; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) +{ + return 0x005046f0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) +{ + return 0x00504700; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) +{ + return 0x005046f4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) +{ + return 0x00504704; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) +{ + return 0x005046f8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) +{ + return 0x00504708; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) +{ + return 0x005046fc; +} +static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) +{ + return 0x0050470c; +} +static inline u32 gr_fe_pwr_mode_r(void) +{ + return 0x00404170; +} +static inline u32 gr_fe_pwr_mode_mode_auto_f(void) +{ + return 0x0; +} +static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) +{ + return 0x2; +} +static inline u32 gr_fe_pwr_mode_req_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fe_pwr_mode_req_send_f(void) +{ + return 0x10; +} +static inline u32 gr_fe_pwr_mode_req_done_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) +{ + return 0x00419f88; +} +static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) +{ + return 0x00419f80; +} +static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) +{ + return 0x00419ccc; +} +static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) +{ + return 0x00418880; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) +{ + return 0x1 << 0; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) +{ + return 0x1 << 2; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) +{ + return 0x3 << 3; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) +{ + return 0x3 << 5; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) +{ + return 0x3 << 28; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) +{ + return 0x00418890; +} +static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) +{ + return 0x00418894; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) +{ + return 0x004188b0; +} +static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) +{ + return 0x004188b4; +} +static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) +{ + return 0x004188b8; +} +static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) +{ + return 0x004188ac; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h new file mode 100644 index 000000000..1ead0679b --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ltc_gp10b_h_ +#define _hw_ltc_gp10b_h_ + +static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) +{ + return 0x0014046c; +} +static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) +{ + return 0x00140518; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) +{ + return 0x0017e318; +} +static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) +{ + return 0x1 << 15; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) +{ + return 0x00140494; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) +{ + return (r >> 16) & 0x3; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) +{ + return 0x00000000; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) +{ + return 0x00000002; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) +{ + return 0x2; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) +{ + return 0x4; +} +static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) +{ + return 0x0017e26c; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) +{ + return 0x0017e270; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) +{ + return 0x0017e274; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) +{ + return 0x0001ffff; +} +static inline u32 ltc_ltcs_ltss_cbc_base_r(void) +{ + return 0x0017e278; +} +static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) +{ + return 0x0000000b; +} +static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) +{ + return (r >> 0) & 0x3ffffff; +} +static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) +{ + return 0x0017e27c; +} +static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) +{ + return 0x0017e000; +} +static inline u32 ltc_ltcs_ltss_cbc_param_r(void) +{ + return 0x0017e280; +} +static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) +{ + return (r >> 24) & 0xf; +} +static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) +{ + return (r >> 28) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) +{ + return 0x0017e2ac; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) +{ + return 0x0017e338; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) +{ + return 0x0017e33c + i*4; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) +{ + return 0x0017e34c; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) +{ + return 32; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) +{ + return 0x0017e2b0; +} +static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_g_elpg_r(void) +{ + return 0x0017e214; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_r(void) +{ + return 0x00140214; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_r(void) +{ + return 0x00142214; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_intr_r(void) +{ + return 0x0014020c; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h new file mode 100644 index 000000000..f45fdc99a --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_mc_gp10b_h_ +#define _hw_mc_gp10b_h_ + +static inline u32 mc_intr_0_r(void) +{ + return 0x00000100; +} +static inline u32 mc_intr_0_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_0_pgraph_pending_f(void) +{ + return 0x1000; +} +static inline u32 mc_intr_0_pmu_pending_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_0_ltc_pending_f(void) +{ + return 0x2000000; +} +static inline u32 mc_intr_0_priv_ring_pending_f(void) +{ + return 0x40000000; +} +static inline u32 mc_intr_0_pbus_pending_f(void) +{ + return 0x10000000; +} +static inline u32 mc_intr_mask_0_r(void) +{ + return 0x00000640; +} +static inline u32 mc_intr_mask_0_pmu_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 mc_intr_en_0_r(void) +{ + return 0x00000140; +} +static inline u32 mc_intr_en_0_inta_disabled_f(void) +{ + return 0x0; +} +static inline u32 mc_intr_en_0_inta_hardware_f(void) +{ + return 0x1; +} +static inline u32 mc_intr_en_1_r(void) +{ + return 0x00000144; +} +static inline u32 mc_intr_en_1_inta_disabled_f(void) +{ + return 0x0; +} +static inline u32 mc_enable_r(void) +{ + return 0x00000200; +} +static inline u32 mc_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_enable_l2_enabled_f(void) +{ + return 0x8; +} +static inline u32 mc_enable_pmedia_s(void) +{ + return 1; +} +static inline u32 mc_enable_pmedia_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 mc_enable_pmedia_m(void) +{ + return 0x1 << 4; +} +static inline u32 mc_enable_pmedia_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 mc_enable_priv_ring_enabled_f(void) +{ + return 0x20; +} +static inline u32 mc_enable_ce0_m(void) +{ + return 0x1 << 6; +} +static inline u32 mc_enable_pfifo_enabled_f(void) +{ + return 0x100; +} +static inline u32 mc_enable_pgraph_enabled_f(void) +{ + return 0x1000; +} +static inline u32 mc_enable_pwr_v(u32 r) +{ + return (r >> 13) & 0x1; +} +static inline u32 mc_enable_pwr_disabled_v(void) +{ + return 0x00000000; +} +static inline u32 mc_enable_pwr_enabled_f(void) +{ + return 0x2000; +} +static inline u32 mc_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_enable_ce2_m(void) +{ + return 0x1 << 21; +} +static inline u32 mc_enable_ce2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 mc_enable_blg_enabled_f(void) +{ + return 0x8000000; +} +static inline u32 mc_enable_perfmon_enabled_f(void) +{ + return 0x10000000; +} +static inline u32 mc_enable_hub_enabled_f(void) +{ + return 0x20000000; +} +static inline u32 mc_enable_pb_r(void) +{ + return 0x00000204; +} +static inline u32 mc_enable_pb_0_s(void) +{ + return 1; +} +static inline u32 mc_enable_pb_0_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 mc_enable_pb_0_m(void) +{ + return 0x1 << 0; +} +static inline u32 mc_enable_pb_0_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 mc_enable_pb_0_enabled_v(void) +{ + return 0x00000001; +} +static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) +{ + return (v & 0x1) << (0 + i*1); +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h new file mode 100644 index 000000000..d3fa8553d --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -0,0 +1,469 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pbdma_gp10b_h_ +#define _hw_pbdma_gp10b_h_ + +static inline u32 pbdma_gp_entry1_r(void) +{ + return 0x10000004; +} +static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pbdma_gp_entry1_length_f(u32 v) +{ + return (v & 0x1fffff) << 10; +} +static inline u32 pbdma_gp_entry1_length_v(u32 r) +{ + return (r >> 10) & 0x1fffff; +} +static inline u32 pbdma_gp_base_r(u32 i) +{ + return 0x00040048 + i*8192; +} +static inline u32 pbdma_gp_base__size_1_v(void) +{ + return 0x00000001; +} +static inline u32 pbdma_gp_base_offset_f(u32 v) +{ + return (v & 0x1fffffff) << 3; +} +static inline u32 pbdma_gp_base_rsvd_s(void) +{ + return 3; +} +static inline u32 pbdma_gp_base_hi_r(u32 i) +{ + return 0x0004004c + i*8192; +} +static inline u32 pbdma_gp_base_hi_offset_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) +{ + return (v & 0x1f) << 16; +} +static inline u32 pbdma_gp_fetch_r(u32 i) +{ + return 0x00040050 + i*8192; +} +static inline u32 pbdma_gp_get_r(u32 i) +{ + return 0x00040014 + i*8192; +} +static inline u32 pbdma_gp_put_r(u32 i) +{ + return 0x00040000 + i*8192; +} +static inline u32 pbdma_pb_fetch_r(u32 i) +{ + return 0x00040054 + i*8192; +} +static inline u32 pbdma_pb_fetch_hi_r(u32 i) +{ + return 0x00040058 + i*8192; +} +static inline u32 pbdma_get_r(u32 i) +{ + return 0x00040018 + i*8192; +} +static inline u32 pbdma_get_hi_r(u32 i) +{ + return 0x0004001c + i*8192; +} +static inline u32 pbdma_put_r(u32 i) +{ + return 0x0004005c + i*8192; +} +static inline u32 pbdma_put_hi_r(u32 i) +{ + return 0x00040060 + i*8192; +} +static inline u32 pbdma_formats_r(u32 i) +{ + return 0x0004009c + i*8192; +} +static inline u32 pbdma_formats_gp_fermi0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_formats_pb_fermi1_f(void) +{ + return 0x100; +} +static inline u32 pbdma_formats_mp_fermi0_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_r(u32 i) +{ + return 0x00040084 + i*8192; +} +static inline u32 pbdma_pb_header_priv_user_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_method_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_subchannel_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_level_main_f(void) +{ + return 0x0; +} +static inline u32 pbdma_pb_header_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_pb_header_type_inc_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_subdevice_r(u32 i) +{ + return 0x00040094 + i*8192; +} +static inline u32 pbdma_subdevice_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 pbdma_subdevice_status_active_f(void) +{ + return 0x10000000; +} +static inline u32 pbdma_subdevice_channel_dma_enable_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_method0_r(u32 i) +{ + return 0x000400c0 + i*8192; +} +static inline u32 pbdma_data0_r(u32 i) +{ + return 0x000400c4 + i*8192; +} +static inline u32 pbdma_target_r(u32 i) +{ + return 0x000400ac + i*8192; +} +static inline u32 pbdma_target_engine_sw_f(void) +{ + return 0x1f; +} +static inline u32 pbdma_acquire_r(u32 i) +{ + return 0x00040030 + i*8192; +} +static inline u32 pbdma_acquire_retry_man_2_f(void) +{ + return 0x2; +} +static inline u32 pbdma_acquire_retry_exp_2_f(void) +{ + return 0x100; +} +static inline u32 pbdma_acquire_timeout_exp_max_f(void) +{ + return 0x7800; +} +static inline u32 pbdma_acquire_timeout_man_max_f(void) +{ + return 0x7fff8000; +} +static inline u32 pbdma_acquire_timeout_en_disable_f(void) +{ + return 0x0; +} +static inline u32 pbdma_status_r(u32 i) +{ + return 0x00040100 + i*8192; +} +static inline u32 pbdma_channel_r(u32 i) +{ + return 0x00040120 + i*8192; +} +static inline u32 pbdma_signature_r(u32 i) +{ + return 0x00040010 + i*8192; +} +static inline u32 pbdma_signature_hw_valid_f(void) +{ + return 0xface; +} +static inline u32 pbdma_signature_sw_zero_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_r(u32 i) +{ + return 0x00040008 + i*8192; +} +static inline u32 pbdma_userd_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 pbdma_userd_addr_f(u32 v) +{ + return (v & 0x7fffff) << 9; +} +static inline u32 pbdma_userd_hi_r(u32 i) +{ + return 0x0004000c + i*8192; +} +static inline u32 pbdma_userd_hi_addr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pbdma_hce_ctrl_r(u32 i) +{ + return 0x000400e4 + i*8192; +} +static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_r(u32 i) +{ + return 0x00040108 + i*8192; +} +static inline u32 pbdma_intr_0_memreq_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pbdma_intr_0_memreq_pending_f(void) +{ + return 0x1; +} +static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) +{ + return 0x2; +} +static inline u32 pbdma_intr_0_memack_extra_pending_f(void) +{ + return 0x4; +} +static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) +{ + return 0x8; +} +static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) +{ + return 0x10; +} +static inline u32 pbdma_intr_0_memflush_pending_f(void) +{ + return 0x20; +} +static inline u32 pbdma_intr_0_memop_pending_f(void) +{ + return 0x40; +} +static inline u32 pbdma_intr_0_lbconnect_pending_f(void) +{ + return 0x80; +} +static inline u32 pbdma_intr_0_lbreq_pending_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) +{ + return 0x200; +} +static inline u32 pbdma_intr_0_lback_extra_pending_f(void) +{ + return 0x400; +} +static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) +{ + return 0x800; +} +static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) +{ + return 0x1000; +} +static inline u32 pbdma_intr_0_gpfifo_pending_f(void) +{ + return 0x2000; +} +static inline u32 pbdma_intr_0_gpptr_pending_f(void) +{ + return 0x4000; +} +static inline u32 pbdma_intr_0_gpentry_pending_f(void) +{ + return 0x8000; +} +static inline u32 pbdma_intr_0_gpcrc_pending_f(void) +{ + return 0x10000; +} +static inline u32 pbdma_intr_0_pbptr_pending_f(void) +{ + return 0x20000; +} +static inline u32 pbdma_intr_0_pbentry_pending_f(void) +{ + return 0x40000; +} +static inline u32 pbdma_intr_0_pbcrc_pending_f(void) +{ + return 0x80000; +} +static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) +{ + return 0x100000; +} +static inline u32 pbdma_intr_0_method_pending_f(void) +{ + return 0x200000; +} +static inline u32 pbdma_intr_0_methodcrc_pending_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_intr_0_device_pending_f(void) +{ + return 0x800000; +} +static inline u32 pbdma_intr_0_semaphore_pending_f(void) +{ + return 0x2000000; +} +static inline u32 pbdma_intr_0_acquire_pending_f(void) +{ + return 0x4000000; +} +static inline u32 pbdma_intr_0_pri_pending_f(void) +{ + return 0x8000000; +} +static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) +{ + return 0x20000000; +} +static inline u32 pbdma_intr_0_pbseg_pending_f(void) +{ + return 0x40000000; +} +static inline u32 pbdma_intr_0_signature_pending_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_intr_1_r(u32 i) +{ + return 0x00040148 + i*8192; +} +static inline u32 pbdma_intr_en_0_r(u32 i) +{ + return 0x0004010c + i*8192; +} +static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_intr_en_1_r(u32 i) +{ + return 0x0004014c + i*8192; +} +static inline u32 pbdma_intr_stall_r(u32 i) +{ + return 0x0004013c + i*8192; +} +static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) +{ + return 0x100; +} +static inline u32 pbdma_udma_nop_r(void) +{ + return 0x00000008; +} +static inline u32 pbdma_syncpointa_r(u32 i) +{ + return 0x000400a4 + i*8192; +} +static inline u32 pbdma_syncpointa_payload_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pbdma_syncpointb_r(u32 i) +{ + return 0x000400a8 + i*8192; +} +static inline u32 pbdma_syncpointb_op_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 pbdma_syncpointb_op_wait_v(void) +{ + return 0x00000000; +} +static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pbdma_syncpointb_wait_switch_en_v(void) +{ + return 0x00000001; +} +static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) +{ + return (r >> 8) & 0xff; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h new file mode 100644 index 000000000..7a4588585 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h @@ -0,0 +1,145 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringmaster_gp10b_h_ +#define _hw_pri_ringmaster_gp10b_h_ + +static inline u32 pri_ringmaster_command_r(void) +{ + return 0x0012004c; +} +static inline u32 pri_ringmaster_command_cmd_m(void) +{ + return 0x3f << 0; +} +static inline u32 pri_ringmaster_command_cmd_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) +{ + return 0x00000000; +} +static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) +{ + return 0x2; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) +{ + return 0x3; +} +static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_command_data_r(void) +{ + return 0x00120048; +} +static inline u32 pri_ringmaster_start_results_r(void) +{ + return 0x00120050; +} +static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) +{ + return 0x00000001; +} +static inline u32 pri_ringmaster_intr_status0_r(void) +{ + return 0x00120058; +} +static inline u32 pri_ringmaster_intr_status1_r(void) +{ + return 0x0012005c; +} +static inline u32 pri_ringmaster_global_ctl_r(void) +{ + return 0x00120060; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) +{ + return 0x1; +} +static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) +{ + return 0x0; +} +static inline u32 pri_ringmaster_enum_fbp_r(void) +{ + return 0x00120074; +} +static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_gpc_r(void) +{ + return 0x00120078; +} +static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 pri_ringmaster_enum_ltc_r(void) +{ + return 0x0012006c; +} +static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h new file mode 100644 index 000000000..eb711452f --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h @@ -0,0 +1,69 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pri_ringstation_sys_gp10b_h_ +#define _hw_pri_ringstation_sys_gp10b_h_ + +static inline u32 pri_ringstation_sys_master_config_r(u32 i) +{ + return 0x00122300 + i*4; +} +static inline u32 pri_ringstation_sys_decode_config_r(void) +{ + return 0x00122204; +} +static inline u32 pri_ringstation_sys_decode_config_ring_m(void) +{ + return 0x7 << 0; +} +static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) +{ + return 0x1; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h new file mode 100644 index 000000000..a315ae2d6 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_proj_gp10b_h_ +#define _hw_proj_gp10b_h_ + +static inline u32 proj_gpc_base_v(void) +{ + return 0x00500000; +} +static inline u32 proj_gpc_shared_base_v(void) +{ + return 0x00418000; +} +static inline u32 proj_gpc_stride_v(void) +{ + return 0x00008000; +} +static inline u32 proj_ltc_stride_v(void) +{ + return 0x00002000; +} +static inline u32 proj_lts_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_ppc_in_gpc_base_v(void) +{ + return 0x00003000; +} +static inline u32 proj_ppc_in_gpc_stride_v(void) +{ + return 0x00000200; +} +static inline u32 proj_rop_base_v(void) +{ + return 0x00410000; +} +static inline u32 proj_rop_shared_base_v(void) +{ + return 0x00408800; +} +static inline u32 proj_rop_stride_v(void) +{ + return 0x00000400; +} +static inline u32 proj_tpc_in_gpc_base_v(void) +{ + return 0x00004000; +} +static inline u32 proj_tpc_in_gpc_stride_v(void) +{ + return 0x00000800; +} +static inline u32 proj_tpc_in_gpc_shared_base_v(void) +{ + return 0x00001800; +} +static inline u32 proj_host_num_pbdma_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_litter_num_fbps_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_gpcs_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) +{ + return 0x00000001; +} +static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) +{ + return 0x00000002; +} +static inline u32 proj_scal_litter_num_zcull_banks_v(void) +{ + return 0x00000004; +} +static inline u32 proj_scal_max_gpcs_v(void) +{ + return 0x00000020; +} +static inline u32 proj_scal_max_tpc_per_gpc_v(void) +{ + return 0x00000008; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h new file mode 100644 index 000000000..d76095ac2 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h @@ -0,0 +1,805 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_pwr_gp10b_h_ +#define _hw_pwr_gp10b_h_ + +static inline u32 pwr_falcon_irqsset_r(void) +{ + return 0x0010a000; +} +static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqsclr_r(void) +{ + return 0x0010a004; +} +static inline u32 pwr_falcon_irqstat_r(void) +{ + return 0x0010a008; +} +static inline u32 pwr_falcon_irqstat_halt_true_f(void) +{ + return 0x10; +} +static inline u32 pwr_falcon_irqstat_exterr_true_f(void) +{ + return 0x20; +} +static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) +{ + return 0x40; +} +static inline u32 pwr_falcon_irqmode_r(void) +{ + return 0x0010a00c; +} +static inline u32 pwr_falcon_irqmset_r(void) +{ + return 0x0010a010; +} +static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmset_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_r(void) +{ + return 0x0010a014; +} +static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqmask_r(void) +{ + return 0x0010a018; +} +static inline u32 pwr_falcon_irqdest_r(void) +{ + return 0x0010a01c; +} +static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) +{ + return (v & 0x1) << 3; +} +static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) +{ + return (v & 0x1) << 7; +} +static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) +{ + return (v & 0x1) << 19; +} +static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) +{ + return (v & 0x1) << 21; +} +static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) +{ + return (v & 0x1) << 22; +} +static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) +{ + return (v & 0x1) << 23; +} +static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 pwr_falcon_curctx_r(void) +{ + return 0x0010a050; +} +static inline u32 pwr_falcon_nxtctx_r(void) +{ + return 0x0010a054; +} +static inline u32 pwr_falcon_mailbox0_r(void) +{ + return 0x0010a040; +} +static inline u32 pwr_falcon_mailbox1_r(void) +{ + return 0x0010a044; +} +static inline u32 pwr_falcon_itfen_r(void) +{ + return 0x0010a048; +} +static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) +{ + return 0x1; +} +static inline u32 pwr_falcon_idlestate_r(void) +{ + return 0x0010a04c; +} +static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) +{ + return (r >> 1) & 0x7fff; +} +static inline u32 pwr_falcon_os_r(void) +{ + return 0x0010a080; +} +static inline u32 pwr_falcon_engctl_r(void) +{ + return 0x0010a0a4; +} +static inline u32 pwr_falcon_cpuctl_r(void) +{ + return 0x0010a100; +} +static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) +{ + return 0x1 << 4; +} +static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) +{ + return 0x1 << 6; +} +static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 pwr_falcon_cpuctl_alias_r(void) +{ + return 0x0010a130; +} +static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 pwr_pmu_scpctl_stat_r(void) +{ + return 0x0010ac08; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) +{ + return 0x1 << 20; +} +static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 pwr_falcon_imemc_r(u32 i) +{ + return 0x0010a180 + i*16; +} +static inline u32 pwr_falcon_imemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_imemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_imemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_imemd_r(u32 i) +{ + return 0x0010a184 + i*16; +} +static inline u32 pwr_falcon_imemt_r(u32 i) +{ + return 0x0010a188 + i*16; +} +static inline u32 pwr_falcon_sctl_r(void) +{ + return 0x0010a240; +} +static inline u32 pwr_falcon_mmu_phys_sec_r(void) +{ + return 0x00100ce4; +} +static inline u32 pwr_falcon_bootvec_r(void) +{ + return 0x0010a104; +} +static inline u32 pwr_falcon_bootvec_vec_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_falcon_hwcfg_r(void) +{ + return 0x0010a108; +} +static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) +{ + return (r >> 0) & 0x1ff; +} +static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) +{ + return (r >> 9) & 0x1ff; +} +static inline u32 pwr_falcon_dmatrfbase_r(void) +{ + return 0x0010a110; +} +static inline u32 pwr_falcon_dmatrfmoffs_r(void) +{ + return 0x0010a114; +} +static inline u32 pwr_falcon_dmatrfcmd_r(void) +{ + return 0x0010a118; +} +static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) +{ + return (v & 0x7) << 12; +} +static inline u32 pwr_falcon_dmatrffboffs_r(void) +{ + return 0x0010a11c; +} +static inline u32 pwr_falcon_exterraddr_r(void) +{ + return 0x0010a168; +} +static inline u32 pwr_falcon_exterrstat_r(void) +{ + return 0x0010a16c; +} +static inline u32 pwr_falcon_exterrstat_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 pwr_falcon_exterrstat_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 pwr_pmu_falcon_icd_cmd_r(void) +{ + return 0x0010a200; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) +{ + return 4; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) +{ + return (v & 0xf) << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) +{ + return 0xf << 0; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) +{ + return 0x8; +} +static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) +{ + return 0xe; +} +static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 pwr_pmu_falcon_icd_rdata_r(void) +{ + return 0x0010a20c; +} +static inline u32 pwr_falcon_dmemc_r(u32 i) +{ + return 0x0010a1c0 + i*8; +} +static inline u32 pwr_falcon_dmemc_offs_f(u32 v) +{ + return (v & 0x3f) << 2; +} +static inline u32 pwr_falcon_dmemc_offs_m(void) +{ + return 0x3f << 2; +} +static inline u32 pwr_falcon_dmemc_blk_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 pwr_falcon_dmemc_blk_m(void) +{ + return 0xff << 8; +} +static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) +{ + return (v & 0x1) << 25; +} +static inline u32 pwr_falcon_dmemd_r(u32 i) +{ + return 0x0010a1c4 + i*8; +} +static inline u32 pwr_pmu_new_instblk_r(void) +{ + return 0x0010a480; +} +static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 pwr_pmu_new_instblk_target_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) +{ + return (v & 0x1) << 30; +} +static inline u32 pwr_pmu_mutex_id_r(void) +{ + return 0x0010a488; +} +static inline u32 pwr_pmu_mutex_id_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_id_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) +{ + return 0x000000ff; +} +static inline u32 pwr_pmu_mutex_id_release_r(void) +{ + return 0x0010a48c; +} +static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_m(void) +{ + return 0xff << 0; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) +{ + return 0x00000000; +} +static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_mutex_r(u32 i) +{ + return 0x0010a580 + i*4; +} +static inline u32 pwr_pmu_mutex__size_1_v(void) +{ + return 0x00000010; +} +static inline u32 pwr_pmu_mutex_value_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 pwr_pmu_mutex_value_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_queue_head_r(u32 i) +{ + return 0x0010a4a0 + i*4; +} +static inline u32 pwr_pmu_queue_head__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_queue_head_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_head_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_queue_tail_r(u32 i) +{ + return 0x0010a4b0 + i*4; +} +static inline u32 pwr_pmu_queue_tail__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_queue_tail_address_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_queue_tail_address_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_head_r(void) +{ + return 0x0010a4c8; +} +static inline u32 pwr_pmu_msgq_head_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_head_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_msgq_tail_r(void) +{ + return 0x0010a4cc; +} +static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) +{ + return (r >> 0) & 0xffffffff; +} +static inline u32 pwr_pmu_idle_mask_r(u32 i) +{ + return 0x0010a504 + i*16; +} +static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) +{ + return 0x1; +} +static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) +{ + return 0x200000; +} +static inline u32 pwr_pmu_idle_count_r(u32 i) +{ + return 0x0010a508 + i*16; +} +static inline u32 pwr_pmu_idle_count_value_f(u32 v) +{ + return (v & 0x7fffffff) << 0; +} +static inline u32 pwr_pmu_idle_count_value_v(u32 r) +{ + return (r >> 0) & 0x7fffffff; +} +static inline u32 pwr_pmu_idle_count_reset_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pwr_pmu_idle_ctrl_r(u32 i) +{ + return 0x0010a50c + i*16; +} +static inline u32 pwr_pmu_idle_ctrl_value_m(void) +{ + return 0x3 << 0; +} +static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) +{ + return 0x2; +} +static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) +{ + return 0x3; +} +static inline u32 pwr_pmu_idle_ctrl_filter_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) +{ + return 0x0; +} +static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) +{ + return 0x0010a9f0 + i*8; +} +static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) +{ + return 0x0010a9f4 + i*8; +} +static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) +{ + return 0x0010aa30 + i*8; +} +static inline u32 pwr_pmu_debug_r(u32 i) +{ + return 0x0010a5c0 + i*4; +} +static inline u32 pwr_pmu_debug__size_1_v(void) +{ + return 0x00000004; +} +static inline u32 pwr_pmu_mailbox_r(u32 i) +{ + return 0x0010a450 + i*4; +} +static inline u32 pwr_pmu_mailbox__size_1_v(void) +{ + return 0x0000000c; +} +static inline u32 pwr_pmu_bar0_addr_r(void) +{ + return 0x0010a7a0; +} +static inline u32 pwr_pmu_bar0_data_r(void) +{ + return 0x0010a7a4; +} +static inline u32 pwr_pmu_bar0_ctl_r(void) +{ + return 0x0010a7ac; +} +static inline u32 pwr_pmu_bar0_timeout_r(void) +{ + return 0x0010a7a8; +} +static inline u32 pwr_pmu_bar0_fecs_error_r(void) +{ + return 0x0010a988; +} +static inline u32 pwr_pmu_bar0_error_status_r(void) +{ + return 0x0010a7b0; +} +static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) +{ + return 0x0010a6c0 + i*4; +} +static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) +{ + return 0x0010a6e8 + i*4; +} +static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) +{ + return 0x0010a710 + i*4; +} +static inline u32 pwr_pmu_pg_intren_r(u32 i) +{ + return 0x0010a760 + i*4; +} +static inline u32 pwr_fbif_transcfg_r(u32 i) +{ + return 0x0010ae00 + i*4; +} +static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) +{ + return 0x1; +} +static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) +{ + return 0x2; +} +static inline u32 pwr_fbif_transcfg_mem_type_s(void) +{ + return 1; +} +static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_m(void) +{ + return 0x1 << 2; +} +static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) +{ + return 0x0; +} +static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h new file mode 100644 index 000000000..ef53882b1 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -0,0 +1,385 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ram_gp10b_h_ +#define _hw_ram_gp10b_h_ + +static inline u32 ram_in_ramfc_s(void) +{ + return 4096; +} +static inline u32 ram_in_ramfc_w(void) +{ + return 0; +} +static inline u32 ram_in_page_dir_base_target_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ram_in_page_dir_base_target_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ram_in_page_dir_base_vol_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_vol_true_f(void) +{ + return 0x4; +} +static inline u32 ram_in_page_dir_base_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_page_dir_base_lo_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_page_dir_base_hi_w(void) +{ + return 129; +} +static inline u32 ram_in_adr_limit_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_adr_limit_lo_w(void) +{ + return 130; +} +static inline u32 ram_in_adr_limit_hi_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ram_in_adr_limit_hi_w(void) +{ + return 131; +} +static inline u32 ram_in_engine_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_engine_cs_wfi_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_engine_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_engine_cs_fg_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_engine_cs_fg_f(void) +{ + return 0x8; +} +static inline u32 ram_in_gr_cs_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_cs_wfi_f(void) +{ + return 0x0; +} +static inline u32 ram_in_gr_wfi_target_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_mode_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_mode_physical_v(void) +{ + return 0x00000000; +} +static inline u32 ram_in_gr_wfi_mode_physical_f(void) +{ + return 0x0; +} +static inline u32 ram_in_gr_wfi_mode_virtual_v(void) +{ + return 0x00000001; +} +static inline u32 ram_in_gr_wfi_mode_virtual_f(void) +{ + return 0x4; +} +static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 ram_in_gr_wfi_ptr_lo_w(void) +{ + return 132; +} +static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 ram_in_gr_wfi_ptr_hi_w(void) +{ + return 133; +} +static inline u32 ram_in_base_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 ram_in_alloc_size_v(void) +{ + return 0x00001000; +} +static inline u32 ram_fc_size_val_v(void) +{ + return 0x00000200; +} +static inline u32 ram_fc_gp_put_w(void) +{ + return 0; +} +static inline u32 ram_fc_userd_w(void) +{ + return 2; +} +static inline u32 ram_fc_userd_hi_w(void) +{ + return 3; +} +static inline u32 ram_fc_signature_w(void) +{ + return 4; +} +static inline u32 ram_fc_gp_get_w(void) +{ + return 5; +} +static inline u32 ram_fc_pb_get_w(void) +{ + return 6; +} +static inline u32 ram_fc_pb_get_hi_w(void) +{ + return 7; +} +static inline u32 ram_fc_pb_top_level_get_w(void) +{ + return 8; +} +static inline u32 ram_fc_pb_top_level_get_hi_w(void) +{ + return 9; +} +static inline u32 ram_fc_acquire_w(void) +{ + return 12; +} +static inline u32 ram_fc_semaphorea_w(void) +{ + return 14; +} +static inline u32 ram_fc_semaphoreb_w(void) +{ + return 15; +} +static inline u32 ram_fc_semaphorec_w(void) +{ + return 16; +} +static inline u32 ram_fc_semaphored_w(void) +{ + return 17; +} +static inline u32 ram_fc_gp_base_w(void) +{ + return 18; +} +static inline u32 ram_fc_gp_base_hi_w(void) +{ + return 19; +} +static inline u32 ram_fc_gp_fetch_w(void) +{ + return 20; +} +static inline u32 ram_fc_pb_fetch_w(void) +{ + return 21; +} +static inline u32 ram_fc_pb_fetch_hi_w(void) +{ + return 22; +} +static inline u32 ram_fc_pb_put_w(void) +{ + return 23; +} +static inline u32 ram_fc_pb_put_hi_w(void) +{ + return 24; +} +static inline u32 ram_fc_pb_header_w(void) +{ + return 33; +} +static inline u32 ram_fc_pb_count_w(void) +{ + return 34; +} +static inline u32 ram_fc_subdevice_w(void) +{ + return 37; +} +static inline u32 ram_fc_formats_w(void) +{ + return 39; +} +static inline u32 ram_fc_syncpointa_w(void) +{ + return 41; +} +static inline u32 ram_fc_syncpointb_w(void) +{ + return 42; +} +static inline u32 ram_fc_target_w(void) +{ + return 43; +} +static inline u32 ram_fc_hce_ctrl_w(void) +{ + return 57; +} +static inline u32 ram_fc_chid_w(void) +{ + return 58; +} +static inline u32 ram_fc_chid_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_fc_chid_id_w(void) +{ + return 0; +} +static inline u32 ram_fc_pb_timeslice_w(void) +{ + return 62; +} +static inline u32 ram_userd_base_shift_v(void) +{ + return 0x00000009; +} +static inline u32 ram_userd_chan_size_v(void) +{ + return 0x00000200; +} +static inline u32 ram_userd_put_w(void) +{ + return 16; +} +static inline u32 ram_userd_get_w(void) +{ + return 17; +} +static inline u32 ram_userd_ref_w(void) +{ + return 18; +} +static inline u32 ram_userd_put_hi_w(void) +{ + return 19; +} +static inline u32 ram_userd_ref_threshold_w(void) +{ + return 20; +} +static inline u32 ram_userd_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_userd_get_hi_w(void) +{ + return 24; +} +static inline u32 ram_userd_gp_get_w(void) +{ + return 34; +} +static inline u32 ram_userd_gp_put_w(void) +{ + return 35; +} +static inline u32 ram_userd_gp_top_level_get_w(void) +{ + return 22; +} +static inline u32 ram_userd_gp_top_level_get_hi_w(void) +{ + return 23; +} +static inline u32 ram_rl_entry_size_v(void) +{ + return 0x00000008; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h new file mode 100644 index 000000000..16bbb3cab --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_therm_gp10b_h_ +#define _hw_therm_gp10b_h_ + +static inline u32 therm_use_a_r(void) +{ + return 0x00020798; +} +static inline u32 therm_evt_ext_therm_0_r(void) +{ + return 0x00020700; +} +static inline u32 therm_evt_ext_therm_1_r(void) +{ + return 0x00020704; +} +static inline u32 therm_evt_ext_therm_2_r(void) +{ + return 0x00020708; +} +static inline u32 therm_weight_1_r(void) +{ + return 0x00020024; +} +static inline u32 therm_peakpower_config1_r(u32 i) +{ + return 0x00020154 + i*4; +} +static inline u32 therm_peakpower_config1_window_period_2m_v(void) +{ + return 0x00000015; +} +static inline u32 therm_peakpower_config1_window_period_2m_f(void) +{ + return 0x15; +} +static inline u32 therm_peakpower_config1_window_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 therm_peakpower_config1_r(u32 i) +{ + return 0x000202e8 + i*4; +} +static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) +{ + return 5; +} +static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) +{ + return (r >> 8) & 0x1f; +} +static inline u32 therm_peakpower_config2_r(u32 i) +{ + return 0x00020170 + i*4; +} +static inline u32 therm_peakpower_config4_r(u32 i) +{ + return 0x000201c0 + i*4; +} +static inline u32 therm_peakpower_config8_r(u32 i) +{ + return 0x000202e8 + i*4; +} +static inline u32 therm_peakpower_config9_r(u32 i) +{ + return 0x000202f4 + i*4; +} +static inline u32 therm_config1_r(void) +{ + return 0x00020050; +} +static inline u32 therm_gate_ctrl_r(u32 i) +{ + return 0x00020200 + i*4; +} +static inline u32 therm_gate_ctrl_eng_clk_m(void) +{ + return 0x3 << 0; +} +static inline u32 therm_gate_ctrl_eng_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) +{ + return 0x1; +} +static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) +{ + return 0x2; +} +static inline u32 therm_gate_ctrl_blk_clk_m(void) +{ + return 0x3 << 2; +} +static inline u32 therm_gate_ctrl_blk_clk_run_f(void) +{ + return 0x0; +} +static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) +{ + return 0x4; +} +static inline u32 therm_gate_ctrl_eng_pwr_m(void) +{ + return 0x3 << 4; +} +static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) +{ + return 0x10; +} +static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) +{ + return 0x00000002; +} +static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) +{ + return 0x20; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) +{ + return (v & 0x1f) << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) +{ + return 0x1f << 8; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) +{ + return (v & 0x7) << 13; +} +static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) +{ + return 0x7 << 13; +} +static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) +{ + return (v & 0xf) << 20; +} +static inline u32 therm_gate_ctrl_eng_delay_after_m(void) +{ + return 0xf << 20; +} +static inline u32 therm_fecs_idle_filter_r(void) +{ + return 0x00020288; +} +static inline u32 therm_fecs_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +static inline u32 therm_hubmmu_idle_filter_r(void) +{ + return 0x0002028c; +} +static inline u32 therm_hubmmu_idle_filter_value_m(void) +{ + return 0xffffffff << 0; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h new file mode 100644 index 000000000..88d221284 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h @@ -0,0 +1,101 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_timer_gp10b_h_ +#define _hw_timer_gp10b_h_ + +static inline u32 timer_pri_timeout_r(void) +{ + return 0x00009080; +} +static inline u32 timer_pri_timeout_period_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 timer_pri_timeout_period_m(void) +{ + return 0xffffff << 0; +} +static inline u32 timer_pri_timeout_period_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 timer_pri_timeout_en_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 timer_pri_timeout_en_m(void) +{ + return 0x1 << 31; +} +static inline u32 timer_pri_timeout_en_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 timer_pri_timeout_en_en_enabled_f(void) +{ + return 0x80000000; +} +static inline u32 timer_pri_timeout_en_en_disabled_f(void) +{ + return 0x0; +} +static inline u32 timer_pri_timeout_save_0_r(void) +{ + return 0x00009084; +} +static inline u32 timer_pri_timeout_save_1_r(void) +{ + return 0x00009088; +} +static inline u32 timer_pri_timeout_fecs_errcode_r(void) +{ + return 0x0000908c; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h new file mode 100644 index 000000000..ca6457c70 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_top_gp10b_h_ +#define _hw_top_gp10b_h_ + +static inline u32 top_num_gpcs_r(void) +{ + return 0x00022430; +} +static inline u32 top_num_gpcs_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_tpc_per_gpc_r(void) +{ + return 0x00022434; +} +static inline u32 top_tpc_per_gpc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_fbps_r(void) +{ + return 0x00022438; +} +static inline u32 top_num_fbps_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_num_ltcs_r(void) +{ + return 0x00022454; +} +static inline u32 top_device_info_r(u32 i) +{ + return 0x00022700 + i*4; +} +static inline u32 top_device_info__size_1_v(void) +{ + return 0x00000040; +} +static inline u32 top_device_info_chain_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 top_device_info_chain_enable_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_engine_enum_v(u32 r) +{ + return (r >> 26) & 0xf; +} +static inline u32 top_device_info_runlist_enum_v(u32 r) +{ + return (r >> 21) & 0xf; +} +static inline u32 top_device_info_type_enum_v(u32 r) +{ + return (r >> 2) & 0x1fffffff; +} +static inline u32 top_device_info_type_enum_graphics_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_type_enum_graphics_f(void) +{ + return 0x0; +} +static inline u32 top_device_info_type_enum_copy0_v(void) +{ + return 0x00000001; +} +static inline u32 top_device_info_type_enum_copy0_f(void) +{ + return 0x4; +} +static inline u32 top_device_info_entry_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 top_device_info_entry_not_valid_v(void) +{ + return 0x00000000; +} +static inline u32 top_device_info_entry_enum_v(void) +{ + return 0x00000002; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h new file mode 100644 index 000000000..76597f69d --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_trim_gp10b_h_ +#define _hw_trim_gp10b_h_ + +static inline u32 trim_sys_gpcpll_cfg_r(void) +{ + return 0x00137000; +} +static inline u32 trim_sys_gpcpll_cfg_enable_m(void) +{ + return 0x1 << 0; +} +static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) +{ + return 0x0; +} +static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) +{ + return 0x1; +} +static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) +{ + return 0x1 << 1; +} +static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) +{ + return 0x00000000; +} +static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) +{ + return 0x1 << 4; +} +static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) +{ + return 0x0; +} +static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) +{ + return 0x10; +} +static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) +{ + return (r >> 17) & 0x1; +} +static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) +{ + return 0x20000; +} +static inline u32 trim_sys_gpcpll_coeff_r(void) +{ + return 0x00137004; +} +static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) +{ + return (v & 0xff) << 8; +} +static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) +{ + return 0xff << 8; +} +static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) +{ + return (r >> 8) & 0xff; +} +static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 trim_sys_sel_vco_r(void) +{ + return 0x00137100; +} +static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) +{ + return 0x1 << 0; +} +static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) +{ + return 0x00000000; +} +static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) +{ + return 0x0; +} +static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) +{ + return 0x0; +} +static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) +{ + return 0x1; +} +static inline u32 trim_sys_gpc2clk_out_r(void) +{ + return 0x00137250; +} +static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) +{ + return 6; +} +static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) +{ + return 0x3f << 0; +} +static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) +{ + return (r >> 0) & 0x3f; +} +static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) +{ + return 0x3c; +} +static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) +{ + return 0x3f << 8; +} +static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) +{ + return 0x0; +} +static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) +{ + return 0x1 << 31; +} +static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) +{ + return 0x80000000; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) +{ + return 0x00134124 + i*512; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) +{ + return (v & 0x3fff) << 0; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) +{ + return 0x10000; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) +{ + return 0x100000; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) +{ + return 0x1000000; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) +{ + return 0x00134128 + i*512; +} +static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) +{ + return (r >> 0) & 0xfffff; +} +static inline u32 trim_sys_gpcpll_cfg2_r(void) +{ + return 0x0013700c; +} +static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) +{ + return 0xff << 24; +} +static inline u32 trim_sys_gpcpll_cfg3_r(void) +{ + return 0x00137018; +} +static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) +{ + return (v & 0xff) << 16; +} +static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) +{ + return 0xff << 16; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) +{ + return 0x0013701c; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) +{ + return 0x1 << 22; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) +{ + return 0x400000; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) +{ + return 0x0; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) +{ + return 0x1 << 31; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) +{ + return 0x80000000; +} +static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) +{ + return 0x0; +} +static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) +{ + return 0x001328a0; +} +static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) +{ + return (r >> 24) & 0x1; +} +#endif -- cgit v1.2.2 From 6204b2d225e37bafeaf6426e1b7620b2d2cd51c0 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Thu, 2 Oct 2014 20:39:32 -0700 Subject: gpu: nvgpu: headers for linsim CL 33688874 Bug 1561645 Change-Id: Iccd909d54fc5b1d1c8fbc903b5908bf6f7f22ec8 Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/553151 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt --- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 54 ++++++++++++++++++-------------- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 24 ++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 32 +++---------------- drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 4 +-- drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 8 ++--- 5 files changed, 65 insertions(+), 57 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 7a4761d6b..031649575 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1126,18 +1126,6 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) { return 0x00000182; } -static inline u32 gr_pd_pagepool_r(void) -{ - return 0x004064cc; -} -static inline u32 gr_pd_pagepool_total_pages_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_pd_pagepool_valid_true_f(void) -{ - return 0x80000000; -} static inline u32 gr_pd_dist_skip_table_r(u32 i) { return 0x004064d0 + i*4; @@ -1302,6 +1290,18 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) { return 0x4; } +static inline u32 gr_ds_tga_constraintlogic_r(void) +{ + return 0xffffffff; +} +static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) +{ + return (v & 0x1) << -1; +} +static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) +{ + return (v & 0x1) << -1; +} static inline u32 gr_ds_hww_esr_r(void) { return 0x00405840; @@ -1536,7 +1536,7 @@ static inline u32 gr_scc_pagepool_r(void) } static inline u32 gr_scc_pagepool_total_pages_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0x3ff) << 0; } static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) { @@ -1544,7 +1544,7 @@ static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) } static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) { - return 0x00000080; + return 0x00000200; } static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) { @@ -1552,19 +1552,19 @@ static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) } static inline u32 gr_scc_pagepool_max_valid_pages_s(void) { - return 8; + return 10; } static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) { - return (v & 0xff) << 8; + return (v & 0x3ff) << 10; } static inline u32 gr_scc_pagepool_max_valid_pages_m(void) { - return 0xff << 8; + return 0x3ff << 10; } static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) { - return (r >> 8) & 0xff; + return (r >> 10) & 0x3ff; } static inline u32 gr_scc_pagepool_valid_true_f(void) { @@ -1788,7 +1788,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { - return 0x00100000; + return 0x00030000; } static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { @@ -2068,11 +2068,19 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0x3fffff) << 0; + return (v & 0xffffffff) << -1; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0x3fffff << 0; + return 0xffffffff << -1; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) +{ + return (v & 0xffffffff) << -1; +} +static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) +{ + return 0xffffffff << -1; } static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) { @@ -2080,7 +2088,7 @@ static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) } static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0x3ff) << 0; } static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) { @@ -2464,7 +2472,7 @@ static inline u32 gr_gpcs_gcc_pagepool_r(void) } static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) { - return (v & 0xff) << 0; + return (v & 0x3ff) << 0; } static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 1ead0679b..32c4a01d3 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -50,6 +50,30 @@ #ifndef _hw_ltc_gp10b_h_ #define _hw_ltc_gp10b_h_ +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0xffffffff; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0xffffffff; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0xffffffff; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0xffffffff; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0xffffffff; +} static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { return 0x0014046c; diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index f45fdc99a..83e06e8e0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -50,9 +50,9 @@ #ifndef _hw_mc_gp10b_h_ #define _hw_mc_gp10b_h_ -static inline u32 mc_intr_0_r(void) +static inline u32 mc_intr_0_r(u32 i) { - return 0x00000100; + return 0x00000100 + i*4; } static inline u32 mc_intr_0_pfifo_pending_f(void) { @@ -78,33 +78,9 @@ static inline u32 mc_intr_0_pbus_pending_f(void) { return 0x10000000; } -static inline u32 mc_intr_mask_0_r(void) +static inline u32 mc_intr_en_0_r(u32 i) { - return 0x00000640; -} -static inline u32 mc_intr_mask_0_pmu_enabled_f(void) -{ - return 0x1000000; -} -static inline u32 mc_intr_en_0_r(void) -{ - return 0x00000140; -} -static inline u32 mc_intr_en_0_inta_disabled_f(void) -{ - return 0x0; -} -static inline u32 mc_intr_en_0_inta_hardware_f(void) -{ - return 0x1; -} -static inline u32 mc_intr_en_1_r(void) -{ - return 0x00000144; -} -static inline u32 mc_intr_en_1_inta_disabled_f(void) -{ - return 0x0; + return 0x00000140 + i*4; } static inline u32 mc_enable_r(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index d3fa8553d..5720cde1a 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -448,7 +448,7 @@ static inline u32 pbdma_syncpointb_r(u32 i) } static inline u32 pbdma_syncpointb_op_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0) & 0x1; } static inline u32 pbdma_syncpointb_op_wait_v(void) { @@ -464,6 +464,6 @@ static inline u32 pbdma_syncpointb_wait_switch_en_v(void) } static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) { - return (r >> 8) & 0xff; + return (r >> 8) & 0xfff; } #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h index 76597f69d..94da91b0d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h @@ -200,11 +200,11 @@ static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) } static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) { - return 0x00134124 + i*512; + return 0x001e0124 + i*1024; } static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) { - return (v & 0x3fff) << 0; + return (v & 0xffff) << 0; } static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) { @@ -220,11 +220,11 @@ static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) } static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) { - return 0x00134128 + i*512; + return 0x001e0128 + i*1024; } static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) { - return (r >> 0) & 0xfffff; + return (r >> 0) & 0xfffffff; } static inline u32 trim_sys_gpcpll_cfg2_r(void) { -- cgit v1.2.2 From e1166b09af5c2505466f0a8a1e3878e6e581c916 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Tue, 14 Oct 2014 18:16:32 -0700 Subject: gpu: nvgpu: headers for linsim CL 33759297 Change-Id: Iaafb651875481b7fa31504642df86311ec9933a5 Signed-off-by: Adeel Raza --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 161c1ce0c..f6020434c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x1ffff) << 12; + return (v & 0x3ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 32c4a01d3..2b20199e4 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -148,7 +148,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x3ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { @@ -156,7 +156,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x3ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { -- cgit v1.2.2 From 937b3598f322ad52a0b2c1a8f19458f366970569 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 09:47:25 +0200 Subject: gpu: nvgpu: Synchronize gp10b headers with gm20b Added all registers added to gk20a and gm20b to gp10b. Remove gp10b trim registers, because they will not be accessed by CPU. Bug 1567274 Change-Id: Ib6be34ce3d55901bd7e1f30eea8e43725719a912 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/590312 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 68 +++++- drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 32 ++- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 20 ++ drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 44 ++++ drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 228 ++++++++++++-------- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 250 +++++++++++++++++++--- drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 50 ++++- drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 20 ++ drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 12 ++ drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 62 +++++- drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 72 ++----- drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h | 289 -------------------------- 13 files changed, 662 insertions(+), 487 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 6339cf5b6..79890f3cb 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -90,13 +90,25 @@ static inline u32 ctxsw_prog_main_image_pm_o(void) { return 0x00000028; } -static inline u32 ctxsw_prog_main_image_pm_mode_v(u32 r) +static inline u32 ctxsw_prog_main_image_pm_mode_m(void) { - return (r >> 0) & 0x7; + return 0x7 << 0; } -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_v(void) +static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) { - return 0x00000000; + return 0x0; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) +{ + return 0x7 << 3; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) +{ + return 0x8; +} +static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) +{ + return 0x0; } static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) { @@ -178,4 +190,52 @@ static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_strid { return 0x00000002; } +static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) +{ + return 0x000000a0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) +{ + return 2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) +{ + return 0x3 << 0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) +{ + return 0x2; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) +{ + return 0x000000a4; +} +static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) +{ + return 0x000000a8; +} +static inline u32 ctxsw_prog_main_image_misc_options_o(void) +{ + return 0x0000003c; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) +{ + return 0x1 << 3; +} +static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h index 9dacabce5..d2ecdce12 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h @@ -66,6 +66,10 @@ static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) { return 0x0; } +static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) +{ + return 0x1; +} static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) { return (r >> 15) & 0x1; @@ -78,6 +82,22 @@ static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) { return (r >> 16) & 0xff; } +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) +{ + return 0x800; +} +static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) +{ + return 0x0; +} +static inline u32 fb_priv_mmu_phy_secure_r(void) +{ + return 0x00100ce4; +} static inline u32 fb_mmu_invalidate_pdb_r(void) { return 0x00100cb8; @@ -158,9 +178,9 @@ static inline u32 fb_mmu_debug_wr_vol_true_f(void) { return 0x4; } -static inline u32 fb_mmu_debug_wr_addr_v(u32 r) +static inline u32 fb_mmu_debug_wr_addr_f(u32 v) { - return (r >> 4) & 0xfffffff; + return (v & 0xfffffff) << 4; } static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) { @@ -178,9 +198,9 @@ static inline u32 fb_mmu_debug_rd_vol_false_f(void) { return 0x0; } -static inline u32 fb_mmu_debug_rd_addr_v(u32 r) +static inline u32 fb_mmu_debug_rd_addr_f(u32 v) { - return (r >> 4) & 0xfffffff; + return (v & 0xfffffff) << 4; } static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) { @@ -202,10 +222,6 @@ static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0; } -static inline u32 fb_mmu_vpr_info_fetch_f(u32 v) -{ - return (v & 0x1) << 2; -} static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) { return (r >> 2) & 0x1; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 764c1b6c6..b79758d21 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -206,6 +206,10 @@ static inline u32 fifo_intr_en_0_r(void) { return 0x00002140; } +static inline u32 fifo_intr_en_0_sched_error_m(void) +{ + return 0x1 << 8; +} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; @@ -346,10 +350,18 @@ static inline u32 fifo_preempt_type_channel_f(void) { return 0x0; } +static inline u32 fifo_preempt_type_tsg_f(void) +{ + return 0x1000000; +} static inline u32 fifo_preempt_chid_f(u32 v) { return (v & 0xfff) << 0; } +static inline u32 fifo_preempt_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} static inline u32 fifo_trigger_mmu_fault_r(u32 i) { return 0x00002a30 + i*4; @@ -382,6 +394,10 @@ static inline u32 fifo_engine_status_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_engine_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} static inline u32 fifo_engine_status_ctx_status_v(u32 r) { return (r >> 13) & 0x7; @@ -466,6 +482,10 @@ static inline u32 fifo_pbdma_status_id_type_chid_v(void) { return 0x00000000; } +static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) +{ + return 0x00000001; +} static inline u32 fifo_pbdma_status_chan_status_v(u32 r) { return (r >> 13) & 0x7; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index 00291d301..272f7fb3e 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h @@ -54,4 +54,48 @@ static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) { return 0x00021c38 + i*4; } +static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) +{ + return 0x00021838 + i*4; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) +{ + return 0x00021944; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) +{ + return 0x3 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) +{ + return (r >> 0) & 0x3; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) +{ + return 0x00021948; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) +{ + return 0x1 << 0; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) +{ + return 0x1; +} +static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index f6020434c..161c1ce0c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x3ffff) << 12; + return (v & 0x1ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 031649575..f86076187 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -78,6 +78,26 @@ static inline u32 gr_intr_illegal_method_reset_f(void) { return 0x10; } +static inline u32 gr_intr_illegal_notify_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_illegal_notify_reset_f(void) +{ + return 0x40; +} +static inline u32 gr_intr_firmware_method_f(u32 v) +{ + return (v & 0x1) << 8; +} +static inline u32 gr_intr_firmware_method_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_intr_firmware_method_reset_f(void) +{ + return 0x100; +} static inline u32 gr_intr_illegal_class_pending_f(void) { return 0x20; @@ -86,6 +106,14 @@ static inline u32 gr_intr_illegal_class_reset_f(void) { return 0x20; } +static inline u32 gr_intr_fecs_error_pending_f(void) +{ + return 0x80000; +} +static inline u32 gr_intr_fecs_error_reset_f(void) +{ + return 0x80000; +} static inline u32 gr_intr_class_error_pending_f(void) { return 0x100000; @@ -102,6 +130,26 @@ static inline u32 gr_intr_exception_reset_f(void) { return 0x200000; } +static inline u32 gr_fecs_intr_r(void) +{ + return 0x00400144; +} +static inline u32 gr_class_error_r(void) +{ + return 0x00400110; +} +static inline u32 gr_class_error_code_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_intr_nonstall_r(void) +{ + return 0x00400120; +} +static inline u32 gr_intr_nonstall_trap_pending_f(void) +{ + return 0x2; +} static inline u32 gr_intr_en_r(void) { return 0x0040013c; @@ -198,6 +246,10 @@ static inline u32 gr_status_r(void) { return 0x00400700; } +static inline u32 gr_status_fe_method_upper_v(u32 r) +{ + return (r >> 1) & 0x1; +} static inline u32 gr_status_fe_method_lower_v(u32 r) { return (r >> 2) & 0x1; @@ -206,6 +258,10 @@ static inline u32 gr_status_fe_method_lower_idle_v(void) { return 0x00000000; } +static inline u32 gr_status_fe_gi_v(u32 r) +{ + return (r >> 21) & 0x1; +} static inline u32 gr_status_mask_r(void) { return 0x00400610; @@ -662,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { return 0x21; } +static inline u32 gr_fecs_host_int_status_r(void) +{ + return 0x00409c18; +} +static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) +{ + return (v & 0x1) << 17; +} +static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) +{ + return (v & 0x1) << 18; +} +static inline u32 gr_fecs_host_int_clear_r(void) +{ + return 0x00409c20; +} static inline u32 gr_fecs_host_int_enable_r(void) { return 0x00409c24; @@ -1292,15 +1364,19 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) } static inline u32 gr_ds_tga_constraintlogic_r(void) { - return 0xffffffff; + return 0x00405830; } static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { - return (v & 0x1) << -1; + return (v & 0x3fffff) << 0; +} +static inline u32 gr_ds_tga_constraintlogic_r(void) +{ + return 0x0040585c; } static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) { - return (v & 0x1) << -1; + return (v & 0xffff) << 0; } static inline u32 gr_ds_hww_esr_r(void) { @@ -1674,6 +1750,34 @@ static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) { return (r >> 0) & 0x3f; } +static inline u32 gr_gpccs_rc_lane_size_r(void) +{ + return 0x00502910; +} +static inline u32 gr_gpccs_rc_lane_size_v_s(void) +{ + return 24; +} +static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_m(void) +{ + return 0xffffff << 0; +} +static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) +{ + return 0x0; +} static inline u32 gr_gpc0_zcull_fs_r(void) { return 0x00500910; @@ -2068,19 +2172,11 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) { - return (v & 0xffffffff) << -1; + return (v & 0x3fffff) << 0; } static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { - return 0xffffffff << -1; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_f(u32 v) -{ - return (v & 0xffffffff) << -1; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_div3_m(void) -{ - return 0xffffffff << -1; + return 0x3fffff << 0; } static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) { @@ -2526,26 +2622,6 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) { return 0x10000000; } -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_r(void) -{ - return 0x00419e00; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_m(void) -{ - return 0x1 << 7; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_core_enable_enable_f(void) -{ - return 0x80; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_m(void) -{ - return 0x1 << 15; -} -static inline u32 gr_gpcs_tpcs_sm_pm_ctrl_qctl_enable_enable_f(void) -{ - return 0x8000; -} static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) { return 0x00419e44; @@ -2670,51 +2746,51 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complet { return 0x40; } -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) { - return 0x0050450c; + return 0x00419d0c; } -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { return 0x2; } -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_disabled_f(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { - return 0x0; + return 0x0050450c; } -static inline u32 gr_gpc0_gpccs_gpc_exception_en_r(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { - return 0x00502c94; + return 0x2; } -static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f(void) +static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) { - return 0x10000; + return 0x0041ac94; } -static inline u32 gr_gpc0_gpccs_gpc_exception_en_tpc_0_disabled_f(void) +static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) { - return 0x0; + return (v & 0xff) << 16; } -static inline u32 gr_gpcs_gpccs_gpc_exception_r(void) +static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) { - return 0x0041ac90; + return 0x00502c90; } -static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_v(u32 r) +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) { return (r >> 16) & 0xff; } -static inline u32 gr_gpcs_gpccs_gpc_exception_tpc_0_pending_v(void) +static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) { return 0x00000001; } -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_r(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { - return 0x00419d08; + return 0x00504508; } -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_v(u32 r) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { return (r >> 1) & 0x1; } -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_sm_pending_v(void) +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) { return 0x00000001; } @@ -2810,10 +2886,6 @@ static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) { return (v & 0x1) << 0; } -static inline u32 gr_gpcs_tpcs_sm_power_throttle_r(void) -{ - return 0x00419ed8; -} static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) { return 0x0041be08; @@ -3078,42 +3150,6 @@ static inline u32 gr_fe_pwr_mode_req_done_v(void) { return 0x00000000; } -static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_r(void) -{ - return 0x00419f88; -} -static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_sm_sfe_ba_control_blkactivity_enable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_r(void) -{ - return 0x00419f80; -} -static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_sm_quad_ba_control_blkactivity_enable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_r(void) -{ - return 0x00419ccc; -} -static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_sm_mio_ba_control_blkactivity_enable_m(void) -{ - return 0x1 << 31; -} static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) { return 0x00418880; @@ -3166,6 +3202,14 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) { return 0x004188b0; } +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) +{ + return 0x00000001; +} static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) { return 0x004188b4; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 2b20199e4..a38cfe8de 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -50,30 +50,6 @@ #ifndef _hw_ltc_gp10b_h_ #define _hw_ltc_gp10b_h_ -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0xffffffff; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0xffffffff; -} static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) { return 0x0014046c; @@ -140,7 +116,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) } static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) { - return 0x0017e26c; + return 0x0014046c; } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) { @@ -148,7 +124,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x1ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { @@ -156,7 +132,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x3ffff) << 0; + return (v & 0x1ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { @@ -298,8 +274,224 @@ static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) { return 0x1; } -static inline u32 ltc_ltc0_ltss_intr_r(void) +static inline u32 ltc_ltcs_ltss_intr_r(void) { - return 0x0014020c; + return 0x0017e20c; +} +static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) +{ + return 0x1 << 20; +} +static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) +{ + return 0x1 << 30; +} +static inline u32 ltc_ltc0_lts0_intr_r(void) +{ + return 0x0014040c; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) +{ + return 0x0017e2a0; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) +{ + return 0x0017e2a4; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) +{ + return (r >> 8) & 0xf; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) +{ + return 0x00000003; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) +{ + return 0x300; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) +{ + return (r >> 16) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) +{ + return 0x10000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) +{ + return (r >> 28) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) +{ + return 0x10000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) +{ + return (r >> 29) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) +{ + return 0x20000000; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) +{ + return 0x40000000; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) +{ + return 0x001402a0; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) +{ + return 0x001402a4; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) +{ + return 0x001422a0; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) +{ + return 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) +{ + return 0x001422a4; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) +{ + return 0x00000001; +} +static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) +{ + return 0x1; } #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index 83e06e8e0..ba0af4973 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -50,38 +50,62 @@ #ifndef _hw_mc_gp10b_h_ #define _hw_mc_gp10b_h_ -static inline u32 mc_intr_0_r(u32 i) +static inline u32 mc_boot_0_r(void) { - return 0x00000100 + i*4; + return 0x00000000; } -static inline u32 mc_intr_0_pfifo_pending_f(void) +static inline u32 mc_boot_0_architecture_v(u32 r) { - return 0x100; + return (r >> 24) & 0x1f; } -static inline u32 mc_intr_0_pgraph_pending_f(void) +static inline u32 mc_boot_0_implementation_v(u32 r) { - return 0x1000; + return (r >> 20) & 0xf; +} +static inline u32 mc_boot_0_major_revision_v(u32 r) +{ + return (r >> 4) & 0xf; +} +static inline u32 mc_boot_0_minor_revision_v(u32 r) +{ + return (r >> 0) & 0xf; +} +static inline u32 mc_intr_r(u32 i) +{ + return 0x00000100 + i*4; } -static inline u32 mc_intr_0_pmu_pending_f(void) +static inline u32 mc_intr_pfifo_pending_f(void) +{ + return 0x100; +} +static inline u32 mc_intr_pmu_pending_f(void) { return 0x1000000; } -static inline u32 mc_intr_0_ltc_pending_f(void) +static inline u32 mc_intr_ltc_pending_f(void) { return 0x2000000; } -static inline u32 mc_intr_0_priv_ring_pending_f(void) +static inline u32 mc_intr_priv_ring_pending_f(void) { return 0x40000000; } -static inline u32 mc_intr_0_pbus_pending_f(void) +static inline u32 mc_intr_pbus_pending_f(void) { return 0x10000000; } -static inline u32 mc_intr_en_0_r(u32 i) +static inline u32 mc_intr_en_r(u32 i) { return 0x00000140 + i*4; } +static inline u32 mc_intr_en_set_r(u32 i) +{ + return 0x00000160 + i*4; +} +static inline u32 mc_intr_en_clear_r(u32 i) +{ + return 0x00000180 + i*4; +} static inline u32 mc_enable_r(void) { return 0x00000200; @@ -162,6 +186,10 @@ static inline u32 mc_enable_hub_enabled_f(void) { return 0x20000000; } +static inline u32 mc_intr_ltc_r(void) +{ + return 0x000001c0; +} static inline u32 mc_enable_pb_r(void) { return 0x00000204; diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index 5720cde1a..91429b47f 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -174,6 +174,10 @@ static inline u32 pbdma_pb_header_type_inc_f(void) { return 0x20000000; } +static inline u32 pbdma_hdr_shadow_r(u32 i) +{ + return 0x00040118 + i*8192; +} static inline u32 pbdma_subdevice_r(u32 i) { return 0x00040094 + i*8192; @@ -466,4 +470,20 @@ static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) { return (r >> 8) & 0xfff; } +static inline u32 pbdma_runlist_timeslice_r(u32 i) +{ + return 0x000400f8 + i*8192; +} +static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) +{ + return 0x80; +} +static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) +{ + return 0x3000; +} +static inline u32 pbdma_runlist_timeslice_enable_true_f(void) +{ + return 0x10000000; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h index d76095ac2..0de70b967 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h @@ -378,6 +378,18 @@ static inline u32 pwr_falcon_bootvec_vec_f(u32 v) { return (v & 0xffffffff) << 0; } +static inline u32 pwr_falcon_dmactl_r(void) +{ + return 0x0010a10c; +} +static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) +{ + return 0x1 << 1; +} +static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) +{ + return 0x1 << 2; +} static inline u32 pwr_falcon_hwcfg_r(void) { return 0x0010a108; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index ef53882b1..509031e5d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,6 +78,26 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_big_page_size_f(u32 v) +{ + return (v & 0x1) << 11; +} +static inline u32 ram_in_big_page_size_m(void) +{ + return 0x1 << 11; +} +static inline u32 ram_in_big_page_size_w(void) +{ + return 128; +} +static inline u32 ram_in_big_page_size_128kb_f(void) +{ + return 0x0; +} +static inline u32 ram_in_big_page_size_64kb_f(void) +{ + return 0x800; +} static inline u32 ram_in_page_dir_base_lo_f(u32 v) { return (v & 0xfffff) << 12; @@ -318,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void) { return 0; } -static inline u32 ram_fc_pb_timeslice_w(void) +static inline u32 ram_fc_runlist_timeslice_w(void) { return 62; } @@ -382,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void) { return 0x00000008; } +static inline u32 ram_rl_entry_chid_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_id_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 ram_rl_entry_type_f(u32 v) +{ + return (v & 0x1) << 13; +} +static inline u32 ram_rl_entry_type_chid_f(void) +{ + return 0x0; +} +static inline u32 ram_rl_entry_type_tsg_f(void) +{ + return 0x2000; +} +static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) +{ + return (v & 0xf) << 14; +} +static inline u32 ram_rl_entry_timeslice_scale_3_f(void) +{ + return 0xc000; +} +static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) +{ + return (v & 0xff) << 18; +} +static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) +{ + return 0x2000000; +} +static inline u32 ram_rl_entry_tsg_length_f(u32 v) +{ + return (v & 0x3f) << 26; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h index 16bbb3cab..25eecb702 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h @@ -70,58 +70,6 @@ static inline u32 therm_weight_1_r(void) { return 0x00020024; } -static inline u32 therm_peakpower_config1_r(u32 i) -{ - return 0x00020154 + i*4; -} -static inline u32 therm_peakpower_config1_window_period_2m_v(void) -{ - return 0x00000015; -} -static inline u32 therm_peakpower_config1_window_period_2m_f(void) -{ - return 0x15; -} -static inline u32 therm_peakpower_config1_window_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 therm_peakpower_config1_r(u32 i) -{ - return 0x000202e8 + i*4; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) -{ - return 5; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) -{ - return 0x1f << 8; -} -static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) -{ - return (r >> 8) & 0x1f; -} -static inline u32 therm_peakpower_config2_r(u32 i) -{ - return 0x00020170 + i*4; -} -static inline u32 therm_peakpower_config4_r(u32 i) -{ - return 0x000201c0 + i*4; -} -static inline u32 therm_peakpower_config8_r(u32 i) -{ - return 0x000202e8 + i*4; -} -static inline u32 therm_peakpower_config9_r(u32 i) -{ - return 0x000202f4 + i*4; -} static inline u32 therm_config1_r(void) { return 0x00020050; @@ -214,4 +162,24 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void) { return 0xffffffff << 0; } +static inline u32 therm_clk_slowdown_r(u32 i) +{ + return 0x00020160 + i*4; +} +static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) +{ + return (v & 0x3f) << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_m(void) +{ + return 0x3f << 16; +} +static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) +{ + return (r >> 16) & 0x3f; +} +static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h deleted file mode 100644 index 94da91b0d..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_trim_gp10b.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_trim_gp10b_h_ -#define _hw_trim_gp10b_h_ - -static inline u32 trim_sys_gpcpll_cfg_r(void) -{ - return 0x00137000; -} -static inline u32 trim_sys_gpcpll_cfg_enable_m(void) -{ - return 0x1 << 0; -} -static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void) -{ - return 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_m(void) -{ - return 0x1 << 1; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) -{ - return 0x00000000; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) -{ - return 0x1 << 4; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void) -{ - return 0x10; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r) -{ - return (r >> 17) & 0x1; -} -static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void) -{ - return 0x20000; -} -static inline u32 trim_sys_gpcpll_coeff_r(void) -{ - return 0x00137004; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void) -{ - return 0xff << 8; -} -static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r) -{ - return (r >> 8) & 0xff; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v) -{ - return (v & 0x3f) << 16; -} -static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r) -{ - return (r >> 16) & 0x3f; -} -static inline u32 trim_sys_sel_vco_r(void) -{ - return 0x00137100; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void) -{ - return 0x1 << 0; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void) -{ - return 0x00000000; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void) -{ - return 0x1; -} -static inline u32 trim_sys_gpc2clk_out_r(void) -{ - return 0x00137250; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void) -{ - return 6; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void) -{ - return 0x3f << 0; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) -{ - return 0x3c; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) -{ - return 0x3f << 8; -} -static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void) -{ - return 0x1 << 31; -} -static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void) -{ - return 0x80000000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i) -{ - return 0x001e0124 + i*1024; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) -{ - return 0x10000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) -{ - return 0x100000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) -{ - return 0x1000000; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i) -{ - return 0x001e0128 + i*1024; -} -static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 trim_sys_gpcpll_cfg2_r(void) -{ - return 0x0013700c; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void) -{ - return 0xff << 24; -} -static inline u32 trim_sys_gpcpll_cfg3_r(void) -{ - return 0x00137018; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void) -{ - return 0xff << 16; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void) -{ - return 0x0013701c; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void) -{ - return 0x1 << 22; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void) -{ - return 0x400000; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void) -{ - return 0x0; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void) -{ - return 0x1 << 31; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void) -{ - return 0x80000000; -} -static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void) -{ - return 0x0; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void) -{ - return 0x001328a0; -} -static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r) -{ - return (r >> 24) & 0x1; -} -#endif -- cgit v1.2.2 From 3e0dd9e802c3f02983e5fcb2222b7252b5246133 Mon Sep 17 00:00:00 2001 From: Kenneth Adams Date: Wed, 1 Oct 2014 08:27:17 -0700 Subject: gpu: nvgpu: t18x, gp10b framework This change adds gp10b to the nvgpu build as well as enabling CMA for buffer allocation. Change-Id: Id3d45ad6ffdab14120395952e68b285dd7364c76 Signed-off-by: Ken Adams Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/553324 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile | 10 ++++ drivers/gpu/nvgpu/gp10b/Makefile | 13 +++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 54 +++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 31 +++++++++++ drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h | 28 ++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 98 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.h | 21 ++++++++ drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h | 30 +++++++++++ 8 files changed, 285 insertions(+) create mode 100644 drivers/gpu/nvgpu/Makefile create mode 100644 drivers/gpu/nvgpu/gp10b/Makefile create mode 100644 drivers/gpu/nvgpu/gp10b/gr_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/gr_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hal_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/hal_gp10b.h create mode 100644 drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile new file mode 100644 index 000000000..c583f6d5b --- /dev/null +++ b/drivers/gpu/nvgpu/Makefile @@ -0,0 +1,10 @@ +GCOV_PROFILE := y + +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/include/linux +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include +ccflags-$(CONFIG_GK20A) += -Wno-multichar +ccflags-$(CONFIG_GK20A) += -Werror + +obj-$(CONFIG_GK20A) += gp10b/ + diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile new file mode 100644 index 000000000..64cd41798 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -0,0 +1,13 @@ +GCOV_PROFILE := y + +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi + +ccflags-$(CONFIG_GK20A) += -Wno-multichar + +obj-$(CONFIG_GK20A) += \ + gr_gp10b.o \ + hal_gp10b.o diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c new file mode 100644 index 000000000..f4a63fad1 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -0,0 +1,54 @@ +/* + * GP10B GPU GR + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ + +#include "gk20a/gr_gk20a.h" + +#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ +#include "gp10b/gr_gp10b.h" + + +bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) +{ + bool valid = false; + + switch (class_num) { + case PASCAL_COMPUTE_A: + case PASCAL_A: + case PASCAL_DMA_COPY_A: + valid = true; + break; + + case MAXWELL_COMPUTE_B: + case MAXWELL_B: + case FERMI_TWOD_A: + case KEPLER_DMA_COPY_A: + case MAXWELL_DMA_COPY_A: + valid = true; + break; + + default: + break; + } + gk20a_dbg_info("class=0x%x valid=%d", class_num, valid); + return valid; +} + +void gp10b_init_gr(struct gpu_ops *gops) +{ + gm20b_init_gr(gops); + gops->gr.is_valid_class = gr_gp10b_is_valid_class; +} diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h new file mode 100644 index 000000000..58616debc --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -0,0 +1,31 @@ +/* + * GM20B GPU GR + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GR_GP10B_H_ +#define _NVGPU_GR_GP10B_H_ + +struct gk20a; + +enum { + PASCAL_CHANNEL_GPFIFO_A = 0xC06F, + PASCAL_A = 0xC097, + PASCAL_COMPUTE_A = 0xC0C0, + PASCAL_DMA_COPY_A = 0xC0B5, +}; + +void gp10b_init_gr(struct gpu_ops *ops); + + +#endif diff --git a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h new file mode 100644 index 000000000..c32770178 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h @@ -0,0 +1,28 @@ +/* + * GP10B GPU graphics ops + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _GR_OPS_GP10B_H_ +#define _GR_OPS_GP10B_H_ + +#include "gr_ops.h" + +#define __gr_gp10b_op(X) gr_gp10b_ ## X +#define __set_gr_gp10b_op(X) . X = gr_gp10b_ ## X + +bool __gr_gp10b_op(is_valid_class)(struct gk20a *, u32); +int __gr_gp10b_op(alloc_obj_ctx)(struct channel_gk20a *, struct nvgpu_alloc_obj_ctx_args *); + + +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c new file mode 100644 index 000000000..61bae5c79 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -0,0 +1,98 @@ +/* + * GP10B Tegra HAL interface + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#include + +#include "gk20a/gk20a.h" + +#include "gp10b/gr_gp10b.h" + +#include "gm20b/ltc_gm20b.h" +#include "gm20b/fb_gm20b.h" +#include "gm20b/gm20b_gating_reglist.h" +#include "gm20b/fifo_gm20b.h" +#include "gm20b/gr_ctx_gm20b.h" +#include "gm20b/mm_gm20b.h" +#include "gm20b/pmu_gm20b.h" +#include "gm20b/clk_gm20b.h" + +struct gpu_ops gp10b_ops = { + .clock_gating = { + .slcg_bus_load_gating_prod = + gm20b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gm20b_slcg_ce2_load_gating_prod, + .slcg_chiplet_load_gating_prod = + gm20b_slcg_chiplet_load_gating_prod, + .slcg_ctxsw_firmware_load_gating_prod = + gm20b_slcg_ctxsw_firmware_load_gating_prod, + .slcg_fb_load_gating_prod = + gm20b_slcg_fb_load_gating_prod, + .slcg_fifo_load_gating_prod = + gm20b_slcg_fifo_load_gating_prod, + .slcg_gr_load_gating_prod = + gr_gm20b_slcg_gr_load_gating_prod, + .slcg_ltc_load_gating_prod = + ltc_gm20b_slcg_ltc_load_gating_prod, + .slcg_perf_load_gating_prod = + gm20b_slcg_perf_load_gating_prod, + .slcg_priring_load_gating_prod = + gm20b_slcg_priring_load_gating_prod, + .slcg_pmu_load_gating_prod = + gm20b_slcg_pmu_load_gating_prod, + .slcg_therm_load_gating_prod = + gm20b_slcg_therm_load_gating_prod, + .slcg_xbar_load_gating_prod = + gm20b_slcg_xbar_load_gating_prod, + .blcg_bus_load_gating_prod = + gm20b_blcg_bus_load_gating_prod, + .blcg_ctxsw_firmware_load_gating_prod = + gm20b_blcg_ctxsw_firmware_load_gating_prod, + .blcg_fb_load_gating_prod = + gm20b_blcg_fb_load_gating_prod, + .blcg_fifo_load_gating_prod = + gm20b_blcg_fifo_load_gating_prod, + .blcg_gr_load_gating_prod = + gm20b_blcg_gr_load_gating_prod, + .blcg_ltc_load_gating_prod = + gm20b_blcg_ltc_load_gating_prod, + .blcg_pwr_csb_load_gating_prod = + gm20b_blcg_pwr_csb_load_gating_prod, + .blcg_pmu_load_gating_prod = + gm20b_blcg_pmu_load_gating_prod, + .pg_gr_load_gating_prod = + gr_gm20b_pg_gr_load_gating_prod, + } +}; + +int gp10b_init_hal(struct gpu_ops *gops) +{ + *gops = gp10b_ops; + gm20b_init_ltc(gops); + gp10b_init_gr(gops); + gm20b_init_ltc(gops); + gm20b_init_fb(gops); + gm20b_init_fifo(gops); + gm20b_init_gr_ctx(gops); + gm20b_init_mm(gops); + gm20b_init_pmu_ops(gops); + gm20b_init_clk_ops(gops); + gops->name = "gp10b"; + + return 0; +} diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h new file mode 100644 index 000000000..78615ed10 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h @@ -0,0 +1,21 @@ +/* + * GP10B Tegra HAL interface + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_HAL_GP10B_H +#define _NVGPU_HAL_GP10B_H +struct gpu_ops; + +int gp10b_init_hal(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h new file mode 100644 index 000000000..fe027fb01 --- /dev/null +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h @@ -0,0 +1,30 @@ +/* + * NVIDIA GPU ID functions, definitions. + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPU_GPUID_T18X_H_ +#define _NVGPU_GPUID_T18X_H_ + +#define NVGPU_GPUID_GP10B \ + GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP10B) + +#define NVGPU_COMPAT_TEGRA_GP10B "nvidia,tegra186-gp10b" +#define NVGPU_COMPAT_GENERIC_GP10B "nvidia,generic-gp10b" + +#define TEGRA_18x_GPUID NVGPU_GPUID_GP10B +#define TEGRA_18x_GPUID_HAL gp10b_init_hal +#define TEGRA_18x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GP10B +#define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B +struct gpu_ops; +extern int gp10b_init_hal(struct gpu_ops *); +#endif -- cgit v1.2.2 From 5e4fa3555ffb611a2517f2451080f533ab643b87 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 27 Oct 2014 15:05:45 +0200 Subject: gpu: nvgpu: Implement gp10b intr processing Bug 1567274 Change-Id: I2a6cef954b56d1f97208d29584e0748ec1c5e29d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/591628 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 + drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 4 + drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 135 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 24 ++++++ 5 files changed, 166 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 64cd41798..722cc5503 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -10,4 +10,5 @@ ccflags-$(CONFIG_GK20A) += -Wno-multichar obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ + mc_gp10b.o \ hal_gp10b.o diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 61bae5c79..235254c84 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gp10b/gr_gp10b.h" +#include "gp10b/mc_gp10b.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/fb_gm20b.h" @@ -83,6 +84,7 @@ struct gpu_ops gp10b_ops = { int gp10b_init_hal(struct gpu_ops *gops) { *gops = gp10b_ops; + gp10b_init_mc(gops); gm20b_init_ltc(gops); gp10b_init_gr(gops); gm20b_init_ltc(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index ba0af4973..21c592da5 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) { return 0x100; } +static inline u32 mc_intr_pgraph_pending_f(void) +{ + return 0x1000; +} static inline u32 mc_intr_pmu_pending_f(void) { return 0x1000000; diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c new file mode 100644 index 000000000..cdafaf562 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -0,0 +1,135 @@ +/* + * GP20B master + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "mc_gp10b.h" +#include "hw_mc_gp10b.h" + +void mc_gp10b_intr_enable(struct gk20a *g) +{ + if (!tegra_platform_is_linsim()) { + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(0), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f()); + gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(1), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f()); + } +} + +irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) +{ + u32 mc_intr_0; + + if (!g->power_on) + return IRQ_NONE; + + /* not from gpu when sharing irq with others */ + mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + if (unlikely(!mc_intr_0)) + return IRQ_NONE; + + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); + + return IRQ_WAKE_THREAD; +} + +irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) +{ + u32 mc_intr_1; + + if (!g->power_on) + return IRQ_NONE; + + /* not from gpu when sharing irq with others */ + mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); + if (unlikely(!mc_intr_1)) + return IRQ_NONE; + + gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); + + return IRQ_WAKE_THREAD; +} + +irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) +{ + u32 mc_intr_0; + + gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); + + mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); + + gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); + + if (mc_intr_0 & mc_intr_pgraph_pending_f()) + gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + if (mc_intr_0 & mc_intr_pfifo_pending_f()) + gk20a_fifo_isr(g); + if (mc_intr_0 & mc_intr_pmu_pending_f()) + gk20a_pmu_isr(g); + if (mc_intr_0 & mc_intr_priv_ring_pending_f()) + gk20a_priv_ring_isr(g); + if (mc_intr_0 & mc_intr_ltc_pending_f()) + g->ops.ltc.isr(g); + if (mc_intr_0 & mc_intr_pbus_pending_f()) + gk20a_pbus_isr(g); + + gk20a_writel(g, mc_intr_en_set_r(0), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f()); + + return IRQ_HANDLED; +} + +irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) +{ + u32 mc_intr_1; + + gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); + + mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); + + gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1); + + if (mc_intr_1 & mc_intr_pfifo_pending_f()) + gk20a_fifo_nonstall_isr(g); + if (mc_intr_1 & mc_intr_pgraph_pending_f()) + gk20a_gr_nonstall_isr(g); + + gk20a_writel(g, mc_intr_en_set_r(1), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f()); + + return IRQ_HANDLED; +} + +void gp10b_init_mc(struct gpu_ops *gops) +{ + gops->mc.intr_enable = mc_gp10b_intr_enable; + gops->mc.isr_stall = mc_gp10b_isr_stall; + gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; + gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; + gops->mc.isr_thread_nonstall = mc_gp10b_intr_thread_nonstall; +} diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h new file mode 100644 index 000000000..f274ce059 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MC_GP20B_H +#define MC_GP20B_H +struct gk20a; + +void gp10b_init_mc(struct gpu_ops *gops); +void mc_gp10b_intr_enable(struct gk20a *g); +irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); +irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); +irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); +irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g); +#endif -- cgit v1.2.2 From e77c8fd3466489f7673c43f2b674b564e078cb4b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 31 Oct 2014 12:12:25 +0200 Subject: gpu: nvgpu: gp10b specific CB callbacks Bug 1570662 Change-Id: Icb7e90b1216acfd19bb3027dc9e9844eb08c99d9 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/592101 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 115 +++++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 ++- 2 files changed, 120 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f4a63fad1..b7a52be0d 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -19,7 +19,8 @@ #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ #include "gp10b/gr_gp10b.h" - +#include "hw_gr_gp10b.h" +#include "hw_proj_gp10b.h" bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -47,8 +48,120 @@ bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) return valid; } +int gr_gp10b_commit_global_cb_manager(struct gk20a *g, + struct channel_gk20a *c, bool patch) +{ + struct gr_gk20a *gr = &g->gr; + struct channel_ctx_gk20a *ch_ctx = NULL; + u32 attrib_offset_in_chunk = 0; + u32 alpha_offset_in_chunk = 0; + u32 pd_ab_max_output; + u32 gpc_index, ppc_index; + u32 temp; + u32 cbm_cfg_size1, cbm_cfg_size2; + + gk20a_dbg_fn(""); + + if (patch) { + int err; + ch_ctx = &c->ch_ctx; + err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + if (err) + return err; + } + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), + gr->attrib_cb_default_size, patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(), + gr->alpha_cb_default_size, patch); + + pd_ab_max_output = (gr->alpha_cb_default_size * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) / + gr_pd_ab_dist_cfg1_max_output_granularity_v(); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(), + gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | + gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); + + alpha_offset_in_chunk = attrib_offset_in_chunk + + gr->tpc_count * gr->attrib_cb_size; + + for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { + temp = proj_gpc_stride_v() * gpc_index; + for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; + ppc_index++) { + cbm_cfg_size1 = gr->attrib_cb_default_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + cbm_cfg_size2 = gr->alpha_cb_default_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + cbm_cfg_size1, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + attrib_offset_in_chunk, patch); + + attrib_offset_in_chunk += gr->attrib_cb_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + cbm_cfg_size2, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + alpha_offset_in_chunk, patch); + + alpha_offset_in_chunk += gr->alpha_cb_size * + gr->pes_tpc_count[ppc_index][gpc_index]; + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index], + patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index), + gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1), + patch); + } + } + + if (patch) + gr_gk20a_ctx_patch_write_end(g, ch_ctx); + + return 0; +} + +void gr_gp10b_commit_global_pagepool(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, u32 size, bool patch) +{ + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(), + gr_scc_pagepool_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(), + gr_scc_pagepool_total_pages_f(size) | + gr_scc_pagepool_valid_true_f(), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(), + gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(), + gr_gpcs_gcc_pagepool_total_pages_f(size), patch); +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); gops->gr.is_valid_class = gr_gp10b_is_valid_class; + gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; + gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index f86076187..9b6811048 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1362,7 +1362,7 @@ static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) { return 0x4; } -static inline u32 gr_ds_tga_constraintlogic_r(void) +static inline u32 gr_ds_tga_constraintlogic_beta_r(void) { return 0x00405830; } @@ -1370,7 +1370,7 @@ static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) { return (v & 0x3fffff) << 0; } -static inline u32 gr_ds_tga_constraintlogic_r(void) +static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) { return 0x0040585c; } @@ -1926,6 +1926,10 @@ static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) { return 0x005030f8; } +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) +{ + return 0x005030f0; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; -- cgit v1.2.2 From e806b05c8c2bf05bf0aaa19f053bfad59be61d4f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 3 Nov 2014 10:37:29 +0200 Subject: gpu: nvgpu: gp10b: Add SM debug registers Add SM debug registers to gp10b, and regenerate headers. Bug 1567274 Change-Id: Ifcfa65a6fbf16e89023caa5aaf4ae3a7846df749 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/592646 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 64 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 4 +-- 3 files changed, 67 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 161c1ce0c..f6020434c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -200,7 +200,7 @@ static inline u32 gmmu_pte_read_disable_true_f(void) } static inline u32 gmmu_pte_comptagline_f(u32 v) { - return (v & 0x1ffff) << 12; + return (v & 0x3ffff) << 12; } static inline u32 gmmu_pte_comptagline_w(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 9b6811048..f314c75c4 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -2814,6 +2814,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) { return 0x0050460c; @@ -2826,6 +2834,22 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) { return 0x00000001; } +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) +{ + return 0x00419e50; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) +{ + return 0x40; +} static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) { return 0x00504650; @@ -3226,4 +3250,44 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) { return 0x004188ac; } +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) +{ + return 0x00419e10; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) +{ + return 0x00000001; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) +{ + return 0x80000000; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) +{ + return 0x1 << 30; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) +{ + return (r >> 30) & 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) +{ + return 0x40000000; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index a38cfe8de..68f5a128d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -124,7 +124,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x3ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) { @@ -132,7 +132,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) { - return (v & 0x1ffff) << 0; + return (v & 0x3ffff) << 0; } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { -- cgit v1.2.2 From 65113d002b81cb06f7cb95ea84a2aa7c24727524 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 31 Oct 2014 11:59:39 +0200 Subject: gpu: nvgpu: Add own platform data to enable host1x Add gp10b platform data to enable sync point support. Bug 1572701 Change-Id: Iaf03ecb8fb6b8bf4bb824e2a012c80dfe3f4fcae Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/592099 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/Makefile | 2 + drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 99 ++++++++++++++++++++++++++ drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h | 1 + 3 files changed, 102 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 722cc5503..193efee0d 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -12,3 +12,5 @@ obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ mc_gp10b.o \ hal_gp10b.o + +obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c new file mode 100644 index 000000000..7a25a3fc3 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -0,0 +1,99 @@ +/* + * drivers/video/tegra/host/gk20a/platform_gk20a_tegra.c + * + * GK20A Tegra Platform Interface + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gk20a/platform_gk20a.h" +#include "gk20a/gk20a.h" + +static int gp10b_tegra_probe(struct platform_device *pdev) +{ + struct gk20a_platform *platform = gk20a_get_platform(pdev); + struct device_node *np = pdev->dev.of_node; + struct device_node *host1x_node; + struct platform_device *host1x_pdev; + const __be32 *host1x_ptr; + + host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); + if (!host1x_ptr) { + gk20a_err(&pdev->dev, "host1x device not available"); + return -ENOSYS; + } + + host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); + host1x_pdev = of_find_device_by_node(host1x_node); + if (!host1x_pdev) { + gk20a_err(&pdev->dev, "host1x device not available"); + return -ENOSYS; + } + + platform->g->host1x_dev = host1x_pdev; + + return 0; +} + +static int gp10b_tegra_late_probe(struct platform_device *pdev) +{ + return 0; +} + +static bool gp10b_tegra_is_railgated(struct platform_device *pdev) +{ + return false; +} + +static int gp10b_tegra_railgate(struct platform_device *pdev) +{ + return 0; +} + +static int gp10b_tegra_unrailgate(struct platform_device *pdev) +{ + return 0; +} + +static int gp10b_tegra_suspend(struct device *dev) +{ + return 0; +} + +struct gk20a_platform t18x_gpu_tegra_platform = { + .has_syncpoints = true, + + .default_big_page_size = SZ_128K, + + .probe = gp10b_tegra_probe, + .late_probe = gp10b_tegra_late_probe, + + /* power management callbacks */ + .suspend = gp10b_tegra_suspend, + .railgate = gp10b_tegra_railgate, + .unrailgate = gp10b_tegra_unrailgate, + .is_railgated = gp10b_tegra_is_railgated, + + .busy = gk20a_tegra_busy, + .idle = gk20a_tegra_idle, + + .dump_platform_dependencies = gk20a_tegra_debug_dump, +}; diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h index fe027fb01..ac65af189 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h @@ -27,4 +27,5 @@ #define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B struct gpu_ops; extern int gp10b_init_hal(struct gpu_ops *); +extern struct gk20a_platform t18x_gpu_tegra_platform; #endif -- cgit v1.2.2 From e88cb5b80b5a990d61366940cc62478e474855af Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 5 Nov 2014 11:21:03 +0200 Subject: gpu: nvgpu: gp10b: Fill class numbers Fill class numbers to characteristics structure. Bug 1567274 Change-Id: I129e79fa3f850899ae0c7d93704dc4786ad514d9 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/594404 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 13 ++++++++++++- drivers/gpu/nvgpu/gp10b/hal_gp10b.h | 4 ++-- drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h | 2 +- 3 files changed, 15 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 235254c84..067c9bf4a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -23,6 +23,7 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/mc_gp10b.h" +#include "gm20b/gr_gm20b.h" #include "gm20b/ltc_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" @@ -81,8 +82,11 @@ struct gpu_ops gp10b_ops = { } }; -int gp10b_init_hal(struct gpu_ops *gops) +int gp10b_init_hal(struct gk20a *g) { + struct gpu_ops *gops = &g->ops; + struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; + *gops = gp10b_ops; gp10b_init_mc(gops); gm20b_init_ltc(gops); @@ -96,5 +100,12 @@ int gp10b_init_hal(struct gpu_ops *gops) gm20b_init_clk_ops(gops); gops->name = "gp10b"; + c->twod_class = FERMI_TWOD_A; + c->threed_class = PASCAL_A; + c->compute_class = PASCAL_COMPUTE_A; + c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A; + c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; + c->dma_copy_class = MAXWELL_DMA_COPY_A; + return 0; } diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h index 78615ed10..0b464d07c 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h @@ -15,7 +15,7 @@ #ifndef _NVGPU_HAL_GP10B_H #define _NVGPU_HAL_GP10B_H -struct gpu_ops; +struct gk20a; -int gp10b_init_hal(struct gpu_ops *gops); +int gp10b_init_hal(struct gk20a *gops); #endif diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h index ac65af189..59ecefee3 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h @@ -26,6 +26,6 @@ #define TEGRA_18x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GP10B #define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B struct gpu_ops; -extern int gp10b_init_hal(struct gpu_ops *); +extern int gp10b_init_hal(struct gk20a *); extern struct gk20a_platform t18x_gpu_tegra_platform; #endif -- cgit v1.2.2 From 5277d4941ee248ed0a1cb24b53b3da530b01ac81 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sat, 1 Nov 2014 19:29:28 +0200 Subject: gpu: nvgpu: gp10b: Enable interrupts in linsim Change-Id: I7d4211743793b905a20080bb44c62c036f23c854 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/592336 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index cdafaf562..4f7ab6989 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -21,19 +21,17 @@ void mc_gp10b_intr_enable(struct gk20a *g) { - if (!tegra_platform_is_linsim()) { - gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(0), - mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); - gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(1), - mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); - } + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(0), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f()); + gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); + gk20a_writel(g, mc_intr_en_set_r(1), + mc_intr_pfifo_pending_f() + | mc_intr_pgraph_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f()); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) -- cgit v1.2.2 From 1ee74f473436c4d7575baa46aafddc3262e7f705 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Wed, 5 Nov 2014 19:31:45 -0800 Subject: gpu: nvgpu: headers for linsim CL 33823014 Change-Id: I1b9172f0afa0391ce6289aa24dc1a993c723c90e Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/594681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 12 ------------ drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 2 +- 2 files changed, 1 insertion(+), 13 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index f314c75c4..372c5e51b 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -2182,18 +2182,6 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { return 0x3fffff << 0; } -static inline u32 gr_gpcs_swdx_rm_pagepool_r(void) -{ - return 0x00418e30; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 gr_gpcs_swdx_rm_pagepool_valid_true_f(void) -{ - return 0x80000000; -} static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { return 0x00418810; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 68f5a128d..45bb1d428 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -136,7 +136,7 @@ static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) } static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) { - return 0x0001ffff; + return 0x0003ffff; } static inline u32 ltc_ltcs_ltss_cbc_base_r(void) { -- cgit v1.2.2 From 2d488ab083e04312b928ff6b4e1dcd2cccae720c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 13 Nov 2014 13:30:52 +0200 Subject: gpu: nvgpu: gp10b: Implement L2 query Bug 1567274 Change-Id: I0b8eaebc0949e70f6d8bfbb101048a3d95bec5e3 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/602858 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 5 ++-- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 12 +++++++++ drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 47 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/ltc_gp10b.h | 19 ++++++++++++++ 5 files changed, 81 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/ltc_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/ltc_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 193efee0d..4ecf761a8 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -11,6 +11,7 @@ ccflags-$(CONFIG_GK20A) += -Wno-multichar obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ mc_gp10b.o \ + ltc_gp10b.o \ hal_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 067c9bf4a..5ef64e1f0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -22,9 +22,9 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/mc_gp10b.h" +#include "gp10b/ltc_gp10b.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/ltc_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" @@ -89,9 +89,8 @@ int gp10b_init_hal(struct gk20a *g) *gops = gp10b_ops; gp10b_init_mc(gops); - gm20b_init_ltc(gops); gp10b_init_gr(gops); - gm20b_init_ltc(gops); + gp10b_init_ltc(gops); gm20b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 45bb1d428..32683dc26 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -494,4 +494,16 @@ static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) { return 0x1; } +static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) +{ + return 0x0014058c; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) +{ + return (r >> 16) & 0x1f; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c new file mode 100644 index 000000000..9f5c16ba9 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -0,0 +1,47 @@ +/* + * GP10B L2 + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gm20b/ltc_gm20b.h" +#include "hw_ltc_gp10b.h" + +static int gp10b_determine_L2_size_bytes(struct gk20a *g) +{ + u32 tmp; + int ret; + + gk20a_dbg_fn(""); + + tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r()); + + ret = g->ltc_count * + ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp) * + ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp); + + gk20a_dbg(gpu_dbg_info, "L2 size: %d\n", ret); + + gk20a_dbg_fn("done"); + + return ret; +} + +void gp10b_init_ltc(struct gpu_ops *gops) +{ + gm20b_init_ltc(gops); + + gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; +} diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h new file mode 100644 index 000000000..7408348e7 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef LTC_GP10B_H +#define LTC_GP10B_H +struct gpu_ops; + +void gp10b_init_ltc(struct gpu_ops *gops); +#endif -- cgit v1.2.2 From 4322b5bbd7b6280c38f538ff84b229ad55fc6719 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 11 Nov 2014 11:13:11 +0200 Subject: gpu: nvgpu: Use queried interrupt ids Change-Id: I258b54447d09b32adc076de50997d792f0567af5 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601019 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 8 ++++++++ drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 20 ++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index ca6457c70..0982bc098 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h @@ -102,6 +102,14 @@ static inline u32 top_device_info_runlist_enum_v(u32 r) { return (r >> 21) & 0xf; } +static inline u32 top_device_info_intr_enum_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 top_device_info_reset_enum_v(u32 r) +{ + return (r >> 9) & 0x1f; +} static inline u32 top_device_info_type_enum_v(u32 r) { return (r >> 2) & 0x1fffffff; diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4f7ab6989..3fae4ea39 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -21,17 +21,19 @@ void mc_gp10b_intr_enable(struct gk20a *g) { + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); + gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); gk20a_writel(g, mc_intr_en_set_r(0), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); + | eng_intr_mask); gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); gk20a_writel(g, mc_intr_en_set_r(1), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); + | mc_intr_pbus_pending_f() + | eng_intr_mask); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) @@ -71,6 +73,7 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) { u32 mc_intr_0; + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -78,7 +81,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - if (mc_intr_0 & mc_intr_pgraph_pending_f()) + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); @@ -93,7 +96,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) gk20a_writel(g, mc_intr_en_set_r(0), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f()); + | eng_intr_mask); return IRQ_HANDLED; } @@ -101,6 +104,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) { u32 mc_intr_1; + u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -110,15 +114,15 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & mc_intr_pfifo_pending_f()) gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & mc_intr_pgraph_pending_f()) + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); gk20a_writel(g, mc_intr_en_set_r(1), mc_intr_pfifo_pending_f() - | mc_intr_pgraph_pending_f() | mc_intr_priv_ring_pending_f() | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f()); + | mc_intr_pbus_pending_f() + | eng_intr_mask); return IRQ_HANDLED; } -- cgit v1.2.2 From b3dd929134636ed62a73be1666526b8a81f9973c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 11 Nov 2014 11:13:41 +0200 Subject: gpu: nvgpu: Add SM registers Add SM registers which were taken into use in GPU characteristics. Bug 1551769 Bug 1558186 Change-Id: I705da9ac25556b6b94137199e0acd9af3c8e6422 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601020 --- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 372c5e51b..ca4aa6bdd 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1866,6 +1866,22 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) { return (v & 0xffff) << 0; } +static inline u32 gr_gpc0_tpc0_sm_arch_r(void) +{ + return 0x0050469c; +} +static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) +{ + return (r >> 8) & 0xfff; +} +static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) +{ + return (r >> 20) & 0xfff; +} static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) { return 0x00503018; -- cgit v1.2.2 From 658f89321a9de40d70f9ebf2747d19a9e5142e9b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sat, 8 Nov 2014 19:11:24 +0200 Subject: gpu: nvgpu: Define gp10b big page size Set default big page size of 128kB. Bug 1567274 Change-Id: Ie27c6ffa23b8d75ebd21afca267068604fb57f0b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/603498 --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 7a25a3fc3..f199d5693 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -96,4 +96,6 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .idle = gk20a_tegra_idle, .dump_platform_dependencies = gk20a_tegra_debug_dump, + + .default_big_page_size = SZ_128K, }; -- cgit v1.2.2 From 23a876dbf6ba451e12901dd7b5b1cdfef8fa6df9 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 11 Nov 2014 13:47:03 +0200 Subject: gpu: nvgpu: Write ZBC registers to DSS Bug 1567274 Change-Id: Ife98ae512c62bd26450e59338719c7a10635b5dd Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601108 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 141 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 48 ++++++++++++ 2 files changed, 189 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index b7a52be0d..250dc65c0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -158,10 +158,151 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, gr_gpcs_gcc_pagepool_total_pages_f(size), patch); } +static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *color_val, u32 index) +{ + struct fifo_gk20a *f = &g->fifo; + struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; + u32 i; + unsigned long end_jiffies = jiffies + + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); + u32 ret; + u32 zbc_c; + + ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to disable gr engine activity\n"); + return ret; + } + + ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to idle graphics\n"); + goto clean_up; + } + + /* update l2 table */ + g->ops.ltc.set_zbc_color_entry(g, color_val, index); + + /* update ds table */ + gk20a_writel(g, gr_ds_zbc_color_r_r(), + gr_ds_zbc_color_r_val_f(color_val->color_ds[0])); + gk20a_writel(g, gr_ds_zbc_color_g_r(), + gr_ds_zbc_color_g_val_f(color_val->color_ds[1])); + gk20a_writel(g, gr_ds_zbc_color_b_r(), + gr_ds_zbc_color_b_val_f(color_val->color_ds[2])); + gk20a_writel(g, gr_ds_zbc_color_a_r(), + gr_ds_zbc_color_a_val_f(color_val->color_ds[3])); + + gk20a_writel(g, gr_ds_zbc_color_fmt_r(), + gr_ds_zbc_color_fmt_val_f(color_val->format)); + + gk20a_writel(g, gr_ds_zbc_tbl_index_r(), + gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); + + /* trigger the write */ + gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), + gr_ds_zbc_tbl_ld_select_c_f() | + gr_ds_zbc_tbl_ld_action_write_f() | + gr_ds_zbc_tbl_ld_trigger_active_f()); + + /* update local copy */ + for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { + gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i]; + gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i]; + } + gr->zbc_col_tbl[index].format = color_val->format; + gr->zbc_col_tbl[index].ref_cnt++; + + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), color_val->color_ds[0]); + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]); + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]); + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); + zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4)); + zbc_c |= color_val->format << (index % 4) * 6; + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); + +clean_up: + ret = gk20a_fifo_enable_engine_activity(g, gr_info); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to enable gr engine activity\n"); + } + + return ret; +} + +static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, + struct zbc_entry *depth_val, u32 index) +{ + struct fifo_gk20a *f = &g->fifo; + struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; + unsigned long end_jiffies = jiffies + + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); + u32 ret; + u32 zbc_z; + + ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to disable gr engine activity\n"); + return ret; + } + + ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to idle graphics\n"); + goto clean_up; + } + + /* update l2 table */ + g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); + + /* update ds table */ + gk20a_writel(g, gr_ds_zbc_z_r(), + gr_ds_zbc_z_val_f(depth_val->depth)); + + gk20a_writel(g, gr_ds_zbc_z_fmt_r(), + gr_ds_zbc_z_fmt_val_f(depth_val->format)); + + gk20a_writel(g, gr_ds_zbc_tbl_index_r(), + gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); + + /* trigger the write */ + gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), + gr_ds_zbc_tbl_ld_select_z_f() | + gr_ds_zbc_tbl_ld_action_write_f() | + gr_ds_zbc_tbl_ld_trigger_active_f()); + + /* update local copy */ + gr->zbc_dep_tbl[index].depth = depth_val->depth; + gr->zbc_dep_tbl[index].format = depth_val->format; + gr->zbc_dep_tbl[index].ref_cnt++; + + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); + zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4)); + zbc_z |= depth_val->format << (index % 4) * 6; + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); + +clean_up: + ret = gk20a_fifo_enable_engine_activity(g, gr_info); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "failed to enable gr engine activity\n"); + } + + return ret; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); gops->gr.is_valid_class = gr_gp10b_is_valid_class; gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; + gops->gr.add_zbc_color = gr_gp10b_add_zbc_color; + gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index ca4aa6bdd..f2237a50a 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -2198,6 +2198,54 @@ static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) { return 0x3fffff << 0; } +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) +{ + return 0x00418010 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) +{ + return 0x0041804c + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) +{ + return 0x00418088 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) +{ + return 0x004180c4 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) +{ + return 0x00500100; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) +{ + return 0x00418110 + i*4; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) +{ + return 0x0050014c; +} static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) { return 0x00418810; -- cgit v1.2.2 From 1164f6bd1b6f9aa97aba1100efe4fc8745d3d1ac Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 12 Nov 2014 14:32:29 +0200 Subject: gpu: nvgpu: gp10b: Define physical address width GP10B physical address width is 37 bits. Use old width for now, and add gp10b specific definition. We can switch to new definition once we've verified them. Bug 1567274 Change-Id: I33cc1b99f14f1a7ee5f6fe3bd3d8b3126c23ecbe Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/601703 --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++-- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 19 +++++++++++++++++++ 4 files changed, 50 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/mm_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/mm_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 4ecf761a8..ecb09cf64 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ mc_gp10b.o \ ltc_gp10b.o \ + mm_gp10b.o \ hal_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 5ef64e1f0..acd1b73c8 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -23,13 +23,13 @@ #include "gp10b/gr_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" +#include "gp10b/mm_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/gr_ctx_gm20b.h" -#include "gm20b/mm_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" @@ -94,7 +94,7 @@ int gp10b_init_hal(struct gk20a *g) gm20b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); - gm20b_init_mm(gops); + gp10b_init_mm(gops); gm20b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); gops->name = "gp10b"; diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c new file mode 100644 index 000000000..a0b6a7d17 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -0,0 +1,28 @@ +/* + * GP10B MMU + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "gk20a/gk20a.h" + +u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) +{ + return 37; +} + +void gp10b_init_mm(struct gpu_ops *gops) +{ + gm20b_init_mm(gops); + gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; +} diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h new file mode 100644 index 000000000..38ca93a4f --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef MM_GP10B_H +#define MM_GP10B_H +struct gpu_ops; + +void gp10b_init_mm(struct gpu_ops *gops); +#endif -- cgit v1.2.2 From 12ff6b585f2bdab2cb4a932330a7b0d1699b7740 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 20 Nov 2014 15:51:50 +0200 Subject: gpu: nvgpu: gp10b: Define pagepool size Bug 1567274 Change-Id: I4369458d3af0c4da32af8a5881c8fe60b11f7632 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/606932 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 250dc65c0..7a3161064 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -297,6 +297,14 @@ clean_up: return ret; } +static void gr_gp10b_buffer_size_defaults(struct gk20a *g) +{ + g->gr.pagepool_default_size = + gr_scc_pagepool_total_pages_hwmax_value_v(); + g->gr.pagepool_max_size = + gr_scc_pagepool_total_pages_hwmax_value_v(); +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -305,4 +313,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; gops->gr.add_zbc_color = gr_gp10b_add_zbc_color; gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth; + gops->gr.buffer_size_defaults = gr_gp10b_buffer_size_defaults; } -- cgit v1.2.2 From 6eb92596db63766ffc1d793df8e6d1b3057a9a5b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 13 Nov 2014 14:55:51 +0200 Subject: gpu: nvgpu: gp10b: Add new supported kind Bug 1567274 Change-Id: I38c3ffd6129893b02f6bef878a579925cf2bfa1e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/606931 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/fb_gp10b.c | 96 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/fb_gp10b.h | 21 ++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 +- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 28 ++++++++++ 5 files changed, 148 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/fb_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/fb_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index ecb09cf64..6f1fb9e2d 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -13,6 +13,7 @@ obj-$(CONFIG_GK20A) += \ mc_gp10b.o \ ltc_gp10b.o \ mm_gp10b.o \ + fb_gp10b.o \ hal_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c new file mode 100644 index 000000000..df35c5b0a --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c @@ -0,0 +1,96 @@ +/* + * GP10B FB + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +* + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gm20b/fb_gm20b.h" +#include "gk20a/kind_gk20a.h" + +#include "hw_gmmu_gp10b.h" + +static void gp10b_init_uncompressed_kind_map(void) +{ + gm20b_init_uncompressed_kind_map(); + + gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] = + gmmu_pte_kind_z16_v(); + + gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] = + gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] = + gmmu_pte_kind_generic_16bx2_v(); +} + +static bool gp10b_kind_supported(u8 k) +{ + return (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) + || k == gmmu_pte_kind_z16_ms16_2cz_v() + || k == gmmu_pte_kind_c32_ms4_4cbra_v() + || k == gmmu_pte_kind_c64_ms4_4cbra_v(); +} + +static bool gp10b_kind_z(u8 k) +{ + return (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) || + k == gmmu_pte_kind_z16_ms16_2cz_v(); +} + +static bool gp10b_kind_compressible(u8 k) +{ + return (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) || + k == gmmu_pte_kind_z16_ms16_2cz_v() || + (k >= gmmu_pte_kind_z16_4cz_v() && + k <= gmmu_pte_kind_z16_ms16_4cz_v()); +} + +static bool gp10b_kind_zbc(u8 k) +{ + return (k >= gmmu_pte_kind_z16_2cz_v() && + k <= gmmu_pte_kind_z16_ms8_2cz_v()) || + k == gmmu_pte_kind_z16_ms16_2cz_v(); +} + +static void gp10b_init_kind_attr(void) +{ + u16 k; + + gm20b_init_kind_attr(); + + for (k = 0; k < 256; k++) { + if (gp10b_kind_supported((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; + if (gp10b_kind_compressible((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; + if (gp10b_kind_z((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; + if (gp10b_kind_zbc((u8)k)) + gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; + } +} + +void gp10b_init_fb(struct gpu_ops *gops) +{ + gm20b_init_fb(gops); + + gp10b_init_uncompressed_kind_map(); + gp10b_init_kind_attr(); +} diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h new file mode 100644 index 000000000..76efd3319 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h @@ -0,0 +1,21 @@ +/* + * GP10B FB + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_GP10B_FB +#define _NVGPU_GP10B_FB +struct gpu_ops; + +void gp10b_init_fb(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index acd1b73c8..a739ce779 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -24,9 +24,9 @@ #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/fb_gp10b.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/fb_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" #include "gm20b/gr_ctx_gm20b.h" @@ -91,7 +91,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mc(gops); gp10b_init_gr(gops); gp10b_init_ltc(gops); - gm20b_init_fb(gops); + gp10b_init_fb(gops); gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); gp10b_init_mm(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index f6020434c..5a0f9fe27 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -270,6 +270,26 @@ static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) { return 0x0000000b; } +static inline u32 gmmu_pte_kind_z16_2cz_v(void) +{ + return 0x00000036; +} +static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) +{ + return 0x00000037; +} +static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) +{ + return 0x00000038; +} +static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) +{ + return 0x00000039; +} +static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) +{ + return 0x0000005f; +} static inline u32 gmmu_pte_kind_z16_4cz_v(void) { return 0x0000000c; @@ -1026,6 +1046,10 @@ static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) { return 0x000000e3; } +static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) +{ + return 0x0000002c; +} static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) { return 0x000000e4; @@ -1086,6 +1110,10 @@ static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) { return 0x000000f1; } +static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) +{ + return 0x0000002d; +} static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) { return 0x000000f2; -- cgit v1.2.2 From e562135ff69e115f1a1110721cc3660628b81231 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 26 Nov 2014 08:23:34 +0200 Subject: gpu: nvgpu: gp10b: Calc global context buffer size In gp10b we need to limit global context buffer size, and it needs to be 128b aligned. Change-Id: I51570e2457a374c09be4d611e683ae30917f9fc0 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/657911 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 7a3161064..b8fbc28e1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -305,6 +305,34 @@ static void gr_gp10b_buffer_size_defaults(struct gk20a *g) gr_scc_pagepool_total_pages_hwmax_value_v(); } +static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + int size; + + gr->attrib_cb_size = gr->attrib_cb_default_size + + (gr->attrib_cb_default_size >> 1); + gr->alpha_cb_size = gr->alpha_cb_default_size + + (gr->alpha_cb_default_size >> 1); + + gr->attrib_cb_size = min(gr->attrib_cb_size, + gr_gpc0_ppc0_cbm_beta_cb_size_v_f(0xffffffff)); + gr->alpha_cb_size = min(gr->attrib_cb_size, + gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(0xffffffff)); + + size = gr->attrib_cb_size * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + gr->max_tpc_count; + + size += gr->alpha_cb_size * + gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() * + gr->max_tpc_count; + + size = ALIGN(size, 128); + + return size; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -314,4 +342,6 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.add_zbc_color = gr_gp10b_add_zbc_color; gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth; gops->gr.buffer_size_defaults = gr_gp10b_buffer_size_defaults; + gops->gr.calc_global_ctx_buffer_size = + gr_gp10b_calc_global_ctx_buffer_size; } -- cgit v1.2.2 From e030251ba4205c3a52df319125f452bb1b9051bc Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 21 Nov 2014 14:15:13 +0200 Subject: gpu: nvgpu: gp10b: Implement SW methods Bug 1567274 Change-Id: I6d760eca7ac0931847f9a04a9d4a408519ade511 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/654098 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 37 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 6 +++++- 2 files changed, 42 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index b8fbc28e1..844ba81fd 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -333,6 +333,42 @@ static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) return size; } +static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, + u32 class_num, u32 offset, u32 data) +{ + gk20a_dbg_fn(""); + + if (class_num == PASCAL_COMPUTE_A) { + switch (offset << 2) { + case NVC0C0_SET_SHADER_EXCEPTIONS: + gk20a_gr_set_shader_exceptions(g, data); + break; + default: + goto fail; + } + } + + if (class_num == PASCAL_A) { + switch (offset << 2) { + case NVC097_SET_SHADER_EXCEPTIONS: + gk20a_gr_set_shader_exceptions(g, data); + break; + case NVC097_SET_CIRCULAR_BUFFER_SIZE: + g->ops.gr.set_circular_buffer_size(g, data); + break; + case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: + g->ops.gr.set_alpha_circular_buffer_size(g, data); + break; + default: + goto fail; + } + } + return 0; + +fail: + return -EINVAL; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -344,4 +380,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.buffer_size_defaults = gr_gp10b_buffer_size_defaults; gops->gr.calc_global_ctx_buffer_size = gr_gp10b_calc_global_ctx_buffer_size; + gops->gr.handle_sw_method = gr_gp10b_handle_sw_method; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 58616debc..536a7d277 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -25,7 +25,11 @@ enum { PASCAL_DMA_COPY_A = 0xC0B5, }; -void gp10b_init_gr(struct gpu_ops *ops); +#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 +#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 +void gp10b_init_gr(struct gpu_ops *ops); #endif -- cgit v1.2.2 From 5a2213ee8aea6f09e47e421dc4a781cf5fb5a1a7 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 21 Nov 2014 14:08:07 +0200 Subject: gpu: nvgpu: gp10b: Program CB sizes Program CB sizes. Bug 1567274 Change-Id: Idc88f69b70e85bf950af852a9ca80a328d95883f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/654097 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 109 +++++++++++++++++++++++++++++++++++++ 1 file changed, 109 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 844ba81fd..81e040958 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -369,6 +369,110 @@ fail: return -EINVAL; } +static void gr_gp10b_cb_size_default(struct gk20a *g) +{ + struct gr_gk20a *gr = &g->gr; + + gr->attrib_cb_default_size = + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); + gr->alpha_cb_default_size = + gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); +} + +static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) +{ + struct gr_gk20a *gr = &g->gr; + u32 gpc_index, ppc_index, stride, val; + u32 pd_ab_max_output; + u32 alpha_cb_size = data * 4; + + gk20a_dbg_fn(""); + + if (alpha_cb_size > gr->alpha_cb_size) + alpha_cb_size = gr->alpha_cb_size; + + gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), + (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & + ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~0)) | + gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size)); + + pd_ab_max_output = alpha_cb_size * + gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() / + gr_pd_ab_dist_cfg1_max_output_granularity_v(); + + gk20a_writel(g, gr_pd_ab_dist_cfg1_r(), + gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output)); + + for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { + stride = proj_gpc_stride_v() * gpc_index; + + for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; + ppc_index++) { + + val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index); + + val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(), + gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size * + gr->pes_tpc_count[ppc_index][gpc_index])); + + gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index, val); + } + } +} + +static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) +{ + struct gr_gk20a *gr = &g->gr; + u32 gpc_index, ppc_index, stride, val; + u32 cb_size = data * 4; + + gk20a_dbg_fn(""); + + if (cb_size > gr->attrib_cb_size) + cb_size = gr->attrib_cb_size; + + gk20a_writel(g, gr_ds_tga_constraintlogic_beta_r(), + (gk20a_readl(g, gr_ds_tga_constraintlogic_beta_r()) & + ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) | + gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size)); + + for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { + stride = proj_gpc_stride_v() * gpc_index; + + for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; + ppc_index++) { + + val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index); + + val = set_field(val, + gr_gpc0_ppc0_cbm_beta_cb_size_v_m(), + gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size * + gr->pes_tpc_count[ppc_index][gpc_index])); + + gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + + stride + + proj_ppc_in_gpc_stride_v() * ppc_index, val); + + val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r( + ppc_index + gpc_index)); + + val = set_field(val, + gr_gpcs_swdx_tc_beta_cb_size_v_m(), + gr_gpcs_swdx_tc_beta_cb_size_v_f(cb_size * + gr->gpc_ppc_count[gpc_index])); + + gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r( + ppc_index + gpc_index), val); + } + } +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -381,4 +485,9 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.calc_global_ctx_buffer_size = gr_gp10b_calc_global_ctx_buffer_size; gops->gr.handle_sw_method = gr_gp10b_handle_sw_method; + gops->gr.cb_size_default = gr_gp10b_cb_size_default; + gops->gr.set_alpha_circular_buffer_size = + gr_gp10b_set_alpha_circular_buffer_size; + gops->gr.set_circular_buffer_size = + gr_gp10b_set_circular_buffer_size; } -- cgit v1.2.2 From 1ce61c33641f9a8ba788a62c7a658c2cff4dad43 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 1 Dec 2014 14:33:01 +0200 Subject: gpu: nvgpu: gp10b: Change order of alpha & beta Change order of alpha & attribute buffers in CB. The new order follows RM. Change-Id: I2b24daa46055b3bd667a1026c282f74d56882623 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/657907 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 81e040958..0dce115ac 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -83,8 +83,8 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); - alpha_offset_in_chunk = attrib_offset_in_chunk + - gr->tpc_count * gr->attrib_cb_size; + attrib_offset_in_chunk = alpha_offset_in_chunk + + gr->tpc_count * gr->alpha_cb_size; for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { temp = proj_gpc_stride_v() * gpc_index; @@ -105,6 +105,12 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, proj_ppc_in_gpc_stride_v() * ppc_index, attrib_offset_in_chunk, patch); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + + proj_ppc_in_gpc_stride_v() * ppc_index, + gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index], + patch); + attrib_offset_in_chunk += gr->attrib_cb_size * gr->pes_tpc_count[ppc_index][gpc_index]; @@ -121,12 +127,6 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, alpha_offset_in_chunk += gr->alpha_cb_size * gr->pes_tpc_count[ppc_index][gpc_index]; - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index], - patch); - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index), gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1), -- cgit v1.2.2 From f680c6c6c19b29bbe30908578c912999577326cb Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 3 Dec 2014 09:35:37 +0200 Subject: gpu: nvgpu: gp10b: Correct SMMU bit number Bit 36 is the correct bit to indicate SMMU translation. Bug 1580756 Change-Id: I761e70265d5981b07940f1d43716416829993827 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/658827 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Hiroshi Doyu --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index a0b6a7d17..ff248f519 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -18,7 +18,7 @@ u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) { - return 37; + return 36; } void gp10b_init_mm(struct gpu_ops *gops) -- cgit v1.2.2 From 14feb97f3b0b598e1bcf375c9b5dfdf38113bf0e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 3 Dec 2014 16:11:50 +0200 Subject: gpu: nvgpu: Implement gp10b context creation Implement context creation for gp10b. GfxP contexts need per channel buffers. Bug 1517461 Change-Id: Ifecb59002f89f0407457730a35bfb3fe988b907a Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/660236 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 221 +++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 19 ++- drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 16 ++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 64 ++++++++ drivers/gpu/nvgpu/gr_t18x.h | 20 +++ 5 files changed, 333 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/nvgpu/gr_t18x.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 0dce115ac..0a60612d0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -21,6 +21,7 @@ #include "gp10b/gr_gp10b.h" #include "hw_gr_gp10b.h" #include "hw_proj_gp10b.h" +#include "hw_ctxsw_prog_gp10b.h" bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -297,12 +298,9 @@ clean_up: return ret; } -static void gr_gp10b_buffer_size_defaults(struct gk20a *g) +static u32 gr_gp10b_pagepool_default_size(struct gk20a *g) { - g->gr.pagepool_default_size = - gr_scc_pagepool_total_pages_hwmax_value_v(); - g->gr.pagepool_max_size = - gr_scc_pagepool_total_pages_hwmax_value_v(); + return gr_scc_pagepool_total_pages_hwmax_value_v(); } static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) @@ -473,6 +471,212 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) } } +static int gr_gp10b_init_ctx_state(struct gk20a *g) +{ + struct fecs_method_op_gk20a op = { + .mailbox = { .id = 0, .data = 0, + .clr = ~0, .ok = 0, .fail = 0}, + .method.data = 0, + .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, + .cond.fail = GR_IS_UCODE_OP_SKIP, + }; + int err; + + gk20a_dbg_fn(""); + + err = gr_gk20a_init_ctx_state(g); + if (err) + return err; + + if (!g->gr.t18x.ctx_vars.preempt_image_size) { + op.method.addr = + gr_fecs_method_push_adr_discover_preemption_image_size_v(); + op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; + err = gr_gk20a_submit_fecs_method_op(g, op); + if (err) { + gk20a_err(dev_from_gk20a(g), + "query preempt image size failed"); + return err; + } + } + + gk20a_dbg_info("preempt image size: %u", + g->gr.t18x.ctx_vars.preempt_image_size); + + gk20a_dbg_fn("done"); + + return 0; +} + +int gr_gp10b_alloc_gr_ctx(struct gk20a *g, + struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, + u32 flags) +{ + int err; + + gk20a_dbg_fn(""); + + err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, flags); + if (err) + return err; + + if (flags == NVGPU_GR_PREEMPTION_MODE_GFXP) { + u32 spill_size = + gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(); + u32 betacb_size = ALIGN( + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count) + + (g->gr.alpha_cb_size * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count), + 128); + u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); + + err = gk20a_gmmu_alloc_map(vm, g->gr.t18x.ctx_vars.preempt_image_size, + &(*gr_ctx)->t18x.preempt_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate preempt buffer"); + goto fail_free_gk20a_ctx; + } + + err = gk20a_gmmu_alloc_map(vm, spill_size, + &(*gr_ctx)->t18x.spill_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate spill buffer"); + goto fail_free_preempt; + } + + err = gk20a_gmmu_alloc_map(vm, betacb_size, + &(*gr_ctx)->t18x.betacb_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate beta buffer"); + goto fail_free_spill; + } + + err = gk20a_gmmu_alloc_map(vm, pagepool_size, + &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); + if (err) { + gk20a_err(dev_from_gk20a(vm->mm->g), + "cannot allocate page pool"); + goto fail_free_betacb; + } + + (*gr_ctx)->t18x.preempt_mode = flags; + } + + gk20a_dbg_fn("done"); + + return err; + +fail_free_betacb: + gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); +fail_free_spill: + gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer); +fail_free_preempt: + gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); +fail_free_gk20a_ctx: + gr_gk20a_free_gr_ctx(g, vm, *gr_ctx); + *gr_ctx = NULL; + + return err; +} + +static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) +{ + gk20a_dbg_fn(""); + + if (!gr_ctx) + return; + + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); + gr_gk20a_free_gr_ctx(g, vm, gr_ctx); + + gk20a_dbg_fn("done"); +} + +static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + void *ctx_ptr) +{ + struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; + u32 gfxp_preempt_option = + ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); + int err; + + gk20a_dbg_fn(""); + + if (gr_ctx->t18x.preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); + gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, + gfxp_preempt_option); + } + + if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { + u32 addr; + u32 size; + u32 cbes_reserve; + + gk20a_mem_wr32(ctx_ptr, ctxsw_prog_main_image_full_preemption_ptr_o(), + gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); + + err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); + + addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> + gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | + (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) << + (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); + + gk20a_dbg_info("attrib cb addr : 0x%016x", addr); + g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); + + addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >> + gr_scc_pagepool_base_addr_39_8_align_bits_v()) | + (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << + (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); + size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; + g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); + + addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> + gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | + (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << + (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); + + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_swdx_rm_spill_buffer_addr_r(), + gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr), + true); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpc0_swdx_rm_spill_buffer_size_r(), + gr_gpc0_swdx_rm_spill_buffer_size_256b_f(addr), + true); + + cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_swdx_beta_cb_ctrl_r(), + gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f( + cbes_reserve), + true); + gr_gk20a_ctx_patch_write(g, ch_ctx, + gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(), + gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f( + cbes_reserve), + true); + + gr_gk20a_ctx_patch_write_end(g, ch_ctx); + } + + gk20a_dbg_fn("done"); +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -481,7 +685,7 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; gops->gr.add_zbc_color = gr_gp10b_add_zbc_color; gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth; - gops->gr.buffer_size_defaults = gr_gp10b_buffer_size_defaults; + gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size; gops->gr.calc_global_ctx_buffer_size = gr_gp10b_calc_global_ctx_buffer_size; gops->gr.handle_sw_method = gr_gp10b_handle_sw_method; @@ -490,4 +694,9 @@ void gp10b_init_gr(struct gpu_ops *gops) gr_gp10b_set_alpha_circular_buffer_size; gops->gr.set_circular_buffer_size = gr_gp10b_set_circular_buffer_size; + gops->gr.init_ctx_state = gr_gp10b_init_ctx_state; + gops->gr.alloc_gr_ctx = gr_gp10b_alloc_gr_ctx; + gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx; + gops->gr.update_ctxsw_preemption_mode = + gr_gp10b_update_ctxsw_preemption_mode; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 536a7d277..6bbda564e 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -16,7 +16,7 @@ #ifndef _NVGPU_GR_GP10B_H_ #define _NVGPU_GR_GP10B_H_ -struct gk20a; +struct gpu_ops; enum { PASCAL_CHANNEL_GPFIFO_A = 0xC06F, @@ -32,4 +32,21 @@ enum { void gp10b_init_gr(struct gpu_ops *ops); +struct gr_t18x { + struct { + u32 preempt_image_size; + } ctx_vars; +}; + +struct gr_ctx_desc_t18x { + int preempt_mode; + struct mem_desc preempt_ctxsw_buffer; + struct mem_desc spill_ctxsw_buffer; + struct mem_desc betacb_ctxsw_buffer; + struct mem_desc pagepool_ctxsw_buffer; +}; + +#define NVGPU_GR_PREEMPTION_MODE_WFI 0 +#define NVGPU_GR_PREEMPTION_MODE_GFXP 1 + #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 79890f3cb..0892f12e4 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -238,4 +238,20 @@ static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(v { return 0x0; } +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) +{ + return 0x00000068; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index f2237a50a..0bd707db8 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -718,6 +718,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { return 0x21; } +static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) +{ + return 0x0000001a; +} static inline u32 gr_fecs_host_int_status_r(void) { return 0x00409c18; @@ -1910,6 +1914,10 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) { return 0x00030000; } +static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) +{ + return 0x00030a00; +} static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) { return 0x00000020; @@ -2186,6 +2194,50 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) { return 0x80000000; } +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) +{ + return 0x00500ee4; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) +{ + return 0x00000250; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) +{ + return 0x00500ee0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) +{ + return 0x00000008; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) +{ + return 0x00418eec; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} +static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) +{ + return 0x00000100; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) +{ + return 0x0041befc; +} +static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) +{ + return (v & 0xfff) << 0; +} static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) { return 0x00418ea0 + i*4; @@ -3342,4 +3394,16 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } +static inline u32 gr_fe_gfxp_wfi_timeout_r(void) +{ + return 0x004041c0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) +{ + return 0x0; +} #endif diff --git a/drivers/gpu/nvgpu/gr_t18x.h b/drivers/gpu/nvgpu/gr_t18x.h new file mode 100644 index 000000000..95601116f --- /dev/null +++ b/drivers/gpu/nvgpu/gr_t18x.h @@ -0,0 +1,20 @@ +/* + * NVIDIA T18x GR + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef _NVGPU_GR_T18X_H_ +#define _NVGPU_GR_T18X_H_ + +#include "gp10b/gr_gp10b.h" + +#endif -- cgit v1.2.2 From 024d20dacaf63bfecb04bea09c5c317377139bbd Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 11 Dec 2014 12:40:03 +0530 Subject: gpu: nvgpu: gp10b: gpmu elpg support Temporally used gm20b elpg sequencing values for gp10b elpg. Bug 1525971 Change-Id: Ibffb5180979be9d7ee68cad67cd6f10cf23590c3 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/662517 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 3 + drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 167 +++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 21 ++++ 5 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gp10b/pmu_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/pmu_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 6f1fb9e2d..b2c143a6c 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_GK20A) += \ ltc_gp10b.o \ mm_gp10b.o \ fb_gp10b.o \ + pmu_gp10b.o \ hal_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a739ce779..526caff14 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -25,6 +25,7 @@ #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" #include "gp10b/fb_gp10b.h" +#include "gp10b/pmu_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" @@ -95,7 +96,7 @@ int gp10b_init_hal(struct gk20a *g) gm20b_init_fifo(gops); gm20b_init_gr_ctx(gops); gp10b_init_mm(gops); - gm20b_init_pmu_ops(gops); + gp10b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); gops->name = "gp10b"; diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index f199d5693..0f2d290f3 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -81,6 +81,9 @@ static int gp10b_tegra_suspend(struct device *dev) struct gk20a_platform t18x_gpu_tegra_platform = { .has_syncpoints = true, + /* power management configuration */ + .enable_elpg = false, + .default_big_page_size = SZ_128K, .probe = gp10b_tegra_probe, diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c new file mode 100644 index 000000000..3db0d4c31 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -0,0 +1,167 @@ +/* + * GP10B PMU + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. +* + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* for udelay */ +#include "gk20a/gk20a.h" +#include "gk20a/pmu_gk20a.h" +#include "gm20b/acr_gm20b.h" +#include "gm20b/pmu_gm20b.h" + +#include "pmu_gp10b.h" + +/*! + * Structure/object which single register write need to be done during PG init + * sequence to set PROD values. + */ +struct pg_init_sequence_list { + u32 regaddr; + u32 writeval; +}; + +/* PROD settings for ELPG sequencing registers*/ +static struct pg_init_sequence_list _pginitseq_gm20b[] = { + { 0x0010ab10, 0x8180}, + { 0x0010e118, 0x83828180}, + { 0x0010e068, 0}, + { 0x0010e06c, 0x00000080}, + { 0x0010e06c, 0x00000081}, + { 0x0010e06c, 0x00000082}, + { 0x0010e06c, 0x00000083}, + { 0x0010e06c, 0x00000084}, + { 0x0010e06c, 0x00000085}, + { 0x0010e06c, 0x00000086}, + { 0x0010e06c, 0x00000087}, + { 0x0010e06c, 0x00000088}, + { 0x0010e06c, 0x00000089}, + { 0x0010e06c, 0x0000008a}, + { 0x0010e06c, 0x0000008b}, + { 0x0010e06c, 0x0000008c}, + { 0x0010e06c, 0x0000008d}, + { 0x0010e06c, 0x0000008e}, + { 0x0010e06c, 0x0000008f}, + { 0x0010e06c, 0x00000090}, + { 0x0010e06c, 0x00000091}, + { 0x0010e06c, 0x00000092}, + { 0x0010e06c, 0x00000093}, + { 0x0010e06c, 0x00000094}, + { 0x0010e06c, 0x00000095}, + { 0x0010e06c, 0x00000096}, + { 0x0010e06c, 0x00000097}, + { 0x0010e06c, 0x00000098}, + { 0x0010e06c, 0x00000099}, + { 0x0010e06c, 0x0000009a}, + { 0x0010e06c, 0x0000009b}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010e06c, 0x00000000}, + { 0x0010ab14, 0x00000000}, + { 0x0010ab18, 0x00000000}, + { 0x0010e024, 0x00000000}, + { 0x0010e028, 0x00000000}, + { 0x0010e11c, 0x00000000}, + { 0x0010e120, 0x00000000}, + { 0x0010ab1c, 0x02010155}, + { 0x0010e020, 0x001b1b55}, + { 0x0010e124, 0x01030355}, + { 0x0010ab20, 0x89abcdef}, + { 0x0010ab24, 0x00000000}, + { 0x0010e02c, 0x89abcdef}, + { 0x0010e030, 0x00000000}, + { 0x0010e128, 0x89abcdef}, + { 0x0010e12c, 0x00000000}, + { 0x0010ab28, 0x74444444}, + { 0x0010ab2c, 0x70000000}, + { 0x0010e034, 0x74444444}, + { 0x0010e038, 0x70000000}, + { 0x0010e130, 0x74444444}, + { 0x0010e134, 0x70000000}, + { 0x0010ab30, 0x00000000}, + { 0x0010ab34, 0x00000001}, + { 0x00020004, 0x00000000}, + { 0x0010e138, 0x00000000}, + { 0x0010e040, 0x00000000}, +}; + +static int gp10b_pmu_setup_elpg(struct gk20a *g) +{ + int ret = 0; + u32 reg_writes; + u32 index; + + gk20a_dbg_fn(""); + + if (g->elpg_enabled) { + reg_writes = ((sizeof(_pginitseq_gm20b) / + sizeof((_pginitseq_gm20b)[0]))); + /* Initialize registers with production values*/ + for (index = 0; index < reg_writes; index++) { + gk20a_writel(g, _pginitseq_gm20b[index].regaddr, + _pginitseq_gm20b[index].writeval); + } + } + + gk20a_dbg_fn("done"); + return ret; +} + +void gp10b_init_pmu_ops(struct gpu_ops *gops) +{ + if (gops->privsecurity) { + gm20b_init_secure_pmu(gops); + gops->pmu.init_wpr_region = NULL; + } else { + gk20a_init_pmu_ops(gops); + gops->pmu.init_wpr_region = NULL; + } + gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; + gops->pmu.lspmuwprinitdone = false; + gops->pmu.fecsbootstrapdone = false; + gops->pmu.fecsrecoveryinprogress = 0; +} diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h new file mode 100644 index 000000000..f61f6a93c --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h @@ -0,0 +1,21 @@ +/* + * GP10B PMU + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PMU_GP10B_H_ +#define __PMU_GP10B_H_ + +void gp10b_init_pmu_ops(struct gpu_ops *gops); + +#endif /*__PMU_GP10B_H_*/ -- cgit v1.2.2 From 04d0c5efb20fb39fcb78087317c63e885234e5a7 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 9 Dec 2014 11:48:54 +0530 Subject: gpu: nvgpu: Handle MC pmu interrupts - Made changes to MC to get pmu interrrupts Change-Id: I07aaec8392b1fbb34ae727bc7547a571aaeeb814 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/661212 Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 65 +++++++++++++++++++++++++------------- drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 7 ++++ 2 files changed, 50 insertions(+), 22 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 3fae4ea39..c7a4bc753 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -23,17 +23,44 @@ void mc_gp10b_intr_enable(struct gk20a *g) { u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(0), - mc_intr_pfifo_pending_f() - | eng_intr_mask); - gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); - gk20a_writel(g, mc_intr_en_set_r(1), - mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() - | eng_intr_mask); + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = + mc_intr_pfifo_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); + + gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), + 0xffffffff); + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = + mc_intr_pfifo_pending_f() + | mc_intr_priv_ring_pending_f() + | mc_intr_ltc_pending_f() + | mc_intr_pbus_pending_f() + | eng_intr_mask; + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); +} + +void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask) +{ + u32 intr_index = 0; + u32 reg = 0; + + intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : + NVGPU_MC_INTR_NONSTALLING); + if (enable) { + reg = mc_intr_en_set_r(intr_index); + g->ops.mc.intr_mask_restore[intr_index] |= mask; + + } else { + reg = mc_intr_en_clear_r(intr_index); + g->ops.mc.intr_mask_restore[intr_index] &= ~mask; + } + + gk20a_writel(g, reg, mask); } irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) @@ -73,7 +100,6 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) { u32 mc_intr_0; - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -94,9 +120,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) if (mc_intr_0 & mc_intr_pbus_pending_f()) gk20a_pbus_isr(g); - gk20a_writel(g, mc_intr_en_set_r(0), - mc_intr_pfifo_pending_f() - | eng_intr_mask); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); return IRQ_HANDLED; } @@ -104,7 +129,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) { u32 mc_intr_1; - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); @@ -117,12 +141,8 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); - gk20a_writel(g, mc_intr_en_set_r(1), - mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() - | eng_intr_mask); + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), + g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); return IRQ_HANDLED; } @@ -130,6 +150,7 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) void gp10b_init_mc(struct gpu_ops *gops) { gops->mc.intr_enable = mc_gp10b_intr_enable; + gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; gops->mc.isr_stall = mc_gp10b_isr_stall; gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h index f274ce059..b2ec4be4c 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h @@ -15,8 +15,15 @@ #define MC_GP20B_H struct gk20a; +enum MC_INTERRUPT_REGLIST { + NVGPU_MC_INTR_STALLING = 0, + NVGPU_MC_INTR_NONSTALLING, +}; + void gp10b_init_mc(struct gpu_ops *gops); void mc_gp10b_intr_enable(struct gk20a *g); +void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, + bool is_stalling, u32 mask); irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); -- cgit v1.2.2 From e50334dea6504221289eb89e8a21b67fa987833e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 9 Dec 2014 10:49:08 +0200 Subject: gpu: nvgpu: gp10b: Enable CILP mode for compute Allow enabling CILP for compute. Set CTA by default. Bug 1517461 Change-Id: I85cc931b810afb3ee6116de1200d01b52e1bc29e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/661298 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 21 ++++++++++++++++++--- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 3 +-- drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 16 ++++++++++++++++ 3 files changed, 35 insertions(+), 5 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 0a60612d0..576cdf45e 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -510,13 +510,14 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g) int gr_gp10b_alloc_gr_ctx(struct gk20a *g, struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, + u32 class, u32 flags) { int err; gk20a_dbg_fn(""); - err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, flags); + err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); if (err) return err; @@ -566,9 +567,15 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g, goto fail_free_betacb; } - (*gr_ctx)->t18x.preempt_mode = flags; + (*gr_ctx)->preempt_mode = flags; } + if (class == PASCAL_COMPUTE_A) + if (flags == NVGPU_GR_PREEMPTION_MODE_CILP) + (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; + else + (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + gk20a_dbg_fn("done"); return err; @@ -610,16 +617,24 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; u32 gfxp_preempt_option = ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); + u32 cilp_preempt_option = + ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(); int err; gk20a_dbg_fn(""); - if (gr_ctx->t18x.preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, gfxp_preempt_option); } + if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) { + gk20a_dbg_info("CILP: %x", cilp_preempt_option); + gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0, + cilp_preempt_option); + } + if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { u32 addr; u32 size; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 6bbda564e..1b99cafba 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -39,14 +39,13 @@ struct gr_t18x { }; struct gr_ctx_desc_t18x { - int preempt_mode; struct mem_desc preempt_ctxsw_buffer; struct mem_desc spill_ctxsw_buffer; struct mem_desc betacb_ctxsw_buffer; struct mem_desc pagepool_ctxsw_buffer; }; -#define NVGPU_GR_PREEMPTION_MODE_WFI 0 #define NVGPU_GR_PREEMPTION_MODE_GFXP 1 +#define NVGPU_GR_PREEMPTION_MODE_CILP 3 #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 0892f12e4..7872c19c8 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -254,4 +254,20 @@ static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) { return 0x00000068; } +static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) +{ + return 0x00000084; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) +{ + return (v & 0x3) << 0; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) +{ + return 0x1; +} +static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) +{ + return 0x2; +} #endif -- cgit v1.2.2 From 17c2fc8b1567432d9c36fba7dd85f08a4b0b2f5c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 12 Jan 2015 19:19:16 +0200 Subject: gpu: nvgpu: gp10b: Fix L2 size calculation L2 size is expressed in kB, so add a multiplier. Bug 1592495 Change-Id: I4c10034cd21bf874c84c96f1adc25261b195063d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/671704 --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 9f5c16ba9..88f7b072f 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -29,7 +29,7 @@ static int gp10b_determine_L2_size_bytes(struct gk20a *g) tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r()); ret = g->ltc_count * - ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp) * + ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp)*1024 * ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp); gk20a_dbg(gpu_dbg_info, "L2 size: %d\n", ret); -- cgit v1.2.2 From dc4fc36d1b019154aad3c8d981ea50c052ec1db3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 12 Jan 2015 19:20:59 +0200 Subject: gpu: nvgpu: gp10b: Default page size 64kB Set default big page size to 64kB. Bug 1592495 Change-Id: Id23dac012cde75f2809a49779e1a1cee879d08a0 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/671705 --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 0f2d290f3..0542086ce 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -84,8 +84,6 @@ struct gk20a_platform t18x_gpu_tegra_platform = { /* power management configuration */ .enable_elpg = false, - .default_big_page_size = SZ_128K, - .probe = gp10b_tegra_probe, .late_probe = gp10b_tegra_late_probe, @@ -100,5 +98,5 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .dump_platform_dependencies = gk20a_tegra_debug_dump, - .default_big_page_size = SZ_128K, + .default_big_page_size = SZ_64K, }; -- cgit v1.2.2 From d548c03581abf21cf4857e9b289af3fe4ac7f591 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 22 Jan 2015 08:02:21 -0800 Subject: gpu: nvgpu: gp10b: Enable cycling through ctx bins Remove hard coded NETB for gp10b. This enables cycling through available firmware files. Change-Id: I60765a05b1cf6c2e6003341f611c5ecc3f16e9b7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/676557 Reviewed-by: Peng Du GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 72 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h | 28 +++++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 +- 4 files changed, 103 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index b2c143a6c..3575d4146 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -10,6 +10,7 @@ ccflags-$(CONFIG_GK20A) += -Wno-multichar obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ + gr_ctx_gp10b.o \ mc_gp10b.o \ ltc_gp10b.o \ mm_gp10b.o \ diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c new file mode 100644 index 000000000..1d77ad659 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c @@ -0,0 +1,72 @@ +/* + * drivers/video/tegra/host/gp10b/gr_ctx_gp10b.c + * + * GM20B Graphics Context + * + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gk20a/gk20a.h" +#include "gr_ctx_gp10b.h" + +static int gr_gp10b_get_netlist_name(int index, char *name) +{ + switch (index) { +#ifdef GP10B_NETLIST_IMAGE_FW_NAME + case NETLIST_FINAL: + sprintf(name, GP10B_NETLIST_IMAGE_FW_NAME); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_A + case NETLIST_SLOT_A: + sprintf(name, GK20A_NETLIST_IMAGE_A); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_B + case NETLIST_SLOT_B: + sprintf(name, GK20A_NETLIST_IMAGE_B); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_C + case NETLIST_SLOT_C: + sprintf(name, GK20A_NETLIST_IMAGE_C); + return 0; +#endif +#ifdef GK20A_NETLIST_IMAGE_D + case NETLIST_SLOT_D: + sprintf(name, GK20A_NETLIST_IMAGE_D); + return 0; +#endif + default: + return -1; + } + + return -1; +} + +static bool gr_gp10b_is_firmware_defined(void) +{ +#ifdef GM20B_NETLIST_IMAGE_FW_NAME + return true; +#else + return false; +#endif +} + +void gp10b_init_gr_ctx(struct gpu_ops *gops) { + gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; + gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; +} diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h new file mode 100644 index 000000000..b1184f9db --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h @@ -0,0 +1,28 @@ +/* + * GP10B Graphics Context + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __GR_CTX_GM10B_H__ +#define __GR_CTX_GM10B_H__ + +#include "gk20a/gr_ctx_gk20a.h" + +/* production netlist, one and only one from below */ +/*#undef GM20B_NETLIST_IMAGE_FW_NAME*/ + +void gp10b_init_gr_ctx(struct gpu_ops *gops); + +#endif /*__GR_CTX_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 526caff14..161c20c6d 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -26,11 +26,11 @@ #include "gp10b/mm_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" +#include "gp10b/gr_ctx_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" -#include "gm20b/gr_ctx_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" @@ -94,7 +94,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_ltc(gops); gp10b_init_fb(gops); gm20b_init_fifo(gops); - gm20b_init_gr_ctx(gops); + gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); -- cgit v1.2.2 From 901f65c7ae5a679fa62f89f0f7d7887b5879a007 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 8 Dec 2014 18:15:37 -0800 Subject: gpu: nvgpu: gp10b: update headers Update replayable page fault fifo, interrupt and bar2 block headers. Bug 1587825 Change-Id: Ifa0d3b640bdd5f3f6fbc7826c1d1edba494340df Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/661117 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h | 20 ++++ drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 130 +++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 6 +- drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 4 + drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 34 ++++++- 6 files changed, 192 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h index e443738fd..c04b01c1f 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h @@ -66,10 +66,30 @@ static inline u32 bus_bar1_block_mode_virtual_f(void) { return 0x80000000; } +static inline u32 bus_bar2_block_r(void) +{ + return 0x00001714; +} +static inline u32 bus_bar2_block_ptr_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 bus_bar2_block_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 bus_bar2_block_mode_virtual_f(void) +{ + return 0x80000000; +} static inline u32 bus_bar1_block_ptr_shift_v(void) { return 0x0000000c; } +static inline u32 bus_bar2_block_ptr_shift_v(void) +{ + return 0x0000000c; +} static inline u32 bus_intr_0_r(void) { return 0x00001100; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 7872c19c8..3b97c9da6 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index b79758d21..d2629b086 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -178,6 +178,10 @@ static inline u32 fifo_intr_0_lb_error_reset_f(void) { return 0x1000000; } +static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) +{ + return 0x2000000; +} static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) { return 0x8000000; @@ -526,4 +530,128 @@ static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) { return 0x00000001; } +static inline u32 fifo_replay_fault_buffer_lo_r(void) +{ + return 0x00002a70; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) +{ + return (v & 0xfffff) << 12; +} +static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_hi_r(void) +{ + return 0x00002a74; +} +static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_size_r(void) +{ + return 0x00002a78; +} +static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) +{ + return 0x000000c0; +} +static inline u32 fifo_replay_fault_buffer_get_r(void) +{ + return 0x00002a7c; +} +static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_put_r(void) +{ + return 0x00002a80; +} +static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) +{ + return (v & 0x1ff) << 0; +} +static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_r(void) +{ + return 0x00002a84; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) +{ + return 0x00000000; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) +{ + return 0x00000001; +} +static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) +{ + return 0x00000001; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 0bd707db8..49078f115 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1294,6 +1294,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) { return 0x00000004; } +static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) +{ + return 0x00000028; +} static inline u32 gr_ds_zbc_z_r(void) { return 0x00405818; diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index 21c592da5..7d153b6f7 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) { return 0x100; } +static inline u32 mc_intr_replayable_fault_pending_f(void) +{ + return 0x200; +} static inline u32 mc_intr_pgraph_pending_f(void) { return 0x1000; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 509031e5d..dea53f966 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -78,6 +78,38 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) +{ + return 0x10; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) +{ + return 128; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) +{ + return 0x20; +} static inline u32 ram_in_big_page_size_f(u32 v) { return (v & 0x1) << 11; -- cgit v1.2.2 From 8d50993d11bb8b9bf2ba28a0c7b2dd15e6e4dcc1 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Mon, 22 Dec 2014 16:16:29 -0800 Subject: gpu: nvgpu: headers for linsim CL 34000094 Change-Id: I43380fda328414e96601e1c03c3e0ec28c0b4871 Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/666905 Tested-by: Terje Bergstrom Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 12 ++++++------ drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index d2629b086..d10345c3d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -276,23 +276,23 @@ static inline u32 fifo_intr_mmu_fault_info_r(u32 i) } static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) { - return (r >> 0) & 0xf; + return (r >> 0) & 0x1f; } -static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) +static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) { - return (r >> 6) & 0x1; + return (r >> 20) & 0x1; } -static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) +static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) { return 0x00000000; } -static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) +static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) { return 0x00000001; } static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) { - return (r >> 8) & 0x3f; + return (r >> 8) & 0x7f; } static inline u32 fifo_intr_pbdma_id_r(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index 272f7fb3e..cdb28d088 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h @@ -64,15 +64,15 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) { - return (v & 0x3) << 0; + return (v & 0xff) << 0; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) { - return 0x3 << 0; + return 0xff << 0; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) { - return (r >> 0) & 0x3; + return (r >> 0) & 0xff; } static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) { -- cgit v1.2.2 From e438d859fece7c2a27bca658ca3649c3bd8091b7 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 3 Dec 2014 11:20:11 -0800 Subject: gpu: nvgpu: gp10b: enable replayable fault interrupt Bug 1587825 Change-Id: I6df2f870b4488bb3d5ada52b4819f6f80624becd Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/659092 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index c7a4bc753..1760b6adf 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -1,7 +1,7 @@ /* * GP20B master * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,6 +27,7 @@ void mc_gp10b_intr_enable(struct gk20a *g) 0xffffffff); g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = mc_intr_pfifo_pending_f() + | mc_intr_replayable_fault_pending_f() | eng_intr_mask; gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); -- cgit v1.2.2 From 8bedf4bc01ea4450829f335f2bf4bd29aabd9a61 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 3 Dec 2014 17:55:05 -0800 Subject: gpu: nvgpu: gp10b: Add Bar2 support Add bar2 support for gp10b and set-up bar2 binding. Bug 1587825 Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/659236 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 58 +++++++++++++++++++++++++++++++++++++- 1 file changed, 57 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index ff248f519..00e41fa7e 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B MMU * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,15 +14,71 @@ */ #include +#include #include "gk20a/gk20a.h" +#include "mm_gp10b.h" +#include "hw_ram_gp10b.h" +#include "hw_bus_gp10b.h" u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) { return 36; } +static int gb10b_init_bar2_vm(struct gk20a *g) +{ + int err; + struct mm_gk20a *mm = &g->mm; + struct vm_gk20a *vm = &mm->bar2.vm; + struct inst_desc *inst_block = &mm->bar2.inst_block; + u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; + + /* BAR2 aperture size is 32MB */ + mm->bar2.aperture_size = 32 << 20; + gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size); + gk20a_init_vm(mm, vm, big_page_size, SZ_4K, + mm->bar2.aperture_size, false, "bar2"); + + /* allocate instance mem for bar2 */ + err = gk20a_alloc_inst_block(g, inst_block); + if (err) + goto clean_up_va; + + gk20a_init_inst_block(inst_block, vm, big_page_size); + + return 0; + +clean_up_va: + gk20a_deinit_vm(vm); + return err; +} + + +static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct inst_desc *inst_block = &mm->bar2.inst_block; + phys_addr_t inst_pa = inst_block->cpu_pa; + + gk20a_dbg_fn(""); + + g->ops.fb.set_mmu_page_size(g); + + inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); + gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa); + + gk20a_writel(g, bus_bar2_block_r(), + bus_bar2_block_target_vid_mem_f() | + bus_bar2_block_mode_virtual_f() | + bus_bar2_block_ptr_f(inst_pa)); + + gk20a_dbg_fn("done"); + return 0; +} void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; + gops->mm.init_bar2_vm = gb10b_init_bar2_vm; + gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; } -- cgit v1.2.2 From 92617fa9677dc6a35969c646502f02b3f177d4f1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 27 Jan 2015 09:19:10 -0800 Subject: gpu: nvgpu: gp10b: Compression page size to 64k Define compression page size for gp10b to be 64k. We also need to copy some LTC initialization code from gm20b to gp10b. Change-Id: I0235c32cdb1486a23d33eb98ebbc79c97a3c32d4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/677837 --- drivers/gpu/nvgpu/gp10b/fb_gp10b.c | 6 +++ drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 95 ++++++++++++++++++++++++++++++++++++- 2 files changed, 99 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c index df35c5b0a..bd1b7bf0c 100644 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c @@ -87,9 +87,15 @@ static void gp10b_init_kind_attr(void) } } +static int gp10b_fb_compression_page_size(struct gk20a *g) +{ + return SZ_64K; +} + void gp10b_init_fb(struct gpu_ops *gops) { gm20b_init_fb(gops); + gops->fb.compression_page_size = gp10b_fb_compression_page_size; gp10b_init_uncompressed_kind_map(); gp10b_init_kind_attr(); diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 88f7b072f..034542401 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -19,6 +19,8 @@ #include "gm20b/ltc_gm20b.h" #include "hw_ltc_gp10b.h" +#include "gk20a/ltc_common.c" + static int gp10b_determine_L2_size_bytes(struct gk20a *g) { u32 tmp; @@ -39,9 +41,98 @@ static int gp10b_determine_L2_size_bytes(struct gk20a *g) return ret; } -void gp10b_init_ltc(struct gpu_ops *gops) +static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) { - gm20b_init_ltc(gops); + /* max memory size (MB) to cover */ + u32 max_size = gr->max_comptag_mem; + /* one tag line covers 64KB */ + u32 max_comptag_lines = max_size << 4; + + u32 hw_max_comptag_lines = + ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); + + u32 cbc_param = + gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); + u32 comptags_per_cacheline = + ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); + u32 cacheline_size = + 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); + u32 slices_per_ltc = + ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); + + u32 compbit_backing_size; + + int err; + + gk20a_dbg_fn(""); + + if (max_comptag_lines == 0) { + gr->compbit_store.size = 0; + return 0; + } + + if (max_comptag_lines > hw_max_comptag_lines) + max_comptag_lines = hw_max_comptag_lines; + + compbit_backing_size = + DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * + cacheline_size * slices_per_ltc * g->ltc_count; + + /* aligned to 2KB * ltc_count */ + compbit_backing_size += + g->ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); + + /* must be a multiple of 64KB */ + compbit_backing_size = roundup(compbit_backing_size, 64*1024); + max_comptag_lines = + (compbit_backing_size * comptags_per_cacheline) / + (cacheline_size * slices_per_ltc * g->ltc_count); + + if (max_comptag_lines > hw_max_comptag_lines) + max_comptag_lines = hw_max_comptag_lines; + + gk20a_dbg_info("compbit backing store size : %d", + compbit_backing_size); + gk20a_dbg_info("max comptag lines : %d", + max_comptag_lines); + + if (tegra_platform_is_linsim()) + err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); + else + err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); + + if (err) + return err; + + gk20a_allocator_init(&gr->comp_tags, "comptag", + 1, /* start */ + max_comptag_lines - 1); /* length*/ + + gr->comptags_per_cacheline = comptags_per_cacheline; + gr->slices_per_ltc = slices_per_ltc; + gr->cacheline_size = cacheline_size; + + return 0; +} + +void gp10b_init_ltc(struct gpu_ops *gops) +{ gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; + gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; + gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; + gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; + gops->ltc.init_cbc = gk20a_ltc_init_cbc; + + /* GM20b specific ops. */ + gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; + gops->ltc.init_comptags = gp10b_ltc_init_comptags; + gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; + gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; + gops->ltc.isr = gm20b_ltc_isr; + gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; + gops->ltc.flush = gm20b_flush_ltc; +#ifdef CONFIG_DEBUG_FS + gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; +#endif } -- cgit v1.2.2 From 92b486725557e831acbabc9cf7d11f38359eaccc Mon Sep 17 00:00:00 2001 From: Jussi Rasanen Date: Fri, 16 Jan 2015 12:55:28 +0200 Subject: gpu: nvgpu: read gobs_per_comptagline_per_slice Add code to read NV_PLTCG_LTCS_LTSS_CBC_PARAM2_GOBS_PER_COMPTAGLINE_PER_SLICE during t18x ltc init and store it for use in CDE code. Change-Id: I4d4a3a6c7e3ad369d8359ff838e7040a0521b441 Signed-off-by: Jussi Rasanen Reviewed-on: http://git-master/r/673150 Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 10 +++++++++- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 10 +++++++++- 2 files changed, 18 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 32683dc26..01b66c9cf 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -174,6 +174,14 @@ static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) { return (r >> 28) & 0xf; } +static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) +{ + return 0x0017e3f4; +} +static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) { return 0x0017e2ac; diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 034542401..beda30380 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B L2 * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -59,6 +59,10 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); u32 slices_per_ltc = ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); + u32 cbc_param2 = + gk20a_readl(g, ltc_ltcs_ltss_cbc_param2_r()); + u32 gobs_per_comptagline_per_slice = + ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(cbc_param2); u32 compbit_backing_size; @@ -96,6 +100,8 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) compbit_backing_size); gk20a_dbg_info("max comptag lines : %d", max_comptag_lines); + gk20a_dbg_info("gobs_per_comptagline_per_slice: %d", + gobs_per_comptagline_per_slice); if (tegra_platform_is_linsim()) err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); @@ -112,6 +118,7 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; gr->cacheline_size = cacheline_size; + gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice; return 0; } @@ -136,3 +143,4 @@ void gp10b_init_ltc(struct gpu_ops *gops) gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; #endif } + -- cgit v1.2.2 From 30cad2cd4804c87144d32eb701f1eaf68f4be60a Mon Sep 17 00:00:00 2001 From: Jussi Rasanen Date: Tue, 13 Jan 2015 11:36:49 +0200 Subject: gpu: nvgpu: enable CDE for t18x Mark CDE as supported on t18x. Change-Id: I03c23178712b9018137edddfa8e1ff3a2ad9106c Signed-off-by: Jussi Rasanen Reviewed-on: http://git-master/r/672384 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 0542086ce..ab98cbdec 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -3,7 +3,7 @@ * * GK20A Tegra Platform Interface * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -99,4 +99,6 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .dump_platform_dependencies = gk20a_tegra_debug_dump, .default_big_page_size = SZ_64K, + + .has_cde = true, }; -- cgit v1.2.2 From 43ff5016e787866c1c886277ca26bd7620be062d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 30 Jan 2015 15:14:55 -0800 Subject: gpu: nvgpu: gp10b: Enable debug spew Change-Id: I58811bbce0e39b85074f3aa9022a730f696e407e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/679704 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 161c20c6d..1a34688a6 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -98,6 +98,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gm20b_init_clk_ops(gops); + gk20a_init_debug_ops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From 25915d02e3f6cfa7d1e1d9808597e868efb557a6 Mon Sep 17 00:00:00 2001 From: Peng Du Date: Mon, 26 Jan 2015 14:49:49 -0800 Subject: gpu: nvgpu: headers for linsim CL 34116551 Change-Id: Ia8760772b0135813475f96a786484d7caef3759d Signed-off-by: Peng Du Reviewed-on: http://git-master/r/677464 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bo Yan --- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 16 ---------------- 2 files changed, 1 insertion(+), 17 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index d10345c3d..2c0367d51 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -560,7 +560,7 @@ static inline u32 fifo_replay_fault_buffer_hi_r(void) } static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) { - return (v & 0xffff) << 0; + return (v & 0xff) << 0; } static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) { diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index dea53f966..6ddff281c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,14 +78,6 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1 << 4; -} static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { return 128; @@ -94,14 +86,6 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { return 0x10; } -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1 << 5; -} static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { return 128; -- cgit v1.2.2 From cf4f170a33de9e49824a3583d488001863c82785 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Thu, 12 Feb 2015 16:09:02 +0530 Subject: gpu: nvgpu: gp10b: use tight loop for fecs method bug 200078367 Change-Id: I9a68e988fa7921276e334c75afa5ee4b15aab464 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/707313 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 576cdf45e..90514b82d 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B GPU GR * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -492,7 +492,7 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g) op.method.addr = gr_fecs_method_push_adr_discover_preemption_image_size_v(); op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; - err = gr_gk20a_submit_fecs_method_op(g, op); + err = gr_gk20a_submit_fecs_method_op(g, op, false); if (err) { gk20a_err(dev_from_gk20a(g), "query preempt image size failed"); -- cgit v1.2.2 From b7e4ec2096c46edd5c448fbda91a17910597b3a0 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 29 Jan 2015 12:20:49 +0530 Subject: gpu: nvgpu: gp10b: dump GR status registers Add function pointer gr_gp10b_dump_gr_status_regs() which will enable dumping GR status registers for gp10b Bug 200062436 Change-Id: Iaecc2f9c9364232079bb03e114f68550bd035372 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/678832 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 120 ++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 156 ++++++++++++++++++++++++++++++++++ 2 files changed, 276 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 90514b82d..e3d4b9735 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -20,6 +20,7 @@ #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ #include "gp10b/gr_gp10b.h" #include "hw_gr_gp10b.h" +#include "hw_fifo_gp10b.h" #include "hw_proj_gp10b.h" #include "hw_ctxsw_prog_gp10b.h" @@ -692,6 +693,124 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, gk20a_dbg_fn("done"); } +static int gr_gp10b_dump_gr_status_regs(struct gk20a *g, + struct gk20a_debug_output *o) +{ + struct gr_gk20a *gr = &g->gr; + + gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", + gk20a_readl(g, gr_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n", + gk20a_readl(g, gr_status_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_STATUS2: 0x%x\n", + gk20a_readl(g, gr_status_2_r())); + gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n", + gk20a_readl(g, gr_engine_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n", + gk20a_readl(g, gr_gpfifo_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n", + gk20a_readl(g, gr_gpfifo_ctl_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n", + gk20a_readl(g, gr_fecs_host_int_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION : 0x%x\n", + gk20a_readl(g, gr_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n", + gk20a_readl(g, gr_fecs_intr_r())); + gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n", + gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A))); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n", + gk20a_readl(g, gr_activity_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY2: 0x%x\n", + gk20a_readl(g, gr_activity_2_r())); + gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n", + gk20a_readl(g, gr_activity_4_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n", + gk20a_readl(g, gr_pri_sked_activity_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); + if (gr->gpc_tpc_count[0] == 2) + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); + if (gr->gpc_tpc_count[0] == 2) + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_be0_becs_be_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_be1_becs_be_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0: 0x%x\n", + gk20a_readl(g, gr_pri_bes_becs_be_activity0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n", + gk20a_readl(g, gr_pri_ds_mpipe_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n", + gk20a_readl(g, gr_fe_go_idle_timeout_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n", + gk20a_readl(g, gr_pri_fe_go_idle_info_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", + gk20a_readl(g, gr_cwd_fs_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", + gk20a_readl(g, gr_fe_tpc_fs_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n", + gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); + gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", + gk20a_readl(g, gr_cwd_sm_id_r(0))); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n", + gk20a_readl(g, gr_fecs_ctxsw_status_fe_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n", + gk20a_readl(g, gr_fecs_ctxsw_status_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n", + gk20a_readl(g, gr_fecs_ctxsw_idlestate_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n", + gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n", + gk20a_readl(g, gr_fecs_current_ctx_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n", + gk20a_readl(g, gr_fecs_new_ctx_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n", + gk20a_readl(g, gr_pri_be0_crop_status1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n", + gk20a_readl(g, gr_pri_bes_crop_status1_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS : 0x%x\n", + gk20a_readl(g, gr_pri_be0_zrop_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS2 : 0x%x\n", + gk20a_readl(g, gr_pri_be0_zrop_status2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS : 0x%x\n", + gk20a_readl(g, gr_pri_bes_zrop_status_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n", + gk20a_readl(g, gr_pri_bes_zrop_status2_r())); + return 0; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -714,4 +833,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx; gops->gr.update_ctxsw_preemption_mode = gr_gp10b_update_ctxsw_preemption_mode; + gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 49078f115..a1cfab573 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -222,6 +222,10 @@ static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) { return 0x10000; } +static inline u32 gr_gpfifo_status_r(void) +{ + return 0x00400504; +} static inline u32 gr_trapped_addr_r(void) { return 0x00400704; @@ -266,6 +270,14 @@ static inline u32 gr_status_mask_r(void) { return 0x00400610; } +static inline u32 gr_status_1_r(void) +{ + return 0x00400604; +} +static inline u32 gr_status_2_r(void) +{ + return 0x00400608; +} static inline u32 gr_engine_status_r(void) { return 0x0040060c; @@ -274,6 +286,130 @@ static inline u32 gr_engine_status_value_busy_f(void) { return 0x1; } +static inline u32 gr_activity_0_r(void) +{ + return 0x00400380; +} +static inline u32 gr_activity_1_r(void) +{ + return 0x00400384; +} +static inline u32 gr_activity_2_r(void) +{ + return 0x00400388; +} +static inline u32 gr_activity_4_r(void) +{ + return 0x00400390; +} +static inline u32 gr_pri_sked_activity_r(void) +{ + return 0x00407054; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) +{ + return 0x00502c80; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) +{ + return 0x00502c84; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) +{ + return 0x00502c88; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) +{ + return 0x00502c8c; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x00504500; +} +static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x00504d00; +} +static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00501d00; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) +{ + return 0x0041ac80; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) +{ + return 0x0041ac84; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) +{ + return 0x0041ac88; +} +static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) +{ + return 0x0041ac8c; +} +static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) +{ + return 0x0041c500; +} +static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) +{ + return 0x0041cd00; +} +static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) +{ + return 0x00419d00; +} +static inline u32 gr_pri_be0_becs_be_activity0_r(void) +{ + return 0x00410200; +} +static inline u32 gr_pri_be1_becs_be_activity0_r(void) +{ + return 0x00410600; +} +static inline u32 gr_pri_bes_becs_be_activity0_r(void) +{ + return 0x00408a00; +} +static inline u32 gr_pri_ds_mpipe_status_r(void) +{ + return 0x00405858; +} +static inline u32 gr_pri_fe_go_idle_info_r(void) +{ + return 0x00404194; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) +{ + return 0x00504238; +} +static inline u32 gr_pri_be0_crop_status1_r(void) +{ + return 0x00410134; +} +static inline u32 gr_pri_bes_crop_status1_r(void) +{ + return 0x00408934; +} +static inline u32 gr_pri_be0_zrop_status_r(void) +{ + return 0x00410048; +} +static inline u32 gr_pri_be0_zrop_status2_r(void) +{ + return 0x0041004c; +} +static inline u32 gr_pri_bes_zrop_status_r(void) +{ + return 0x00408848; +} +static inline u32 gr_pri_bes_zrop_status2_r(void) +{ + return 0x0040884c; +} static inline u32 gr_pipe_bundle_address_r(void) { return 0x00400200; @@ -1062,6 +1198,26 @@ static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) { return (r >> 0) & 0x1f; } +static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) +{ + return 0x00409c00; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) +{ + return 0x00502c04; +} +static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) +{ + return 0x00502400; +} +static inline u32 gr_fecs_ctxsw_idlestate_r(void) +{ + return 0x00409420; +} +static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) +{ + return 0x00502420; +} static inline u32 gr_rstr2d_gpc_map0_r(void) { return 0x0040780c; -- cgit v1.2.2 From d7b5b51ba5e1b8c24fe1a1423791b1907dd9d267 Mon Sep 17 00:00:00 2001 From: Supriya Date: Thu, 19 Feb 2015 10:40:22 +0530 Subject: gpu: nvgpu: reg with FECS HALT method Change-Id: Ia196b98c79a71c9545e555260660e274982455a3 Signed-off-by: Supriya Reviewed-on: http://git-master/r/709279 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index a1cfab573..ca4254472 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -858,6 +858,10 @@ static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) { return 0x0000001a; } +static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) +{ + return 0x00000004; +} static inline u32 gr_fecs_host_int_status_r(void) { return 0x00409c18; -- cgit v1.2.2 From d78f29237ba1c634423f3e512bba0f39c627a3a4 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 20 Feb 2015 08:39:31 -0800 Subject: gpu: nvgpu: gp10b: Enable warnings as errors Change-Id: I86de27309ebecd038a7b32c6f86d87ce0156eb14 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/709867 --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 3575d4146..e897ab9c0 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -7,6 +7,7 @@ ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi ccflags-$(CONFIG_GK20A) += -Wno-multichar +ccflags-y += -Werror obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index e3d4b9735..271a6d0c0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -571,11 +571,12 @@ int gr_gp10b_alloc_gr_ctx(struct gk20a *g, (*gr_ctx)->preempt_mode = flags; } - if (class == PASCAL_COMPUTE_A) + if (class == PASCAL_COMPUTE_A) { if (flags == NVGPU_GR_PREEMPTION_MODE_CILP) (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; else (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + } gk20a_dbg_fn("done"); -- cgit v1.2.2 From 9e147669757baeb58cde0533c54c889d6ca858e2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 16 Jan 2015 09:15:20 -0800 Subject: gpu: nvgpu: gp10b: Set correct PBDMA signature GPFIFO class was set to Maxwell class number. Also implement the PBDMA signature HAL. Change-Id: Ieaebcda8af96d5779289b311c0c433e8b4349234 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/672921 --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 32 ++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | 18 ++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 5 +++-- 4 files changed, 54 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/fifo_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/fifo_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index e897ab9c0..e14cd0ee5 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_GK20A) += \ mm_gp10b.o \ fb_gp10b.o \ pmu_gp10b.o \ + fifo_gp10b.o \ hal_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c new file mode 100644 index 000000000..d67c7ee2a --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -0,0 +1,32 @@ +/* + * GP10B fifo + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gm20b/fifo_gm20b.h" +#include "hw_pbdma_gp10b.h" + +static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) +{ + return g->gpu_characteristics.gpfifo_class + | pbdma_signature_sw_zero_f(); +} + +void gp10b_init_fifo(struct gpu_ops *gops) +{ + gm20b_init_fifo(gops); + gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; +} diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h new file mode 100644 index 000000000..18e2034fa --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h @@ -0,0 +1,18 @@ +/* + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef FIFO_GP10B_H +#define FIFO_GP10B_H +struct gpu_ops; +void gp10b_init_fifo(struct gpu_ops *gops); +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 1a34688a6..30b56a5c7 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -31,6 +31,7 @@ #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" +#include "gp10b/fifo_gp10b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" @@ -93,7 +94,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gm20b_init_fifo(gops); + gp10b_init_fifo(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); @@ -104,7 +105,7 @@ int gp10b_init_hal(struct gk20a *g) c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; c->compute_class = PASCAL_COMPUTE_A; - c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A; + c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A; c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; c->dma_copy_class = MAXWELL_DMA_COPY_A; -- cgit v1.2.2 From afa6efb3362d703513560f883243583b4caba75a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 19 Feb 2015 12:55:19 -0800 Subject: gpu: nvgpu: gp10b specific LTC ISR LTC interrupt register got moved, so use the new offset. Bug 1587638 Change-Id: I3dbd44d92f2bcb3634c21ed46870ec1620d936cf Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/709571 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index beda30380..b32e29798 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -17,6 +17,8 @@ #include "gk20a/gk20a.h" #include "gm20b/ltc_gm20b.h" +#include "hw_proj_gp10b.h" +#include "hw_mc_gp10b.h" #include "hw_ltc_gp10b.h" #include "gk20a/ltc_common.c" @@ -123,6 +125,31 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) return 0; } +void gp10b_ltc_isr(struct gk20a *g) +{ + u32 mc_intr, ltc_intr; + int ltc, slice; + + mc_intr = gk20a_readl(g, mc_intr_ltc_r()); + gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x", + mc_intr); + for (ltc = 0; ltc < g->ltc_count; ltc++) { + if ((mc_intr & 1 << ltc) == 0) + continue; + for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { + ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + + proj_ltc_stride_v() * ltc + + proj_lts_stride_v() * slice); + gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", + ltc, slice, ltc_intr); + gk20a_writel(g, ltc_ltc0_lts0_intr_r() + + proj_ltc_stride_v() * ltc + + proj_lts_stride_v() * slice, + ltc_intr); + } + } +} + void gp10b_init_ltc(struct gpu_ops *gops) { gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; @@ -136,7 +163,7 @@ void gp10b_init_ltc(struct gpu_ops *gops) gops->ltc.init_comptags = gp10b_ltc_init_comptags; gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; - gops->ltc.isr = gm20b_ltc_isr; + gops->ltc.isr = gp10b_ltc_isr; gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; gops->ltc.flush = gm20b_flush_ltc; #ifdef CONFIG_DEBUG_FS -- cgit v1.2.2 From 9fbc68444bb147c3a1e6fe3a3119b74c9e190733 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 11 Feb 2015 14:34:48 -0800 Subject: gpu: nvgpu: Add ELPG_ENABLE register Change-Id: I8b2272641c7f406cec9bb2649846e4b4b195e21a Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/708720 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index 7d153b6f7..30165e66d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h @@ -226,4 +226,20 @@ static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) { return (v & 0x1) << (0 + i*1); } +static inline u32 mc_elpg_enable_r(void) +{ + return 0x0000020c; +} +static inline u32 mc_elpg_enable_xbar_enabled_f(void) +{ + return 0x4; +} +static inline u32 mc_elpg_enable_pfb_enabled_f(void) +{ + return 0x100000; +} +static inline u32 mc_elpg_enable_hub_enabled_f(void) +{ + return 0x20000000; +} #endif -- cgit v1.2.2 From fe80680b3ec1ca566bdf386a62b0c04981309153 Mon Sep 17 00:00:00 2001 From: Sam Payne Date: Thu, 5 Feb 2015 10:46:35 -0800 Subject: gpu: nvgpu: gp10b: add ce interrupt support ce interrupts use different register mapping and format from gk20a and gm20b. Change-Id: Icfe33bad940b2b829b6f57d07a3300adaf53d43c Signed-off-by: Sam Payne Reviewed-on: http://git-master/r/681646 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 83 ++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/ce2_gp10b.h | 29 ++++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 ++- drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h | 81 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 8 ++++ 6 files changed, 206 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.h create mode 100644 drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index e14cd0ee5..421e50f6c 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -12,6 +12,7 @@ ccflags-y += -Werror obj-$(CONFIG_GK20A) += \ gr_gp10b.o \ gr_ctx_gp10b.o \ + ce2_gp10b.o \ mc_gp10b.o \ ltc_gp10b.o \ mm_gp10b.o \ diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c new file mode 100644 index 000000000..d76b97a5e --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c @@ -0,0 +1,83 @@ +/* + * GK20A Graphics Copy Engine (gr host) + * + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include "hw_ce2_gp10b.h" +#include "ce2_gp10b.h" + +static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); + + /* wake theads waiting in this channel */ + gk20a_channel_semaphore_wakeup(g); + return ce2_intr_status_nonblockpipe_pending_f(); +} + +static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); + + return ce2_intr_status_blockpipe_pending_f(); +} + +static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) +{ + gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); + + return ce2_intr_status_launcherr_pending_f(); +} + +void gp10b_ce2_isr(struct gk20a *g) +{ + u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); + + /* clear blocking interrupts: they exibit broken behavior */ + if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) + clear_intr |= ce2_blockpipe_isr(g, ce2_intr); + + if (ce2_intr & ce2_intr_status_launcherr_pending_f()) + clear_intr |= ce2_launcherr_isr(g, ce2_intr); + + gk20a_writel(g, ce2_intr_status_r(0), clear_intr); + return; +} + +void gp10b_ce2_nonstall_isr(struct gk20a *g) +{ + u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); + u32 clear_intr = 0; + + gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); + + if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) + clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); + + gk20a_writel(g, ce2_intr_status_r(0), clear_intr); + + return; +} +void gp10b_init_ce2(struct gpu_ops *gops) +{ + gops->ce2.isr_stall = gp10b_ce2_isr; + gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr; +} diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h new file mode 100644 index 000000000..d432d1e0f --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h @@ -0,0 +1,29 @@ +/* + * drivers/video/tegra/host/gk20a/fifo_gk20a.h + * + * GK20A graphics copy engine (gr host) + * + * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __CE2_GP10B_H__ +#define __CE2_GP10B_H__ + +#include "gk20a/channel_gk20a.h" +#include "gk20a/tsg_gk20a.h" + +void gp10b_init_ce2(struct gpu_ops *gops); + +#endif /*__CE2_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 30b56a5c7..c23c0f17b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,7 @@ #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" +#include "gp10b/ce2_gp10b.h" #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" @@ -94,7 +95,8 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gp10b_init_fifo(gops); + gm20b_init_fifo(gops); + gp10b_init_ce2(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h new file mode 100644 index 000000000..b0c35a302 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_ce2_gp10b_h_ +#define _hw_ce2_gp10b_h_ + +static inline u32 ce2_intr_status_r(u32 i) +{ + return 0x00104410 + i*128; +} +static inline u32 ce2_intr_status_blockpipe_pending_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_blockpipe_reset_f(void) +{ + return 0x1; +} +static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) +{ + return 0x2; +} +static inline u32 ce2_intr_status_launcherr_pending_f(void) +{ + return 0x4; +} +static inline u32 ce2_intr_status_launcherr_reset_f(void) +{ + return 0x4; +} +#endif diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 1760b6adf..47c8fcc6f 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c @@ -110,6 +110,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); + if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + && g->ops.ce2.isr_stall) + g->ops.ce2.isr_stall(g); if (mc_intr_0 & mc_intr_pfifo_pending_f()) gk20a_fifo_isr(g); if (mc_intr_0 & mc_intr_pmu_pending_f()) @@ -141,6 +144,11 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) gk20a_fifo_nonstall_isr(g); if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) gk20a_gr_nonstall_isr(g); + if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) + && g->ops.ce2.isr_nonstall) + g->ops.ce2.isr_nonstall(g); + + gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -- cgit v1.2.2 From 5e69f335f87e9b6a2f816ef13a201d5cc38336b8 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 20 Feb 2015 10:09:08 -0800 Subject: gpu: nvgpu: gp10b: update headers Sync with latest hw includes and generated header files. Bug 1587825 Change-Id: I165b541e3215245eb43614e34670093b8420a7df Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/709881 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index 6ddff281c..dea53f966 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -78,6 +78,14 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) { return 0x4; } +static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) +{ + return 0x1 << 4; +} static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) { return 128; @@ -86,6 +94,14 @@ static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) { return 0x10; } +static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) +{ + return 0x1 << 5; +} static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) { return 128; -- cgit v1.2.2 From 3508ea181d01089ce1a356d26fa32688cf2fb1e4 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 3 Feb 2015 12:56:24 -0800 Subject: gpu: nvgpu: gp10b: update fb headers Update fb header with new mmu invalidate fields. Bug 1587836 Change-Id: I33a30dc742f35d325c528a9bc73fea8cfc21e856 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/680800 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 214 +++++++++++++++++++++++++++++++++- 1 file changed, 213 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h index d2ecdce12..2078bdca7 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -122,6 +122,218 @@ static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) { return 0x2; } +static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) +{ + return (v & 0x1) << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) +{ + return 0x1 << 2; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) +{ + return 0x4; +} +static inline u32 fb_mmu_invalidate_replay_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_replay_f(u32 v) +{ + return (v & 0x7) << 3; +} +static inline u32 fb_mmu_invalidate_replay_m(void) +{ + return 0x7 << 3; +} +static inline u32 fb_mmu_invalidate_replay_v(u32 r) +{ + return (r >> 3) & 0x7; +} +static inline u32 fb_mmu_invalidate_replay_none_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_replay_start_f(void) +{ + return 0x8; +} +static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) +{ + return 0x10; +} +static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) +{ + return 0x18; +} +static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_invalidate_replay_cancel_f(void) +{ + return 0x20; +} +static inline u32 fb_mmu_invalidate_sys_membar_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) +{ + return (v & 0x1) << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_m(void) +{ + return 0x1 << 6; +} +static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) +{ + return (r >> 6) & 0x1; +} +static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) +{ + return 0x40; +} +static inline u32 fb_mmu_invalidate_ack_s(void) +{ + return 2; +} +static inline u32 fb_mmu_invalidate_ack_f(u32 v) +{ + return (v & 0x3) << 7; +} +static inline u32 fb_mmu_invalidate_ack_m(void) +{ + return 0x3 << 7; +} +static inline u32 fb_mmu_invalidate_ack_v(u32 r) +{ + return (r >> 7) & 0x3; +} +static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) +{ + return 0x100; +} +static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) +{ + return 0x80; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) +{ + return 6; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) +{ + return (v & 0x3f) << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) +{ + return 0x3f << 9; +} +static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) +{ + return (r >> 9) & 0x3f; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) +{ + return 5; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) +{ + return (v & 0x1f) << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) +{ + return 0x1f << 15; +} +static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) +{ + return (r >> 15) & 0x1f; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) +{ + return 1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) +{ + return (v & 0x1) << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) +{ + return 0x1 << 20; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) +{ + return (r >> 20) & 0x1; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) +{ + return 0x100000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) +{ + return 3; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) +{ + return (v & 0x7) << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) +{ + return 0x7 << 24; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) +{ + return (r >> 24) & 0x7; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) +{ + return 0x0; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) +{ + return 0x1000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) +{ + return 0x2000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) +{ + return 0x3000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) +{ + return 0x4000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) +{ + return 0x5000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) +{ + return 0x6000000; +} +static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) +{ + return 0x7000000; +} static inline u32 fb_mmu_invalidate_trigger_s(void) { return 1; -- cgit v1.2.2 From 50c8c0458d736c1453f90802453b74d9ec6a3d89 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 5 Feb 2015 17:38:49 -0800 Subject: gpu: nvgpu: gp10b: setup mm hw init Add support for gp10b specific mm hw init. Bug 1587825 Change-Id: Iaccf1bf73468cfdd1842a001ab5e682ac06f1950 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/681787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 00e41fa7e..293eb9998 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -25,6 +25,39 @@ u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) return 36; } +static int gp10b_init_mm_setup_hw(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + struct inst_desc *inst_block = &mm->bar1.inst_block; + phys_addr_t inst_pa = inst_block->cpu_pa; + int err = 0; + + gk20a_dbg_fn(""); + + g->ops.fb.set_mmu_page_size(g); + + inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a()); + gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); + + gk20a_writel(g, bus_bar1_block_r(), + bus_bar1_block_target_vid_mem_f() | + bus_bar1_block_mode_virtual_f() | + bus_bar1_block_ptr_f(inst_pa)); + + if (g->ops.mm.init_bar2_mm_hw_setup) { + err = g->ops.mm.init_bar2_mm_hw_setup(g); + if (err) + return err; + } + + if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) + return -EBUSY; + + gk20a_dbg_fn("done"); + return err; + +} + static int gb10b_init_bar2_vm(struct gk20a *g) { int err; @@ -79,6 +112,7 @@ void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; + gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; gops->mm.init_bar2_vm = gb10b_init_bar2_vm; gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; } -- cgit v1.2.2 From 5265ecf919a0b2667411efc246b71c7bedb29c45 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 5 Feb 2015 14:01:59 -0800 Subject: gpu: nvgpu: gp10b: support for replayable faults Add support for enabling replayable faults during channel instance block binding. Also fixed register programing sequence for setting channel pbdma timeout. Bug 1587825 Change-Id: I5a25819b960001d184507bc597aca051f2ac43ad Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/681703 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 2 +- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 124 +++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | 4 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 +- 4 files changed, 130 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 421e50f6c..e44aaecac 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -14,11 +14,11 @@ obj-$(CONFIG_GK20A) += \ gr_ctx_gp10b.o \ ce2_gp10b.o \ mc_gp10b.o \ + fifo_gp10b.o \ ltc_gp10b.o \ mm_gp10b.o \ fb_gp10b.o \ pmu_gp10b.o \ - fifo_gp10b.o \ hal_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index d67c7ee2a..db5d4ede6 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -13,11 +13,133 @@ * more details. */ +#include #include #include "gk20a/gk20a.h" #include "gm20b/fifo_gm20b.h" #include "hw_pbdma_gp10b.h" +#include "fifo_gp10b.h" +#include "hw_ccsr_gp10b.h" +#include "hw_fifo_gp10b.h" +#include "hw_ram_gp10b.h" + +static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, + void *inst_ptr) +{ + u32 val; + + gk20a_dbg_fn(""); + + val = gk20a_mem_rd32(inst_ptr, + ram_in_page_dir_base_fault_replay_tex_w()); + val &= ~ram_in_page_dir_base_fault_replay_tex_m(); + val |= ram_in_page_dir_base_fault_replay_tex_true_f(); + gk20a_mem_wr32(inst_ptr, + ram_in_page_dir_base_fault_replay_tex_w(), val); + + val = gk20a_mem_rd32(inst_ptr, + ram_in_page_dir_base_fault_replay_gcc_w()); + val &= ~ram_in_page_dir_base_fault_replay_gcc_m(); + val |= ram_in_page_dir_base_fault_replay_gcc_true_f(); + gk20a_mem_wr32(inst_ptr, + ram_in_page_dir_base_fault_replay_gcc_w(), val); + + gk20a_dbg_fn("done"); +} + +static int channel_gp10b_commit_userd(struct channel_gk20a *c) +{ + u32 addr_lo; + u32 addr_hi; + void *inst_ptr; + + gk20a_dbg_fn(""); + + inst_ptr = c->inst_block.cpuva; + if (!inst_ptr) + return -ENOMEM; + + addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v()); + addr_hi = u64_hi32(c->userd_iova); + + gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", + c->hw_chid, (u64)c->userd_iova); + + gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_w(), + pbdma_userd_target_vid_mem_f() | + pbdma_userd_addr_f(addr_lo)); + + gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_hi_w(), + pbdma_userd_target_vid_mem_f() | + pbdma_userd_hi_addr_f(addr_hi)); + + return 0; +} + +static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, + u64 gpfifo_base, u32 gpfifo_entries) +{ + void *inst_ptr; + + gk20a_dbg_fn(""); + + inst_ptr = c->inst_block.cpuva; + if (!inst_ptr) + return -ENOMEM; + + memset(inst_ptr, 0, ram_fc_size_val_v()); + + gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_w(), + pbdma_gp_base_offset_f( + u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); + + gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_hi_w(), + pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | + pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); + + gk20a_mem_wr32(inst_ptr, ram_fc_signature_w(), + pbdma_signature_hw_valid_f() | pbdma_signature_sw_zero_f()); + + gk20a_mem_wr32(inst_ptr, ram_fc_formats_w(), + pbdma_formats_gp_fermi0_f() | + pbdma_formats_pb_fermi1_f() | + pbdma_formats_mp_fermi0_f()); + + gk20a_mem_wr32(inst_ptr, ram_fc_pb_header_w(), + pbdma_pb_header_priv_user_f() | + pbdma_pb_header_method_zero_f() | + pbdma_pb_header_subchannel_zero_f() | + pbdma_pb_header_level_main_f() | + pbdma_pb_header_first_true_f() | + pbdma_pb_header_type_inc_f()); + + gk20a_mem_wr32(inst_ptr, ram_fc_subdevice_w(), + pbdma_subdevice_id_f(1) | + pbdma_subdevice_status_active_f() | + pbdma_subdevice_channel_dma_enable_f()); + + gk20a_mem_wr32(inst_ptr, ram_fc_target_w(), pbdma_target_engine_sw_f()); + + gk20a_mem_wr32(inst_ptr, ram_fc_acquire_w(), + pbdma_acquire_retry_man_2_f() | + pbdma_acquire_retry_exp_2_f() | + pbdma_acquire_timeout_exp_max_f() | + pbdma_acquire_timeout_man_max_f() | + pbdma_acquire_timeout_en_disable_f()); + + gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(), + pbdma_runlist_timeslice_timeout_128_f() | + pbdma_runlist_timeslice_timescale_3_f() | + pbdma_runlist_timeslice_enable_true_f()); + + gp10b_set_pdb_fault_replay_flags(c->g, inst_ptr); + + + gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); + + return channel_gp10b_commit_userd(c); +} static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) { @@ -28,5 +150,7 @@ static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) void gp10b_init_fifo(struct gpu_ops *gops) { gm20b_init_fifo(gops); + gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; + } diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h index 18e2034fa..ad3679aa7 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h @@ -1,5 +1,7 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * GP10B Fifo + * + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index c23c0f17b..ff140a04e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -28,6 +28,7 @@ #include "gp10b/fb_gp10b.h" #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" +#include "gp10b/fifo_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/gm20b_gating_reglist.h" @@ -95,7 +96,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); - gm20b_init_fifo(gops); + gp10b_init_fifo(gops); gp10b_init_ce2(gops); gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); -- cgit v1.2.2 From e0346a6809c315b7b228c8f476b4810db6bb63ef Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 6 Feb 2015 12:39:05 -0800 Subject: gpu: nvgpu: gp10b: Add replayable pagefault buffer Add support for replayable fault buffer and enable it. Bug 1587836 Change-Id: Iee4ba42ab175c0d72d2c041fdb3ac9d845358847 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/661668 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 3 + drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c | 146 +++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h | 30 +++++++ 4 files changed, 181 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index e44aaecac..9d0c0311e 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_GK20A) += \ mm_gp10b.o \ fb_gp10b.o \ pmu_gp10b.o \ - hal_gp10b.o + hal_gp10b.o \ + rpfb_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 293eb9998..65bc6cbc9 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -17,6 +17,7 @@ #include #include "gk20a/gk20a.h" #include "mm_gp10b.h" +#include "rpfb_gp10b.h" #include "hw_ram_gp10b.h" #include "hw_bus_gp10b.h" @@ -53,6 +54,8 @@ static int gp10b_init_mm_setup_hw(struct gk20a *g) if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) return -EBUSY; + err = gp10b_replayable_pagefault_buffer_init(g); + gk20a_dbg_fn("done"); return err; diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c new file mode 100644 index 000000000..ba91403ca --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c @@ -0,0 +1,146 @@ +/* + * GP10B RPFB + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include "gk20a/gk20a.h" +#include "rpfb_gp10b.h" +#include "hw_fifo_gp10b.h" +#include "hw_fb_gp10b.h" +#include "hw_bus_gp10b.h" +#include "hw_gmmu_gp10b.h" + +int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) +{ + u32 addr_lo; + u32 addr_hi; + struct vm_gk20a *vm = &g->mm.bar2.vm; + int err; + size_t rbfb_size = NV_UVM_FAULT_BUF_SIZE * + fifo_replay_fault_buffer_size_hw_entries_v(); + + gk20a_dbg_fn(""); + + err = gk20a_gmmu_alloc_map(vm, rbfb_size, &g->mm.bar2_desc); + if (err) { + dev_err(dev_from_gk20a(g), "%s Error in replayable fault buffer\n", + __func__); + return err; + } + addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12); + addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va); + gk20a_writel(g, fifo_replay_fault_buffer_hi_r(), + fifo_replay_fault_buffer_hi_base_f(addr_hi)); + + gk20a_writel(g, fifo_replay_fault_buffer_lo_r(), + fifo_replay_fault_buffer_lo_base_f(addr_lo) | + fifo_replay_fault_buffer_lo_enable_true_v()); + + gk20a_dbg_fn("done"); + return 0; +} + +void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g) +{ + struct vm_gk20a *vm = &g->mm.bar2.vm; + gk20a_gmmu_unmap_free(vm, &g->mm.bar2_desc); +} + +u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g) +{ + u32 get_idx = 0; + gk20a_dbg_fn(""); + + get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); + + if (get_idx >= fifo_replay_fault_buffer_size_hw_entries_v()) + dev_err(dev_from_gk20a(g), "%s Error in replayable fault buffer\n", + __func__); + gk20a_dbg_fn("done"); + return get_idx; +} + +u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g) +{ + u32 put_idx = 0; + + gk20a_dbg_fn(""); + put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r()); + + if (put_idx >= fifo_replay_fault_buffer_size_hw_entries_v()) + dev_err(dev_from_gk20a(g), "%s Error in UVM\n", + __func__); + gk20a_dbg_fn("done"); + return put_idx; +} + +bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g) +{ + u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); + u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r()); + + return (get_idx == put_idx ? true : false); +} + +bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g) +{ + u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); + u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r()); + u32 hw_entries = gk20a_readl(g, fifo_replay_fault_buffer_size_r()); + + return (get_idx == ((put_idx + 1) % hw_entries) ? true : false); +} + +bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g) +{ + u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r()); + + return fifo_replay_fault_buffer_info_overflow_f(info); +} + +void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g) +{ + u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r()); + + info |= fifo_replay_fault_buffer_info_overflow_clear_v(); + gk20a_writel(g, fifo_replay_fault_buffer_info_r(), info); + +} + +void gp10b_replayable_pagefault_buffer_info(struct gk20a *g) +{ + + gk20a_dbg_fn(""); + pr_info("rpfb low: 0x%x\n", + (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) >> 12)); + pr_info("rpfb hi: 0x%x\n", + gk20a_readl(g, fifo_replay_fault_buffer_hi_r())); + pr_info("rpfb enabled: 0x%x\n", + (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) & 0x1)); + pr_info("rpfb size: %d\n", + gk20a_readl(g, fifo_replay_fault_buffer_size_r())); + pr_info("rpfb get index: %d\n", + gp10b_replayable_pagefault_buffer_get_index(g)); + pr_info("rpfb put index: %d\n", + gp10b_replayable_pagefault_buffer_put_index(g)); + pr_info("rpfb empty: %d\n", + gp10b_replayable_pagefault_buffer_is_empty(g)); + pr_info("rpfb full %d\n", + gp10b_replayable_pagefault_buffer_is_full(g)); + pr_info("rpfb overflow %d\n", + gp10b_replayable_pagefault_buffer_is_overflow(g)); + + gk20a_dbg_fn("done"); +} diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h new file mode 100644 index 000000000..965c9573c --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef RPFB_GP20B_H +#define RPFB_GP20B_H +struct gk20a; + +#define NV_UVM_FAULT_BUF_SIZE 32 + +int gp10b_replayable_pagefault_buffer_init(struct gk20a *g); +u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g); +u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g); +bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g); +bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g); +bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g); +void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g); +void gp10b_replayable_pagefault_buffer_info(struct gk20a *g); +void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g); + +#endif -- cgit v1.2.2 From dc787445a5f64083dc7ab75a2caf696aba356b4d Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Tue, 3 Mar 2015 17:29:19 +0200 Subject: gpu: nvgpu: gp10b: fix swdx_rm_spill size and pointer Fixed incorrectly encoded pointer and size. bug 1525327 bug 1581799 Change-Id: Ie6e94e47c3b11e9d9aa63a70b61e6e89f69e971b Signed-off-by: Kirill Artamonov Reviewed-on: http://git-master/r/713209 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 271a6d0c0..4d0de15fb 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -664,8 +664,9 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << + (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); + size = gr_ctx->t18x.spill_ctxsw_buffer.size; gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_swdx_rm_spill_buffer_addr_r(), @@ -673,7 +674,7 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, true); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_swdx_rm_spill_buffer_size_r(), - gr_gpc0_swdx_rm_spill_buffer_size_256b_f(addr), + gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), true); cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); -- cgit v1.2.2 From 764500501bc9c83a8c1f6f008ee8fa32ece78879 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 2 Mar 2015 14:48:00 +0530 Subject: gpu: nvgpu: add exception registers to dump Add below exception registers to GR dump : NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN Bug 200078514 Change-Id: I2400e360fea0b3bdcdf5f3dd6ef250867fb191e6 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/712481 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 12 ++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 24 ++++++++++++++++++++++++ 2 files changed, 36 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 4d0de15fb..306c42233 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -810,6 +810,18 @@ static int gr_gp10b_dump_gr_status_regs(struct gk20a *g, gk20a_readl(g, gr_pri_bes_zrop_status_r())); gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n", gk20a_readl(g, gr_pri_bes_zrop_status2_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n", + gk20a_readl(g, gr_pri_be0_becs_be_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n", + gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r())); + gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n", + gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r())); return 0; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index ca4254472..3ee1cbfe5 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -286,6 +286,30 @@ static inline u32 gr_engine_status_value_busy_f(void) { return 0x1; } +static inline u32 gr_pri_be0_becs_be_exception_r(void) +{ + return 0x00410204; +} +static inline u32 gr_pri_be0_becs_be_exception_en_r(void) +{ + return 0x00410208; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) +{ + return 0x00502c90; +} +static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) +{ + return 0x00502c94; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) +{ + return 0x00504508; +} +static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) +{ + return 0x0050450c; +} static inline u32 gr_activity_0_r(void) { return 0x00400380; -- cgit v1.2.2 From 44f086b577e364f256ca15bbf9afca17ee3057c4 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 5 Mar 2015 09:34:06 -0800 Subject: gpu: nvgpu: gp10b: Use gp10b version of phys bits Use gp10b version of get_physical_addr_bits. Change-Id: I56d1299e259e91a61fa82dc061e7ca3a5130b9d4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/714402 --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 65bc6cbc9..6b140c920 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -114,7 +114,7 @@ static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); - gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; + gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits; gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; gops->mm.init_bar2_vm = gb10b_init_bar2_vm; gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; -- cgit v1.2.2 From e8f23e76beab2f9382b0089a1feaa9fded46593b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 11 Mar 2015 15:55:14 -0700 Subject: gpu: nvgpu: gp10b: Fix offset for preemption ptr Offset for preemption pointer was calculated incorrectly. Bug 1617214 Change-Id: I9c1a9ae24dcd523f4ae17eae0a5b07831839fadb Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/716528 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 306c42233..84faa252f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -642,7 +642,7 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, u32 size; u32 cbes_reserve; - gk20a_mem_wr32(ctx_ptr, ctxsw_prog_main_image_full_preemption_ptr_o(), + gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_full_preemption_ptr_o(), 0, gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); -- cgit v1.2.2 From 1266ade4bec99ff60cf8fcf7efe4a5768ab2e5de Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 2 Mar 2015 17:52:21 -0800 Subject: gpu: nvgpu: gp10b: Use mem_desc for buffers Change-Id: Ia986125bf1a6e06121291f6dde24e580f0a1b61f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/712836 --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 4 ++-- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 10 +++++----- 2 files changed, 7 insertions(+), 7 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index db5d4ede6..59f7deefc 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -56,7 +56,7 @@ static int channel_gp10b_commit_userd(struct channel_gk20a *c) gk20a_dbg_fn(""); - inst_ptr = c->inst_block.cpuva; + inst_ptr = c->inst_block.cpu_va; if (!inst_ptr) return -ENOMEM; @@ -84,7 +84,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, gk20a_dbg_fn(""); - inst_ptr = c->inst_block.cpuva; + inst_ptr = c->inst_block.cpu_va; if (!inst_ptr) return -ENOMEM; diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 6b140c920..9fde61479 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -29,8 +29,8 @@ u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) static int gp10b_init_mm_setup_hw(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; - struct inst_desc *inst_block = &mm->bar1.inst_block; - phys_addr_t inst_pa = inst_block->cpu_pa; + struct mem_desc *inst_block = &mm->bar1.inst_block; + phys_addr_t inst_pa = gk20a_mem_phys(inst_block); int err = 0; gk20a_dbg_fn(""); @@ -66,7 +66,7 @@ static int gb10b_init_bar2_vm(struct gk20a *g) int err; struct mm_gk20a *mm = &g->mm; struct vm_gk20a *vm = &mm->bar2.vm; - struct inst_desc *inst_block = &mm->bar2.inst_block; + struct mem_desc *inst_block = &mm->bar2.inst_block; u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; /* BAR2 aperture size is 32MB */ @@ -93,8 +93,8 @@ clean_up_va: static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) { struct mm_gk20a *mm = &g->mm; - struct inst_desc *inst_block = &mm->bar2.inst_block; - phys_addr_t inst_pa = inst_block->cpu_pa; + struct mem_desc *inst_block = &mm->bar2.inst_block; + phys_addr_t inst_pa = gk20a_mem_phys(inst_block); gk20a_dbg_fn(""); -- cgit v1.2.2 From 14bbb79dc672ede99b381c04eb6281025ee97361 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 4 Mar 2015 15:15:44 +0530 Subject: gpu: nvgpu: accessor for memfmt exception Add accessor for NV_PGRAPH_EXCEPTION_MEMFMT Bug 200078514 Change-Id: Ibf4ce91dfac12d7f6cffb7c65873696e080ff1a5 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/714167 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 3ee1cbfe5..3cac1f70b 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -166,6 +166,10 @@ static inline u32 gr_exception_gpc_m(void) { return 0x1 << 24; } +static inline u32 gr_exception_memfmt_m(void) +{ + return 0x1 << 1; +} static inline u32 gr_exception1_r(void) { return 0x00400118; -- cgit v1.2.2 From 80cb20e5067464815dd81a9ac6fc859bb28ff01a Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 9 Mar 2015 12:12:26 +0200 Subject: gpu: nvgpu: zbc: disable activity only from ioctl Move the fifo engine activity disabling and wait-for-idle from the lowest-level functions higher, into the ioctl path of zbc operations, so that the sw initialization path wouldn't call them. During the init path, the disable isn't necessary, and the code path could result in a deadlock in the fifo runlist mutex. Change-Id: I56e73204e288331165358fc9856390f1eb724488 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/715196 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 56 ++------------------------------------ 1 file changed, 2 insertions(+), 54 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 84faa252f..1b7dd405d 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -163,28 +163,9 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *color_val, u32 index) { - struct fifo_gk20a *f = &g->fifo; - struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; u32 i; - unsigned long end_jiffies = jiffies + - msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); - u32 ret; u32 zbc_c; - ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to disable gr engine activity\n"); - return ret; - } - - ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to idle graphics\n"); - goto clean_up; - } - /* update l2 table */ g->ops.ltc.set_zbc_color_entry(g, color_val, index); @@ -226,40 +207,14 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, zbc_c |= color_val->format << (index % 4) * 6; gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); -clean_up: - ret = gk20a_fifo_enable_engine_activity(g, gr_info); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to enable gr engine activity\n"); - } - - return ret; + return 0; } static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, struct zbc_entry *depth_val, u32 index) { - struct fifo_gk20a *f = &g->fifo; - struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; - unsigned long end_jiffies = jiffies + - msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); - u32 ret; u32 zbc_z; - ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to disable gr engine activity\n"); - return ret; - } - - ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to idle graphics\n"); - goto clean_up; - } - /* update l2 table */ g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); @@ -289,14 +244,7 @@ static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, zbc_z |= depth_val->format << (index % 4) * 6; gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); -clean_up: - ret = gk20a_fifo_enable_engine_activity(g, gr_info); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "failed to enable gr engine activity\n"); - } - - return ret; + return 0; } static u32 gr_gp10b_pagepool_default_size(struct gk20a *g) -- cgit v1.2.2 From 09ef2cf44163384b8ee8a6a88d08cfdc1261780b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sat, 21 Mar 2015 09:02:22 -0700 Subject: gpu: nvgpu: gp10b: Do not clear compbit store size Do not clear compbit store size if max size is zero. It's already zero at this point. Change-Id: I70d99cfe459fae27d8c1be4aa569ac0717a454d7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/720599 --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index b32e29798..dbeed474b 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -72,10 +72,8 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) gk20a_dbg_fn(""); - if (max_comptag_lines == 0) { - gr->compbit_store.size = 0; + if (max_comptag_lines == 0) return 0; - } if (max_comptag_lines > hw_max_comptag_lines) max_comptag_lines = hw_max_comptag_lines; -- cgit v1.2.2 From 2d346207ba1a35fdbf89428ffa2889abcd2fef57 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 20 Mar 2015 13:34:59 +0530 Subject: gpu: nvgpu: add get_iova_addr() for gp10b Add platform specific gp10b_mm_iova_addr() to get iova/phys address for gp10b If SMMU is not enabled and IO coherence flag is set, set 34th bit in the physical address and return the physical address If SMMU is enabled, return the iova address Bug 1605653 Change-Id: I5c91a8c8d85d8a8e422406e3c91fc1dda3cb0870 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/713106 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 3 +++ 2 files changed, 31 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 9fde61479..c316aa9f9 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -111,6 +111,33 @@ static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) gk20a_dbg_fn("done"); return 0; } + +static u64 gp10b_mm_phys_addr_translate(struct gk20a *g, u64 phys_addr, + u32 flags) +{ + if (!device_is_iommuable(dev_from_gk20a(g))) + if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT) + return phys_addr | + 1ULL << NVGPU_MM_GET_IO_COHERENCE_BIT; + + return phys_addr; +} + +static u64 gp10b_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, + u32 flags) +{ + if (!device_is_iommuable(dev_from_gk20a(g))) + return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags); + + if (sg_dma_address(sgl) == 0) + return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags); + + if (sg_dma_address(sgl) == DMA_ERROR_CODE) + return 0; + + return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); +} + void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); @@ -118,4 +145,5 @@ void gp10b_init_mm(struct gpu_ops *gops) gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; gops->mm.init_bar2_vm = gb10b_init_bar2_vm; gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; + gops->mm.get_iova_addr = gp10b_mm_iova_addr; } diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 38ca93a4f..034944e05 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -13,6 +13,9 @@ #ifndef MM_GP10B_H #define MM_GP10B_H + +#define NVGPU_MM_GET_IO_COHERENCE_BIT 35 + struct gpu_ops; void gp10b_init_mm(struct gpu_ops *gops); -- cgit v1.2.2 From dcdb8fa8f463a00bff7b5a26909ed15018ba7c6e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 25 Mar 2015 10:50:41 -0700 Subject: gpu: nvgpu: gp10b: Regenerate HW headers Change-Id: Id1954b6e96dbc75ab217a4b36a11a0457f9ceef1 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/722845 --- drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 8 ++++ drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 12 ++++++ drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 30 ++++++++++++- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 76 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 18 +++++++- 5 files changed, 142 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h index 2078bdca7..1fee19b14 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h @@ -426,10 +426,18 @@ static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) { return (r >> 16) & 0x1; } +static inline u32 fb_mmu_debug_ctrl_debug_m(void) +{ + return 0x1 << 16; +} static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) { return 0x00000001; } +static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) +{ + return 0x00000000; +} static inline u32 fb_mmu_vpr_info_r(void) { return 0x00100cd0; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 2c0367d51..6f7e09ff9 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h @@ -210,10 +210,22 @@ static inline u32 fifo_intr_en_0_r(void) { return 0x00002140; } +static inline u32 fifo_intr_en_0_sched_error_f(u32 v) +{ + return (v & 0x1) << 8; +} static inline u32 fifo_intr_en_0_sched_error_m(void) { return 0x1 << 8; } +static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) +{ + return (v & 0x1) << 28; +} +static inline u32 fifo_intr_en_0_mmu_fault_m(void) +{ + return 0x1 << 28; +} static inline u32 fifo_intr_en_1_r(void) { return 0x00002528; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index cdb28d088..b6b687186 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -98,4 +98,32 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) { return 0x0; } +static inline u32 fuse_status_opt_fbio_r(void) +{ + return 0x00021c14; +} +static inline u32 fuse_status_opt_fbio_data_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 fuse_status_opt_fbio_data_m(void) +{ + return 0xffff << 0; +} +static inline u32 fuse_status_opt_fbio_data_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) +{ + return 0x00021d70 + i*4; +} +static inline u32 fuse_status_opt_fbp_r(void) +{ + return 0x00021d38; +} +static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) +{ + return (r >> (0 + i*0)) & 0x1; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 3cac1f70b..72f1d68c7 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -170,6 +170,10 @@ static inline u32 gr_exception_memfmt_m(void) { return 0x1 << 1; } +static inline u32 gr_exception_ds_m(void) +{ + return 0x1 << 4; +} static inline u32 gr_exception1_r(void) { return 0x00400118; @@ -330,6 +334,30 @@ static inline u32 gr_activity_4_r(void) { return 0x00400390; } +static inline u32 gr_pri_gpc0_gcc_dbg_r(void) +{ + return 0x00501000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_r(void) +{ + return 0x00419000; +} +static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) +{ + return 0x1 << 1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) +{ + return 0x005046a4; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) +{ + return 0x00419ea4; +} +static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) +{ + return 0x1 << 0; +} static inline u32 gr_pri_sked_activity_r(void) { return 0x00407054; @@ -3058,6 +3086,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { return 0x0050450c; } +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) +{ + return (r >> 1) & 0x1; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) { return 0x2; @@ -3106,6 +3138,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) { return 0x00000001; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) +{ + return 0x00000000; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) { return 0x80000000; @@ -3118,10 +3154,50 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) +{ + return (r >> 2) & 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) +{ + return 0x00504614; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) +{ + return 0x00504624; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) +{ + return 0x00504634; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) +{ + return 0x00000000; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) +{ + return 0x00000000; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) { return 0x0050460c; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) +{ + return (r >> 0) & 0x1; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) { return (r >> 4) & 0x1; diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index 0982bc098..ab6f63736 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -74,6 +74,22 @@ static inline u32 top_num_fbps_value_v(u32 r) { return (r >> 0) & 0x1f; } +static inline u32 top_ltc_per_fbp_r(void) +{ + return 0x00022450; +} +static inline u32 top_ltc_per_fbp_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} +static inline u32 top_slices_per_ltc_r(void) +{ + return 0x0002245c; +} +static inline u32 top_slices_per_ltc_value_v(u32 r) +{ + return (r >> 0) & 0x1f; +} static inline u32 top_num_ltcs_r(void) { return 0x00022454; -- cgit v1.2.2 From c81ce0ad668172920e2179a58f4e2b4a90eac9a3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 27 Mar 2015 10:13:16 -0700 Subject: gpu: nvgpu: gp10b: Program stream id to LTC Program a constant stream id 31 to LTC. Bug 1610019 Change-Id: I9b5fb794b5ea8da0fba67a2376126d89e056f955 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/724348 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 8 ++++++++ drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 10 +++++++++- 2 files changed, 17 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 01b66c9cf..ea96a9aaa 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -514,4 +514,12 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) { return (r >> 16) & 0x1f; } +static inline u32 ltc_ltca_g_axi_pctrl_r(void) +{ + return 0x00160000; +} +static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) +{ + return (v & 0xff) << 2; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index dbeed474b..78c85f3e3 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -148,6 +148,14 @@ void gp10b_ltc_isr(struct gk20a *g) } } +void gp10b_ltc_init_fs_state(struct gk20a *g) +{ + gm20b_ltc_init_fs_state(g); + + gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), + ltc_ltca_g_axi_pctrl_user_sid_f(31)); +} + void gp10b_init_ltc(struct gpu_ops *gops) { gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; @@ -157,7 +165,7 @@ void gp10b_init_ltc(struct gpu_ops *gops) gops->ltc.init_cbc = gk20a_ltc_init_cbc; /* GM20b specific ops. */ - gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; + gops->ltc.init_fs_state = gp10b_ltc_init_fs_state; gops->ltc.init_comptags = gp10b_ltc_init_comptags; gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; -- cgit v1.2.2 From 8ce2af1eeb85a801163514c7ba47719b31da4982 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 30 Mar 2015 11:21:27 -0700 Subject: gpu: nvgpu: gp10b: Correct steady state CB size Program steady state CB size to be the HW default. Bug 1626065 Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/725106 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 1b7dd405d..f91ef1ba4 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -110,7 +110,7 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + proj_ppc_in_gpc_stride_v() * ppc_index, - gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index], + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(), patch); attrib_offset_in_chunk += gr->attrib_cb_size * diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 72f1d68c7..02674d6be 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -2174,6 +2174,14 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) { return 0x005030f0; } +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) +{ + return (v & 0x3fffff) << 0; +} +static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) +{ + return 0x00030000; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; -- cgit v1.2.2 From ca1e91529228d869b3673b5d4eb3317ea9ee7e87 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 31 Mar 2015 14:50:10 -0700 Subject: gpu: nvgpu: gp10b: Define compressible page size gp10b can compress 4k pages. Bug 1605769 Change-Id: I15cf4b9ead0fefdfc430cfc4919dcb16721f5cb2 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/725794 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/fb_gp10b.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c index bd1b7bf0c..3a143ceda 100644 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c @@ -92,10 +92,16 @@ static int gp10b_fb_compression_page_size(struct gk20a *g) return SZ_64K; } +static int gp10b_fb_compressible_page_size(struct gk20a *g) +{ + return SZ_4K; +} + void gp10b_init_fb(struct gpu_ops *gops) { gm20b_init_fb(gops); gops->fb.compression_page_size = gp10b_fb_compression_page_size; + gops->fb.compressible_page_size = gp10b_fb_compressible_page_size; gp10b_init_uncompressed_kind_map(); gp10b_init_kind_attr(); -- cgit v1.2.2 From 3c1f13428fba1afb94181a06bb4ce336d4b3c8c9 Mon Sep 17 00:00:00 2001 From: Alex Van Brunt Date: Mon, 6 Apr 2015 13:35:36 -0700 Subject: gpu: nvgpu: gp10b: Fix include path Remove the requirement that srcdir is called kernel. Change-Id: I9379ef530ac34009bd0461a29d65d6d707bc8014 Signed-off-by: Alex Van Brunt Reviewed-on: http://git-master/r/728153 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile | 4 ++-- drivers/gpu/nvgpu/gp10b/Makefile | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index c583f6d5b..f259eefa6 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,7 +1,7 @@ GCOV_PROFILE := y -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/include/linux +ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/include/linux ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include ccflags-$(CONFIG_GK20A) += -Wno-multichar ccflags-$(CONFIG_GK20A) += -Werror diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 9d0c0311e..a51ba15ea 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -1,7 +1,7 @@ GCOV_PROFILE := y -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/include ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi -- cgit v1.2.2 From 0ef7f249ee31307dcf261cc72d5cf4a749c6285e Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 6 Apr 2015 16:32:29 +0530 Subject: gpu: nvgpu: gp10b: fix sparse warnings of static symbol Fix sparse warnings of below type by making necessary symbols static: warning: symbol '' was not declared. Should it be static? Bug 200088648 Change-Id: Ic20ef3eb73dcbfe5f13506b5afa629c3e1db59d0 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/728012 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 4 ++-- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 8 ++++---- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 4 ++-- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c index d76b97a5e..b2d417b79 100644 --- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c @@ -44,7 +44,7 @@ static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) return ce2_intr_status_launcherr_pending_f(); } -void gp10b_ce2_isr(struct gk20a *g) +static void gp10b_ce2_isr(struct gk20a *g) { u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); u32 clear_intr = 0; @@ -62,7 +62,7 @@ void gp10b_ce2_isr(struct gk20a *g) return; } -void gp10b_ce2_nonstall_isr(struct gk20a *g) +static void gp10b_ce2_nonstall_isr(struct gk20a *g) { u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); u32 clear_intr = 0; diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f91ef1ba4..a2c981a02 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -24,7 +24,7 @@ #include "hw_proj_gp10b.h" #include "hw_ctxsw_prog_gp10b.h" -bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) +static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) { bool valid = false; @@ -50,7 +50,7 @@ bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) return valid; } -int gr_gp10b_commit_global_cb_manager(struct gk20a *g, +static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, struct channel_gk20a *c, bool patch) { struct gr_gk20a *gr = &g->gr; @@ -142,7 +142,7 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, return 0; } -void gr_gp10b_commit_global_pagepool(struct gk20a *g, +static void gr_gp10b_commit_global_pagepool(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, u64 addr, u32 size, bool patch) { @@ -457,7 +457,7 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g) return 0; } -int gr_gp10b_alloc_gr_ctx(struct gk20a *g, +static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, u32 class, u32 flags) diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index ff140a04e..315977537 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -37,7 +37,7 @@ #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" -struct gpu_ops gp10b_ops = { +static struct gpu_ops gp10b_ops = { .clock_gating = { .slcg_bus_load_gating_prod = gm20b_slcg_bus_load_gating_prod, diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 78c85f3e3..3c809eaf7 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -123,7 +123,7 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) return 0; } -void gp10b_ltc_isr(struct gk20a *g) +static void gp10b_ltc_isr(struct gk20a *g) { u32 mc_intr, ltc_intr; int ltc, slice; @@ -148,7 +148,7 @@ void gp10b_ltc_isr(struct gk20a *g) } } -void gp10b_ltc_init_fs_state(struct gk20a *g) +static void gp10b_ltc_init_fs_state(struct gk20a *g) { gm20b_ltc_init_fs_state(g); diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index c316aa9f9..e3e2c1734 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -21,7 +21,7 @@ #include "hw_ram_gp10b.h" #include "hw_bus_gp10b.h" -u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) +static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) { return 36; } -- cgit v1.2.2 From 051b467753456ab931dfcfc2872b3d9f2b94328e Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Wed, 1 Apr 2015 18:15:44 +0300 Subject: gpu: nvgpu: set zbc format field properly Add a missing bitmask for clearing existing bits before setting a new value, and shift the value the correct amount. Also format register needs to be rounded down. Bug 200087330 Change-Id: I39051be7eb68327fc010495f0c16c879447c8e4c Signed-off-by: Konsta Holtta Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/726265 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a2c981a02..4f7a037b2 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -203,9 +203,10 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]); gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]); gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); - zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4)); - zbc_c |= color_val->format << (index % 4) * 6; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); + zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); + zbc_c &= ~(0x7f << ((index % 4) * 7)); + zbc_c |= color_val->format << ((index % 4) * 7); + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); return 0; } @@ -240,9 +241,10 @@ static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, gr->zbc_dep_tbl[index].ref_cnt++; gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); - zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4)); - zbc_z |= depth_val->format << (index % 4) * 6; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); + zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); + zbc_z &= ~(0x7f << (index % 4) * 7); + zbc_z |= depth_val->format << (index % 4) * 7; + gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); return 0; } -- cgit v1.2.2 From 9e13f1846a3da68e87b20bd28e4274c8b2db4adf Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 29 Jan 2015 11:29:56 -0800 Subject: gpu: nvgpu: gp10b: Implement new page table format Implement the 5-level Pascal page table format. It is enabled only for simulation. Change-Id: I6767fac8b52fe0f6a2e2f86312de5fc93af6518e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/682114 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 168 +++++++++++++++++---------- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 197 ++++++++++++++++++++++++++++++++ 2 files changed, 303 insertions(+), 62 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 5a0f9fe27..fc65f57d4 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -50,163 +50,207 @@ #ifndef _hw_gmmu_gp10b_h_ #define _hw_gmmu_gp10b_h_ -static inline u32 gmmu_pde_aperture_big_w(void) +static inline u32 gmmu_new_pde_is_pte_w(void) { return 0; } -static inline u32 gmmu_pde_aperture_big_invalid_f(void) +static inline u32 gmmu_new_pde_is_pte_false_f(void) { return 0x0; } -static inline u32 gmmu_pde_aperture_big_video_memory_f(void) +static inline u32 gmmu_new_pde_aperture_w(void) { - return 0x1; + return 0; +} +static inline u32 gmmu_new_pde_aperture_invalid_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_aperture_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_pde_address_sys_f(u32 v) +{ + return (v & 0xffffff) << 8; +} +static inline u32 gmmu_new_pde_address_sys_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pde_vol_true_f(void) +{ + return 0x8; +} +static inline u32 gmmu_new_pde_vol_false_f(void) +{ + return 0x0; +} +static inline u32 gmmu_new_pde_address_shift_v(void) +{ + return 0x0000000c; +} +static inline u32 gmmu_new_pde__size_v(void) +{ + return 0x00000008; +} +static inline u32 gmmu_new_dual_pde_is_pte_w(void) +{ + return 0; +} +static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) +{ + return 0x0; } -static inline u32 gmmu_pde_size_w(void) +static inline u32 gmmu_new_dual_pde_aperture_big_w(void) { return 0; } -static inline u32 gmmu_pde_size_full_f(void) +static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) { return 0x0; } -static inline u32 gmmu_pde_address_big_sys_f(u32 v) +static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) +{ + return 0x2; +} +static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) { return (v & 0xfffffff) << 4; } -static inline u32 gmmu_pde_address_big_sys_w(void) +static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) { return 0; } -static inline u32 gmmu_pde_aperture_small_w(void) +static inline u32 gmmu_new_dual_pde_aperture_small_w(void) { - return 1; + return 2; } -static inline u32 gmmu_pde_aperture_small_invalid_f(void) +static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) { return 0x0; } -static inline u32 gmmu_pde_aperture_small_video_memory_f(void) +static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) { - return 0x1; + return 0x2; } -static inline u32 gmmu_pde_vol_small_w(void) +static inline u32 gmmu_new_dual_pde_vol_small_w(void) { - return 1; + return 2; } -static inline u32 gmmu_pde_vol_small_true_f(void) +static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) { - return 0x4; + return 0x8; } -static inline u32 gmmu_pde_vol_small_false_f(void) +static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) { return 0x0; } -static inline u32 gmmu_pde_vol_big_w(void) +static inline u32 gmmu_new_dual_pde_vol_big_w(void) { - return 1; + return 0; } -static inline u32 gmmu_pde_vol_big_true_f(void) +static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) { return 0x8; } -static inline u32 gmmu_pde_vol_big_false_f(void) +static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) { return 0x0; } -static inline u32 gmmu_pde_address_small_sys_f(u32 v) +static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xffffff) << 8; } -static inline u32 gmmu_pde_address_small_sys_w(void) +static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { - return 1; + return 2; } -static inline u32 gmmu_pde_address_shift_v(void) +static inline u32 gmmu_new_dual_pde_address_shift_v(void) { return 0x0000000c; } -static inline u32 gmmu_pde__size_v(void) +static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) { return 0x00000008; } -static inline u32 gmmu_pte__size_v(void) +static inline u32 gmmu_new_dual_pde__size_v(void) +{ + return 0x00000010; +} +static inline u32 gmmu_new_pte__size_v(void) { return 0x00000008; } -static inline u32 gmmu_pte_valid_w(void) +static inline u32 gmmu_new_pte_valid_w(void) { return 0; } -static inline u32 gmmu_pte_valid_true_f(void) +static inline u32 gmmu_new_pte_valid_true_f(void) { return 0x1; } -static inline u32 gmmu_pte_valid_false_f(void) +static inline u32 gmmu_new_pte_valid_false_f(void) { return 0x0; } -static inline u32 gmmu_pte_address_sys_f(u32 v) +static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xfffffff) << 4; + return (v & 0xffffff) << 8; } -static inline u32 gmmu_pte_address_sys_w(void) +static inline u32 gmmu_new_pte_address_sys_w(void) { return 0; } -static inline u32 gmmu_pte_vol_w(void) +static inline u32 gmmu_new_pte_vol_w(void) { - return 1; + return 0; } -static inline u32 gmmu_pte_vol_true_f(void) +static inline u32 gmmu_new_pte_vol_true_f(void) { - return 0x1; + return 0x8; } -static inline u32 gmmu_pte_vol_false_f(void) +static inline u32 gmmu_new_pte_vol_false_f(void) { return 0x0; } -static inline u32 gmmu_pte_aperture_w(void) +static inline u32 gmmu_new_pte_aperture_w(void) { - return 1; + return 0; } -static inline u32 gmmu_pte_aperture_video_memory_f(void) +static inline u32 gmmu_new_pte_aperture_video_memory_f(void) { return 0x0; } -static inline u32 gmmu_pte_read_only_w(void) +static inline u32 gmmu_new_pte_read_only_w(void) { return 0; } -static inline u32 gmmu_pte_read_only_true_f(void) +static inline u32 gmmu_new_pte_read_only_true_f(void) { - return 0x4; + return 0x40; } -static inline u32 gmmu_pte_write_disable_w(void) +static inline u32 gmmu_new_pte_comptagline_f(u32 v) { - return 1; + return (v & 0x3ffff) << 4; } -static inline u32 gmmu_pte_write_disable_true_f(void) -{ - return 0x80000000; -} -static inline u32 gmmu_pte_read_disable_w(void) +static inline u32 gmmu_new_pte_comptagline_w(void) { return 1; } -static inline u32 gmmu_pte_read_disable_true_f(void) -{ - return 0x40000000; -} -static inline u32 gmmu_pte_comptagline_f(u32 v) +static inline u32 gmmu_new_pte_kind_f(u32 v) { - return (v & 0x3ffff) << 12; + return (v & 0xff) << 24; } -static inline u32 gmmu_pte_comptagline_w(void) +static inline u32 gmmu_new_pte_kind_w(void) { return 1; } -static inline u32 gmmu_pte_address_shift_v(void) +static inline u32 gmmu_new_pte_address_shift_v(void) { return 0x0000000c; } diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index e3e2c1734..1608b176a 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -20,6 +20,8 @@ #include "rpfb_gp10b.h" #include "hw_ram_gp10b.h" #include "hw_bus_gp10b.h" +#include "hw_gmmu_gp10b.h" +#include "gk20a/semaphore_gk20a.h" static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) { @@ -138,6 +140,197 @@ static u64 gp10b_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); } +u32 *pde3_from_index(struct gk20a_mm_entry *entry, u32 i) +{ + return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_pde__size_v()); +} + +static int update_gmmu_pde3_locked(struct vm_gk20a *vm, + struct gk20a_mm_entry *parent, + u32 i, u32 gmmu_pgsz_idx, + u64 iova, + u32 kind_v, u32 *ctag, + bool cacheable, bool unmapped_pte, + int rw_flag, bool sparse, u32 flags) +{ + u64 pte_addr = 0; + u64 pde_addr = 0; + struct gk20a_mm_entry *pte = parent->entries + i; + u32 pde_v[2] = {0, 0}; + u32 *pde; + struct gk20a *g = vm->mm->g; + + gk20a_dbg_fn(""); + + pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0) + >> gmmu_new_pde_address_shift_v(); + pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0); + + pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); + pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); + + pde = pde3_from_index(parent, i); + + gk20a_mem_wr32(pde, 0, pde_v[0]); + gk20a_mem_wr32(pde, 1, pde_v[1]); + + gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d = 0x%x,0x%08x", + i, gmmu_pgsz_idx, pde_v[1], pde_v[0]); + gk20a_dbg_fn("done"); + return 0; +} + +u32 *pde0_from_index(struct gk20a_mm_entry *entry, u32 i) +{ + return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_dual_pde__size_v()); +} + +static int update_gmmu_pde0_locked(struct vm_gk20a *vm, + struct gk20a_mm_entry *pte, + u32 i, u32 gmmu_pgsz_idx, + u64 iova, + u32 kind_v, u32 *ctag, + bool cacheable, bool unmapped_pte, + int rw_flag, bool sparse, u32 flags) +{ + bool small_valid, big_valid; + u32 pte_addr_small = 0, pte_addr_big = 0; + struct gk20a_mm_entry *entry = pte->entries + i; + u32 pde_v[4] = {0, 0, 0, 0}; + u32 *pde; + struct gk20a *g = vm->mm->g; + + gk20a_dbg_fn(""); + + small_valid = entry->size && entry->pgsz == gmmu_page_size_small; + big_valid = entry->size && entry->pgsz == gmmu_page_size_big; + + if (small_valid) + pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) + >> gmmu_new_dual_pde_address_shift_v(); + + if (big_valid) + pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) + >> gmmu_new_dual_pde_address_big_shift_v(); + + if (small_valid) { + pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); + pde_v[2] |= gmmu_new_dual_pde_aperture_small_video_memory_f(); + pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); + } + + if (big_valid) { + pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); + pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); + pde_v[0] |= gmmu_new_dual_pde_aperture_big_video_memory_f(); + } + + pde = pde0_from_index(pte, i); + + gk20a_mem_wr32(pde, 0, pde_v[0]); + gk20a_mem_wr32(pde, 1, pde_v[1]); + gk20a_mem_wr32(pde, 2, pde_v[2]); + gk20a_mem_wr32(pde, 3, pde_v[3]); + + gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d [0x%08x, 0x%08x, 0x%x, 0x%08x]", + i, gmmu_pgsz_idx, pde_v[3], pde_v[2], pde_v[1], pde_v[0]); + gk20a_dbg_fn("done"); + return 0; +} + +static int update_gmmu_pte_locked(struct vm_gk20a *vm, + struct gk20a_mm_entry *pte, + u32 i, u32 gmmu_pgsz_idx, + u64 iova, + u32 kind_v, u32 *ctag, + bool cacheable, bool unmapped_pte, + int rw_flag, bool sparse, u32 flags) +{ + u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; + u32 pte_w[2] = {0, 0}; /* invalid pte */ + + gk20a_dbg_fn(""); + + if (iova) { + pte_w[0] = gmmu_new_pte_valid_true_f() | + gmmu_new_pte_address_sys_f(iova + >> gmmu_new_pte_address_shift_v()); + pte_w[1] = gmmu_new_pte_aperture_video_memory_f() | + gmmu_new_pte_kind_f(kind_v) | + gmmu_new_pte_comptagline_f(*ctag / SZ_128K); + + if (rw_flag == gk20a_mem_flag_read_only) + pte_w[0] |= gmmu_new_pte_read_only_true_f(); + if (!cacheable) + pte_w[1] |= gmmu_new_pte_vol_true_f(); + + gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d" + " ctag=%d vol=%d" + " [0x%08x, 0x%08x]", + i, iova, + kind_v, *ctag, !cacheable, + pte_w[1], pte_w[0]); + + if (*ctag) + *ctag += page_size; + } else if (sparse) { + pte_w[0] = gmmu_new_pte_valid_false_f(); + pte_w[1] |= gmmu_new_pte_vol_true_f(); + } else { + gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i); + } + + gk20a_mem_wr32(pte->cpu_va + i*8, 0, pte_w[0]); + gk20a_mem_wr32(pte->cpu_va + i*8, 1, pte_w[1]); + + gk20a_dbg_fn("done"); + return 0; +} + +const struct gk20a_mmu_level gp10b_mm_levels[] = { + {.hi_bit = {48, 48}, + .lo_bit = {47, 47}, + .update_entry = update_gmmu_pde3_locked, + .entry_size = 8}, + {.hi_bit = {46, 46}, + .lo_bit = {38, 38}, + .update_entry = update_gmmu_pde3_locked, + .entry_size = 8}, + {.hi_bit = {37, 37}, + .lo_bit = {29, 29}, + .update_entry = update_gmmu_pde3_locked, + .entry_size = 8}, + {.hi_bit = {28, 28}, + .lo_bit = {21, 21}, + .update_entry = update_gmmu_pde0_locked, + .entry_size = 16}, + {.hi_bit = {20, 20}, + .lo_bit = {12, 16}, + .update_entry = update_gmmu_pte_locked, + .entry_size = 8}, + {.update_entry = NULL} +}; + +const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size) +{ + return gp10b_mm_levels; +} + +static void gp10b_mm_init_pdb(struct gk20a *g, void *inst_ptr, u64 pdb_addr) +{ + u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); + u32 pdb_addr_hi = u64_hi32(pdb_addr); + + gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), + ram_in_page_dir_base_target_vid_mem_f() | + ram_in_page_dir_base_vol_true_f() | + ram_in_page_dir_base_lo_f(pdb_addr_lo) | + 1 << 10); + + gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(), + ram_in_page_dir_base_hi_f(pdb_addr_hi)); +} + void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); @@ -146,4 +339,8 @@ void gp10b_init_mm(struct gpu_ops *gops) gops->mm.init_bar2_vm = gb10b_init_bar2_vm; gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; gops->mm.get_iova_addr = gp10b_mm_iova_addr; + if (tegra_platform_is_linsim()) { + gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; + gops->mm.init_pdb = gp10b_mm_init_pdb; + } } -- cgit v1.2.2 From 4ac17631932908d7b5373bbc93cf3e8ce45c4462 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Thu, 16 Apr 2015 16:16:47 +0530 Subject: gpu: nvgpu: gp10b:inherit gm20b acr init wpr func -method gm20b_pmu_init_acr() used for gp10b acr init wpr region Bug 200085428 Change-Id: I897aa42b0a8ef7478d4b3f64fe1834532d35b303 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/732213 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Tested-by: Vijayakumar Subbu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 3db0d4c31..4ba0f997e 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B PMU * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -155,7 +155,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { gm20b_init_secure_pmu(gops); - gops->pmu.init_wpr_region = NULL; + gops->pmu.init_wpr_region = gm20b_pmu_init_acr; } else { gk20a_init_pmu_ops(gops); gops->pmu.init_wpr_region = NULL; -- cgit v1.2.2 From 372842cf5916b8afddd4f2082fcb55cd553c65f8 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Wed, 8 Apr 2015 23:06:11 +0530 Subject: gpu: nvgpu: secure boot flag, default disabled - set "privsecurity" to 1 to enable secure boot else set to 0. Bug 200085428 Change-Id: Ia4bf214f4a4bb2573c8869ea2182bbe680f67782 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/729101 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu Tested-by: Vijayakumar Subbu Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 315977537..914d8089b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -92,6 +92,8 @@ int gp10b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; *gops = gp10b_ops; + gops->privsecurity = 0; + gp10b_init_mc(gops); gp10b_init_gr(gops); gp10b_init_ltc(gops); -- cgit v1.2.2 From 009640c1ca0b8fe2e4ce62f6f56a2440f02e4c51 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 17 Apr 2015 11:43:40 +0530 Subject: gpu: nvgpu: gp10b: update elpg sequencing value - Added final elpg sequencing value - by default elpg is disabled. Bug 1525971 Change-Id: I2c306d9f03e361560a95fcfa723eafe14d004191 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/732574 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 201 ++++++++++++++++++------------------ 1 file changed, 101 insertions(+), 100 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 4ba0f997e..9ecf3964b 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -31,102 +31,103 @@ struct pg_init_sequence_list { }; /* PROD settings for ELPG sequencing registers*/ -static struct pg_init_sequence_list _pginitseq_gm20b[] = { - { 0x0010ab10, 0x8180}, - { 0x0010e118, 0x83828180}, - { 0x0010e068, 0}, - { 0x0010e06c, 0x00000080}, - { 0x0010e06c, 0x00000081}, - { 0x0010e06c, 0x00000082}, - { 0x0010e06c, 0x00000083}, - { 0x0010e06c, 0x00000084}, - { 0x0010e06c, 0x00000085}, - { 0x0010e06c, 0x00000086}, - { 0x0010e06c, 0x00000087}, - { 0x0010e06c, 0x00000088}, - { 0x0010e06c, 0x00000089}, - { 0x0010e06c, 0x0000008a}, - { 0x0010e06c, 0x0000008b}, - { 0x0010e06c, 0x0000008c}, - { 0x0010e06c, 0x0000008d}, - { 0x0010e06c, 0x0000008e}, - { 0x0010e06c, 0x0000008f}, - { 0x0010e06c, 0x00000090}, - { 0x0010e06c, 0x00000091}, - { 0x0010e06c, 0x00000092}, - { 0x0010e06c, 0x00000093}, - { 0x0010e06c, 0x00000094}, - { 0x0010e06c, 0x00000095}, - { 0x0010e06c, 0x00000096}, - { 0x0010e06c, 0x00000097}, - { 0x0010e06c, 0x00000098}, - { 0x0010e06c, 0x00000099}, - { 0x0010e06c, 0x0000009a}, - { 0x0010e06c, 0x0000009b}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010e06c, 0x00000000}, - { 0x0010ab14, 0x00000000}, - { 0x0010ab18, 0x00000000}, - { 0x0010e024, 0x00000000}, - { 0x0010e028, 0x00000000}, - { 0x0010e11c, 0x00000000}, - { 0x0010e120, 0x00000000}, - { 0x0010ab1c, 0x02010155}, - { 0x0010e020, 0x001b1b55}, - { 0x0010e124, 0x01030355}, - { 0x0010ab20, 0x89abcdef}, - { 0x0010ab24, 0x00000000}, - { 0x0010e02c, 0x89abcdef}, - { 0x0010e030, 0x00000000}, - { 0x0010e128, 0x89abcdef}, - { 0x0010e12c, 0x00000000}, - { 0x0010ab28, 0x74444444}, - { 0x0010ab2c, 0x70000000}, - { 0x0010e034, 0x74444444}, - { 0x0010e038, 0x70000000}, - { 0x0010e130, 0x74444444}, - { 0x0010e134, 0x70000000}, - { 0x0010ab30, 0x00000000}, - { 0x0010ab34, 0x00000001}, - { 0x00020004, 0x00000000}, - { 0x0010e138, 0x00000000}, - { 0x0010e040, 0x00000000}, +static struct pg_init_sequence_list _pginitseq_gp10b[] = { + {0x0010ab10, 0x0000868B} , + {0x0010e118, 0x8590848F} , + {0x0010e000, 0} , + {0x0010e06c, 0x000000A3} , + {0x0010e06c, 0x000000A0} , + {0x0010e06c, 0x00000095} , + {0x0010e06c, 0x000000A6} , + {0x0010e06c, 0x0000008C} , + {0x0010e06c, 0x00000080} , + {0x0010e06c, 0x00000081} , + {0x0010e06c, 0x00000087} , + {0x0010e06c, 0x00000088} , + {0x0010e06c, 0x0000008D} , + {0x0010e06c, 0x000000A00} , + {0x0010e06c, 0x000000A01} , + {0x0010e06c, 0x000000A02} , + {0x0010e06c, 0x000000A03} , + {0x0010e06c, 0x000000A04} , + {0x0010e06c, 0x000000A05} , + {0x0010e06c, 0x000000A06} , + {0x0010e06c, 0x000000A07} , + {0x0010e06c, 0x000000A08} , + {0x0010e06c, 0x000000A09} , + {0x0010e06c, 0x000000950} , + {0x0010e06c, 0x000000951} , + {0x0010e06c, 0x000000952} , + {0x0010e06c, 0x000000953} , + {0x0010e06c, 0x000000954} , + {0x0010e06c, 0x000000955} , + {0x0010e06c, 0x000000956} , + {0x0010e06c, 0x000000957} , + {0x0010ab14, 0x00000000} , + {0x0010e024, 0x00000000} , + {0x0010e028, 0x00000000} , + {0x0010e11c, 0x00000000} , + {0x0010ab1c, 0x140B0B55} , + {0x0010e020, 0x0E262655} , + {0x0010e124, 0x25101055} , + {0x0010ab20, 0x89abcdef} , + {0x0010ab24, 0x00000000} , + {0x0010e02c, 0x89abcdef} , + {0x0010e030, 0x00000000} , + {0x0010e128, 0x89abcdef} , + {0x0010e12c, 0x00000000} , + {0x0010ab28, 0x75555555} , + {0x0010ab2c, 0x70000000} , + {0x0010e034, 0x75555555} , + {0x0010e038, 0x70000000} , + {0x0010e130, 0x75555555} , + {0x0010e134, 0x70000000} , + {0x0010ab30, 0x00000000} , + {0x0010ab34, 0x00000001} , + {0x00020004, 0x00000000} , + {0x0010e138, 0x00000000} , + {0x0010e040, 0x00000000} , + {0x0010e168, 0x00000000} , + {0x0010e114, 0x0000A5A4} , + {0x0010e110, 0x00000000} , + {0x0010e10c, 0x8590848F} , + {0x0010e05c, 0x00000000} , + {0x0010e044, 0x00000000} , + {0x0010a644, 0x0000868B} , + {0x0010a648, 0x00000000 } , + {0x0010a64c, 0x00829493 } , + {0x0010a650, 0x00000000} , + {0x0010e000, 0} , + {0x0010e068, 0x000000A3} , + {0x0010e068, 0x000000A0} , + {0x0010e068, 0x00000095} , + {0x0010e068, 0x000000A6} , + {0x0010e068, 0x0000008C} , + {0x0010e068, 0x00000080} , + {0x0010e068, 0x00000081} , + {0x0010e068, 0x00000087} , + {0x0010e068, 0x00000088} , + {0x0010e068, 0x0000008D} , + {0x0010e068, 0x000000A00} , + {0x0010e068, 0x000000A01} , + {0x0010e068, 0x000000A02} , + {0x0010e068, 0x000000A03} , + {0x0010e068, 0x000000A04} , + {0x0010e068, 0x000000A05} , + {0x0010e068, 0x000000A06} , + {0x0010e068, 0x000000A07} , + {0x0010e068, 0x000000A08} , + {0x0010e068, 0x000000A09} , + {0x0010e068, 0x000000950} , + {0x0010e068, 0x000000951} , + {0x0010e068, 0x000000952} , + {0x0010e068, 0x000000953} , + {0x0010e068, 0x000000954} , + {0x0010e068, 0x000000955} , + {0x0010e068, 0x000000956} , + {0x0010e068, 0x000000957} , + {0x0010e000, 0} , + {0x0010e004, 0x0000008E}, }; static int gp10b_pmu_setup_elpg(struct gk20a *g) @@ -138,12 +139,12 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) gk20a_dbg_fn(""); if (g->elpg_enabled) { - reg_writes = ((sizeof(_pginitseq_gm20b) / - sizeof((_pginitseq_gm20b)[0]))); + reg_writes = ((sizeof(_pginitseq_gp10b) / + sizeof((_pginitseq_gp10b)[0]))); /* Initialize registers with production values*/ for (index = 0; index < reg_writes; index++) { - gk20a_writel(g, _pginitseq_gm20b[index].regaddr, - _pginitseq_gm20b[index].writeval); + gk20a_writel(g, _pginitseq_gp10b[index].regaddr, + _pginitseq_gp10b[index].writeval); } } -- cgit v1.2.2 From f9e7e87aea49c6da47a253e0b26b3bd719e963fb Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 22 Apr 2015 12:47:15 -0700 Subject: gpu: nvgpu: gp10b: Make page mapping scatter aware Augment new page mapping code to be aware of scattered buffers. Bug 1605769 Change-Id: Ifdb326563d28ccf07fc4d3d76a24492a68493fe3 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/734355 --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 49 +++++++++++++++++++++++++++++++------- 1 file changed, 40 insertions(+), 9 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 1608b176a..3633e9d97 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -148,7 +148,9 @@ u32 *pde3_from_index(struct gk20a_mm_entry *entry, u32 i) static int update_gmmu_pde3_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *parent, u32 i, u32 gmmu_pgsz_idx, - u64 iova, + struct scatterlist **sgl, + u64 *offset, + u64 *iova, u32 kind_v, u32 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, u32 flags) @@ -188,7 +190,9 @@ u32 *pde0_from_index(struct gk20a_mm_entry *entry, u32 i) static int update_gmmu_pde0_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *pte, u32 i, u32 gmmu_pgsz_idx, - u64 iova, + struct scatterlist **sgl, + u64 *offset, + u64 *iova, u32 kind_v, u32 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, u32 flags) @@ -241,7 +245,9 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, static int update_gmmu_pte_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *pte, u32 i, u32 gmmu_pgsz_idx, - u64 iova, + struct scatterlist **sgl, + u64 *offset, + u64 *iova, u32 kind_v, u32 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, u32 flags) @@ -251,23 +257,31 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, gk20a_dbg_fn(""); - if (iova) { - pte_w[0] = gmmu_new_pte_valid_true_f() | - gmmu_new_pte_address_sys_f(iova - >> gmmu_new_pte_address_shift_v()); + if (*iova) { + if (unmapped_pte) + pte_w[0] = gmmu_new_pte_valid_false_f() | + gmmu_new_pte_address_sys_f(*iova + >> gmmu_new_pte_address_shift_v()); + else + pte_w[0] = gmmu_new_pte_valid_true_f() | + gmmu_new_pte_address_sys_f(*iova + >> gmmu_new_pte_address_shift_v()); + pte_w[1] = gmmu_new_pte_aperture_video_memory_f() | gmmu_new_pte_kind_f(kind_v) | gmmu_new_pte_comptagline_f(*ctag / SZ_128K); if (rw_flag == gk20a_mem_flag_read_only) pte_w[0] |= gmmu_new_pte_read_only_true_f(); - if (!cacheable) + if (unmapped_pte && !cacheable) + pte_w[0] |= gmmu_new_pte_read_only_true_f(); + else if (!cacheable) pte_w[1] |= gmmu_new_pte_vol_true_f(); gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d" " ctag=%d vol=%d" " [0x%08x, 0x%08x]", - i, iova, + i, *iova, kind_v, *ctag, !cacheable, pte_w[1], pte_w[0]); @@ -283,6 +297,23 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, gk20a_mem_wr32(pte->cpu_va + i*8, 0, pte_w[0]); gk20a_mem_wr32(pte->cpu_va + i*8, 1, pte_w[1]); + if (*iova) { + *iova += page_size; + *offset += page_size; + if (*sgl && *offset + page_size > (*sgl)->length) { + u64 new_iova; + *sgl = sg_next(*sgl); + if (*sgl) { + new_iova = sg_phys(*sgl); + gk20a_dbg(gpu_dbg_pte, "chunk address %llx, size %d", + new_iova, (*sgl)->length); + if (new_iova) { + *offset = 0; + *iova = new_iova; + } + } + } + } gk20a_dbg_fn("done"); return 0; } -- cgit v1.2.2 From 616247cc2d69365f6fba1bc7dd3ae223c976825c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 27 Mar 2015 09:09:54 -0700 Subject: gpu: nvgpu: gp10b: Gating reglist Change-Id: I4931958c21692306d6c78bffdc45e21c553b913c Signed-off-by: Terje Bergstrom Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/731494 --- drivers/gpu/nvgpu/gp10b/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 621 +++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h | 87 ++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 47 +- 4 files changed, 732 insertions(+), 26 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c create mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index a51ba15ea..f25f7b342 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -20,6 +20,7 @@ obj-$(CONFIG_GK20A) += \ fb_gp10b.o \ pmu_gp10b.o \ hal_gp10b.o \ - rpfb_gp10b.o + rpfb_gp10b.o \ + gp10b_gating_reglist.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c new file mode 100644 index 000000000..f8ee80c33 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c @@ -0,0 +1,621 @@ +/* + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * This file is autogenerated. Do not edit. + */ + +#ifndef __gp10b_gating_reglist_h__ +#define __gp10b_gating_reglist_h__ + +#include +#include "gp10b_gating_reglist.h" + +struct gating_desc { + u32 addr; + u32 prod; + u32 disable; +}; +/* slcg bus */ +static const struct gating_desc gp10b_slcg_bus[] = { + {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, +}; + +/* slcg ce2 */ +static const struct gating_desc gp10b_slcg_ce2[] = { + {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, +}; + +/* slcg chiplet */ +static const struct gating_desc gp10b_slcg_chiplet[] = { + {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, + {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, +}; + +/* slcg fb */ +static const struct gating_desc gp10b_slcg_fb[] = { + {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, +}; + +/* slcg fifo */ +static const struct gating_desc gp10b_slcg_fifo[] = { + {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, +}; + +/* slcg gr */ +static const struct gating_desc gp10b_slcg_gr[] = { + {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x03fffffe}, + {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, + {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, + {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, + {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, + {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, + {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, + {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, + {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, + {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, + {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, + {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, + {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, + {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, + {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, + {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, + {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, + {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, + {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, + {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, + {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, + {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, + {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, + {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, + {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, + {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, + {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, +}; + +/* slcg ltc */ +static const struct gating_desc gp10b_slcg_ltc[] = { + {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, + {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, +}; + +/* slcg perf */ +static const struct gating_desc gp10b_slcg_perf[] = { + {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, + {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, +}; + +/* slcg PriRing */ +static const struct gating_desc gp10b_slcg_priring[] = { + {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, +}; + +/* slcg pwr_csb */ +static const struct gating_desc gp10b_slcg_pwr_csb[] = { + {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, + {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg pmu */ +static const struct gating_desc gp10b_slcg_pmu[] = { + {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, + {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* therm gr */ +static const struct gating_desc gp10b_slcg_therm[] = { + {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, +}; + +/* slcg Xbar */ +static const struct gating_desc gp10b_slcg_xbar[] = { + {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, + {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, +}; + +/* blcg bus */ +static const struct gating_desc gp10b_blcg_bus[] = { + {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* blcg ctxsw prog */ +static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { +}; + +/* blcg fb */ +static const struct gating_desc gp10b_blcg_fb[] = { + {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, + {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, +}; + +/* blcg fifo */ +static const struct gating_desc gp10b_blcg_fifo[] = { + {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg gr */ +static const struct gating_desc gp10b_blcg_gr[] = { + {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, + {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c141, .disable = 0x00000000}, + {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, + {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, + {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, + {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, + {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, + {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, + {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, + {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, + {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, + {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, + {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, + {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, + {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, + {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, +}; + +/* blcg ltc */ +static const struct gating_desc gp10b_blcg_ltc[] = { + {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, + {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, +}; + +/* blcg pwr_csb */ +static const struct gating_desc gp10b_blcg_pwr_csb[] = { + {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg pmu */ +static const struct gating_desc gp10b_blcg_pmu[] = { + {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, +}; + +/* blcg Xbar */ +static const struct gating_desc gp10b_blcg_xbar[] = { + {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, + {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, +}; + +/* pg gr */ +static const struct gating_desc gp10b_pg_gr[] = { +}; + +/* inline functions */ +void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_bus[i].addr, + gp10b_slcg_bus[i].prod); + else + gk20a_writel(g, gp10b_slcg_bus[i].addr, + gp10b_slcg_bus[i].disable); + } +} + +void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_ce2[i].addr, + gp10b_slcg_ce2[i].prod); + else + gk20a_writel(g, gp10b_slcg_ce2[i].addr, + gp10b_slcg_ce2[i].disable); + } +} + +void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_chiplet[i].addr, + gp10b_slcg_chiplet[i].prod); + else + gk20a_writel(g, gp10b_slcg_chiplet[i].addr, + gp10b_slcg_chiplet[i].disable); + } +} + +void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ +} + +void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_fb[i].addr, + gp10b_slcg_fb[i].prod); + else + gk20a_writel(g, gp10b_slcg_fb[i].addr, + gp10b_slcg_fb[i].disable); + } +} + +void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_fifo[i].addr, + gp10b_slcg_fifo[i].prod); + else + gk20a_writel(g, gp10b_slcg_fifo[i].addr, + gp10b_slcg_fifo[i].disable); + } +} + +void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_gr[i].addr, + gp10b_slcg_gr[i].prod); + else + gk20a_writel(g, gp10b_slcg_gr[i].addr, + gp10b_slcg_gr[i].disable); + } +} + +void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_ltc[i].addr, + gp10b_slcg_ltc[i].prod); + else + gk20a_writel(g, gp10b_slcg_ltc[i].addr, + gp10b_slcg_ltc[i].disable); + } +} + +void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_perf[i].addr, + gp10b_slcg_perf[i].prod); + else + gk20a_writel(g, gp10b_slcg_perf[i].addr, + gp10b_slcg_perf[i].disable); + } +} + +void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_priring[i].addr, + gp10b_slcg_priring[i].prod); + else + gk20a_writel(g, gp10b_slcg_priring[i].addr, + gp10b_slcg_priring[i].disable); + } +} + +void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, + gp10b_slcg_pwr_csb[i].prod); + else + gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, + gp10b_slcg_pwr_csb[i].disable); + } +} + +void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_pmu[i].addr, + gp10b_slcg_pmu[i].prod); + else + gk20a_writel(g, gp10b_slcg_pmu[i].addr, + gp10b_slcg_pmu[i].disable); + } +} + +void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_therm[i].addr, + gp10b_slcg_therm[i].prod); + else + gk20a_writel(g, gp10b_slcg_therm[i].addr, + gp10b_slcg_therm[i].disable); + } +} + +void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_slcg_xbar[i].addr, + gp10b_slcg_xbar[i].prod); + else + gk20a_writel(g, gp10b_slcg_xbar[i].addr, + gp10b_slcg_xbar[i].disable); + } +} + +void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_bus[i].addr, + gp10b_blcg_bus[i].prod); + else + gk20a_writel(g, gp10b_blcg_bus[i].addr, + gp10b_blcg_bus[i].disable); + } +} + +void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, + gp10b_blcg_ctxsw_prog[i].prod); + else + gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, + gp10b_blcg_ctxsw_prog[i].disable); + } +} + +void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_fb[i].addr, + gp10b_blcg_fb[i].prod); + else + gk20a_writel(g, gp10b_blcg_fb[i].addr, + gp10b_blcg_fb[i].disable); + } +} + +void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_fifo[i].addr, + gp10b_blcg_fifo[i].prod); + else + gk20a_writel(g, gp10b_blcg_fifo[i].addr, + gp10b_blcg_fifo[i].disable); + } +} + +void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_gr[i].addr, + gp10b_blcg_gr[i].prod); + else + gk20a_writel(g, gp10b_blcg_gr[i].addr, + gp10b_blcg_gr[i].disable); + } +} + +void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_ltc[i].addr, + gp10b_blcg_ltc[i].prod); + else + gk20a_writel(g, gp10b_blcg_ltc[i].addr, + gp10b_blcg_ltc[i].disable); + } +} + +void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, + gp10b_blcg_pwr_csb[i].prod); + else + gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, + gp10b_blcg_pwr_csb[i].disable); + } +} + +void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_pmu[i].addr, + gp10b_blcg_pmu[i].prod); + else + gk20a_writel(g, gp10b_blcg_pmu[i].addr, + gp10b_blcg_pmu[i].disable); + } +} + +void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_xbar[i].addr, + gp10b_blcg_xbar[i].prod); + else + gk20a_writel(g, gp10b_blcg_xbar[i].addr, + gp10b_blcg_xbar[i].disable); + } +} + +void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_pg_gr[i].addr, + gp10b_pg_gr[i].prod); + else + gk20a_writel(g, gp10b_pg_gr[i].addr, + gp10b_pg_gr[i].disable); + } +} + +#endif /* __gp10b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h new file mode 100644 index 000000000..465a0b4de --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2015, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "gk20a/gk20a.h" + +void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, + bool prod); + +void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, + bool prod); + +void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, + bool prod); + diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 914d8089b..9d099479e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -29,60 +29,57 @@ #include "gp10b/pmu_gp10b.h" #include "gp10b/gr_ctx_gp10b.h" #include "gp10b/fifo_gp10b.h" +#include "gp10b/gp10b_gating_reglist.h" #include "gm20b/gr_gm20b.h" -#include "gm20b/gm20b_gating_reglist.h" #include "gm20b/fifo_gm20b.h" -#include "gp10b/fifo_gp10b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" static struct gpu_ops gp10b_ops = { .clock_gating = { .slcg_bus_load_gating_prod = - gm20b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gm20b_slcg_ce2_load_gating_prod, + gp10b_slcg_bus_load_gating_prod, .slcg_chiplet_load_gating_prod = - gm20b_slcg_chiplet_load_gating_prod, + gp10b_slcg_chiplet_load_gating_prod, .slcg_ctxsw_firmware_load_gating_prod = - gm20b_slcg_ctxsw_firmware_load_gating_prod, + gp10b_slcg_ctxsw_firmware_load_gating_prod, .slcg_fb_load_gating_prod = - gm20b_slcg_fb_load_gating_prod, + gp10b_slcg_fb_load_gating_prod, .slcg_fifo_load_gating_prod = - gm20b_slcg_fifo_load_gating_prod, + gp10b_slcg_fifo_load_gating_prod, .slcg_gr_load_gating_prod = - gr_gm20b_slcg_gr_load_gating_prod, + gr_gp10b_slcg_gr_load_gating_prod, .slcg_ltc_load_gating_prod = - ltc_gm20b_slcg_ltc_load_gating_prod, + ltc_gp10b_slcg_ltc_load_gating_prod, .slcg_perf_load_gating_prod = - gm20b_slcg_perf_load_gating_prod, + gp10b_slcg_perf_load_gating_prod, .slcg_priring_load_gating_prod = - gm20b_slcg_priring_load_gating_prod, + gp10b_slcg_priring_load_gating_prod, .slcg_pmu_load_gating_prod = - gm20b_slcg_pmu_load_gating_prod, + gp10b_slcg_pmu_load_gating_prod, .slcg_therm_load_gating_prod = - gm20b_slcg_therm_load_gating_prod, + gp10b_slcg_therm_load_gating_prod, .slcg_xbar_load_gating_prod = - gm20b_slcg_xbar_load_gating_prod, + gp10b_slcg_xbar_load_gating_prod, .blcg_bus_load_gating_prod = - gm20b_blcg_bus_load_gating_prod, + gp10b_blcg_bus_load_gating_prod, .blcg_ctxsw_firmware_load_gating_prod = - gm20b_blcg_ctxsw_firmware_load_gating_prod, + gp10b_blcg_ctxsw_firmware_load_gating_prod, .blcg_fb_load_gating_prod = - gm20b_blcg_fb_load_gating_prod, + gp10b_blcg_fb_load_gating_prod, .blcg_fifo_load_gating_prod = - gm20b_blcg_fifo_load_gating_prod, + gp10b_blcg_fifo_load_gating_prod, .blcg_gr_load_gating_prod = - gm20b_blcg_gr_load_gating_prod, + gp10b_blcg_gr_load_gating_prod, .blcg_ltc_load_gating_prod = - gm20b_blcg_ltc_load_gating_prod, + gp10b_blcg_ltc_load_gating_prod, .blcg_pwr_csb_load_gating_prod = - gm20b_blcg_pwr_csb_load_gating_prod, + gp10b_blcg_pwr_csb_load_gating_prod, .blcg_pmu_load_gating_prod = - gm20b_blcg_pmu_load_gating_prod, + gp10b_blcg_pmu_load_gating_prod, .pg_gr_load_gating_prod = - gr_gm20b_pg_gr_load_gating_prod, + gr_gp10b_pg_gr_load_gating_prod, } }; -- cgit v1.2.2 From 4f127185e1e0804eee7ce08494d07f09d7546dee Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 15 Apr 2015 16:22:05 -0700 Subject: gpu: nvgpu: gp10b: Enable SMMU bypass Change-Id: I1fcc7e93d3e31bfbb5d540b43b655566f6dc13cd Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/732010 --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index ab98cbdec..58b55d4b3 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -49,6 +49,8 @@ static int gp10b_tegra_probe(struct platform_device *pdev) } platform->g->host1x_dev = host1x_pdev; + platform->bypass_smmu = !device_is_iommuable(&pdev->dev); + platform->disable_bigpage = platform->bypass_smmu; return 0; } -- cgit v1.2.2 From 02d581c0632c5c3063fa342bf7c19dc679651830 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 28 Apr 2015 14:07:05 +0530 Subject: gpu: nvgpu: gp10b: fix sparse warnings of static symbol Fix sparse warnings of below type by making necessary symbols static: warning: symbol '' was not declared. Should it be static? Bug 200088648 Change-Id: I222bebd958e29b3a95d161f05a3052389200fc10 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/736663 GVS: Gerrit_Virtual_Submit Reviewed-by: Amit Sharma (SW-TEGRA) Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 3633e9d97..b998ed4d7 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -140,7 +140,7 @@ static u64 gp10b_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); } -u32 *pde3_from_index(struct gk20a_mm_entry *entry, u32 i) +static u32 *pde3_from_index(struct gk20a_mm_entry *entry, u32 i) { return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_pde__size_v()); } @@ -182,7 +182,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, return 0; } -u32 *pde0_from_index(struct gk20a_mm_entry *entry, u32 i) +static u32 *pde0_from_index(struct gk20a_mm_entry *entry, u32 i) { return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_dual_pde__size_v()); } @@ -318,7 +318,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, return 0; } -const struct gk20a_mmu_level gp10b_mm_levels[] = { +static const struct gk20a_mmu_level gp10b_mm_levels[] = { {.hi_bit = {48, 48}, .lo_bit = {47, 47}, .update_entry = update_gmmu_pde3_locked, @@ -342,7 +342,8 @@ const struct gk20a_mmu_level gp10b_mm_levels[] = { {.update_entry = NULL} }; -const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, u32 big_page_size) +static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, + u32 big_page_size) { return gp10b_mm_levels; } -- cgit v1.2.2 From 9cff1591712ff97c936c957f99c2275d8cf6f0f7 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 23 Feb 2015 15:20:36 -0800 Subject: gpu: nvgpu: Implement syncpt protection Change-Id: I05b2554588e5e1001cdbb54551cf8a064ea531bd Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/711303 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Reviewed-by: Deepak Nibade --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 27 ++++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 26 +++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 4 ++++ 3 files changed, 55 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 59f7deefc..08f1c13c4 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -147,10 +147,35 @@ static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) | pbdma_signature_sw_zero_f(); } +static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) +{ + int syncpt_id; + void *inst_ptr; + + gk20a_dbg_fn(""); + + inst_ptr = c->inst_block.cpu_va; + if (c->sync) { + u32 v = pbdma_allowed_syncpoints_0_valid_f(1); + + syncpt_id = c->sync->syncpt_id(c->sync); + gk20a_dbg_info("Channel %d, syncpt id %d\n", + c->hw_chid, syncpt_id); + + v |= pbdma_allowed_syncpoints_0_index_f(syncpt_id); + + gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v); + } + + gk20a_dbg_fn("done"); + + return 0; +} + void gp10b_init_fifo(struct gpu_ops *gops) { gm20b_init_fifo(gops); gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; - + gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index 91429b47f..18db8595b 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -410,6 +410,10 @@ static inline u32 pbdma_intr_0_signature_pending_f(void) { return 0x80000000; } +static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) +{ + return 0x10000000; +} static inline u32 pbdma_intr_1_r(u32 i) { return 0x00040148 + i*8192; @@ -438,6 +442,26 @@ static inline u32 pbdma_udma_nop_r(void) { return 0x00000008; } +static inline u32 pbdma_allowed_syncpoints_r(u32 i) +{ + return 0x000400e8 + i*8192; +} +static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) +{ + return (v & 0x7fff) << 16; +} +static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) +{ + return (v & 0x1) << 15; +} +static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) +{ + return (v & 0x7fff) << 0; +} static inline u32 pbdma_syncpointa_r(u32 i) { return 0x000400a4 + i*8192; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h index dea53f966..863b15b85 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h @@ -342,6 +342,10 @@ static inline u32 ram_fc_formats_w(void) { return 39; } +static inline u32 ram_fc_allowed_syncpoints_w(void) +{ + return 58; +} static inline u32 ram_fc_syncpointa_w(void) { return 41; -- cgit v1.2.2 From 7a6afcba27971ad6ab0634075e8e0482cba3f7fb Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 20 Apr 2015 15:48:12 -0700 Subject: gpu: nvgpu: gp10b: Use betacb size from debugfs If betacb size has been given via debugfs, use that instead of the calculated number. Bug 1628352 Change-Id: I8c68c27a2bfdd7f013776734ef846377a89b0033 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/733332 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 4f7a037b2..96070df77 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -322,8 +322,9 @@ static void gr_gp10b_cb_size_default(struct gk20a *g) { struct gr_gk20a *gr = &g->gr; - gr->attrib_cb_default_size = - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); + if (!gr->attrib_cb_default_size) + gr->attrib_cb_default_size = + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); gr->alpha_cb_default_size = gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } -- cgit v1.2.2 From 8ed2961d992610b5a016d7c7c278d7fbd95adef7 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 24 Apr 2015 10:13:43 -0700 Subject: gpu: nvgpu: gp10b: Dynamic GfxP buffer size Calculate GFXP attrib cb buffer size from the global buffer size. Bug 1628352 Change-Id: If4edfbf5700334b791dbf8e5cf38fd0208ee7fa1 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/735717 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 96070df77..1b88112ec 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -476,17 +476,20 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (flags == NVGPU_GR_PREEMPTION_MODE_GFXP) { u32 spill_size = gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(); - u32 betacb_size = ALIGN( - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - g->gr.max_tpc_count) + - (g->gr.alpha_cb_size * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - g->gr.max_tpc_count), - 128); u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * gr_scc_pagepool_total_pages_byte_granularity_v(); - + u32 betacb_size = g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count; + attrib_cb_size = ALIGN(attrib_cb_size, 128); + + gk20a_dbg_info("gfxp context spill_size=%d", spill_size); + gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size); + gk20a_dbg_info("gfxp context attrib_cb_size=%d", + attrib_cb_size); err = gk20a_gmmu_alloc_map(vm, g->gr.t18x.ctx_vars.preempt_image_size, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); if (err) { -- cgit v1.2.2 From 966624468f02f8d778fd89981229809a0a0f0b22 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Apr 2015 13:30:28 -0700 Subject: gpu: nvgpu: gp10b: Fix caching attribute Fix caching attribute on 5-level page tables. Bug 1525976 Change-Id: I5c5bf336d87c642f42a387206a55a889e6e07ba6 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/737923 --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index b998ed4d7..1aba16c41 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -170,6 +170,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); + pde_v[0] |= gmmu_new_pde_vol_true_f(); pde = pde3_from_index(parent, i); @@ -259,24 +260,22 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, if (*iova) { if (unmapped_pte) - pte_w[0] = gmmu_new_pte_valid_false_f() | - gmmu_new_pte_address_sys_f(*iova - >> gmmu_new_pte_address_shift_v()); + pte_w[0] = gmmu_new_pte_valid_false_f(); else - pte_w[0] = gmmu_new_pte_valid_true_f() | - gmmu_new_pte_address_sys_f(*iova - >> gmmu_new_pte_address_shift_v()); + pte_w[0] = gmmu_new_pte_valid_true_f(); + pte_w[0] |= gmmu_new_pte_aperture_video_memory_f() | + gmmu_new_pte_address_sys_f(*iova + >> gmmu_new_pte_address_shift_v()); - pte_w[1] = gmmu_new_pte_aperture_video_memory_f() | - gmmu_new_pte_kind_f(kind_v) | - gmmu_new_pte_comptagline_f(*ctag / SZ_128K); + pte_w[1] = gmmu_new_pte_kind_f(kind_v) | + gmmu_new_pte_comptagline_f(*ctag / SZ_128K); if (rw_flag == gk20a_mem_flag_read_only) pte_w[0] |= gmmu_new_pte_read_only_true_f(); if (unmapped_pte && !cacheable) pte_w[0] |= gmmu_new_pte_read_only_true_f(); else if (!cacheable) - pte_w[1] |= gmmu_new_pte_vol_true_f(); + pte_w[0] |= gmmu_new_pte_vol_true_f(); gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d" " ctag=%d vol=%d" @@ -289,7 +288,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, *ctag += page_size; } else if (sparse) { pte_w[0] = gmmu_new_pte_valid_false_f(); - pte_w[1] |= gmmu_new_pte_vol_true_f(); + pte_w[0] |= gmmu_new_pte_vol_true_f(); } else { gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i); } -- cgit v1.2.2 From bb95d9f0979689016ceda0657f48dd24035619b3 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Apr 2015 14:28:13 -0700 Subject: gpu: nvgpu: gp10b: Enable new page table format Enable new page table format for all platforms. Bug 1525976 Change-Id: I9a3cfabdef7dc6ec33e18a8a4f32063c40f680fa Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/737364 --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 1aba16c41..9b347f00d 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -370,8 +370,6 @@ void gp10b_init_mm(struct gpu_ops *gops) gops->mm.init_bar2_vm = gb10b_init_bar2_vm; gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; gops->mm.get_iova_addr = gp10b_mm_iova_addr; - if (tegra_platform_is_linsim()) { - gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; - gops->mm.init_pdb = gp10b_mm_init_pdb; - } + gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; + gops->mm.init_pdb = gp10b_mm_init_pdb; } -- cgit v1.2.2 From db656810f590a21baa9a8d22e77d2e219c99b749 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Apr 2015 15:28:57 -0700 Subject: gpu: nvgpu: gp10b: Fix comptag index calculation Used 128k comptag spacing, when 64k is the correct one. Bug 1525976 Change-Id: Ie2f926929fa89cf715b86a57ffbf4dd1e4920473 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/737947 --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 9b347f00d..c651eeb9a 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -253,7 +253,9 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, u32 flags) { + struct gk20a *g = vm->mm->g; u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; + u32 ctag_granularity = g->ops.fb.compression_page_size(g); u32 pte_w[2] = {0, 0}; /* invalid pte */ gk20a_dbg_fn(""); @@ -268,7 +270,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, >> gmmu_new_pte_address_shift_v()); pte_w[1] = gmmu_new_pte_kind_f(kind_v) | - gmmu_new_pte_comptagline_f(*ctag / SZ_128K); + gmmu_new_pte_comptagline_f(*ctag / ctag_granularity); if (rw_flag == gk20a_mem_flag_read_only) pte_w[0] |= gmmu_new_pte_read_only_true_f(); @@ -281,7 +283,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, " ctag=%d vol=%d" " [0x%08x, 0x%08x]", i, *iova, - kind_v, *ctag, !cacheable, + kind_v, *ctag / ctag_granularity, !cacheable, pte_w[1], pte_w[0]); if (*ctag) -- cgit v1.2.2 From 4608151fb3a5f5dfddf16619c120de03eb22b6e9 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 30 Apr 2015 09:52:37 -0700 Subject: gpu: nvgpu: gp10b: Define VPR allocator VPR allocator needs to be used when allocating graphics context for VPR channels. Define it for gp10b. Bug 1625090 Change-Id: Ie2e3a865c310c34c629627891ac0b579f299983f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/737846 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 58b55d4b3..efecb1e36 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -26,6 +26,7 @@ #include #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" +#include "platform_tegra.h" static int gp10b_tegra_probe(struct platform_device *pdev) { @@ -103,4 +104,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .default_big_page_size = SZ_64K, .has_cde = true, + + .secure_alloc = gk20a_tegra_secure_alloc, + .secure_page_alloc = gk20a_tegra_secure_page_alloc, }; -- cgit v1.2.2 From 54fc7700919df3d1e0e91eb53071ae36ba764ca5 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Fri, 17 Apr 2015 09:49:50 +0530 Subject: gpu:nvgpu:gp10b: support secure gpccs changes bug 200080684 Change-Id: I5888939017877a50b9bd596393ee8ad1547c18e5 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/732535 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 9ecf3964b..b8b985b38 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -164,5 +164,4 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; - gops->pmu.fecsrecoveryinprogress = 0; } -- cgit v1.2.2 From 3a4f0285c7e9212b394b2c1b151987a7084de927 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Mon, 23 Mar 2015 16:26:14 -0700 Subject: gpu: nvgpu: gp10b part of new VA allocator The comptag allocator is made in the chip-specific init code for the comptags. Thus, a t18x change needs to be made to make sure the new allocator code compiles and works on t18x. Change-Id: I57a34f3c61ebd31f875caa577378e829812f2d4c Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/721171 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 3c809eaf7..68f4eafa1 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -16,6 +16,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" #include "hw_proj_gp10b.h" #include "hw_mc_gp10b.h" @@ -111,9 +112,8 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) if (err) return err; - gk20a_allocator_init(&gr->comp_tags, "comptag", - 1, /* start */ - max_comptag_lines - 1); /* length*/ + __gk20a_allocator_init(&gr->comp_tags, NULL, "comptag", + 1, max_comptag_lines - 1, 1, 10, 0); gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; -- cgit v1.2.2 From 30e5947fa1f26ed6bb4f137fd76c8869e91b9829 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 11 May 2015 19:27:34 -0700 Subject: Revert "gpu: nvgpu: gp10b part of new VA allocator" This reverts commit 3a4f0285c7e9212b394b2c1b151987a7084de927. Signed-off-by: Terje Bergstrom Change-Id: I886e434ce98e85f99b0a77749179e31c0bd00620 Reviewed-on: http://git-master/r/741468 Reviewed-by: Hiroshi Doyu Tested-by: Hiroshi Doyu --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 68f4eafa1..3c809eaf7 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -16,7 +16,6 @@ #include #include "gk20a/gk20a.h" -#include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" #include "hw_proj_gp10b.h" #include "hw_mc_gp10b.h" @@ -112,8 +111,9 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) if (err) return err; - __gk20a_allocator_init(&gr->comp_tags, NULL, "comptag", - 1, max_comptag_lines - 1, 1, 10, 0); + gk20a_allocator_init(&gr->comp_tags, "comptag", + 1, /* start */ + max_comptag_lines - 1); /* length*/ gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; -- cgit v1.2.2 From c6ec774e1041f5b53b2efb5aedb347de6c9a53d2 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Fri, 15 May 2015 09:16:58 -0700 Subject: Revert "Revert "gpu: nvgpu: gp10b part of new VA allocator"" This reverts commit 30e5947fa1f26ed6bb4f137fd76c8869e91b9829. The original commit was actually fine. Signed-off-by: Alex Waterman Change-Id: I0454415981d29ed0b877f7a21db6f54bc4c30470 Reviewed-on: http://git-master/r/743302 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 3c809eaf7..68f4eafa1 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -16,6 +16,7 @@ #include #include "gk20a/gk20a.h" +#include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" #include "hw_proj_gp10b.h" #include "hw_mc_gp10b.h" @@ -111,9 +112,8 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) if (err) return err; - gk20a_allocator_init(&gr->comp_tags, "comptag", - 1, /* start */ - max_comptag_lines - 1); /* length*/ + __gk20a_allocator_init(&gr->comp_tags, NULL, "comptag", + 1, max_comptag_lines - 1, 1, 10, 0); gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; -- cgit v1.2.2 From d2c1720e2c96a8beb65e27b843668a50cb7a7268 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 26 May 2015 16:12:19 -0700 Subject: gpu: nvgpu: gp10b: Fix PDE/PTE address handling We were dropping the part of address that span word bounary. The register generator does not know how to real with multi-word fields, to edit things in manually. Bug 1646531 Change-Id: I3ef06d6dfcb0a499ed45456d165fe60c91492250 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/747468 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 6 +++--- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 7 +++++-- 2 files changed, 8 insertions(+), 5 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index fc65f57d4..844cb1420 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -72,7 +72,7 @@ static inline u32 gmmu_new_pde_aperture_video_memory_f(void) } static inline u32 gmmu_new_pde_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_pde_address_sys_w(void) { @@ -164,7 +164,7 @@ static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) } static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) { @@ -200,7 +200,7 @@ static inline u32 gmmu_new_pte_valid_false_f(void) } static inline u32 gmmu_new_pte_address_sys_f(u32 v) { - return (v & 0xffffff) << 8; + return (v & 0xfffffff) << 8; } static inline u32 gmmu_new_pte_address_sys_w(void) { diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index c651eeb9a..bcdee9fc7 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -171,7 +171,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); pde_v[0] |= gmmu_new_pde_vol_true_f(); - + pde_v[1] |= pte_addr >> 24; pde = pde3_from_index(parent, i); gk20a_mem_wr32(pde, 0, pde_v[0]); @@ -222,12 +222,14 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); pde_v[2] |= gmmu_new_dual_pde_aperture_small_video_memory_f(); pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); + pde_v[3] |= pte_addr_small >> 24; } if (big_valid) { pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); pde_v[0] |= gmmu_new_dual_pde_aperture_big_video_memory_f(); + pde_v[1] |= pte_addr_big >> 28; } pde = pde0_from_index(pte, i); @@ -269,7 +271,8 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, gmmu_new_pte_address_sys_f(*iova >> gmmu_new_pte_address_shift_v()); - pte_w[1] = gmmu_new_pte_kind_f(kind_v) | + pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) | + gmmu_new_pte_kind_f(kind_v) | gmmu_new_pte_comptagline_f(*ctag / ctag_granularity); if (rw_flag == gk20a_mem_flag_read_only) -- cgit v1.2.2 From 03240399ab9b4eae7226860d6ca2414df8ea1245 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 21 May 2015 08:53:53 -0700 Subject: gpu: nvgpu: gp10b: Wait for preempted or empty ZBC is safe to update and GPU is safe to rail gate when units are in preempted or empty state. Idle may never be reached in case of graphics preemption, so relax the ZBC update wait condition. Bug 1640378 Change-Id: I40c59e9af22a7a30b777c6b9f87e69d130042e44 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/745655 Reviewed-by: Deepak Nibade Reviewed-by: Seshendra Gadagottu Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 66 +++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 24 +++++++++++++ 2 files changed, 90 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 1b88112ec..03462d5f2 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -14,6 +14,7 @@ */ #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ +#include #include "gk20a/gr_gk20a.h" @@ -23,6 +24,7 @@ #include "hw_fifo_gp10b.h" #include "hw_proj_gp10b.h" #include "hw_ctxsw_prog_gp10b.h" +#include "hw_mc_gp10b.h" static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -779,6 +781,69 @@ static int gr_gp10b_dump_gr_status_regs(struct gk20a *g, return 0; } +static bool gr_activity_empty_or_preempted(u32 val) +{ + while(val) { + u32 v = val & 7; + if (v != gr_activity_4_gpc0_empty_v() && + v != gr_activity_4_gpc0_preempted_v()) + return false; + val >>= 3; + } + + return true; +} + +static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long end_jiffies, + u32 expect_delay) +{ + u32 delay = expect_delay; + bool gr_enabled; + bool ctxsw_active; + bool gr_busy; + u32 gr_status; + u32 activity0, activity1, activity2, activity4; + + gk20a_dbg_fn(""); + + do { + /* fmodel: host gets fifo_engine_status(gr) from gr + only when gr_status is read */ + gr_status = gk20a_readl(g, gr_status_r()); + + gr_enabled = gk20a_readl(g, mc_enable_r()) & + mc_enable_pgraph_enabled_f(); + + ctxsw_active = gr_status & 1<<7; + + activity0 = gk20a_readl(g, gr_activity_0_r()); + activity1 = gk20a_readl(g, gr_activity_1_r()); + activity2 = gk20a_readl(g, gr_activity_2_r()); + activity4 = gk20a_readl(g, gr_activity_4_r()); + + gr_busy = !(gr_activity_empty_or_preempted(activity0) && + gr_activity_empty_or_preempted(activity1) && + activity2 == 0 && + gr_activity_empty_or_preempted(activity4)); + + if (!gr_enabled || (!gr_busy && !ctxsw_active)) { + gk20a_dbg_fn("done"); + return 0; + } + + usleep_range(delay, delay * 2); + delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); + + } while (time_before(jiffies, end_jiffies) + || !tegra_platform_is_silicon()); + + gk20a_err(dev_from_gk20a(g), + "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x", + ctxsw_active, gr_busy, activity0, activity1, activity2, activity4); + + return -EAGAIN; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -802,4 +867,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.update_ctxsw_preemption_mode = gr_gp10b_update_ctxsw_preemption_mode; gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs; + gops->gr.wait_empty = gr_gp10b_wait_empty; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 02674d6be..b185604e8 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -334,6 +334,30 @@ static inline u32 gr_activity_4_r(void) { return 0x00400390; } +static inline u32 gr_activity_4_gpc0_s(void) +{ + return 3; +} +static inline u32 gr_activity_4_gpc0_f(u32 v) +{ + return (v & 0x7) << 0; +} +static inline u32 gr_activity_4_gpc0_m(void) +{ + return 0x7 << 0; +} +static inline u32 gr_activity_4_gpc0_v(u32 r) +{ + return (r >> 0) & 0x7; +} +static inline u32 gr_activity_4_gpc0_empty_v(void) +{ + return 0x00000000; +} +static inline u32 gr_activity_4_gpc0_preempted_v(void) +{ + return 0x00000004; +} static inline u32 gr_pri_gpc0_gcc_dbg_r(void) { return 0x00501000; -- cgit v1.2.2 From 1be46046ac61ddc3a7c989e55bc13c1a7d99bda9 Mon Sep 17 00:00:00 2001 From: Leonid Moiseichuk Date: Wed, 27 May 2015 14:19:04 +0300 Subject: gpu: nvgpu: gp10b: add hwpm registers The produced wrappers for HW PM registers access which are required for cyclestats support for snapshot buffers mapping. See commit 589e7a9ffe2a5a70f8803a88fcf8429f553e2fba for tools:nvhost generators update. Bug 1573150 Bug 1517458 Change-Id: I9c9332a55f2282c0c626bc8ddbcfdce1289f778b Signed-off-by: Leonid Moiseichuk Reviewed-on: http://git-master/r/747717 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h | 205 ++++++++++++++++++++++++++++++++ 1 file changed, 205 insertions(+) create mode 100644 drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h new file mode 100644 index 000000000..ea1a61d27 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +/* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _o(void) : Returns the offset for element . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ +#ifndef _hw_perf_gp10b_h_ +#define _hw_perf_gp10b_h_ + +static inline u32 perf_pmasys_control_r(void) +{ + return 0x001b4000; +} +static inline u32 perf_pmasys_control_membuf_status_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) +{ + return 0x10; +} +static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) +{ + return (v & 0x1) << 5; +} +static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) +{ + return (r >> 5) & 0x1; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) +{ + return 0x20; +} +static inline u32 perf_pmasys_mem_block_r(void) +{ + return 0x001b4070; +} +static inline u32 perf_pmasys_mem_block_base_f(u32 v) +{ + return (v & 0xfffffff) << 0; +} +static inline u32 perf_pmasys_mem_block_target_f(u32 v) +{ + return (v & 0x3) << 28; +} +static inline u32 perf_pmasys_mem_block_target_v(u32 r) +{ + return (r >> 28) & 0x3; +} +static inline u32 perf_pmasys_mem_block_target_lfb_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_target_lfb_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) +{ + return 0x00000002; +} +static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) +{ + return 0x20000000; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) +{ + return 0x00000003; +} +static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) +{ + return 0x30000000; +} +static inline u32 perf_pmasys_mem_block_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 perf_pmasys_mem_block_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 perf_pmasys_mem_block_valid_true_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_mem_block_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_v(void) +{ + return 0x00000000; +} +static inline u32 perf_pmasys_mem_block_valid_false_f(void) +{ + return 0x0; +} +static inline u32 perf_pmasys_outbase_r(void) +{ + return 0x001b4074; +} +static inline u32 perf_pmasys_outbase_ptr_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_outbaseupper_r(void) +{ + return 0x001b4078; +} +static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 perf_pmasys_outsize_r(void) +{ + return 0x001b407c; +} +static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) +{ + return (v & 0x7ffffff) << 5; +} +static inline u32 perf_pmasys_mem_bytes_r(void) +{ + return 0x001b4084; +} +static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_mem_bump_r(void) +{ + return 0x001b4088; +} +static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) +{ + return (v & 0xfffffff) << 4; +} +static inline u32 perf_pmasys_enginestatus_r(void) +{ + return 0x001b40a4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) +{ + return (v & 0x1) << 4; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) +{ + return 0x00000001; +} +static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) +{ + return 0x10; +} +#endif -- cgit v1.2.2 From 2c520ab9ead069c4c5cdae31be2d162fb451776d Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 15 May 2015 12:32:48 -0700 Subject: gpu:nvgpu: gp10b: update channel_setup_ramfc Enable re-playable faults based on characteristics flags passed in channel_setup_ramfc. Bug 1645628 Change-Id: I7176efb3e5af9fefe5fb92cd5b49eb295e8e2c4a Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/743382 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 08f1c13c4..acf6f8290 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -78,7 +78,7 @@ static int channel_gp10b_commit_userd(struct channel_gk20a *c) } static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, - u64 gpfifo_base, u32 gpfifo_entries) + u64 gpfifo_base, u32 gpfifo_entries, u32 flags) { void *inst_ptr; @@ -133,7 +133,8 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, pbdma_runlist_timeslice_timescale_3_f() | pbdma_runlist_timeslice_enable_true_f()); - gp10b_set_pdb_fault_replay_flags(c->g, inst_ptr); + if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) + gp10b_set_pdb_fault_replay_flags(c->g, inst_ptr); gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); -- cgit v1.2.2 From 053037f1450d6ba6c5d01abcdcd9b24019ae8c85 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 2 Jun 2015 16:13:01 +0530 Subject: gpu: nvgpu: fix allocator_init() calls Change for new VA space allocator is being reverted with http://git-master/r/#/c/749291/ but only for Kernel3.18 In Kernel3.10, we support the new VA allocator Since we support both the kernel versions as of now, use a KERNEL_VERSION based mechanism to select appropriate call Define new macro NVGPU_USE_NEW_ALLOCATOR for Kernel3.10 where we want to use new allocator Bug 200106514 Change-Id: I9af26d555278c40e03fe82b0912961a862c8bf55 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/751353 Reviewed-by: Terje Bergstrom Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 7 +++++++ drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 8 ++++++++ 2 files changed, 15 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 68f4eafa1..9db18aa6c 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -15,6 +15,7 @@ #include +#include "gp10b/mm_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" @@ -112,8 +113,14 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) if (err) return err; +#if NVGPU_USE_NEW_ALLOCATOR __gk20a_allocator_init(&gr->comp_tags, NULL, "comptag", 1, max_comptag_lines - 1, 1, 10, 0); +#else + gk20a_allocator_init(&gr->comp_tags, "comptag", + 1, /* start */ + max_comptag_lines - 1); /* length*/ +#endif gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index 034944e05..f34200a04 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -14,8 +14,16 @@ #ifndef MM_GP10B_H #define MM_GP10B_H +#include + #define NVGPU_MM_GET_IO_COHERENCE_BIT 35 +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0) +#define NVGPU_USE_NEW_ALLOCATOR 1 +#else +#define NVGPU_USE_NEW_ALLOCATOR 0 +#endif + struct gpu_ops; void gp10b_init_mm(struct gpu_ops *gops); -- cgit v1.2.2 From 98652ff7b82c4a3bb4027ae5d852ef5b228e48e1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 13 Apr 2015 15:47:13 -0700 Subject: gpu: nvgpu: gp10b: Use correct PBDMA sig Change-Id: Ic71ff2408bd01a1bf5cf1354453a2fe715438cf0 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/751555 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index acf6f8290..d62f73162 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -99,7 +99,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); gk20a_mem_wr32(inst_ptr, ram_fc_signature_w(), - pbdma_signature_hw_valid_f() | pbdma_signature_sw_zero_f()); + c->g->ops.fifo.get_pbdma_signature(c->g)); gk20a_mem_wr32(inst_ptr, ram_fc_formats_w(), pbdma_formats_gp_fermi0_f() | -- cgit v1.2.2 From 5e720ce568394af23a766676b5647f69391038f4 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 29 May 2015 18:34:37 -0700 Subject: gpu: nvgpu: Expose preemption flags to user space Expose CILP and GFXP flags to user space ioctl NVGPU_IOCTL_CHANNEL_ALLOC_OBJ_CTX. Bug 200111328 Change-Id: I10931db2babd3222e308fd491824d95204355ff3 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/748932 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 03462d5f2..33a52db51 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -475,7 +475,7 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (err) return err; - if (flags == NVGPU_GR_PREEMPTION_MODE_GFXP) { + if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { u32 spill_size = gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(); u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * @@ -528,7 +528,7 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, } if (class == PASCAL_COMPUTE_A) { - if (flags == NVGPU_GR_PREEMPTION_MODE_CILP) + if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; else (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; -- cgit v1.2.2 From 9532651c8d84c16c2623fb994c10ad8b52425ad5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 1 Jun 2015 13:03:38 -0700 Subject: gpu: nvgpu: Disable channel when writing syncpt id Kick channel off PBDMA before writing new sync point id to allowed sync points. Bug 1648297 Bug 1646477 Change-Id: I7c686d474c403fdd54bc64cff63b7d049feecb4d Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/750981 --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index d62f73162..3a6c3c236 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -156,6 +156,13 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) gk20a_dbg_fn(""); inst_ptr = c->inst_block.cpu_va; + + /* disable channel */ + c->g->ops.fifo.disable_channel(c); + + /* preempt the channel */ + WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid)); + if (c->sync) { u32 v = pbdma_allowed_syncpoints_0_valid_f(1); @@ -166,8 +173,15 @@ static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) v |= pbdma_allowed_syncpoints_0_index_f(syncpt_id); gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v); + } else { + gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), 0); } + /* enable channel */ + gk20a_writel(c->g, ccsr_channel_r(c->hw_chid), + gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) | + ccsr_channel_enable_set_true_f()); + gk20a_dbg_fn("done"); return 0; -- cgit v1.2.2 From aa60ed1302d15b905f97179dab2d19dd1910d765 Mon Sep 17 00:00:00 2001 From: Bharat Nihalani Date: Thu, 4 Jun 2015 05:11:04 -0700 Subject: Revert "gpu: nvgpu: fix allocator_init() calls" This reverts commit 053037f1450d6ba6c5d01abcdcd9b24019ae8c85 since the issue seen with bug 200106514 is fixed with change http://git-master/r/#/c/752080/. Bug 200112195 Change-Id: If54eb570fd2ad5de99d180d03d5d90492283fe33 Signed-off-by: Bharat Nihalani Reviewed-on: http://git-master/r/752504 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 7 ------- drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 8 -------- 2 files changed, 15 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 9db18aa6c..68f4eafa1 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -15,7 +15,6 @@ #include -#include "gp10b/mm_gp10b.h" #include "gk20a/gk20a.h" #include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" @@ -113,14 +112,8 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) if (err) return err; -#if NVGPU_USE_NEW_ALLOCATOR __gk20a_allocator_init(&gr->comp_tags, NULL, "comptag", 1, max_comptag_lines - 1, 1, 10, 0); -#else - gk20a_allocator_init(&gr->comp_tags, "comptag", - 1, /* start */ - max_comptag_lines - 1); /* length*/ -#endif gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h index f34200a04..034944e05 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h @@ -14,16 +14,8 @@ #ifndef MM_GP10B_H #define MM_GP10B_H -#include - #define NVGPU_MM_GET_IO_COHERENCE_BIT 35 -#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0) -#define NVGPU_USE_NEW_ALLOCATOR 1 -#else -#define NVGPU_USE_NEW_ALLOCATOR 0 -#endif - struct gpu_ops; void gp10b_init_mm(struct gpu_ops *gops); -- cgit v1.2.2 From 6dab73431e354d6e3ac0763935806c6c7864ae9d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 5 Jun 2015 12:42:12 -0700 Subject: gpu: nvgpu: gp10b: Rewrite compbit backing store calc Compbit backing store did not take into account number of GOBS per comptagline per slice. Bug 1604102 Change-Id: I42666e72ea54697b6fbc7318e65a6a09d867f5b6 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/754706 GVS: Gerrit_Virtual_Submit Reviewed-by: Sami Kiminki --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 68f4eafa1..d6fca6e41 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -80,8 +80,11 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) max_comptag_lines = hw_max_comptag_lines; compbit_backing_size = - DIV_ROUND_UP(max_comptag_lines, comptags_per_cacheline) * - cacheline_size * slices_per_ltc * g->ltc_count; + roundup(max_comptag_lines * gobs_per_comptagline_per_slice, + cacheline_size); + compbit_backing_size = + roundup(compbit_backing_size * slices_per_ltc * g->ltc_count, + g->ops.fb.compressible_page_size(g)); /* aligned to 2KB * ltc_count */ compbit_backing_size += @@ -90,13 +93,6 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) /* must be a multiple of 64KB */ compbit_backing_size = roundup(compbit_backing_size, 64*1024); - max_comptag_lines = - (compbit_backing_size * comptags_per_cacheline) / - (cacheline_size * slices_per_ltc * g->ltc_count); - - if (max_comptag_lines > hw_max_comptag_lines) - max_comptag_lines = hw_max_comptag_lines; - gk20a_dbg_info("compbit backing store size : %d", compbit_backing_size); gk20a_dbg_info("max comptag lines : %d", -- cgit v1.2.2 From fd48fd737a837cd87a7bde021e9174f9783b711e Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 4 Jun 2015 10:28:18 -0700 Subject: gpu: nvgpu: gp10b: Use alpha+beta size for beta cb When allocating betacb for a GfxP channel, add both alpha and beta cb sizes together. Change-Id: I8cef62f6272bfb3b5e9a3835a51590e5eb91dc92 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/752633 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 33a52db51..240bab817 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -508,7 +508,7 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, goto fail_free_preempt; } - err = gk20a_gmmu_alloc_map(vm, betacb_size, + err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); if (err) { gk20a_err(dev_from_gk20a(vm->mm->g), -- cgit v1.2.2 From 8b4db2cdc09d3a43abe8312767068e880b0ff816 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 4 Jun 2015 09:17:50 -0700 Subject: gpu: nvgpu: gp10b: Program TEX RM registers Program CB base to new gp10b registers. Change-Id: I1ab39a487dade58d3a024fb1aba1af5c878f31bb Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/752634 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 29 +++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 52 +++++++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 240bab817..973653a0c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -844,6 +844,34 @@ static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long end_jiffies, return -EAGAIN; } +static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, bool patch) +{ + struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; + int attrBufferSize; + + if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) + attrBufferSize = gr_ctx->t18x.preempt_ctxsw_buffer.size; + else + attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); + + attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); + + gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(), + gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) | + gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(), + gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(), + gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) | + gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -855,6 +883,7 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size; gops->gr.calc_global_ctx_buffer_size = gr_gp10b_calc_global_ctx_buffer_size; + gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb; gops->gr.handle_sw_method = gr_gp10b_handle_sw_method; gops->gr.cb_size_default = gr_gp10b_cb_size_default; gops->gr.set_alpha_circular_buffer_size = diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index b185604e8..32903fbad 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -2206,6 +2206,58 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) { return 0x00030000; } +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) +{ + return 0x00419b00; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) +{ + return 0x00419b04; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) +{ + return 21; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) +{ + return (v & 0x1fffff) << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) +{ + return 0x1fffff << 0; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) +{ + return (r >> 0) & 0x1fffff; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) +{ + return 0x80; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) +{ + return 1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) +{ + return (v & 0x1) << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) +{ + return 0x1 << 31; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) +{ + return (r >> 31) & 0x1; +} +static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) +{ + return 0x80000000; +} static inline u32 gr_gpccs_falcon_addr_r(void) { return 0x0041a0ac; -- cgit v1.2.2 From 8a0d246886430999065b63c0b7ff777bf6320841 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 4 Jun 2015 09:17:50 -0700 Subject: gpu: nvgpu: gp10b: Pascal specific global bundle CB Some fields have different widths, so duplicate the code to program global bundle CB. Change-Id: Ib6af5abf3e90dfa1bcda2fbc6b97ad1031e6ab16 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/752635 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 973653a0c..c6f5022bd 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -872,6 +872,42 @@ static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); } +static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g, + struct channel_ctx_gk20a *ch_ctx, + u64 addr, u64 size, bool patch) +{ + u32 data; + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(), + gr_scc_bundle_cb_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(), + gr_scc_bundle_cb_size_div_256b_f(size) | + gr_scc_bundle_cb_size_valid_true_f(), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(), + gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(), + gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) | + gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch); + + /* data for state_limit */ + data = (g->gr.bundle_cb_default_size * + gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) / + gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(); + + data = min_t(u32, data, g->gr.min_gpm_fifo_depth); + + gk20a_dbg_info("bundle cb token limit : %d, state limit : %d", + g->gr.bundle_cb_token_limit, data); + + gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(), + gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) | + gr_pd_ab_dist_cfg2_state_limit_f(data), patch); + +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -884,6 +920,7 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.calc_global_ctx_buffer_size = gr_gp10b_calc_global_ctx_buffer_size; gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb; + gops->gr.commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb; gops->gr.handle_sw_method = gr_gp10b_handle_sw_method; gops->gr.cb_size_default = gr_gp10b_cb_size_default; gops->gr.set_alpha_circular_buffer_size = -- cgit v1.2.2 From c635424987cf7e390b74a380614353c92cc556b5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 4 Jun 2015 12:15:36 -0700 Subject: gpu: nvgpu: gp10b: Fix clipping of alpha/beta size Alpha and beta sizes need to be clipped to a maximum value. For alpha CB we were using beta size in clipping, and for both we were not using number of TPCs to determine the max value. Change-Id: I0c925464ba4c9f575e6e59dd5ba7759aa1cb6381 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/752667 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index c6f5022bd..045847b25 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -267,9 +267,9 @@ static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) + (gr->alpha_cb_default_size >> 1); gr->attrib_cb_size = min(gr->attrib_cb_size, - gr_gpc0_ppc0_cbm_beta_cb_size_v_f(0xffffffff)); - gr->alpha_cb_size = min(gr->attrib_cb_size, - gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(0xffffffff)); + gr_gpc0_ppc0_cbm_beta_cb_size_v_f(~0) / g->gr.tpc_count); + gr->alpha_cb_size = min(gr->alpha_cb_size, + gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(~0) / g->gr.tpc_count); size = gr->attrib_cb_size * gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * -- cgit v1.2.2 From 5611289c06e408ee2143e243563089737f1b5f8b Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 2 Jun 2015 20:04:18 -0700 Subject: gpu: nvgpu: gp10b: Set address check mode Set address check mode for SM. Bug 1625763 Change-Id: I5ddf8334673b414956e57c55aaa5be1a9f9aeaf1 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/752139 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 12 ++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 12 ++++++++++++ 2 files changed, 24 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 045847b25..265cad667 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -905,12 +905,24 @@ static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g, gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(), gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) | gr_pd_ab_dist_cfg2_state_limit_f(data), patch); +} + +static int gr_gp10b_init_fs_state(struct gk20a *g) +{ + u32 data; + + data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r()); + data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(), + gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); + gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); + return gr_gm20b_ctx_state_floorsweep(g); } void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); + gops->gr.init_fs_state = gr_gp10b_init_fs_state; gops->gr.is_valid_class = gr_gp10b_is_valid_class; gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 32903fbad..54d21eb3c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -3758,4 +3758,16 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) { return 0x0; } +static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) +{ + return 0x00419c84; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) +{ + return (v & 0x7) << 8; +} +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) +{ + return 0x100; +} #endif -- cgit v1.2.2 From c971b743a33be89b7c8a3b6244fa465285fecbc4 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 3 Jun 2015 15:53:12 -0700 Subject: gpu: nvgpu: gp10b: Disable RE suppression Bug 1642669 Change-Id: I683338256b7f2a165a7933aa59de510eb109ea6f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/755150 Reviewed-by: Automatic_Commit_Validation_User --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 5 +++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 16 ++++++++++++++++ 2 files changed, 21 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 265cad667..1942b1e70 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -916,6 +916,11 @@ static int gr_gp10b_init_fs_state(struct gk20a *g) gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); + data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); + data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(), + gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); + gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); + return gr_gm20b_ctx_state_floorsweep(g); } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 54d21eb3c..6e4f7d1ae 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -3766,8 +3766,24 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) { return (v & 0x7) << 8; } +static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) +{ + return 0x7 << 8; +} static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) { return 0x100; } +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) +{ + return 0x00419f78; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) +{ + return 0x3 << 11; +} +static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) +{ + return 0x1000; +} #endif -- cgit v1.2.2 From 36d2bfa24ae7cf540dd3638865ea5ff380a9adff Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 12 Jun 2015 08:42:27 -0700 Subject: gpu: nvgpu: gp10b: Lazy sync point update Update sync point protection field only when we have a valid sync point id, and the new id is different from old id. Bug 1653328 Change-Id: Ie07e26f8abd7c8239ad562603b62fda00164cbc7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/757102 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Deepak Nibade Reviewed-by: Konsta Holtta --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 27 +++++++++++++++------------ drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 4 ++++ 2 files changed, 19 insertions(+), 12 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 3a6c3c236..8c53978bd 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -150,31 +150,34 @@ static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) { - int syncpt_id; + u32 new_syncpt = 0, old_syncpt; void *inst_ptr; + u32 v; gk20a_dbg_fn(""); inst_ptr = c->inst_block.cpu_va; - /* disable channel */ - c->g->ops.fifo.disable_channel(c); + v = gk20a_mem_rd32(inst_ptr, ram_fc_allowed_syncpoints_w()); + old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); + if (c->sync) + new_syncpt = c->sync->syncpt_id(c->sync); - /* preempt the channel */ - WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid)); + if (new_syncpt && new_syncpt != old_syncpt) { + /* disable channel */ + c->g->ops.fifo.disable_channel(c); - if (c->sync) { - u32 v = pbdma_allowed_syncpoints_0_valid_f(1); + /* preempt the channel */ + WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid)); + + v = pbdma_allowed_syncpoints_0_valid_f(1); - syncpt_id = c->sync->syncpt_id(c->sync); gk20a_dbg_info("Channel %d, syncpt id %d\n", - c->hw_chid, syncpt_id); + c->hw_chid, new_syncpt); - v |= pbdma_allowed_syncpoints_0_index_f(syncpt_id); + v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v); - } else { - gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), 0); } /* enable channel */ diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index 18db8595b..977a8ee2f 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -454,6 +454,10 @@ static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) { return (v & 0x7fff) << 16; } +static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) +{ + return (r >> 16) & 0x7fff; +} static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) { return (v & 0x1) << 15; -- cgit v1.2.2 From e90f241a8e5ccd1e15bab640782bbb534a3ebed8 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 22 Jun 2015 12:42:23 -0700 Subject: gpu: nvgpu: gp10b: Do not set up gm20b clocks gm20b clock registers do not exist in gp10b. Skip setting the clock HAL to gm20b variants. Change-Id: Ieaa9a04a8afbe772864d947d968e3e1c7f9968e9 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/760854 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9d099479e..d50ad7910 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -100,7 +100,6 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_gr_ctx(gops); gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); - gm20b_init_clk_ops(gops); gk20a_init_debug_ops(gops); gops->name = "gp10b"; -- cgit v1.2.2 From 0caf257a34a0f48cbbbb681629ef56949ca2f259 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 22 Jun 2015 16:19:44 -0700 Subject: gpu: nvgpu: gp10b: Add regops whitelists Add regops whitelists for gp10b. The whitelist is generated, and is the same for context switched and global registers. Bug 1633363 Change-Id: I6d4d43d036d684c9f0d836a1a032f2c452604902 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/760935 --- drivers/gpu/nvgpu/gp10b/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 + drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 845 +++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/regops_gp10b.h | 24 + 4 files changed, 873 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gp10b/regops_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/regops_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index f25f7b342..688965da2 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -21,6 +21,7 @@ obj-$(CONFIG_GK20A) += \ pmu_gp10b.o \ hal_gp10b.o \ rpfb_gp10b.o \ - gp10b_gating_reglist.o + gp10b_gating_reglist.o \ + regops_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d50ad7910..9eba5571e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -30,6 +30,7 @@ #include "gp10b/gr_ctx_gp10b.h" #include "gp10b/fifo_gp10b.h" #include "gp10b/gp10b_gating_reglist.h" +#include "gp10b/regops_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -101,6 +102,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mm(gops); gp10b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); + gp10b_init_regops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c new file mode 100644 index 000000000..0ab80b78c --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c @@ -0,0 +1,845 @@ +/* + * Tegra GK20A GPU Debugger Driver Register Ops + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include + +#include "gk20a/gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" +#include "gk20a/regops_gk20a.h" +#include "regops_gp10b.h" + +static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { + { 0x000004f0, 1}, + { 0x00001a00, 3}, + { 0x00002800, 128}, + { 0x00009400, 1}, + { 0x00009410, 1}, + { 0x00009480, 1}, + { 0x00020200, 24}, + { 0x00021c00, 4}, + { 0x00021c14, 3}, + { 0x00021c24, 1}, + { 0x00021c2c, 69}, + { 0x00021d44, 1}, + { 0x00021d4c, 1}, + { 0x00021d54, 1}, + { 0x00021d5c, 1}, + { 0x00021d64, 2}, + { 0x00021d70, 16}, + { 0x00022430, 7}, + { 0x00022450, 1}, + { 0x0002245c, 1}, + { 0x00070000, 5}, + { 0x0008e00c, 1}, + { 0x00100c18, 3}, + { 0x00100c84, 1}, + { 0x0010a0a8, 1}, + { 0x0010a4f0, 1}, + { 0x0013cc14, 1}, + { 0x00140028, 1}, + { 0x00140280, 1}, + { 0x001402a0, 1}, + { 0x00140350, 1}, + { 0x00140480, 1}, + { 0x001404a0, 1}, + { 0x00140550, 1}, + { 0x00142028, 1}, + { 0x00142280, 1}, + { 0x001422a0, 1}, + { 0x00142350, 1}, + { 0x00142480, 1}, + { 0x001424a0, 1}, + { 0x00142550, 1}, + { 0x0017e280, 1}, + { 0x0017e294, 1}, + { 0x0017e29c, 2}, + { 0x0017e2ac, 1}, + { 0x0017e350, 1}, + { 0x0017e39c, 1}, + { 0x0017e480, 1}, + { 0x0017e4a0, 1}, + { 0x0017e550, 1}, + { 0x00180040, 41}, + { 0x001800ec, 9}, + { 0x00180240, 41}, + { 0x001802ec, 9}, + { 0x00180440, 41}, + { 0x001804ec, 9}, + { 0x00180640, 41}, + { 0x001806ec, 9}, + { 0x00180840, 41}, + { 0x001808ec, 9}, + { 0x00180a40, 41}, + { 0x00180aec, 9}, + { 0x00180c40, 41}, + { 0x00180cec, 9}, + { 0x00180e40, 41}, + { 0x00180eec, 9}, + { 0x001a0040, 41}, + { 0x001a00ec, 9}, + { 0x001a0240, 41}, + { 0x001a02ec, 9}, + { 0x001a0440, 41}, + { 0x001a04ec, 9}, + { 0x001a0640, 41}, + { 0x001a06ec, 9}, + { 0x001a0840, 41}, + { 0x001a08ec, 9}, + { 0x001a0a40, 41}, + { 0x001a0aec, 9}, + { 0x001a0c40, 41}, + { 0x001a0cec, 9}, + { 0x001a0e40, 41}, + { 0x001a0eec, 9}, + { 0x001b0040, 41}, + { 0x001b00ec, 9}, + { 0x001b0240, 41}, + { 0x001b02ec, 9}, + { 0x001b0440, 41}, + { 0x001b04ec, 9}, + { 0x001b0640, 41}, + { 0x001b06ec, 9}, + { 0x001b0840, 41}, + { 0x001b08ec, 9}, + { 0x001b0a40, 41}, + { 0x001b0aec, 9}, + { 0x001b0c40, 41}, + { 0x001b0cec, 9}, + { 0x001b0e40, 41}, + { 0x001b0eec, 9}, + { 0x001b4000, 1}, + { 0x001b4008, 1}, + { 0x001b4010, 3}, + { 0x001b4020, 3}, + { 0x001b4030, 3}, + { 0x001b4040, 3}, + { 0x001b4050, 3}, + { 0x001b4060, 4}, + { 0x001b4074, 7}, + { 0x001b4094, 3}, + { 0x001b40a4, 1}, + { 0x001b4100, 6}, + { 0x001b4124, 1}, + { 0x001b8000, 1}, + { 0x001b8008, 1}, + { 0x001b8010, 3}, + { 0x001bc000, 1}, + { 0x001bc008, 1}, + { 0x001bc010, 3}, + { 0x001be000, 1}, + { 0x001be008, 1}, + { 0x001be010, 3}, + { 0x00400500, 1}, + { 0x0040415c, 1}, + { 0x00404468, 1}, + { 0x00404498, 1}, + { 0x00405800, 1}, + { 0x00405840, 2}, + { 0x00405850, 1}, + { 0x00405908, 1}, + { 0x00405b40, 1}, + { 0x00405b50, 1}, + { 0x00406024, 5}, + { 0x00407010, 1}, + { 0x00407808, 1}, + { 0x0040803c, 1}, + { 0x00408804, 1}, + { 0x0040880c, 1}, + { 0x00408900, 2}, + { 0x00408910, 1}, + { 0x00408944, 1}, + { 0x00408984, 1}, + { 0x004090a8, 1}, + { 0x004098a0, 1}, + { 0x00409b00, 1}, + { 0x0041000c, 1}, + { 0x00410110, 1}, + { 0x00410184, 1}, + { 0x0041040c, 1}, + { 0x00410510, 1}, + { 0x00410584, 1}, + { 0x00418384, 1}, + { 0x00418400, 2}, + { 0x004184a0, 1}, + { 0x00418604, 1}, + { 0x00418680, 1}, + { 0x00418704, 1}, + { 0x00418714, 1}, + { 0x00418800, 1}, + { 0x0041881c, 1}, + { 0x00418830, 1}, + { 0x00418884, 1}, + { 0x004188b0, 1}, + { 0x004188c8, 3}, + { 0x004188fc, 1}, + { 0x00418b04, 1}, + { 0x00418c04, 1}, + { 0x00418c10, 8}, + { 0x00418c88, 1}, + { 0x00418d00, 1}, + { 0x00418e00, 1}, + { 0x00418e08, 1}, + { 0x00418e34, 1}, + { 0x00418e40, 4}, + { 0x00418e58, 16}, + { 0x00418f08, 1}, + { 0x00419000, 1}, + { 0x0041900c, 1}, + { 0x00419018, 1}, + { 0x00419854, 1}, + { 0x00419864, 1}, + { 0x00419a04, 2}, + { 0x00419a14, 1}, + { 0x00419ab0, 1}, + { 0x00419ab8, 3}, + { 0x00419c0c, 1}, + { 0x00419c8c, 2}, + { 0x00419d00, 1}, + { 0x00419d08, 2}, + { 0x00419e00, 11}, + { 0x00419e34, 2}, + { 0x00419e44, 11}, + { 0x00419e74, 10}, + { 0x00419ea4, 1}, + { 0x00419eac, 2}, + { 0x00419ee8, 1}, + { 0x00419ef0, 28}, + { 0x00419f70, 1}, + { 0x00419f78, 2}, + { 0x00419f98, 2}, + { 0x00419fdc, 1}, + { 0x0041a02c, 2}, + { 0x0041a0a0, 1}, + { 0x0041a0a8, 1}, + { 0x0041a890, 2}, + { 0x0041a8a0, 3}, + { 0x0041a8b0, 2}, + { 0x0041b014, 1}, + { 0x0041b0cc, 1}, + { 0x0041b1dc, 1}, + { 0x0041be0c, 3}, + { 0x0041becc, 1}, + { 0x0041bfdc, 1}, + { 0x0041c054, 1}, + { 0x0041c2b0, 1}, + { 0x0041c2b8, 3}, + { 0x0041c40c, 1}, + { 0x0041c48c, 2}, + { 0x0041c500, 1}, + { 0x0041c508, 2}, + { 0x0041c600, 11}, + { 0x0041c634, 2}, + { 0x0041c644, 11}, + { 0x0041c674, 10}, + { 0x0041c6a4, 1}, + { 0x0041c6ac, 2}, + { 0x0041c6e8, 1}, + { 0x0041c6f0, 28}, + { 0x0041c770, 1}, + { 0x0041c778, 2}, + { 0x0041c798, 2}, + { 0x0041c7dc, 1}, + { 0x0041c854, 1}, + { 0x0041cab0, 1}, + { 0x0041cab8, 3}, + { 0x0041cc0c, 1}, + { 0x0041cc8c, 2}, + { 0x0041cd00, 1}, + { 0x0041cd08, 2}, + { 0x0041ce00, 11}, + { 0x0041ce34, 2}, + { 0x0041ce44, 11}, + { 0x0041ce74, 10}, + { 0x0041cea4, 1}, + { 0x0041ceac, 2}, + { 0x0041cee8, 1}, + { 0x0041cef0, 28}, + { 0x0041cf70, 1}, + { 0x0041cf78, 2}, + { 0x0041cf98, 2}, + { 0x0041cfdc, 1}, + { 0x00500384, 1}, + { 0x005004a0, 1}, + { 0x00500604, 1}, + { 0x00500680, 1}, + { 0x00500714, 1}, + { 0x0050081c, 1}, + { 0x00500884, 1}, + { 0x005008b0, 1}, + { 0x005008c8, 3}, + { 0x005008fc, 1}, + { 0x00500b04, 1}, + { 0x00500c04, 1}, + { 0x00500c10, 8}, + { 0x00500c88, 1}, + { 0x00500d00, 1}, + { 0x00500e08, 1}, + { 0x00500f08, 1}, + { 0x00501000, 1}, + { 0x0050100c, 1}, + { 0x00501018, 1}, + { 0x00501854, 1}, + { 0x00501ab0, 1}, + { 0x00501ab8, 3}, + { 0x00501c0c, 1}, + { 0x00501c8c, 2}, + { 0x00501d00, 1}, + { 0x00501d08, 2}, + { 0x00501e00, 11}, + { 0x00501e34, 2}, + { 0x00501e44, 11}, + { 0x00501e74, 10}, + { 0x00501ea4, 1}, + { 0x00501eac, 2}, + { 0x00501ee8, 1}, + { 0x00501ef0, 28}, + { 0x00501f70, 1}, + { 0x00501f78, 2}, + { 0x00501f98, 2}, + { 0x00501fdc, 1}, + { 0x0050202c, 2}, + { 0x005020a0, 1}, + { 0x005020a8, 1}, + { 0x00502890, 2}, + { 0x005028a0, 3}, + { 0x005028b0, 2}, + { 0x00503014, 1}, + { 0x005030cc, 1}, + { 0x005031dc, 1}, + { 0x00503e14, 1}, + { 0x00503ecc, 1}, + { 0x00503fdc, 1}, + { 0x00504054, 1}, + { 0x005042b0, 1}, + { 0x005042b8, 3}, + { 0x0050440c, 1}, + { 0x0050448c, 2}, + { 0x00504500, 1}, + { 0x00504508, 2}, + { 0x00504600, 11}, + { 0x00504634, 2}, + { 0x00504644, 11}, + { 0x00504674, 10}, + { 0x005046a4, 1}, + { 0x005046ac, 2}, + { 0x005046e8, 1}, + { 0x005046f0, 28}, + { 0x00504770, 1}, + { 0x00504778, 2}, + { 0x00504798, 2}, + { 0x005047dc, 1}, + { 0x00504854, 1}, + { 0x00504ab0, 1}, + { 0x00504ab8, 3}, + { 0x00504c0c, 1}, + { 0x00504c8c, 2}, + { 0x00504d00, 1}, + { 0x00504d08, 2}, + { 0x00504e00, 11}, + { 0x00504e34, 2}, + { 0x00504e44, 11}, + { 0x00504e74, 10}, + { 0x00504ea4, 1}, + { 0x00504eac, 2}, + { 0x00504ee8, 1}, + { 0x00504ef0, 28}, + { 0x00504f70, 1}, + { 0x00504f78, 2}, + { 0x00504f98, 2}, + { 0x00504fdc, 1}, + { 0x00900100, 1}, + { 0x009a0100, 1}, +}; +static const u32 gp10b_global_whitelist_ranges_count = + ARRAY_SIZE(gp10b_global_whitelist_ranges); + +/* context */ + +static const struct regop_offset_range gp10b_context_whitelist_ranges[] = { + { 0x000004f0, 1}, + { 0x00001a00, 3}, + { 0x00002800, 128}, + { 0x00009400, 1}, + { 0x00009410, 1}, + { 0x00009480, 1}, + { 0x00020200, 24}, + { 0x00021c00, 4}, + { 0x00021c14, 3}, + { 0x00021c24, 1}, + { 0x00021c2c, 69}, + { 0x00021d44, 1}, + { 0x00021d4c, 1}, + { 0x00021d54, 1}, + { 0x00021d5c, 1}, + { 0x00021d64, 2}, + { 0x00021d70, 16}, + { 0x00022430, 7}, + { 0x00022450, 1}, + { 0x0002245c, 1}, + { 0x00070000, 5}, + { 0x0008e00c, 1}, + { 0x00100c18, 3}, + { 0x00100c84, 1}, + { 0x0010a0a8, 1}, + { 0x0010a4f0, 1}, + { 0x0013cc14, 1}, + { 0x00140028, 1}, + { 0x00140280, 1}, + { 0x001402a0, 1}, + { 0x00140350, 1}, + { 0x00140480, 1}, + { 0x001404a0, 1}, + { 0x00140550, 1}, + { 0x00142028, 1}, + { 0x00142280, 1}, + { 0x001422a0, 1}, + { 0x00142350, 1}, + { 0x00142480, 1}, + { 0x001424a0, 1}, + { 0x00142550, 1}, + { 0x0017e280, 1}, + { 0x0017e294, 1}, + { 0x0017e29c, 2}, + { 0x0017e2ac, 1}, + { 0x0017e350, 1}, + { 0x0017e39c, 1}, + { 0x0017e480, 1}, + { 0x0017e4a0, 1}, + { 0x0017e550, 1}, + { 0x00180040, 41}, + { 0x001800ec, 9}, + { 0x00180240, 41}, + { 0x001802ec, 9}, + { 0x00180440, 41}, + { 0x001804ec, 9}, + { 0x00180640, 41}, + { 0x001806ec, 9}, + { 0x00180840, 41}, + { 0x001808ec, 9}, + { 0x00180a40, 41}, + { 0x00180aec, 9}, + { 0x00180c40, 41}, + { 0x00180cec, 9}, + { 0x00180e40, 41}, + { 0x00180eec, 9}, + { 0x001a0040, 41}, + { 0x001a00ec, 9}, + { 0x001a0240, 41}, + { 0x001a02ec, 9}, + { 0x001a0440, 41}, + { 0x001a04ec, 9}, + { 0x001a0640, 41}, + { 0x001a06ec, 9}, + { 0x001a0840, 41}, + { 0x001a08ec, 9}, + { 0x001a0a40, 41}, + { 0x001a0aec, 9}, + { 0x001a0c40, 41}, + { 0x001a0cec, 9}, + { 0x001a0e40, 41}, + { 0x001a0eec, 9}, + { 0x001b0040, 41}, + { 0x001b00ec, 9}, + { 0x001b0240, 41}, + { 0x001b02ec, 9}, + { 0x001b0440, 41}, + { 0x001b04ec, 9}, + { 0x001b0640, 41}, + { 0x001b06ec, 9}, + { 0x001b0840, 41}, + { 0x001b08ec, 9}, + { 0x001b0a40, 41}, + { 0x001b0aec, 9}, + { 0x001b0c40, 41}, + { 0x001b0cec, 9}, + { 0x001b0e40, 41}, + { 0x001b0eec, 9}, + { 0x001b4000, 1}, + { 0x001b4008, 1}, + { 0x001b4010, 3}, + { 0x001b4020, 3}, + { 0x001b4030, 3}, + { 0x001b4040, 3}, + { 0x001b4050, 3}, + { 0x001b4060, 4}, + { 0x001b4074, 7}, + { 0x001b4094, 3}, + { 0x001b40a4, 1}, + { 0x001b4100, 6}, + { 0x001b4124, 1}, + { 0x001b8000, 1}, + { 0x001b8008, 1}, + { 0x001b8010, 3}, + { 0x001bc000, 1}, + { 0x001bc008, 1}, + { 0x001bc010, 3}, + { 0x001be000, 1}, + { 0x001be008, 1}, + { 0x001be010, 3}, + { 0x00400500, 1}, + { 0x0040415c, 1}, + { 0x00404468, 1}, + { 0x00404498, 1}, + { 0x00405800, 1}, + { 0x00405840, 2}, + { 0x00405850, 1}, + { 0x00405908, 1}, + { 0x00405b40, 1}, + { 0x00405b50, 1}, + { 0x00406024, 5}, + { 0x00407010, 1}, + { 0x00407808, 1}, + { 0x0040803c, 1}, + { 0x00408804, 1}, + { 0x0040880c, 1}, + { 0x00408900, 2}, + { 0x00408910, 1}, + { 0x00408944, 1}, + { 0x00408984, 1}, + { 0x004090a8, 1}, + { 0x004098a0, 1}, + { 0x00409b00, 1}, + { 0x0041000c, 1}, + { 0x00410110, 1}, + { 0x00410184, 1}, + { 0x0041040c, 1}, + { 0x00410510, 1}, + { 0x00410584, 1}, + { 0x00418384, 1}, + { 0x00418400, 2}, + { 0x004184a0, 1}, + { 0x00418604, 1}, + { 0x00418680, 1}, + { 0x00418704, 1}, + { 0x00418714, 1}, + { 0x00418800, 1}, + { 0x0041881c, 1}, + { 0x00418830, 1}, + { 0x00418884, 1}, + { 0x004188b0, 1}, + { 0x004188c8, 3}, + { 0x004188fc, 1}, + { 0x00418b04, 1}, + { 0x00418c04, 1}, + { 0x00418c10, 8}, + { 0x00418c88, 1}, + { 0x00418d00, 1}, + { 0x00418e00, 1}, + { 0x00418e08, 1}, + { 0x00418e34, 1}, + { 0x00418e40, 4}, + { 0x00418e58, 16}, + { 0x00418f08, 1}, + { 0x00419000, 1}, + { 0x0041900c, 1}, + { 0x00419018, 1}, + { 0x00419854, 1}, + { 0x00419864, 1}, + { 0x00419a04, 2}, + { 0x00419a14, 1}, + { 0x00419ab0, 1}, + { 0x00419ab8, 3}, + { 0x00419c0c, 1}, + { 0x00419c8c, 2}, + { 0x00419d00, 1}, + { 0x00419d08, 2}, + { 0x00419e00, 11}, + { 0x00419e34, 2}, + { 0x00419e44, 11}, + { 0x00419e74, 10}, + { 0x00419ea4, 1}, + { 0x00419eac, 2}, + { 0x00419ee8, 1}, + { 0x00419ef0, 28}, + { 0x00419f70, 1}, + { 0x00419f78, 2}, + { 0x00419f98, 2}, + { 0x00419fdc, 1}, + { 0x0041a02c, 2}, + { 0x0041a0a0, 1}, + { 0x0041a0a8, 1}, + { 0x0041a890, 2}, + { 0x0041a8a0, 3}, + { 0x0041a8b0, 2}, + { 0x0041b014, 1}, + { 0x0041b0cc, 1}, + { 0x0041b1dc, 1}, + { 0x0041be0c, 3}, + { 0x0041becc, 1}, + { 0x0041bfdc, 1}, + { 0x0041c054, 1}, + { 0x0041c2b0, 1}, + { 0x0041c2b8, 3}, + { 0x0041c40c, 1}, + { 0x0041c48c, 2}, + { 0x0041c500, 1}, + { 0x0041c508, 2}, + { 0x0041c600, 11}, + { 0x0041c634, 2}, + { 0x0041c644, 11}, + { 0x0041c674, 10}, + { 0x0041c6a4, 1}, + { 0x0041c6ac, 2}, + { 0x0041c6e8, 1}, + { 0x0041c6f0, 28}, + { 0x0041c770, 1}, + { 0x0041c778, 2}, + { 0x0041c798, 2}, + { 0x0041c7dc, 1}, + { 0x0041c854, 1}, + { 0x0041cab0, 1}, + { 0x0041cab8, 3}, + { 0x0041cc0c, 1}, + { 0x0041cc8c, 2}, + { 0x0041cd00, 1}, + { 0x0041cd08, 2}, + { 0x0041ce00, 11}, + { 0x0041ce34, 2}, + { 0x0041ce44, 11}, + { 0x0041ce74, 10}, + { 0x0041cea4, 1}, + { 0x0041ceac, 2}, + { 0x0041cee8, 1}, + { 0x0041cef0, 28}, + { 0x0041cf70, 1}, + { 0x0041cf78, 2}, + { 0x0041cf98, 2}, + { 0x0041cfdc, 1}, + { 0x00500384, 1}, + { 0x005004a0, 1}, + { 0x00500604, 1}, + { 0x00500680, 1}, + { 0x00500714, 1}, + { 0x0050081c, 1}, + { 0x00500884, 1}, + { 0x005008b0, 1}, + { 0x005008c8, 3}, + { 0x005008fc, 1}, + { 0x00500b04, 1}, + { 0x00500c04, 1}, + { 0x00500c10, 8}, + { 0x00500c88, 1}, + { 0x00500d00, 1}, + { 0x00500e08, 1}, + { 0x00500f08, 1}, + { 0x00501000, 1}, + { 0x0050100c, 1}, + { 0x00501018, 1}, + { 0x00501854, 1}, + { 0x00501ab0, 1}, + { 0x00501ab8, 3}, + { 0x00501c0c, 1}, + { 0x00501c8c, 2}, + { 0x00501d00, 1}, + { 0x00501d08, 2}, + { 0x00501e00, 11}, + { 0x00501e34, 2}, + { 0x00501e44, 11}, + { 0x00501e74, 10}, + { 0x00501ea4, 1}, + { 0x00501eac, 2}, + { 0x00501ee8, 1}, + { 0x00501ef0, 28}, + { 0x00501f70, 1}, + { 0x00501f78, 2}, + { 0x00501f98, 2}, + { 0x00501fdc, 1}, + { 0x0050202c, 2}, + { 0x005020a0, 1}, + { 0x005020a8, 1}, + { 0x00502890, 2}, + { 0x005028a0, 3}, + { 0x005028b0, 2}, + { 0x00503014, 1}, + { 0x005030cc, 1}, + { 0x005031dc, 1}, + { 0x00503e14, 1}, + { 0x00503ecc, 1}, + { 0x00503fdc, 1}, + { 0x00504054, 1}, + { 0x005042b0, 1}, + { 0x005042b8, 3}, + { 0x0050440c, 1}, + { 0x0050448c, 2}, + { 0x00504500, 1}, + { 0x00504508, 2}, + { 0x00504600, 11}, + { 0x00504634, 2}, + { 0x00504644, 11}, + { 0x00504674, 10}, + { 0x005046a4, 1}, + { 0x005046ac, 2}, + { 0x005046e8, 1}, + { 0x005046f0, 28}, + { 0x00504770, 1}, + { 0x00504778, 2}, + { 0x00504798, 2}, + { 0x005047dc, 1}, + { 0x00504854, 1}, + { 0x00504ab0, 1}, + { 0x00504ab8, 3}, + { 0x00504c0c, 1}, + { 0x00504c8c, 2}, + { 0x00504d00, 1}, + { 0x00504d08, 2}, + { 0x00504e00, 11}, + { 0x00504e34, 2}, + { 0x00504e44, 11}, + { 0x00504e74, 10}, + { 0x00504ea4, 1}, + { 0x00504eac, 2}, + { 0x00504ee8, 1}, + { 0x00504ef0, 28}, + { 0x00504f70, 1}, + { 0x00504f78, 2}, + { 0x00504f98, 2}, + { 0x00504fdc, 1}, + { 0x00900100, 1}, + { 0x009a0100, 1}, +}; +static const u32 gp10b_context_whitelist_ranges_count = + ARRAY_SIZE(gp10b_context_whitelist_ranges); + +/* runcontrol */ +static const u32 gp10b_runcontrol_whitelist[] = { +}; +static const u32 gp10b_runcontrol_whitelist_count = + ARRAY_SIZE(gp10b_runcontrol_whitelist); + +static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { +}; +static const u32 gp10b_runcontrol_whitelist_ranges_count = + ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); + + +/* quad ctl */ +static const u32 gp10b_qctl_whitelist[] = { +}; +static const u32 gp10b_qctl_whitelist_count = + ARRAY_SIZE(gp10b_qctl_whitelist); + +static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { +}; +static const u32 gp10b_qctl_whitelist_ranges_count = + ARRAY_SIZE(gp10b_qctl_whitelist_ranges); + +static const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) +{ + return gp10b_global_whitelist_ranges; +} + +static int gp10b_get_global_whitelist_ranges_count(void) +{ + return gp10b_global_whitelist_ranges_count; +} + +static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void) +{ + return gp10b_context_whitelist_ranges; +} + +static int gp10b_get_context_whitelist_ranges_count(void) +{ + return gp10b_context_whitelist_ranges_count; +} + +static const u32 *gp10b_get_runcontrol_whitelist(void) +{ + return gp10b_runcontrol_whitelist; +} + +static int gp10b_get_runcontrol_whitelist_count(void) +{ + return gp10b_runcontrol_whitelist_count; +} + +static const +struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) +{ + return gp10b_runcontrol_whitelist_ranges; +} + +static int gp10b_get_runcontrol_whitelist_ranges_count(void) +{ + return gp10b_runcontrol_whitelist_ranges_count; +} + +static const u32 *gp10b_get_qctl_whitelist(void) +{ + return gp10b_qctl_whitelist; +} + +static int gp10b_get_qctl_whitelist_count(void) +{ + return gp10b_qctl_whitelist_count; +} + +static const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) +{ + return gp10b_qctl_whitelist_ranges; +} + +static int gp10b_get_qctl_whitelist_ranges_count(void) +{ + return gp10b_qctl_whitelist_ranges_count; +} + +static int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) +{ + /* Not needed on gp10b */ + return 0; +} + +void gp10b_init_regops(struct gpu_ops *gops) +{ + gops->regops.get_global_whitelist_ranges = + gp10b_get_global_whitelist_ranges; + gops->regops.get_global_whitelist_ranges_count = + gp10b_get_global_whitelist_ranges_count; + + gops->regops.get_context_whitelist_ranges = + gp10b_get_context_whitelist_ranges; + gops->regops.get_context_whitelist_ranges_count = + gp10b_get_context_whitelist_ranges_count; + + gops->regops.get_runcontrol_whitelist = + gp10b_get_runcontrol_whitelist; + gops->regops.get_runcontrol_whitelist_count = + gp10b_get_runcontrol_whitelist_count; + + gops->regops.get_runcontrol_whitelist_ranges = + gp10b_get_runcontrol_whitelist_ranges; + gops->regops.get_runcontrol_whitelist_ranges_count = + gp10b_get_runcontrol_whitelist_ranges_count; + + gops->regops.get_qctl_whitelist = + gp10b_get_qctl_whitelist; + gops->regops.get_qctl_whitelist_count = + gp10b_get_qctl_whitelist_count; + + gops->regops.get_qctl_whitelist_ranges = + gp10b_get_qctl_whitelist_ranges; + gops->regops.get_qctl_whitelist_ranges_count = + gp10b_get_qctl_whitelist_ranges_count; + + gops->regops.apply_smpc_war = + gp10b_apply_smpc_war; +} diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h new file mode 100644 index 000000000..8727951a6 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h @@ -0,0 +1,24 @@ +/* + * + * Tegra GP10B GPU Debugger Driver Register Ops + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ +#ifndef __REGOPS_GP10B_H_ +#define __REGOPS_GP10B_H_ + +void gp10b_init_regops(struct gpu_ops *gops); + +#endif /* __REGOPS_GP10B_H_ */ -- cgit v1.2.2 From f7bf99929cf2ec5a295ac21c74cf9c4f1afd78c5 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 15 Jun 2015 11:33:35 -0700 Subject: gpu: nvgpu: gp10b: Phys addresses for page tables Use always physical addresses for page tables. In gp10b new format each level fits in one page, so we do not need SMMU translation. Change-Id: Ie46b2bce0f7a4e8d2904d74b1df616e389874141 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/758181 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index bcdee9fc7..5371605f9 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -160,13 +160,12 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *pte = parent->entries + i; u32 pde_v[2] = {0, 0}; u32 *pde; - struct gk20a *g = vm->mm->g; gk20a_dbg_fn(""); - pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0) + pte_addr = virt_to_phys(pte->cpu_va) >> gmmu_new_pde_address_shift_v(); - pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0); + pde_addr = virt_to_phys(parent->cpu_va); pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); @@ -203,7 +202,6 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *entry = pte->entries + i; u32 pde_v[4] = {0, 0, 0, 0}; u32 *pde; - struct gk20a *g = vm->mm->g; gk20a_dbg_fn(""); @@ -211,11 +209,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, big_valid = entry->size && entry->pgsz == gmmu_page_size_big; if (small_valid) - pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) + pte_addr_small = virt_to_phys(entry->cpu_va) >> gmmu_new_dual_pde_address_shift_v(); if (big_valid) - pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) + pte_addr_big = virt_to_phys(entry->cpu_va) >> gmmu_new_dual_pde_address_big_shift_v(); if (small_valid) { -- cgit v1.2.2 From 2c75efce7b4ef9087713dc75d29d0899cd699549 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Mon, 25 May 2015 15:01:04 +0530 Subject: gpu: nvgpu: gp10b: dma support for secure gpccs bug 200080684 Change-Id: I013a0ca7762f6cca0498bd282303597bf683cb7d Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/746737 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 3 +- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 74 ++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c index 1d77ad659..515ba630d 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c @@ -3,7 +3,7 @@ * * GM20B Graphics Context * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -69,4 +69,5 @@ static bool gr_gp10b_is_firmware_defined(void) void gp10b_init_gr_ctx(struct gpu_ops *gops) { gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; + gops->gr_ctx.use_dma_for_fw_bootstrap = false; } diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index b8b985b38..7b8060260 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -21,6 +21,8 @@ #include "pmu_gp10b.h" +#define gp10b_dbg_pmu(fmt, arg...) \ + gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) /*! * Structure/object which single register write need to be done during PG init * sequence to set PROD values. @@ -130,6 +132,76 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e004, 0x0000008E}, }; +void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, + u32 flags) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + gk20a_dbg_fn(""); + + gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); + if (g->ops.pmu.lspmuwprinitdone) { + /* send message to load FECS falcon */ + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_ACR; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons); + cmd.cmd.acr.boot_falcons.cmd_type = + PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS; + cmd.cmd.acr.boot_falcons.flags = flags; + cmd.cmd.acr.boot_falcons.falconidmask = + falconidmask; + cmd.cmd.acr.boot_falcons.usevamask = + 1 << LSF_FALCON_ID_GPCCS; + cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = + u64_lo32(g->pmu.wpr_buf.gpu_va); + cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = + u64_hi32(g->pmu.wpr_buf.gpu_va); + gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", + falconidmask); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); + } + + gk20a_dbg_fn("done"); + return; +} + +int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) +{ + u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; + + /* GM20B PMU supports loading FECS and GPCCS only */ + if (falconidmask == 0) + return -EINVAL; + if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | + (1 << LSF_FALCON_ID_GPCCS))) + return -EINVAL; + g->ops.pmu.lsfloadedfalconid = 0; + /* check whether pmu is ready to bootstrap lsf if not wait for it */ + if (!g->ops.pmu.lspmuwprinitdone) { + pmu_wait_message_cond(&g->pmu, + gk20a_get_gr_idle_timeout(g), + &g->ops.pmu.lspmuwprinitdone, 1); + /* check again if it still not ready indicate an error */ + if (!g->ops.pmu.lspmuwprinitdone) { + gk20a_err(dev_from_gk20a(g), + "PMU not ready to load LSF"); + return -ETIMEDOUT; + } + } + /* load falcon(s) */ + gp10b_pmu_load_multiple_falcons(g, falconidmask, flags); + pmu_wait_message_cond(&g->pmu, + gk20a_get_gr_idle_timeout(g), + &g->ops.pmu.lsfloadedfalconid, falconidmask); + if (g->ops.pmu.lsfloadedfalconid != falconidmask) + return -ETIMEDOUT; + return 0; +} + static int gp10b_pmu_setup_elpg(struct gk20a *g) { int ret = 0; @@ -157,8 +229,10 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) if (gops->privsecurity) { gm20b_init_secure_pmu(gops); gops->pmu.init_wpr_region = gm20b_pmu_init_acr; + gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; } else { gk20a_init_pmu_ops(gops); + gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; } gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; -- cgit v1.2.2 From b071d6f5b1a5d131551eea1faf668880d3fc419c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 24 Jun 2015 10:10:57 -0700 Subject: gpu: nvgpu: gp10b: Implement priv pages Implement support for privileged pages. Use them for kernel allocated buffers. Change-Id: I24778c2b6063b6bc8a4bfd9d97fa6de01d49569a Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/761920 --- drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 12 ++++++++++++ drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 9 ++++++--- 2 files changed, 18 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h index 844cb1420..9ce9448e1 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h @@ -198,6 +198,18 @@ static inline u32 gmmu_new_pte_valid_false_f(void) { return 0x0; } +static inline u32 gmmu_new_pte_privilege_w(void) +{ + return 0; +} +static inline u32 gmmu_new_pte_privilege_true_f(void) +{ + return 0x20; +} +static inline u32 gmmu_new_pte_privilege_false_f(void) +{ + return 0x0; +} static inline u32 gmmu_new_pte_address_sys_f(u32 v) { return (v & 0xfffffff) << 8; diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 5371605f9..9f66c21f7 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -153,7 +153,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, u64 *iova, u32 kind_v, u32 *ctag, bool cacheable, bool unmapped_pte, - int rw_flag, bool sparse, u32 flags) + int rw_flag, bool sparse, bool priv) { u64 pte_addr = 0; u64 pde_addr = 0; @@ -195,7 +195,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, u64 *iova, u32 kind_v, u32 *ctag, bool cacheable, bool unmapped_pte, - int rw_flag, bool sparse, u32 flags) + int rw_flag, bool sparse, bool priv) { bool small_valid, big_valid; u32 pte_addr_small = 0, pte_addr_big = 0; @@ -251,7 +251,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, u64 *iova, u32 kind_v, u32 *ctag, bool cacheable, bool unmapped_pte, - int rw_flag, bool sparse, u32 flags) + int rw_flag, bool sparse, bool priv) { struct gk20a *g = vm->mm->g; u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; @@ -269,6 +269,9 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, gmmu_new_pte_address_sys_f(*iova >> gmmu_new_pte_address_shift_v()); + if (priv) + pte_w[0] |= gmmu_new_pte_privilege_true_f(); + pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) | gmmu_new_pte_kind_f(kind_v) | gmmu_new_pte_comptagline_f(*ctag / ctag_granularity); -- cgit v1.2.2 From 3eac12e16d6cae991a620590fc42b61bde6bc664 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Wed, 1 Jul 2015 12:50:26 +0530 Subject: gpu: nvgpu: gp10b: make local function 'static' Fixed the following sparse warning by making the local function as static: - symbol 'gp10b_pmu_load_multiple_falcons' was not declared. Should it be static? - symbol 'gp10b_load_falcon_ucode' was not declared. Should it be static? bug 200067946 Change-Id: I67d865aef6f57bf614db351929cd4bb1b6077c00 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/764646 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amit Sharma (SW-TEGRA) GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 7b8060260..2a8d968c5 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -132,7 +132,7 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e004, 0x0000008E}, }; -void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, +static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, u32 flags) { struct pmu_gk20a *pmu = &g->pmu; @@ -169,7 +169,7 @@ void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, return; } -int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) +static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) { u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; -- cgit v1.2.2 From f626083c57f323d88d822c57e8017db42c4e6c3d Mon Sep 17 00:00:00 2001 From: Matt Craighead Date: Thu, 9 Jul 2015 14:24:31 -0500 Subject: Revert "gpu: nvgpu: gp10b: Phys addresses for page tables" This reverts commit f7bf99929cf2ec5a295ac21c74cf9c4f1afd78c5. Change-Id: I0acfa18e9cf9bedd4051ec00faa497b3cdb9454b Signed-off-by: Matt Craighead Reviewed-on: http://git-master/r/768599 Reviewed-by: Hiroshi Doyu Tested-by: Hiroshi Doyu --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 9f66c21f7..190dc7f6f 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -160,12 +160,13 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *pte = parent->entries + i; u32 pde_v[2] = {0, 0}; u32 *pde; + struct gk20a *g = vm->mm->g; gk20a_dbg_fn(""); - pte_addr = virt_to_phys(pte->cpu_va) + pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0) >> gmmu_new_pde_address_shift_v(); - pde_addr = virt_to_phys(parent->cpu_va); + pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0); pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); @@ -202,6 +203,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *entry = pte->entries + i; u32 pde_v[4] = {0, 0, 0, 0}; u32 *pde; + struct gk20a *g = vm->mm->g; gk20a_dbg_fn(""); @@ -209,11 +211,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, big_valid = entry->size && entry->pgsz == gmmu_page_size_big; if (small_valid) - pte_addr_small = virt_to_phys(entry->cpu_va) + pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) >> gmmu_new_dual_pde_address_shift_v(); if (big_valid) - pte_addr_big = virt_to_phys(entry->cpu_va) + pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) >> gmmu_new_dual_pde_address_big_shift_v(); if (small_valid) { -- cgit v1.2.2 From 039c2e68273ef0a5122da413ac1e44a3adf17551 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 10 Aug 2015 14:53:47 -0700 Subject: gpu: nvgpu: gp10b: Use phys addresses in PDEs Use physical addresses in PDEs. All page table levels fit in 4k, so no need for SMMU mapping. Change-Id: Id9e418f35a79343f4a332a230e04abda5e0dd5d2 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/783748 GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 190dc7f6f..654495348 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -160,13 +160,11 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *pte = parent->entries + i; u32 pde_v[2] = {0, 0}; u32 *pde; - struct gk20a *g = vm->mm->g; gk20a_dbg_fn(""); - pte_addr = g->ops.mm.get_iova_addr(g, pte->sgt->sgl, 0) - >> gmmu_new_pde_address_shift_v(); - pde_addr = g->ops.mm.get_iova_addr(g, parent->sgt->sgl, 0); + pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v(); + pde_addr = sg_phys(parent->sgt->sgl); pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); @@ -203,7 +201,6 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, struct gk20a_mm_entry *entry = pte->entries + i; u32 pde_v[4] = {0, 0, 0, 0}; u32 *pde; - struct gk20a *g = vm->mm->g; gk20a_dbg_fn(""); @@ -211,11 +208,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, big_valid = entry->size && entry->pgsz == gmmu_page_size_big; if (small_valid) - pte_addr_small = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) + pte_addr_small = sg_phys(entry->sgt->sgl) >> gmmu_new_dual_pde_address_shift_v(); if (big_valid) - pte_addr_big = g->ops.mm.get_iova_addr(g, entry->sgt->sgl, 0) + pte_addr_big = sg_phys(entry->sgt->sgl) >> gmmu_new_dual_pde_address_big_shift_v(); if (small_valid) { -- cgit v1.2.2 From 01a05471ab0a00a9bb4531adf8ed4d308cb71585 Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Wed, 19 Aug 2015 12:35:29 +0530 Subject: gpu: nvgpu: update t186 slcg prod settings bug 1675413 work around for timestamp slcg bug Change-Id: I0950403b89e9ea161bd7eb7052f47de3f9733240 Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/785854 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c index f8ee80c33..fbf146a2a 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c @@ -35,7 +35,7 @@ static const struct gating_desc gp10b_slcg_bus[] = { /* slcg ce2 */ static const struct gating_desc gp10b_slcg_ce2[] = { - {.addr = 0x00106f28, .prod = 0x00000000, .disable = 0x000007fe}, + {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, }; /* slcg chiplet */ @@ -59,7 +59,7 @@ static const struct gating_desc gp10b_slcg_fifo[] = { /* slcg gr */ static const struct gating_desc gp10b_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000000, .disable = 0x03fffffe}, + {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, @@ -136,14 +136,14 @@ static const struct gating_desc gp10b_slcg_priring[] = { static const struct gating_desc gp10b_slcg_pwr_csb[] = { {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, }; /* slcg pmu */ static const struct gating_desc gp10b_slcg_pmu[] = { {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00000000, .disable = 0x00007ffe}, + {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, }; @@ -192,7 +192,7 @@ static const struct gating_desc gp10b_blcg_gr[] = { {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x4000c141, .disable = 0x00000000}, + {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, -- cgit v1.2.2 From 870859de7063b7d6f216d800b86709cf939c65ec Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Tue, 18 Aug 2015 19:34:51 +0300 Subject: gpu: nvgpu: Add CDE program number selection for GP10B Add CDE program number selection for GP10B. Bug 1604102 Change-Id: I0054e670e3bc6b8c2380124eb58204088aaae275 Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/785459 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/cde_gp10b.c | 64 +++++++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/cde_gp10b.h | 23 +++++++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 4 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/nvgpu/gp10b/cde_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/cde_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 688965da2..ad1983278 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_GK20A) += \ hal_gp10b.o \ rpfb_gp10b.o \ gp10b_gating_reglist.o \ - regops_gp10b.o + regops_gp10b.o \ + cde_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c new file mode 100644 index 000000000..acb8aee31 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c @@ -0,0 +1,64 @@ +/* + * GP10B CDE + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "cde_gp10b.h" + +enum gp10b_programs { + GP10B_PROG_HPASS = 0, + GP10B_PROG_HPASS_4K = 1, + GP10B_PROG_VPASS = 2, + GP10B_PROG_VPASS_4K = 3, + GP10B_PROG_HPASS_DEBUG = 4, + GP10B_PROG_HPASS_4K_DEBUG = 5, + GP10B_PROG_VPASS_DEBUG = 6, + GP10B_PROG_VPASS_4K_DEBUG = 7, + GP10B_PROG_PASSTHROUGH = 8, +}; + +static void gp10b_cde_get_program_numbers(struct gk20a *g, + u32 block_height_log2, + int *hprog_out, int *vprog_out) +{ + int hprog, vprog; + + if (g->cde_app.shader_parameter == 1) { + hprog = GP10B_PROG_PASSTHROUGH; + vprog = GP10B_PROG_PASSTHROUGH; + } else { + hprog = GP10B_PROG_HPASS; + vprog = GP10B_PROG_VPASS; + if (g->cde_app.shader_parameter == 2) { + hprog = GP10B_PROG_HPASS_DEBUG; + vprog = GP10B_PROG_VPASS_DEBUG; + } + if (g->mm.bypass_smmu) { + if (!g->mm.disable_bigpage) { + gk20a_warn(&g->dev->dev, + "when bypass_smmu is 1, disable_bigpage must be 1 too"); + } + hprog |= 1; + vprog |= 1; + } + } + + *hprog_out = hprog; + *vprog_out = vprog; +} + +void gp10b_init_cde_ops(struct gpu_ops *gops) +{ + gops->cde.get_program_numbers = gp10b_cde_get_program_numbers; +} diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.h b/drivers/gpu/nvgpu/gp10b/cde_gp10b.h new file mode 100644 index 000000000..52f785f1c --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/cde_gp10b.h @@ -0,0 +1,23 @@ +/* + * GP10B CDE + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVHOST_GP10B_CDE +#define _NVHOST_GP10B_CDE + +struct gpu_ops; + +void gp10b_init_cde_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 9eba5571e..983b985de 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -31,6 +31,7 @@ #include "gp10b/fifo_gp10b.h" #include "gp10b/gp10b_gating_reglist.h" #include "gp10b/regops_gp10b.h" +#include "gp10b/cde_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -103,6 +104,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_pmu_ops(gops); gk20a_init_debug_ops(gops); gp10b_init_regops(gops); + gp10b_init_cde_ops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; -- cgit v1.2.2 From adaa8f1e06260b23120bb89a857eeecd6810c95d Mon Sep 17 00:00:00 2001 From: Supriya Date: Thu, 6 Aug 2015 16:39:39 +0530 Subject: gpu: nvgpu: gp10b: Fix NS boot transcfg Bug 1667322 Accomodate for transcfg address change Change-Id: I83c5d4921040258a480df44a69792c721ff88f05 Signed-off-by: Supriya Reviewed-on: http://git-master/r/779764 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 2a8d968c5..dcf28edfa 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -232,6 +232,8 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; } else { gk20a_init_pmu_ops(gops); + gops->pmu.pmu_setup_hw_and_bootstrap = + gm20b_init_nspmu_setup_hw1; gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; } -- cgit v1.2.2 From a522cda88d0c37cd2caffa3444bb0ac4e595201a Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 25 May 2015 14:49:38 +0300 Subject: gpu: nvgpu: Separate kernel and user GPU VA regions (gp10b) Specify that everything in bar2 VM is kernel reserved. Bug 200077571 Change-Id: I8f6c6ac6352ffd64eedc09187593b6c8d05757ef Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/746802 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 654495348..0c76abb52 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -75,6 +75,7 @@ static int gb10b_init_bar2_vm(struct gk20a *g) mm->bar2.aperture_size = 32 << 20; gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size); gk20a_init_vm(mm, vm, big_page_size, SZ_4K, + mm->bar2.aperture_size - SZ_4K, mm->bar2.aperture_size, false, "bar2"); /* allocate instance mem for bar2 */ -- cgit v1.2.2 From 72bb050ce0a38324a0f71014d77b29104ae691c4 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sun, 13 Sep 2015 13:44:01 -0700 Subject: gpu: nvgpu: priv load for gpccs load. - clear mask to load gpcss with priv load. Bug n/a Change-Id: I21522bda83c4dd5c665d47ae334b9fed5cb8ec74 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/798406 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index dcf28edfa..f29bcbadc 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -153,8 +153,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, cmd.cmd.acr.boot_falcons.flags = flags; cmd.cmd.acr.boot_falcons.falconidmask = falconidmask; - cmd.cmd.acr.boot_falcons.usevamask = - 1 << LSF_FALCON_ID_GPCCS; + cmd.cmd.acr.boot_falcons.usevamask = 0; cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = u64_lo32(g->pmu.wpr_buf.gpu_va); cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = -- cgit v1.2.2 From 9c138f757e74b5d96613c949b2fedf87787bd75d Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 14 Sep 2015 10:03:05 -0700 Subject: gpu: nvgpu: HAL to write DMATRFBASE - Must write DMATRFBASE1 to 0 whenever DMATRFBASE is written. Bug 200137618 Change-Id: Id8526d1bafbd116ffc4d8018983791fe9e9fa604 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/798780 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 4 ++++ drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 10 ++++++++++ 2 files changed, 14 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h index 0de70b967..f66812d68 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h @@ -406,6 +406,10 @@ static inline u32 pwr_falcon_dmatrfbase_r(void) { return 0x0010a110; } +static inline u32 pwr_falcon_dmatrfbase1_r(void) +{ + return 0x0010a128; +} static inline u32 pwr_falcon_dmatrfmoffs_r(void) { return 0x0010a114; diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index f29bcbadc..529491d04 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -20,6 +20,7 @@ #include "gm20b/pmu_gm20b.h" #include "pmu_gp10b.h" +#include "hw_pwr_gp10b.h" #define gp10b_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) @@ -223,6 +224,14 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) return ret; } +void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) +{ + gk20a_writel(g, pwr_falcon_dmatrfbase_r(), + addr); + gk20a_writel(g, pwr_falcon_dmatrfbase1_r(), + 0x0); +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -239,4 +248,5 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; + gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; } -- cgit v1.2.2 From da4181954905d33a519c0b370963567deb0d9452 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 18 Sep 2015 14:15:32 +0530 Subject: gpu: nvgpu: fix sparse warning Fix below sparse warning by declaring gp10b_write_dmatrfbase() as static kernel-t18x/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c:227:6: warning: symbol 'gp10b_write_dmatrfbase' was not declared. Should it be static? Bug 200088648 Change-Id: I3bd2eeaeb7234ab54d7e9342a7512ec28388f751 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/801213 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 529491d04..a4d7a0f71 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -224,7 +224,7 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) return ret; } -void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) +static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) { gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); -- cgit v1.2.2 From 305886e6bc8f1a0e4b160937c5031eb96c1c66af Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 25 Aug 2015 13:00:38 -0700 Subject: gpu: nvgpu: gp10b: Choose netlist A Force usage of netlist slot A. Change-Id: Ib507b0e0c7ff6d0dbb43f91b6c7264424975d681 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/789060 Reviewed-on: http://git-master/r/806183 --- drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 2 +- drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c index 515ba630d..b50698e07 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c @@ -59,7 +59,7 @@ static int gr_gp10b_get_netlist_name(int index, char *name) static bool gr_gp10b_is_firmware_defined(void) { -#ifdef GM20B_NETLIST_IMAGE_FW_NAME +#ifdef GP10B_NETLIST_IMAGE_FW_NAME return true; #else return false; diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h index b1184f9db..b5c76d24d 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h @@ -21,7 +21,7 @@ #include "gk20a/gr_ctx_gk20a.h" /* production netlist, one and only one from below */ -/*#undef GM20B_NETLIST_IMAGE_FW_NAME*/ +#define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A void gp10b_init_gr_ctx(struct gpu_ops *gops); -- cgit v1.2.2 From f5829d5609737173780519a2246c6ede68a2548d Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Tue, 18 Aug 2015 18:16:46 +0300 Subject: gpu: nvgpu: Add CDE scatter buffer code for GP10B Add GP10B-specific code for populating the scatter buffer. Essentially, this enables the use of SMMU bypass mode with 4-kB page compression. Bug 1604102 Change-Id: Ic586e2f93827b9aa1c7b73b53b8f65d518588c26 Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/789434 Reviewed-on: http://git-master/r/806184 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/cde_gp10b.c | 84 +++++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c index acb8aee31..dadec4d26 100644 --- a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c @@ -58,7 +58,91 @@ static void gp10b_cde_get_program_numbers(struct gk20a *g, *vprog_out = vprog; } +static bool gp10b_need_scatter_buffer(struct gk20a *g) +{ + return g->mm.bypass_smmu; +} + +static u8 parity(u32 a) +{ + a ^= a>>16u; + a ^= a>>8u; + a ^= a>>4u; + a &= 0xfu; + return (0x6996u >> a) & 1u; +} + +static int gp10b_populate_scatter_buffer(struct gk20a *g, + struct sg_table *sgt, + size_t surface_size, + void *scatter_buffer_ptr, + size_t scatter_buffer_size) +{ + /* map scatter buffer to CPU VA and fill it */ + const u32 page_size_log2 = 12; + const u32 page_size = 1 << page_size_log2; + const u32 page_size_shift = page_size_log2 - 7u; + + /* 0011 1111 1111 1111 1111 1110 0100 1000 */ + const u32 getSliceMaskGP10B = 0x3ffffe48; + u8 *scatter_buffer = scatter_buffer_ptr; + + size_t i; + struct scatterlist *sg = NULL; + u8 d = 0; + size_t page = 0; + size_t pages_left; + + surface_size = round_up(surface_size, page_size); + + pages_left = surface_size >> page_size_log2; + if ((pages_left >> 3) > scatter_buffer_size) + return -ENOMEM; + + for_each_sg(sgt->sgl, sg, sgt->nents, i) { + unsigned int j; + u64 surf_pa = sg_phys(sg); + unsigned int n = (int)(sg->length >> page_size_log2); + + gk20a_dbg(gpu_dbg_cde, "surfPA=0x%llx + %d pages", surf_pa, n); + + for (j=0; j < n && pages_left > 0; j++, surf_pa += page_size) { + u32 addr = (((u32)(surf_pa>>7)) & getSliceMaskGP10B) >> page_size_shift; + u8 scatter_bit = parity(addr); + u8 bit = page & 7; + + d |= scatter_bit << bit; + if (bit == 7) { + scatter_buffer[page >> 3] = d; + d = 0; + } + + ++page; + --pages_left; + } + + if (pages_left == 0) + break; + } + + /* write the last byte in case the number of pages is not divisible by 8 */ + if ((page & 7) != 0) + scatter_buffer[page >> 3] = d; + +#if defined(GK20A_DEBUG) + if (unlikely(gpu_dbg_cde & gk20a_dbg_mask)) { + gk20a_dbg(gpu_dbg_cde, "scatterBuffer content:"); + for (i=0; i < page>>3; i++) { + gk20a_dbg(gpu_dbg_cde, " %x", scatter_buffer[i]); + } + } +#endif + return 0; +} + void gp10b_init_cde_ops(struct gpu_ops *gops) { gops->cde.get_program_numbers = gp10b_cde_get_program_numbers; + gops->cde.need_scatter_buffer = gp10b_need_scatter_buffer; + gops->cde.populate_scatter_buffer = gp10b_populate_scatter_buffer; } -- cgit v1.2.2 From 8c93a80e6977d00a20e301b225aa93f24b2500d1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 26 Aug 2015 16:00:19 -0700 Subject: gpu: nvgpu: gp10b: Implement NVC0_SET_GO_IDLE_TIMEOUT Bug 1678603 Change-Id: Ib8fb09dace864567b1ce574c216a584831723684 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/790402 Reviewed-on: http://git-master/r/806185 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 8 ++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 1 + 2 files changed, 9 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 1942b1e70..7d9f5f47f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -284,6 +284,11 @@ static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) return size; } +static void gr_gp10b_set_go_idle_timeout(struct gk20a *g, u32 data) +{ + gk20a_writel(g, gr_fe_go_idle_timeout_r(), data); +} + static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { @@ -310,6 +315,9 @@ static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: g->ops.gr.set_alpha_circular_buffer_size(g, data); break; + case NVC097_SET_GO_IDLE_TIMEOUT: + gr_gp10b_set_go_idle_timeout(g, data); + break; default: goto fail; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 1b99cafba..302ea1978 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -28,6 +28,7 @@ enum { #define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC097_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC097_SET_GO_IDLE_TIMEOUT 0x152c #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 void gp10b_init_gr(struct gpu_ops *ops); -- cgit v1.2.2 From 20b925a897f60bff484f4ea77c3bed5434b6099a Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 26 Aug 2015 16:04:04 -0700 Subject: gpu: nvgpu: gp10b: Disable deep binning Disable deep binning by default. Change-Id: I75da95984ac314015c6927e099a3eaa37fcc26fc Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/790403 Reviewed-on: http://git-master/r/806186 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 7d9f5f47f..c9b870c7e 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -333,8 +333,7 @@ static void gr_gp10b_cb_size_default(struct gk20a *g) struct gr_gk20a *gr = &g->gr; if (!gr->attrib_cb_default_size) - gr->attrib_cb_default_size = - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); + gr->attrib_cb_default_size = 0x800; gr->alpha_cb_default_size = gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); } @@ -929,6 +928,9 @@ static int gr_gp10b_init_fs_state(struct gk20a *g) gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); + /* disable deep binning */ + gk20a_writel(g, gr_fe_go_idle_timeout_r(), 0x800); + return gr_gm20b_ctx_state_floorsweep(g); } -- cgit v1.2.2 From 96ca2a0fd0fbf0ea0148546a0d310a40814a8183 Mon Sep 17 00:00:00 2001 From: Robert Morell Date: Tue, 1 Sep 2015 17:59:57 -0700 Subject: gpu: nvgpu: gp10b: Correct C097_SET_GO_IDLE_TIMEOUT offset Bug 1678603 Change-Id: I1c2c3c9395e068fabf554779ded6f0f536622c90 Signed-off-by: Robert Morell Reviewed-on: http://git-master/r/792831 Reviewed-on: http://git-master/r/806187 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 302ea1978..7c3ddf275 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -25,10 +25,10 @@ enum { PASCAL_DMA_COPY_A = 0xC0B5, }; +#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c #define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc #define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC097_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC097_SET_GO_IDLE_TIMEOUT 0x152c #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 void gp10b_init_gr(struct gpu_ops *ops); -- cgit v1.2.2 From 1e9d76b91060c51f42a049f84bd72e373f52090b Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Sat, 29 Aug 2015 05:12:29 +0530 Subject: gpu: nvgpu: fuse read to boot in SECURE mode -Read fuse to boot in secure/production mode else non sercure mode. Bug N/A Change-Id: Ia66acff63a4a5ed9351c01cd8907a337e88dc8eb Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/791323 Reviewed-on: http://git-master/r/806191 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 39 ++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 983b985de..a6131cea7 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -37,6 +37,10 @@ #include "gm20b/fifo_gm20b.h" #include "gm20b/pmu_gm20b.h" #include "gm20b/clk_gm20b.h" +#include + +#define FUSE_OPT_PRIV_SEC_EN_0 0x264 +#define PRIV_SECURITY_ENABLED 0x01 static struct gpu_ops gp10b_ops = { .clock_gating = { @@ -91,7 +95,40 @@ int gp10b_init_hal(struct gk20a *g) struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; *gops = gp10b_ops; - gops->privsecurity = 0; + +#ifdef CONFIG_TEGRA_ACR + if (tegra_platform_is_linsim()) { + gops->privsecurity = 1; + gops->securegpccs = 1; + } else { + if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & + PRIV_SECURITY_ENABLED) { + gops->privsecurity = 1; + gops->securegpccs =1; + } else { + gk20a_dbg_info("priv security is disabled in HW"); + gops->privsecurity = 0; + gops->securegpccs = 0; + } + } +#else + if (tegra_platform_is_linsim()) { + gk20a_dbg_info("running ASIM with PRIV security disabled"); + gops->privsecurity = 0; + gops->securegpccs = 0; + } else { + if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & + PRIV_SECURITY_ENABLED) { + gk20a_dbg_info("priv security is not supported but enabled"); + gops->privsecurity = 1; + gops->securegpccs =1; + return -EPERM; + } else { + gops->privsecurity = 0; + gops->securegpccs = 0; + } + } +#endif gp10b_init_mc(gops); gp10b_init_gr(gops); -- cgit v1.2.2 From 7a2943ae55799f07f9c5f02cc78cf626ed1515d0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 20 Sep 2015 13:36:54 -0700 Subject: gpu: nvgpu: gp10b: Always disable security in sim Change-Id: I1fc8c4c4c71ebf84fe913af07fc2055959e5ab91 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/801850 Reviewed-on: http://git-master/r/806192 --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a6131cea7..70486c4a4 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -98,8 +98,8 @@ int gp10b_init_hal(struct gk20a *g) #ifdef CONFIG_TEGRA_ACR if (tegra_platform_is_linsim()) { - gops->privsecurity = 1; - gops->securegpccs = 1; + gops->privsecurity = 0; + gops->securegpccs = 0; } else { if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & PRIV_SECURITY_ENABLED) { -- cgit v1.2.2 From 14248de9b627c982953167a6935b5eb6a80da337 Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Thu, 27 Aug 2015 14:01:45 -0400 Subject: gpu: nvgpu: vgpu: add gp10b support Add support for gp10b in a virtualized environment. Bug 1677153 VFND-693 Change-Id: I919ffa44c6773940a7a3411ee8bbc403a992b7cb Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/792556 Reviewed-on: http://git-master/r/806193 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 2 +- drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h | 7 +- drivers/gpu/nvgpu/vgpu/gp10b/Makefile | 16 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 20 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h | 21 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 20 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h | 21 +++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 35 +++++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 172 +++++++++++++++++++++++++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h | 21 +++ 10 files changed, 333 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/Makefile create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c create mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index f259eefa6..37cc15a59 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -7,4 +7,4 @@ ccflags-$(CONFIG_GK20A) += -Wno-multichar ccflags-$(CONFIG_GK20A) += -Werror obj-$(CONFIG_GK20A) += gp10b/ - +obj-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += vgpu/gp10b/ diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h index 59ecefee3..96f021252 100644 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h +++ b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h @@ -1,7 +1,7 @@ /* * NVIDIA GPU ID functions, definitions. * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -28,4 +28,9 @@ struct gpu_ops; extern int gp10b_init_hal(struct gk20a *); extern struct gk20a_platform t18x_gpu_tegra_platform; + +#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION +#define TEGRA_18x_GPUID_VGPU_HAL vgpu_gp10b_init_hal +extern int vgpu_gp10b_init_hal(struct gk20a *); +#endif #endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/Makefile b/drivers/gpu/nvgpu/vgpu/gp10b/Makefile new file mode 100644 index 000000000..fed8a08e7 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/Makefile @@ -0,0 +1,16 @@ +GCOV_PROFILE := y + +ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi + +ccflags-$(CONFIG_GK20A) += -Wno-multichar +ccflags-y += -Werror + +obj-$(CONFIG_GK20A) += \ + vgpu_hal_gp10b.o \ + vgpu_gr_gp10b.o \ + vgpu_mm_gp10b.o \ + vgpu_fifo_gp10b.o diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c new file mode 100644 index 000000000..34d942c15 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu_fifo_gp10b.h" + +void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) +{ + /* syncpoint protection not supported yet */ + gops->fifo.resetup_ramfc = NULL; +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h new file mode 100644 index 000000000..4ede0b6df --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VGPU_FIFO_GP10B_H__ +#define __VGPU_FIFO_GP10B_H__ + +#include "gk20a/gk20a.h" + +void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c new file mode 100644 index 000000000..9df29eeee --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu_gr_gp10b.h" +#include "vgpu/gm20b/vgpu_gr_gm20b.h" + +void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) +{ + vgpu_gm20b_init_gr_ops(gops); +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h new file mode 100644 index 000000000..b3be49a77 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VGPU_GR_GP10B_H__ +#define __VGPU_GR_GP10B_H__ + +#include "gk20a/gk20a.h" + +void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops); + +#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c new file mode 100644 index 000000000..14a7768a8 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "vgpu/vgpu.h" +#include "gp10b/hal_gp10b.h" +#include "vgpu_gr_gp10b.h" +#include "vgpu_fifo_gp10b.h" +#include "vgpu_mm_gp10b.h" + +int vgpu_gp10b_init_hal(struct gk20a *g) +{ + int err; + + gk20a_dbg_fn(""); + + err = gp10b_init_hal(g); + if (err) + return err; + + vgpu_init_hal_common(g); + vgpu_gp10b_init_gr_ops(&g->ops); + vgpu_gp10b_init_fifo_ops(&g->ops); + vgpu_gp10b_init_mm_ops(&g->ops); + return 0; +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c new file mode 100644 index 000000000..0a769e944 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -0,0 +1,172 @@ +/* + * Virtualized GPU Memory Management + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "vgpu/vgpu.h" +#include "vgpu_mm_gp10b.h" +#include "gk20a/semaphore_gk20a.h" +#include "gk20a/mm_gk20a.h" + +static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) +{ + g->mm.bypass_smmu = true; + g->mm.disable_bigpage = true; + return 0; +} + +static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, + u64 addr, u64 size, size_t *oob_size) +{ + if (*oob_size < sizeof(*mem_desc)) + return -ENOMEM; + + mem_desc->addr = addr; + mem_desc->length = size; + *oob_size -= sizeof(*mem_desc); + return 0; +} + +static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, + u64 map_offset, + struct sg_table *sgt, + u64 buffer_offset, + u64 size, + int pgsz_idx, + u8 kind_v, + u32 ctag_offset, + u32 flags, + int rw_flag, + bool clear_ctags, + bool sparse, + bool priv, + struct vm_gk20a_mapping_batch *batch) +{ + int err = 0; + struct device *d = dev_from_vm(vm); + struct gk20a *g = gk20a_from_vm(vm); + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; + struct tegra_vgpu_mem_desc *mem_desc; + u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; + u64 space_to_skip = buffer_offset; + u64 buffer_size = 0; + u32 mem_desc_count = 0; + struct scatterlist *sgl; + void *handle = NULL; + size_t oob_size; + u8 prot; + + gk20a_dbg_fn(""); + + /* FIXME: add support for sparse mappings */ + + if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) + return -EINVAL; + + if (space_to_skip & (page_size - 1)) + return -EINVAL; + + /* Allocate (or validate when map_offset != 0) the virtual address. */ + if (!map_offset) { + map_offset = gk20a_vm_alloc_va(vm, size, pgsz_idx); + if (!map_offset) { + gk20a_err(d, "failed to allocate va space"); + err = -ENOMEM; + goto fail; + } + } + + handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, + tegra_gr_comm_get_server_vmid(), + TEGRA_VGPU_QUEUE_CMD, + (void **)&mem_desc, &oob_size); + if (!handle) { + err = -EINVAL; + goto fail; + } + + sgl = sgt->sgl; + while (space_to_skip && sgl && + (space_to_skip + page_size > sgl->length)) { + space_to_skip -= sgl->length; + sgl = sg_next(sgl); + } + WARN_ON(!sgl); + + if (add_mem_desc(&mem_desc[mem_desc_count++], + sg_phys(sgl) + space_to_skip, + sgl->length - space_to_skip, + &oob_size)) { + err = -ENOMEM; + goto fail; + } + buffer_size += sgl->length - space_to_skip; + + sgl = sg_next(sgl); + while (sgl && buffer_size < size) { + if (add_mem_desc(&mem_desc[mem_desc_count++], sg_phys(sgl), + sgl->length, &oob_size)) { + err = -ENOMEM; + goto fail; + } + + buffer_size += sgl->length; + sgl = sg_next(sgl); + } + + if (rw_flag == gk20a_mem_flag_read_only) + prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; + else if (rw_flag == gk20a_mem_flag_write_only) + prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; + else + prot = TEGRA_VGPU_MAP_PROT_NONE; + + msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; + msg.handle = platform->virt_handle; + p->handle = vm->handle; + p->gpu_va = map_offset; + p->size = size; + p->mem_desc_count = mem_desc_count; + p->pgsz_idx = pgsz_idx; + p->iova = 0; + p->kind = kind_v; + p->cacheable = + (flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0; + p->prot = prot; + p->ctag_offset = ctag_offset; + p->clear_ctags = clear_ctags; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + if (err || msg.ret) + goto fail; + + /* TLB invalidate handled on server side */ + + tegra_gr_comm_oob_put_ptr(handle); + return map_offset; +fail: + if (handle) + tegra_gr_comm_oob_put_ptr(handle); + gk20a_err(d, "%s: failed with err=%d\n", __func__, err); + return 0; +} + +void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops) +{ + gk20a_dbg_fn(""); + + gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map; + gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw; +} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h new file mode 100644 index 000000000..5bdc9d1b5 --- /dev/null +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VGPU_MM_GP10B_H__ +#define __VGPU_MM_GP10B_H__ + +#include "gk20a/gk20a.h" + +void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops); + +#endif -- cgit v1.2.2 From a03b5c30818b3e852e847eb28696d906ba52d194 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 15 May 2015 17:03:18 +0530 Subject: gpu: nvgpu: enable gp10b rail calls to bpmp Bug 200086985 Change-Id: I9eaa135b96629636a6b949ae1e3874dd3abd5138 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/794723 Reviewed-on: http://git-master/r/743217 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index efecb1e36..44b27fe7b 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -63,17 +63,28 @@ static int gp10b_tegra_late_probe(struct platform_device *pdev) static bool gp10b_tegra_is_railgated(struct platform_device *pdev) { - return false; + bool ret = false; + + if (!tegra_platform_is_linsim()) + ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU); + + return ret; } static int gp10b_tegra_railgate(struct platform_device *pdev) { + if (!tegra_platform_is_linsim() && + tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) + tegra_powergate_partition(TEGRA_POWERGATE_GPU); return 0; } static int gp10b_tegra_unrailgate(struct platform_device *pdev) { - return 0; + int ret = 0; + if (!tegra_platform_is_linsim()) + ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); + return ret; } static int gp10b_tegra_suspend(struct device *dev) @@ -85,6 +96,11 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .has_syncpoints = true, /* power management configuration */ + .railgate_delay = 500, + .clockgate_delay = 50, + + /* power management configuration */ + .can_railgate = false, .enable_elpg = false, .probe = gp10b_tegra_probe, -- cgit v1.2.2 From 24c2642df144b36be41b603cab28094ff9099870 Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Tue, 4 Aug 2015 16:50:15 +0300 Subject: gpu: nvgpu: gp10b: update headers Add counters for GFXP, WFI, CTA and CILP context switches bug 1525327 bug 1581799 Signed-off-by: Kirill Artamonov Change-Id: Ifd6ee08af8a83ed827a8996725139416d81ca10e Reviewed-on: http://git-master/r/794977 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Reviewed-on: http://git-master/r/778761 Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 3b97c9da6..f358d4054 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -118,6 +118,22 @@ static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) { return 0x000000f4; } +static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) +{ + return 0x000000d0; +} +static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) +{ + return 0x000000d4; +} +static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) +{ + return 0x000000d8; +} +static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) +{ + return 0x000000dc; +} static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) { return 0x000000f8; -- cgit v1.2.2 From 3e43504f860e77fe8277e60c70ca3eaf8d463185 Mon Sep 17 00:00:00 2001 From: Kirill Artamonov Date: Sun, 25 Jan 2015 18:42:18 +0200 Subject: gpu: nvgpu: gp10b: add debug features for gfxp and cilp Add debugfs switch to force cilp and gfx preemption Add debugfs switch to dump context switch stats on channel destruction. bug 1525327 bug 1581799 Signed-off-by: Kirill Artamonov Change-Id: I7d0558cc325ce655411388ea66ad982101f2fe66 Reviewed-on: http://git-master/r/794976 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom Reviewed-on: http://git-master/r/677231 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 47 ++++++++++++++++++++++++-- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 8 ++++- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 24 +++++++++++++ 3 files changed, 76 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index c9b870c7e..e727ee999 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -25,6 +25,7 @@ #include "hw_proj_gp10b.h" #include "hw_ctxsw_prog_gp10b.h" #include "hw_mc_gp10b.h" +#include static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) { @@ -482,6 +483,13 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (err) return err; + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; + + if (class == PASCAL_COMPUTE_A && + g->gr.t18x.ctx_vars.force_preemption_cilp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; + if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { u32 spill_size = gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(); @@ -531,7 +539,7 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, goto fail_free_betacb; } - (*gr_ctx)->preempt_mode = flags; + (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; } if (class == PASCAL_COMPUTE_A) { @@ -558,6 +566,38 @@ fail_free_gk20a_ctx: return err; } +static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) { + void *ctx_ptr = vmap(gr_ctx->mem.pages, + PAGE_ALIGN(gr_ctx->mem.size) >> PAGE_SHIFT, + 0, pgprot_writecombine(PAGE_KERNEL)); + if (!ctx_ptr) { + WARN_ON("Cannot map context"); + return; + } + gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_wfi_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_cta_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_num_cilp_save_ops_o(), 0)); + gk20a_err(dev_from_gk20a(g), + "image gfx preemption option (GFXP is 1) %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_graphics_preemption_options_o(), + 0)); + vunmap(ctx_ptr); +} + static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { @@ -566,15 +606,18 @@ static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, if (!gr_ctx) return; + if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) + dump_ctx_switch_stats(g, vm, gr_ctx); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); gr_gk20a_free_gr_ctx(g, vm, gr_ctx); - gk20a_dbg_fn("done"); } + static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, struct channel_ctx_gk20a *ch_ctx, void *ctx_ptr) diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 7c3ddf275..370e0ea37 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -1,7 +1,7 @@ /* * GM20B GPU GR * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -36,6 +36,12 @@ void gp10b_init_gr(struct gpu_ops *ops); struct gr_t18x { struct { u32 preempt_image_size; + u32 force_preemption_gfxp; + u32 force_preemption_cilp; + u32 dump_ctxsw_stats_on_channel_close; + struct dentry *debugfs_force_preemption_cilp; + struct dentry *debugfs_force_preemption_gfxp; + struct dentry *debugfs_dump_ctxsw_stats; } ctx_vars; }; diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 44b27fe7b..2f81378d1 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -53,6 +53,30 @@ static int gp10b_tegra_probe(struct platform_device *pdev) platform->bypass_smmu = !device_is_iommuable(&pdev->dev); platform->disable_bigpage = platform->bypass_smmu; + platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close + = false; + platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close + = false; + + platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; + platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; + + platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_gfxp = + debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR, + platform->debugfs, + &platform->g->gr.t18x.ctx_vars.force_preemption_gfxp); + + platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_cilp = + debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR, + platform->debugfs, + &platform->g->gr.t18x.ctx_vars.force_preemption_cilp); + + platform->g->gr.t18x.ctx_vars.debugfs_dump_ctxsw_stats = + debugfs_create_bool("dump_ctxsw_stats_on_channel_close", + S_IRUGO|S_IWUSR, + platform->debugfs, + &platform->g->gr.t18x. + ctx_vars.dump_ctxsw_stats_on_channel_close); return 0; } -- cgit v1.2.2 From 6a981bbe078fd279ce87c64c47b2457eac998dc7 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 18 Aug 2015 12:49:38 +0530 Subject: gpu: nvgpu: gp10b: Use clock API to enable clocks Use CCF to enable GPU clocks. Keep an extra reference to prevent runtime PM callbacks from disabling clocks while GPU is powered up. Bug 1673672 Change-Id: I8c34be5ec338fedea62aa3e05bd6bed0513bf1b6 Signed-off-by: Mahantesh Kumbar Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/788814 Reviewed-by: Automatic_Commit_Validation_User Reviewed-on: http://git-master/r/785265 --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 66 +++++++++++++++++++++++++- 1 file changed, 64 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 2f81378d1..fbca62b0d 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -28,6 +28,49 @@ #include "gk20a/gk20a.h" #include "platform_tegra.h" +static struct { + char *name; + unsigned long default_rate; +} tegra_gp10b_clocks[] = { + {"gpu", 1900000000}, + {"gpu_sys", 204000000} }; + +/* + * gp10b_tegra_get_clocks() + * + * This function finds clocks in tegra platform and populates + * the clock information to gp10b platform data. + */ + +static int gp10b_tegra_get_clocks(struct platform_device *pdev) +{ + struct gk20a_platform *platform = platform_get_drvdata(pdev); + struct gk20a *g = get_gk20a(pdev); + struct device *dev = dev_from_gk20a(g); + int i; + + if (tegra_platform_is_linsim()) + return 0; + + platform->num_clks = 0; + for (i = 0; i < ARRAY_SIZE(tegra_gp10b_clocks); i++) { + long rate = tegra_gp10b_clocks[i].default_rate; + struct clk *c; + + c = clk_get(dev, tegra_gp10b_clocks[i].name); + if (IS_ERR(c)) { + gk20a_err(&pdev->dev, "cannot get clock %s", + tegra_gp10b_clocks[i].name); + } else { + clk_set_rate(c, rate); + platform->clk[i] = c; + } + } + platform->num_clks = i; + + return 0; +} + static int gp10b_tegra_probe(struct platform_device *pdev) { struct gk20a_platform *platform = gk20a_get_platform(pdev); @@ -77,6 +120,9 @@ static int gp10b_tegra_probe(struct platform_device *pdev) platform->debugfs, &platform->g->gr.t18x. ctx_vars.dump_ctxsw_stats_on_channel_close); + + gp10b_tegra_get_clocks(pdev); + return 0; } @@ -97,17 +143,33 @@ static bool gp10b_tegra_is_railgated(struct platform_device *pdev) static int gp10b_tegra_railgate(struct platform_device *pdev) { + struct gk20a_platform *platform = gk20a_get_platform(pdev); + if (!tegra_platform_is_linsim() && - tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) + tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) { + int i; + for (i = 0; i < platform->num_clks; i++) { + if (platform->clk[i]) + clk_disable_unprepare(platform->clk[i]); + } tegra_powergate_partition(TEGRA_POWERGATE_GPU); + } return 0; } static int gp10b_tegra_unrailgate(struct platform_device *pdev) { int ret = 0; - if (!tegra_platform_is_linsim()) + struct gk20a_platform *platform = gk20a_get_platform(pdev); + + if (!tegra_platform_is_linsim()) { + int i; ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); + for (i = 0; i < platform->num_clks; i++) { + if (platform->clk[i]) + clk_prepare_enable(platform->clk[i]); + } + } return ret; } -- cgit v1.2.2 From 5cc41d07919b577316271f6b51efbebaccb3881d Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 21 Sep 2015 14:57:54 -0700 Subject: gpu: nvgpu: ELPG init & statistics update - Required init param to start elpg - change in statistics dump Bug 1684939 Change-Id: Icc482c08303d0870ec2e1c18a845074968b15e77 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/802455 Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu Reviewed-by: Terje Bergstrom Reviewed-on: http://git-master/r/806194 Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 56 +++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index a4d7a0f71..6832bf410 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -202,6 +202,60 @@ static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) return 0; } +static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + gk20a_dbg_fn(""); + + if (status != 0) { + gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted"); + /* TBD: disable ELPG */ + return; + } + + gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n", + msg->msg.pg.msg_type); + + return; +} + +static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_PG; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_pg_cmd_gr_init_param); + cmd.cmd.pg.gr_init_param.cmd_type = + PMU_PG_CMD_ID_PG_PARAM; + cmd.cmd.pg.gr_init_param.sub_cmd_id = + PMU_PG_PARAM_CMD_GR_INIT_PARAM; + cmd.cmd.pg.gr_init_param.featuremask = + grfeaturemask; + + gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask); + gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, + pmu_handle_gr_param_msg, pmu, &seq, ~0); + + return 0; +} +void gp10b_pmu_elpg_statistics(struct gk20a *g, + u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_pg_stats_v1 stats; + + pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, + (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0); + + *ingating_time = stats.total_sleep_timeus; + *ungating_time = stats.total_nonsleep_timeus; + *gating_cnt = stats.entry_count; +} + static int gp10b_pmu_setup_elpg(struct gk20a *g) { int ret = 0; @@ -249,4 +303,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; + gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; + gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; } -- cgit v1.2.2 From 431f1c4e4ab2b3e0641439aedd2bd347a1c62b45 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 1 Sep 2015 13:54:49 -0700 Subject: gpu: nvgpu: gp10b: Fix CB size for GfxP Program correct CB size for GfxP channels. We were accidentally using the context image size. Change-Id: I273215256e41e89b7d76f3294a73641804beeb79 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/792713 Reviewed-on: http://git-master/r/806188 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index e727ee999..b614da64c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -902,7 +902,7 @@ static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, int attrBufferSize; if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) - attrBufferSize = gr_ctx->t18x.preempt_ctxsw_buffer.size; + attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size; else attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); -- cgit v1.2.2 From d877481b1b81aa0ef4f75165136dbd6f5cdca3bc Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 7 Sep 2015 08:24:09 -0700 Subject: gpu: nvgpu: gp10b: Fix steady state beta CB size We program the default steady state beta CB size. The default is for deep binning, but we've disabled deep binning. As result steady state CB size was left too high. Bug 1683535 Change-Id: I17029078d9c83e55eec6faacfc83c6d812f8c3c0 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/795306 Reviewed-on: http://git-master/r/806189 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index b614da64c..dff8adaeb 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -113,7 +113,7 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + proj_ppc_in_gpc_stride_v() * ppc_index, - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(), + gr->attrib_cb_default_size, patch); attrib_offset_in_chunk += gr->attrib_cb_size * -- cgit v1.2.2 From 2af4156a3aad40cd0cc9afdb3c774b604cbb1d01 Mon Sep 17 00:00:00 2001 From: Leonid Moiseichuk Date: Wed, 2 Sep 2015 10:41:23 +0300 Subject: gpu: nvgpu: enabling cyclestats for gp10b Enabling cyclestats and cyclestats snapshot support for gp10b (t186) devices. Bug 1674079 Change-Id: I2e14801de3c61d180630bb9dcd2c607749814893 Signed-off-by: Leonid Moiseichuk Reviewed-on: http://git-master/r/792953 Reviewed-on: http://git-master/r/806190 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index dff8adaeb..c339b14dc 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -977,6 +977,18 @@ static int gr_gp10b_init_fs_state(struct gk20a *g) return gr_gm20b_ctx_state_floorsweep(g); } +static void gr_gp10b_init_cyclestats(struct gk20a *g) +{ +#if defined(CONFIG_GK20A_CYCLE_STATS) + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; + g->gpu_characteristics.flags |= + NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; +#else + (void)g; +#endif +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -1004,4 +1016,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gr_gp10b_update_ctxsw_preemption_mode; gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs; gops->gr.wait_empty = gr_gp10b_wait_empty; + gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; } -- cgit v1.2.2 From 922f4da1ae1c7466d0782d959fbade63a5971a73 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 2 Oct 2015 17:27:32 +0530 Subject: gpu: nvgpu: fix sparse warning fix below sparse warning drivers/gpu/nvgpu/gm20b/gr_gm20b.c:1055:6: warning: symbol 'gr_gm20b_enable_cde_in_fecs' was not declared. Should it be static? Bug 200088648 Change-Id: I862100d76f2ed5669d15a8f3b8cb9211df7f98ee Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/810394 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Amit Sharma (SW-TEGRA) GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 6832bf410..77727ff25 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -242,7 +242,7 @@ static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) return 0; } -void gp10b_pmu_elpg_statistics(struct gk20a *g, +static void gp10b_pmu_elpg_statistics(struct gk20a *g, u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) { struct pmu_gk20a *pmu = &g->pmu; -- cgit v1.2.2 From 55ce7fdf8ed1f9364e5edc6d0ae9a0a5e43ab1b1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 21 Sep 2015 11:10:30 -0700 Subject: gpu: nvgpu: gp10b: Implement SetCoalesceBufferSize Implement method for setting the coalesce buffer size at runtime. Bug 1681992 Change-Id: Ice6c00a27f642c2d68d6cd0e30c12df2e48f5374 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/802366 (cherry picked from commit bd763bc8a16b80ccc8f79b2229eccf2fe2417611) Reviewed-on: http://git-master/r/808239 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 17 +++++++++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 1 + drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 12 ++++++++++++ 3 files changed, 30 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index c339b14dc..1a50d29a6 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -290,6 +290,20 @@ static void gr_gp10b_set_go_idle_timeout(struct gk20a *g, u32 data) gk20a_writel(g, gr_fe_go_idle_timeout_r(), data); } +static void gr_gp10b_set_coalesce_buffer_size(struct gk20a *g, u32 data) +{ + u32 val; + + gk20a_dbg_fn(""); + + val = gk20a_readl(g, gr_gpcs_tc_debug0_r()); + val = set_field(val, gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(), + gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(data)); + gk20a_writel(g, gr_gpcs_tc_debug0_r(), val); + + gk20a_dbg_fn("done"); +} + static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, u32 class_num, u32 offset, u32 data) { @@ -319,6 +333,9 @@ static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, case NVC097_SET_GO_IDLE_TIMEOUT: gr_gp10b_set_go_idle_timeout(g, data); break; + case NVC097_SET_COALESCE_BUFFER_SIZE: + gr_gp10b_set_coalesce_buffer_size(g, data); + break; default: goto fail; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 370e0ea37..bf49ba6f7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -27,6 +27,7 @@ enum { #define NVC097_SET_GO_IDLE_TIMEOUT 0x022c #define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc +#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028 #define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 #define NVC097_SET_SHADER_EXCEPTIONS 0x1528 #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 6e4f7d1ae..e33f07342 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -3786,4 +3786,16 @@ static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) { return 0x1000; } +static inline u32 gr_gpcs_tc_debug0_r(void) +{ + return 0x00418708; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) +{ + return (v & 0xff) << 0; +} +static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) +{ + return 0xff << 0; +} #endif -- cgit v1.2.2 From e84d70db74b1b0d50f2e91e49d97c9066c4a77a7 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 10 Sep 2015 21:54:35 +0530 Subject: gpu: nvgpu: implement reset_assert/deassert for gp10b Implement platform specific reset_assert() and reset_deassert() calls for gp10b These APIs will in turn will use reset_control APIs to do their work Also, set force_reset_in_do_idle = true for gp10b, since railgating is not supported yet Bug 200137963 Change-Id: I2c0fe1273d3ecfd0c46704a44374712052ff51d6 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/797150 (cherry picked from commit 6ac04ca84cee8a4d3b089678c81534799880712d) Reviewed-on: http://git-master/r/808240 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 32 ++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index fbca62b0d..a4348f6cf 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" #include "platform_tegra.h" @@ -178,6 +179,32 @@ static int gp10b_tegra_suspend(struct device *dev) return 0; } +static int gp10b_tegra_reset_assert(struct platform_device *dev) +{ + struct gk20a_platform *platform = gk20a_get_platform(dev); + int ret = 0; + + if (!platform->reset_control) + return -EINVAL; + + ret = reset_control_assert(platform->reset_control); + + return ret; +} + +static int gp10b_tegra_reset_deassert(struct platform_device *dev) +{ + struct gk20a_platform *platform = gk20a_get_platform(dev); + int ret = 0; + + if (!platform->reset_control) + return -EINVAL; + + ret = reset_control_deassert(platform->reset_control); + + return ret; +} + struct gk20a_platform t18x_gpu_tegra_platform = { .has_syncpoints = true, @@ -209,4 +236,9 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .secure_alloc = gk20a_tegra_secure_alloc, .secure_page_alloc = gk20a_tegra_secure_page_alloc, + + .reset_assert = gp10b_tegra_reset_assert, + .reset_deassert = gp10b_tegra_reset_deassert, + + .force_reset_in_do_idle = true, }; -- cgit v1.2.2 From 79a72c265f5d5cb6165e273467fbbaf5aa6ed59a Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 10 Sep 2015 17:56:39 +0530 Subject: gpu: nvgpu: implement set_gpc_tpc_mask for gp10b Bug 200137963 Change-Id: Ibd09b206620e6d6826586bb40e1125fc178dd8e4 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/797151 (cherry picked from commit 343c4704564f4b4f22a943a94e66d2c83f63a28f) Reviewed-on: http://git-master/r/808241 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 1a50d29a6..d61ac5bb8 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -15,6 +15,7 @@ #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ #include +#include #include "gk20a/gr_gk20a.h" @@ -1006,6 +1007,19 @@ static void gr_gp10b_init_cyclestats(struct gk20a *g) #endif } +static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) +{ + tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); + tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); + + if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) + tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); + else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) + tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); + else + tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -1034,4 +1048,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs; gops->gr.wait_empty = gr_gp10b_wait_empty; gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; + gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask; } -- cgit v1.2.2 From 048116c4c0aa09d16cd6aa509e0e84b5fac74fd3 Mon Sep 17 00:00:00 2001 From: Jussi Rasanen Date: Tue, 29 Sep 2015 13:21:05 +0300 Subject: gpu: nvgpu: fix ctag computation overflow with 8GB Bug 1689976 Change-Id: Ibf1c296fac4f2a2c6fcf062cbd80b3526a4fd4ed Signed-off-by: Jussi Rasanen Reviewed-on: http://git-master/r/806588 (cherry picked from commit 24b57989dc9636b41004bac32ee56dce90318350) Reviewed-on: http://git-master/r/808242 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 0c76abb52..ae9c5c7e3 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -152,7 +152,7 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, struct scatterlist **sgl, u64 *offset, u64 *iova, - u32 kind_v, u32 *ctag, + u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv) { @@ -193,7 +193,7 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, struct scatterlist **sgl, u64 *offset, u64 *iova, - u32 kind_v, u32 *ctag, + u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv) { @@ -249,13 +249,13 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, struct scatterlist **sgl, u64 *offset, u64 *iova, - u32 kind_v, u32 *ctag, + u32 kind_v, u64 *ctag, bool cacheable, bool unmapped_pte, int rw_flag, bool sparse, bool priv) { struct gk20a *g = vm->mm->g; u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; - u32 ctag_granularity = g->ops.fb.compression_page_size(g); + u64 ctag_granularity = g->ops.fb.compression_page_size(g); u32 pte_w[2] = {0, 0}; /* invalid pte */ gk20a_dbg_fn(""); @@ -274,7 +274,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) | gmmu_new_pte_kind_f(kind_v) | - gmmu_new_pte_comptagline_f(*ctag / ctag_granularity); + gmmu_new_pte_comptagline_f((u32)(*ctag / ctag_granularity)); if (rw_flag == gk20a_mem_flag_read_only) pte_w[0] |= gmmu_new_pte_read_only_true_f(); @@ -287,7 +287,7 @@ static int update_gmmu_pte_locked(struct vm_gk20a *vm, " ctag=%d vol=%d" " [0x%08x, 0x%08x]", i, *iova, - kind_v, *ctag / ctag_granularity, !cacheable, + kind_v, (u32)(*ctag / ctag_granularity), !cacheable, pte_w[1], pte_w[0]); if (*ctag) -- cgit v1.2.2 From 1f92e446eefe3195f6909a1009fcb6782725808c Mon Sep 17 00:00:00 2001 From: Vijayakumar Date: Fri, 13 Feb 2015 17:11:37 +0530 Subject: gpu :nvgpu: gp10b: add ptimer scaling factor as 1x bug 1603226 t18x fixes ptimer bug and ticks at 1ns. Change-Id: I590c94957c93adf70263f81a0cdfcb8dc913639e Signed-off-by: Vijayakumar Reviewed-on: http://git-master/r/799989 (cherry picked from commit 44866e195113b0a44ed2513a81dcaaf079c2a5f1) Reviewed-on: http://git-master/r/707810 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index a4348f6cf..c28c71b56 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -216,6 +216,9 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .can_railgate = false, .enable_elpg = false, + /* ptimer scaling constant */ + .ptimerscaling10x = 10, + .probe = gp10b_tegra_probe, .late_probe = gp10b_tegra_late_probe, -- cgit v1.2.2 From aadf4c21df96525fa64c3c882cdada69e34caff3 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 25 Sep 2015 17:32:29 -0700 Subject: gpu: nvgpu: gp10b: update slcg xbar prod settings Bug 1689806 Change-Id: I98ca5fe006ecdf056ac45b15b2dc128929ea4fd5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/806115 (cherry picked from commit fc15b029187db4f2aba213e89672bd84b5d020cd) Reviewed-on: http://git-master/r/805482 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 70486c4a4..381ee8b12 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -84,6 +84,8 @@ static struct gpu_ops gp10b_ops = { gp10b_blcg_pwr_csb_load_gating_prod, .blcg_pmu_load_gating_prod = gp10b_blcg_pmu_load_gating_prod, + .blcg_xbar_load_gating_prod = + gp10b_blcg_xbar_load_gating_prod, .pg_gr_load_gating_prod = gr_gp10b_pg_gr_load_gating_prod, } -- cgit v1.2.2 From cc9bd2dc24f562e97a87641e7436594fd3b469f2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 29 Sep 2015 12:39:57 -0700 Subject: gpu: nvgpu: gp10b: Force always SMMU bypass Bug 1688709 Change-Id: If778034225dabbd0f9e6ff843ea6f06011c432bd Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/807030 (cherry picked from commit 32f03899ca689f6af12760afe04cf4c8e60ebba1) Reviewed-on: http://git-master/r/808243 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index c28c71b56..eb99a66ca 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -94,7 +94,7 @@ static int gp10b_tegra_probe(struct platform_device *pdev) } platform->g->host1x_dev = host1x_pdev; - platform->bypass_smmu = !device_is_iommuable(&pdev->dev); + platform->bypass_smmu = 1; platform->disable_bigpage = platform->bypass_smmu; platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close -- cgit v1.2.2 From b12163938a74d49146fe0c3aa10bba7c1a4549cc Mon Sep 17 00:00:00 2001 From: Matt Craighead Date: Tue, 6 Oct 2015 17:22:08 -0500 Subject: gpu: nvgpu: gp10b: skip powergate if no BPMP The powergating APIs only work if the BPMP is running. Skip these calls if it's not available, instead of relying on is_linsim, which doesn't work under all environments. Change-Id: I34325847b2ebf33c5db2f31111c57d22ed28ef53 Signed-off-by: Matt Craighead Reviewed-on: http://git-master/r/812415 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index eb99a66ca..559cad2eb 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -25,6 +25,7 @@ #include #include #include +#include #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" #include "platform_tegra.h" @@ -136,7 +137,7 @@ static bool gp10b_tegra_is_railgated(struct platform_device *pdev) { bool ret = false; - if (!tegra_platform_is_linsim()) + if (tegra_bpmp_running()) ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU); return ret; @@ -146,7 +147,7 @@ static int gp10b_tegra_railgate(struct platform_device *pdev) { struct gk20a_platform *platform = gk20a_get_platform(pdev); - if (!tegra_platform_is_linsim() && + if (tegra_bpmp_running() && tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) { int i; for (i = 0; i < platform->num_clks; i++) { @@ -163,7 +164,7 @@ static int gp10b_tegra_unrailgate(struct platform_device *pdev) int ret = 0; struct gk20a_platform *platform = gk20a_get_platform(pdev); - if (!tegra_platform_is_linsim()) { + if (tegra_bpmp_running()) { int i; ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); for (i = 0; i < platform->num_clks; i++) { -- cgit v1.2.2 From 23b6771d335bd60d13a6bf55e42ac9272d84406b Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 5 Oct 2015 11:48:20 +0530 Subject: gpu: nvgpu: set wdt timeout for gp10b set platform specific channel watchdog timeout to 5s for gp10b Bug 200133289 Change-Id: I4478463e22a8167c2fc1235dd9a80e069a27b47c Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/811509 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 559cad2eb..5dc8e33d5 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -220,6 +220,8 @@ struct gk20a_platform t18x_gpu_tegra_platform = { /* ptimer scaling constant */ .ptimerscaling10x = 10, + .ch_wdt_timeout_ms = 5000, + .probe = gp10b_tegra_probe, .late_probe = gp10b_tegra_late_probe, -- cgit v1.2.2 From 85eeb3e72cafb69c68897f8f57a144779be98a89 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 6 Oct 2015 09:37:11 -0700 Subject: gpu:nvgpu: gp10b: modify gpmu hw init Modify gpmu hwinit to take gp10b specific register offsets in non-secure GPMU boot path. Bug 1685722 Change-Id: Id6696fb20c4fd40ee1b168c952a438771721c792 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/812271 (cherry picked from commit b9408892dd08beca5f4b2e056287a2bc28ccff0e) Reviewed-on: http://git-master/r/813979 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 39 +++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 77727ff25..df515d1b6 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -286,6 +286,44 @@ static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) 0x0); } +static int gp10b_init_pmu_setup_hw1(struct gk20a *g) +{ + struct pmu_gk20a *pmu = &g->pmu; + int err; + + gk20a_dbg_fn(""); + + mutex_lock(&pmu->isr_mutex); + pmu_reset(pmu); + pmu->isr_enabled = true; + mutex_unlock(&pmu->isr_mutex); + + /* setup apertures - virtual */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), + pwr_fbif_transcfg_mem_type_virtual_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), + pwr_fbif_transcfg_mem_type_virtual_f()); + + /* setup apertures - physical */ + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_local_fb_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_coherent_sysmem_f()); + gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), + pwr_fbif_transcfg_mem_type_physical_f() | + pwr_fbif_transcfg_target_noncoherent_sysmem_f()); + + err = pmu_bootstrap(pmu); + if (err) + return err; + + gk20a_dbg_fn("done"); + return 0; + +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -299,6 +337,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; } + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; -- cgit v1.2.2 From a4f11aec293afe51f8fe47a7e4a77c537337261f Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 6 Oct 2015 16:07:57 -0700 Subject: gpu: nvgpu: gp10b: enable dma for firmware loading Bug 1692799 Change-Id: Idf825c954c646f649d85b8fa7f76b5b45150bfe5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/812442 (cherry picked from commit f72c0738238c3f9a034c6a8b064226f0d7d5dd63) Reviewed-on: http://git-master/r/813978 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c index b50698e07..b29562574 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c @@ -69,5 +69,5 @@ static bool gr_gp10b_is_firmware_defined(void) void gp10b_init_gr_ctx(struct gpu_ops *gops) { gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; - gops->gr_ctx.use_dma_for_fw_bootstrap = false; + gops->gr_ctx.use_dma_for_fw_bootstrap = true; } -- cgit v1.2.2 From fac90f3be96764595b357c64fa4e0c807d5f2f93 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 18 Sep 2015 14:44:36 -0700 Subject: gpu: nvgpu: gp10b: Fix pagepool max size If pagepool size equals max we should use zero. Add the comparison to do that. Bug 1686189 Change-Id: I15bd43663550b1089a726c0256b89f849c193e21 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/801526 (cherry picked from commit 9d89ea5ba345b19d2cff86130ba9d3c4c5f07e6e) Reviewed-on: http://git-master/r/815681 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index d61ac5bb8..c5f458160 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -684,6 +684,10 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; + + if (size == g->ops.gr.pagepool_default_size(g)) + size = gr_scc_pagepool_total_pages_hwmax_v(); + g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> -- cgit v1.2.2 From 82dad6e59c8f6c86ed2317afd7de8841d3e44456 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 18 Sep 2015 08:16:23 -0700 Subject: gpu: nvgpu: gp10b: Fix spill buffer size Spill buffer size is in chunks of 256B. Multiply the size by granularity to get the size in bytes. Bug 1686189 Change-Id: I0462293668322645bd1eab190c12faaeb6c316c1 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/801344 (cherry picked from commit 4bf6de7d9c9014a9eaeff56b19437d1841d7cfb0) Reviewed-on: http://git-master/r/815680 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 ++++-- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++ 2 files changed, 8 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index c5f458160..61ecddef7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -510,7 +510,8 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(); + gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * gr_scc_pagepool_total_pages_byte_granularity_v(); u32 betacb_size = g->gr.attrib_cb_default_size + @@ -694,7 +695,8 @@ static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); - size = gr_ctx->t18x.spill_ctxsw_buffer.size; + size = gr_ctx->t18x.spill_ctxsw_buffer.size / + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_swdx_rm_spill_buffer_addr_r(), diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index e33f07342..0aa68fa25 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -2510,6 +2510,10 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) { return 0x00000250; } +static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) +{ + return 0x00000100; +} static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) { return 0x00500ee0; -- cgit v1.2.2 From 55685f3747df9249167c235da473ebed54d97108 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Thu, 1 Oct 2015 10:38:32 -0700 Subject: gpu: nvgpu: gp10b: Report Pascal DMA copy class Announce supporting Pascal DMA copy class instead of Maxwell. Change-Id: Ic0b9d50e7423648c5573857142c86b8a8bc87e35 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/808140 (cherry picked from commit c779975d6b40ecb0780ae4167ab26aed4886c7a7) Reviewed-on: http://git-master/r/815679 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 381ee8b12..5222fca65 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -151,7 +151,7 @@ int gp10b_init_hal(struct gk20a *g) c->compute_class = PASCAL_COMPUTE_A; c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A; c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = MAXWELL_DMA_COPY_A; + c->dma_copy_class = PASCAL_DMA_COPY_A; return 0; } -- cgit v1.2.2 From f00dd883b699e9e874713fd71015d607cd5d9d1d Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 18 Sep 2015 14:55:39 -0700 Subject: gpu: nvgpu: gp10b: Fix beta CB sizing Handle beta CB sizing differences for GfxP versus WFI channels. Bug 1686189 Change-Id: Icc421eeb8305f7e4156a74c957662f19504ddad7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/801533 (cherry picked from commit 95b9ae4e5f3c29fdb97567d846b9d2139f1a8ec4) Reviewed-on: http://git-master/r/815682 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 46 +++++++++++++++++++++----------------- 1 file changed, 26 insertions(+), 20 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 61ecddef7..d2acba964 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -58,22 +58,28 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, struct channel_gk20a *c, bool patch) { struct gr_gk20a *gr = &g->gr; - struct channel_ctx_gk20a *ch_ctx = NULL; + struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; + struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; u32 attrib_offset_in_chunk = 0; u32 alpha_offset_in_chunk = 0; u32 pd_ab_max_output; u32 gpc_index, ppc_index; - u32 temp; - u32 cbm_cfg_size1, cbm_cfg_size2; + u32 temp, temp2; + u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate; + u32 attrib_size_in_chunk, cb_attrib_cache_size_init; gk20a_dbg_fn(""); - if (patch) { - int err; - ch_ctx = &c->ch_ctx; - err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); - if (err) - return err; + if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { + attrib_size_in_chunk = gr->attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + cb_attrib_cache_size_init = gr->attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + } else { + attrib_size_in_chunk = gr->attrib_cb_size; + cb_attrib_cache_size_init = gr->attrib_cb_default_size; } gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), @@ -94,17 +100,20 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { temp = proj_gpc_stride_v() * gpc_index; + temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index; for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; ppc_index++) { - cbm_cfg_size1 = gr->attrib_cb_default_size * + cbm_cfg_size_beta = cb_attrib_cache_size_init * + gr->pes_tpc_count[ppc_index][gpc_index]; + cbm_cfg_size_alpha = gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index]; - cbm_cfg_size2 = gr->alpha_cb_default_size * + cbm_cfg_size_steadystate = gr->attrib_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index]; gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size1, patch); + cbm_cfg_size_beta, patch); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + @@ -114,16 +123,16 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + proj_ppc_in_gpc_stride_v() * ppc_index, - gr->attrib_cb_default_size, + cbm_cfg_size_steadystate, patch); - attrib_offset_in_chunk += gr->attrib_cb_size * + attrib_offset_in_chunk += attrib_size_in_chunk * gr->pes_tpc_count[ppc_index][gpc_index]; gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size2, patch); + cbm_cfg_size_alpha, patch); gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + @@ -134,15 +143,12 @@ static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, gr->pes_tpc_count[ppc_index][gpc_index]; gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + gpc_index), - gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size1), + gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2), + gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate), patch); } } - if (patch) - gr_gk20a_ctx_patch_write_end(g, ch_ctx); - return 0; } -- cgit v1.2.2 From 8a58acd91869e319f5dd7bf2124105e2b63a33d2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Sun, 20 Sep 2015 17:14:29 -0700 Subject: gpu: nvgpu: gp10b: Make CB size and default size same We used to allocate 1.5x buffer size. This leads to memory waste, as we do not set the CB size via SW methods anymore. Bug 1686189 Change-Id: I45cbdeadc154f59b65138f99f50a72d97511cb78 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/801865 (cherry picked from commit 791f2fe03d16521206649ab90498443e91e284e2) Reviewed-on: http://git-master/r/815683 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index d2acba964..49ba21e0c 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -269,10 +269,8 @@ static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) struct gr_gk20a *gr = &g->gr; int size; - gr->attrib_cb_size = gr->attrib_cb_default_size - + (gr->attrib_cb_default_size >> 1); - gr->alpha_cb_size = gr->alpha_cb_default_size - + (gr->alpha_cb_default_size >> 1); + gr->attrib_cb_size = gr->attrib_cb_default_size; + gr->alpha_cb_size = gr->alpha_cb_default_size; gr->attrib_cb_size = min(gr->attrib_cb_size, gr_gpc0_ppc0_cbm_beta_cb_size_v_f(~0) / g->gr.tpc_count); -- cgit v1.2.2 From 6f434ba37ab272fb11446a7160794b75eb732064 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Mon, 12 Oct 2015 13:54:43 +0530 Subject: gpu: nvgpu: gp10b non-secure gpmu hw init call gp10b_init_pmu_setup_hw1 during non-secure boot only. Change-Id: Ia90474c7c04edd9be029d013f1da5f73de1b5326 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/815843 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index df515d1b6..57accfb0c 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -336,8 +336,8 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gm20b_init_nspmu_setup_hw1; gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; + gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; } - gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; gops->pmu.lspmuwprinitdone = false; gops->pmu.fecsbootstrapdone = false; -- cgit v1.2.2 From 1209dc518da473aaf343e4b83fade01ee07fb878 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 8 Oct 2015 11:32:47 -0700 Subject: gpu: nvgpu: gp10b: create fault buffer only once Create only one instance of replayable fault buffer mapping. Change-Id: Id766298f338ce54cfca7510cbb9e4528ef1945a3 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/814615 (cherry picked from commit 422d2ced384220668347dc8422876d75f6e8807d) Reviewed-on: http://git-master/r/817696 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c index ba91403ca..59af5cded 100644 --- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c @@ -33,11 +33,14 @@ int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) gk20a_dbg_fn(""); - err = gk20a_gmmu_alloc_map(vm, rbfb_size, &g->mm.bar2_desc); - if (err) { - dev_err(dev_from_gk20a(g), "%s Error in replayable fault buffer\n", - __func__); - return err; + if (!g->mm.bar2_desc.gpu_va) { + err = gk20a_gmmu_alloc_map(vm, rbfb_size, + &g->mm.bar2_desc); + if (err) { + dev_err(dev_from_gk20a(g), + "%s Error in replayable fault buffer\n", __func__); + return err; + } } addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12); addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va); @@ -47,7 +50,6 @@ int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) gk20a_writel(g, fifo_replay_fault_buffer_lo_r(), fifo_replay_fault_buffer_lo_base_f(addr_lo) | fifo_replay_fault_buffer_lo_enable_true_v()); - gk20a_dbg_fn("done"); return 0; } @@ -55,12 +57,14 @@ int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g) { struct vm_gk20a *vm = &g->mm.bar2.vm; + gk20a_gmmu_unmap_free(vm, &g->mm.bar2_desc); } u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g) { u32 get_idx = 0; + gk20a_dbg_fn(""); get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); -- cgit v1.2.2 From ecd0d76d129663cccd7b2a0103d9db9b30cffd93 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 9 Oct 2015 15:38:15 +0530 Subject: gpu: nvgpu: add h/w headers for pbdma_methods Bug 200134238 Change-Id: I263a12b7a3a74d1ab07bca03d5dda685b1e4f22f Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/815128 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 40 ++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index 977a8ee2f..d3f97a440 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -174,6 +174,10 @@ static inline u32 pbdma_pb_header_type_inc_f(void) { return 0x20000000; } +static inline u32 pbdma_pb_header_type_non_inc_f(void) +{ + return 0x60000000; +} static inline u32 pbdma_hdr_shadow_r(u32 i) { return 0x00040118 + i*8192; @@ -198,6 +202,42 @@ static inline u32 pbdma_method0_r(u32 i) { return 0x000400c0 + i*8192; } +static inline u32 pbdma_method0_fifo_size_v(void) +{ + return 0x00000004; +} +static inline u32 pbdma_method0_addr_f(u32 v) +{ + return (v & 0xfff) << 2; +} +static inline u32 pbdma_method0_addr_v(u32 r) +{ + return (r >> 2) & 0xfff; +} +static inline u32 pbdma_method0_subch_v(u32 r) +{ + return (r >> 16) & 0x7; +} +static inline u32 pbdma_method0_first_true_f(void) +{ + return 0x400000; +} +static inline u32 pbdma_method0_valid_true_f(void) +{ + return 0x80000000; +} +static inline u32 pbdma_method1_r(u32 i) +{ + return 0x000400c8 + i*8192; +} +static inline u32 pbdma_method2_r(u32 i) +{ + return 0x000400d0 + i*8192; +} +static inline u32 pbdma_method3_r(u32 i) +{ + return 0x000400d8 + i*8192; +} static inline u32 pbdma_data0_r(u32 i) { return 0x000400c4 + i*8192; -- cgit v1.2.2 From f4e0c704da2ed2cf52da174fcda716e39d43535c Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Wed, 7 Oct 2015 14:52:55 -0700 Subject: gpu: nvgpu: gp10b: Use PROD value for FE_GO_IDLE_TIMEOUT Add gp10b PROD value for FE_GO_IDLE_TIMEOUT. Use the PROD value written in gk20a_init_gr_setup_hw() instead of hard coding here. Change-Id: If3bd981c1c0d9cc8ad19c21c220b7de81fdb529e Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/813959 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 --- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 49ba21e0c..de6023b57 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -999,9 +999,6 @@ static int gr_gp10b_init_fs_state(struct gk20a *g) gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); - /* disable deep binning */ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), 0x800); - return gr_gm20b_ctx_state_floorsweep(g); } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 0aa68fa25..347e530d9 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -538,6 +538,10 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) { return 0x0; } +static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) +{ + return 0x7fffffff; +} static inline u32 gr_fe_object_table_r(u32 i) { return 0x00404200 + i*4; -- cgit v1.2.2 From a4fb2e7afdcca7fd625b3e0f434f86e25835ddc1 Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 12 Oct 2015 14:13:16 +0300 Subject: gpu: nvgpu: gp10b: Fix support for new color compression kinds Fix support for kinds C32_MS4_4CBRA and C64_MS4_4CBRA. They're both compressible and ZBC kinds, so mark them as such, too. Change-Id: Ide09ea79a885361ecfc3c188606799c6b2fbdd2e Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/816015 (cherry picked from commit 302b06b76aed5278286487225d6e7280b747d4b3) Reviewed-on: http://git-master/r/816014 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/fb_gp10b.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c index 3a143ceda..8b3b21530 100644 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c @@ -59,14 +59,18 @@ static bool gp10b_kind_compressible(u8 k) k <= gmmu_pte_kind_z16_ms8_2cz_v()) || k == gmmu_pte_kind_z16_ms16_2cz_v() || (k >= gmmu_pte_kind_z16_4cz_v() && - k <= gmmu_pte_kind_z16_ms16_4cz_v()); + k <= gmmu_pte_kind_z16_ms16_4cz_v()) || + k == gmmu_pte_kind_c32_ms4_4cbra_v() || + k == gmmu_pte_kind_c64_ms4_4cbra_v(); } static bool gp10b_kind_zbc(u8 k) { return (k >= gmmu_pte_kind_z16_2cz_v() && k <= gmmu_pte_kind_z16_ms8_2cz_v()) || - k == gmmu_pte_kind_z16_ms16_2cz_v(); + k == gmmu_pte_kind_z16_ms16_2cz_v() || + k == gmmu_pte_kind_c32_ms4_4cbra_v() || + k == gmmu_pte_kind_c64_ms4_4cbra_v(); } static void gp10b_init_kind_attr(void) -- cgit v1.2.2 From 96e6c093b857b52075b3707962bf6a622cd59d5e Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Tue, 29 Sep 2015 09:57:37 -0700 Subject: gpu: nvgpu: vgpu: add interface to alloc ctxsw buffers gp10b introduces support for preemption (GfxP and CILP). Add a new interface to allow allocating buffers needed to support this functionality. Bug 1677153 Change-Id: I8578a7b0a4327f3496d852eeb8be5fc778e2c225 Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/806963 Signed-off-by: Seema Khowala Reviewed-on: http://git-master/r/817039 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 169 +++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 9df29eeee..5edaa8192 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -11,10 +11,179 @@ * more details. */ +#include "vgpu/vgpu.h" #include "vgpu_gr_gp10b.h" #include "vgpu/gm20b/vgpu_gr_gm20b.h" +#include "gp10b/hw_gr_gp10b.h" + +static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, + struct gr_ctx_desc *gr_ctx) +{ + gk20a_dbg_fn(""); + + if (!gr_ctx || !gr_ctx->mem.gpu_va) + return; + + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); + vgpu_gr_free_gr_ctx(g, vm, gr_ctx); +} + +static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, + struct gr_ctx_desc **__gr_ctx, + struct vm_gk20a *vm, + u32 class, + u32 flags) +{ + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = + &msg.params.gr_bind_ctxsw_buffers; + struct gr_ctx_desc *gr_ctx = *__gr_ctx; + int err; + + gk20a_dbg_fn(""); + + WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX != + TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST); + + err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags); + if (err) + return err; + + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; + + if (class == PASCAL_COMPUTE_A && + g->gr.t18x.ctx_vars.force_preemption_cilp) + flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; + + if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { + u32 spill_size = + gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * + gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); + u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * + gr_scc_pagepool_total_pages_byte_granularity_v(); + u32 betacb_size = g->gr.attrib_cb_default_size + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * + gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * + g->gr.max_tpc_count; + struct mem_desc *desc; + + attrib_cb_size = ALIGN(attrib_cb_size, 128); + + gk20a_dbg_info("gfxp context preempt size=%d", + g->gr.t18x.ctx_vars.preempt_image_size); + gk20a_dbg_info("gfxp context spill size=%d", spill_size); + gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); + gk20a_dbg_info("gfxp context attrib cb size=%d", + attrib_cb_size); + + err = gk20a_gmmu_alloc_map(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &gr_ctx->t18x.preempt_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.preempt_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; + + err = gk20a_gmmu_alloc_map(vm, spill_size, + &gr_ctx->t18x.spill_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.spill_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; + + err = gk20a_gmmu_alloc_map(vm, pagepool_size, + &gr_ctx->t18x.pagepool_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = + desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; + + err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, + &gr_ctx->t18x.betacb_ctxsw_buffer); + if (err) { + err = -ENOMEM; + goto fail; + } + desc = &gr_ctx->t18x.betacb_ctxsw_buffer; + p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = + desc->gpu_va; + p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; + + gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; + } + + if (class == PASCAL_COMPUTE_A) { + if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) { + gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; + } else { + gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; + p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; + } + } + + if (gr_ctx->preempt_mode) { + msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; + msg.handle = platform->virt_handle; + p->handle = gr_ctx->virt_ctx; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + if (err || msg.ret) { + err = -ENOMEM; + goto fail; + } + } + + gk20a_dbg_fn("done"); + return err; + +fail: + vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); + return err; +} + +static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) +{ + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + int err; + + gk20a_dbg_fn(""); + + err = vgpu_gr_init_ctx_state(g); + if (err) + return err; + + vgpu_get_attribute(platform->virt_handle, + TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, + &g->gr.t18x.ctx_vars.preempt_image_size); + if (!g->gr.t18x.ctx_vars.preempt_image_size) + return -ENXIO; + + return 0; +} + void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) { vgpu_gm20b_init_gr_ops(gops); + gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx; + gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx; + gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state; } -- cgit v1.2.2 From 0d35f0b641419cacb36e4ed389236511b8fbf202 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 8 Oct 2015 09:41:49 -0700 Subject: gpu: nvgpu: gp10b: enable clock gating features Enable clock gating power features: slcg, blcg and elcg Bug 200144583 Reviewed-on: http://git-master/r/821149 (cherry picked from commit 1980d443c64e6660e3cd41b8908964c07459dcce) Change-Id: I6ce813552fa57d0fd14dd7ed6a3d9864c88dc58b Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/818636 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 5dc8e33d5..4ddc47fb4 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -216,6 +216,9 @@ struct gk20a_platform t18x_gpu_tegra_platform = { /* power management configuration */ .can_railgate = false, .enable_elpg = false, + .enable_blcg = true, + .enable_slcg = true, + .enable_elcg = true, /* ptimer scaling constant */ .ptimerscaling10x = 10, -- cgit v1.2.2 From b05d5cdbdeded06534d2b03bf27b22705ba81251 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 8 Oct 2015 10:12:46 -0700 Subject: gpu: nvgpu: gp10b: support to remove bar2 vm Implement function to support bar2 vm clean-up. Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/814573 Change-Id: If5d884e4e1ed87bec6284719d90e9e1963c69bed Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/815428 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index ae9c5c7e3..d3297e316 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -368,6 +368,15 @@ static void gp10b_mm_init_pdb(struct gk20a *g, void *inst_ptr, u64 pdb_addr) ram_in_page_dir_base_hi_f(pdb_addr_hi)); } +static void gp10b_remove_bar2_vm(struct gk20a *g) +{ + struct mm_gk20a *mm = &g->mm; + + gp10b_replayable_pagefault_buffer_deinit(g); + gk20a_remove_vm(&mm->bar2.vm, &mm->bar2.inst_block); +} + + void gp10b_init_mm(struct gpu_ops *gops) { gm20b_init_mm(gops); @@ -378,4 +387,5 @@ void gp10b_init_mm(struct gpu_ops *gops) gops->mm.get_iova_addr = gp10b_mm_iova_addr; gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; gops->mm.init_pdb = gp10b_mm_init_pdb; + gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm; } -- cgit v1.2.2 From f8926e9cf42e66bcabf051dd510cd7f2f8a1d963 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 22 Oct 2015 15:31:43 -0700 Subject: gpu: nvgpu: gp10b: update thermal programming Add required fileds and values for thermal slow-down settings in thermal header file and corrected thermal register programming with correct values. Bug 1695567 Reviewed-on: http://git-master/r/822200 (cherry picked from commit 859d1bda6a059b321d859c887fab8d51d2caa981) Change-Id: Id90ebd46bc3d6e4284a91e7f2b775d78502a3eca Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/823013 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 + drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 98 +++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/therm_gp10b.c | 46 +++++++++++++++ drivers/gpu/nvgpu/gp10b/therm_gp10b.h | 19 +++++++ 5 files changed, 166 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/therm_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/therm_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index ad1983278..f34d836d6 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_GK20A) += \ rpfb_gp10b.o \ gp10b_gating_reglist.o \ regops_gp10b.o \ - cde_gp10b.o + cde_gp10b.o \ + therm_gp10b.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 5222fca65..544be96bb 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -32,6 +32,7 @@ #include "gp10b/gp10b_gating_reglist.h" #include "gp10b/regops_gp10b.h" #include "gp10b/cde_gp10b.h" +#include "gp10b/therm_gp10b.h" #include "gm20b/gr_gm20b.h" #include "gm20b/fifo_gm20b.h" @@ -144,6 +145,7 @@ int gp10b_init_hal(struct gk20a *g) gk20a_init_debug_ops(gops); gp10b_init_regops(gops); gp10b_init_cde_ops(gops); + gp10b_init_therm_ops(gops); gops->name = "gp10b"; c->twod_class = FERMI_TWOD_A; diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h index 25eecb702..aed754817 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -54,18 +54,114 @@ static inline u32 therm_use_a_r(void) { return 0x00020798; } +static inline u32 therm_use_a_ext_therm_0_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_use_a_ext_therm_1_enable_f(void) +{ + return 0x2; +} +static inline u32 therm_use_a_ext_therm_2_enable_f(void) +{ + return 0x4; +} static inline u32 therm_evt_ext_therm_0_r(void) { return 0x00020700; } +static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) +{ + return 0x00000003; +} static inline u32 therm_evt_ext_therm_1_r(void) { return 0x00020704; } +static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) +{ + return 0x00000003; +} static inline u32 therm_evt_ext_therm_2_r(void) { return 0x00020708; } +static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) +{ + return 0x00000003; +} +static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) +{ + return (v & 0x3) << 30; +} +static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) +{ + return 0x00000000; +} +static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) +{ + return 0x00000001; +} +static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) +{ + return 0x00000002; +} +static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) +{ + return 0x00000003; +} static inline u32 therm_weight_1_r(void) { return 0x00020024; diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c new file mode 100644 index 000000000..471edb872 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c @@ -0,0 +1,46 @@ +/* + * drivers/gpu/nvgpu/gm20b/therm_gk20a.c + * + * GP10B Therm + * + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "hw_therm_gp10b.h" + +static int gp10b_init_therm_setup_hw(struct gk20a *g) +{ + gk20a_dbg_fn(""); + + /* program NV_THERM registers */ + gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() | + therm_use_a_ext_therm_1_enable_f() | + therm_use_a_ext_therm_2_enable_f()); + gk20a_writel(g, therm_evt_ext_therm_0_r(), + therm_evt_ext_therm_0_slow_factor_f( + therm_evt_ext_therm_0_slow_factor_init_v())); + gk20a_writel(g, therm_evt_ext_therm_1_r(), + therm_evt_ext_therm_1_slow_factor_f( + therm_evt_ext_therm_1_slow_factor_init_v())); + gk20a_writel(g, therm_evt_ext_therm_2_r(), + therm_evt_ext_therm_2_slow_factor_f( + therm_evt_ext_therm_2_slow_factor_init_v())); + + return 0; +} + +void gp10b_init_therm_ops(struct gpu_ops *gops) +{ + gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw; + +} diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/therm_gp10b.h new file mode 100644 index 000000000..18c102fe4 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef THERM_GP10B_H +#define THERM_GP10B_H + +struct gpu_ops; +void gp10b_init_therm_ops(struct gpu_ops *gops); + +#endif /* THERM_GP10B_H */ -- cgit v1.2.2 From c2707054192b058eec24a52c7f586b030f9ff007 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 15 Jun 2015 18:09:47 -0700 Subject: gpu: nvgpu: gp10b: Implement sparse PDEs Change-Id: I260958d8dea1b445f91b8d15bf76d5321bdc76d1 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/758653 --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index d3297e316..b5ea5d684 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -157,17 +157,18 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, int rw_flag, bool sparse, bool priv) { u64 pte_addr = 0; - u64 pde_addr = 0; struct gk20a_mm_entry *pte = parent->entries + i; u32 pde_v[2] = {0, 0}; u32 *pde; gk20a_dbg_fn(""); - pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v(); - pde_addr = sg_phys(parent->sgt->sgl); + if (!sparse) + pte_addr = sg_phys(pte->sgt->sgl) + >> gmmu_new_pde_address_shift_v(); - pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); + pde_v[0] |= sparse ? gmmu_new_pde_aperture_invalid_f() + : gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); pde_v[0] |= gmmu_new_pde_vol_true_f(); pde_v[1] |= pte_addr >> 24; @@ -204,9 +205,12 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, u32 *pde; gk20a_dbg_fn(""); + gk20a_dbg(gpu_dbg_pte, "entry %p\n", entry); - small_valid = entry->size && entry->pgsz == gmmu_page_size_small; - big_valid = entry->size && entry->pgsz == gmmu_page_size_big; + small_valid = !sparse && entry->size + && entry->pgsz == gmmu_page_size_small; + big_valid = !sparse && entry->size + && entry->pgsz == gmmu_page_size_big; if (small_valid) pte_addr_small = sg_phys(entry->sgt->sgl) @@ -230,6 +234,11 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, pde_v[1] |= pte_addr_big >> 28; } + if (sparse) { + pde_v[0] |= gmmu_new_dual_pde_aperture_big_invalid_f(); + pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); + } + pde = pde0_from_index(pte, i); gk20a_mem_wr32(pde, 0, pde_v[0]); -- cgit v1.2.2 From 4760336257165cfb7c0dfda082035861cf6097c2 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 16 Oct 2015 12:38:35 -0700 Subject: gpu: nvgpu: gp10b: set ptimer source frequency Set platform data with ptimer source frequency. Removed ptimerscaling10x platform data, and use ptimer source frequency to calculate ptimerscaling factor. Reviewed-on: http://git-master/r/819031 (cherry picked from commit 6849603024943184b0463233bedd95934c353663) Change-Id: I14b0735fcb602cda2e692f6b842a5ecf469ab724 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/827301 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 4ddc47fb4..c08202ec1 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -220,8 +220,8 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .enable_slcg = true, .enable_elcg = true, - /* ptimer scaling constant */ - .ptimerscaling10x = 10, + /* ptimer src frequency in hz*/ + .ptimer_src_freq = 31250000, .ch_wdt_timeout_ms = 5000, -- cgit v1.2.2 From 07ff983f931c8bc3d5982f1f03d93e9da578e028 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 9 Nov 2015 09:06:37 -0800 Subject: Revert "gpu: nvgpu: gp10b: Implement sparse PDEs" This reverts commit c2707054192b058eec24a52c7f586b030f9ff007. It introduces regression in T124. Bug 1702063 Signed-off-by: Terje Bergstrom Change-Id: I8516c0bfe129bb1ac3d7a1983846061df8ae967b Reviewed-on: http://git-master/r/830787 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index b5ea5d684..d3297e316 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -157,18 +157,17 @@ static int update_gmmu_pde3_locked(struct vm_gk20a *vm, int rw_flag, bool sparse, bool priv) { u64 pte_addr = 0; + u64 pde_addr = 0; struct gk20a_mm_entry *pte = parent->entries + i; u32 pde_v[2] = {0, 0}; u32 *pde; gk20a_dbg_fn(""); - if (!sparse) - pte_addr = sg_phys(pte->sgt->sgl) - >> gmmu_new_pde_address_shift_v(); + pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v(); + pde_addr = sg_phys(parent->sgt->sgl); - pde_v[0] |= sparse ? gmmu_new_pde_aperture_invalid_f() - : gmmu_new_pde_aperture_video_memory_f(); + pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); pde_v[0] |= gmmu_new_pde_vol_true_f(); pde_v[1] |= pte_addr >> 24; @@ -205,12 +204,9 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, u32 *pde; gk20a_dbg_fn(""); - gk20a_dbg(gpu_dbg_pte, "entry %p\n", entry); - small_valid = !sparse && entry->size - && entry->pgsz == gmmu_page_size_small; - big_valid = !sparse && entry->size - && entry->pgsz == gmmu_page_size_big; + small_valid = entry->size && entry->pgsz == gmmu_page_size_small; + big_valid = entry->size && entry->pgsz == gmmu_page_size_big; if (small_valid) pte_addr_small = sg_phys(entry->sgt->sgl) @@ -234,11 +230,6 @@ static int update_gmmu_pde0_locked(struct vm_gk20a *vm, pde_v[1] |= pte_addr_big >> 28; } - if (sparse) { - pde_v[0] |= gmmu_new_dual_pde_aperture_big_invalid_f(); - pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); - } - pde = pde0_from_index(pte, i); gk20a_mem_wr32(pde, 0, pde_v[0]); -- cgit v1.2.2 From bd36578fadd272813a69245c6c837b3145c75f72 Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 12 Oct 2015 15:24:25 -0700 Subject: gpu: nvgpu: vgpu: set correct page size index for gp10b VM server only know big page and small page, so convert gmmu_page_size_kernel to according page size index. JIRA VFND-890 Change-Id: Id1f932752b8ca33d14635ac9d71019364aa89dc4 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/816359 (cherry picked from commit 5bfc4a2a55889f5457bd34aa06861c042ee67421) Reviewed-on: http://git-master/r/827131 GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c index 0a769e944..3a286249c 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c @@ -134,6 +134,19 @@ static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, else prot = TEGRA_VGPU_MAP_PROT_NONE; + if (pgsz_idx == gmmu_page_size_kernel) { + if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { + pgsz_idx = gmmu_page_size_small; + } else if (page_size == + vm->gmmu_page_sizes[gmmu_page_size_big]) { + pgsz_idx = gmmu_page_size_big; + } else { + gk20a_err(d, "invalid kernel page size %d\n", + page_size); + goto fail; + } + } + msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; msg.handle = platform->virt_handle; p->handle = vm->handle; -- cgit v1.2.2 From fb9b92ec8cba3356b91caeb4fac47d7ab83a60a0 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 Nov 2015 08:33:15 -0800 Subject: gpu: nvgpu: gp10b: Add L2 clean comptags regs Bug 1698618 Change-Id: I5bad939d94171d2296897260043f0e67e43802e7 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/829097 (cherry picked from commit a067cfeb8dda03641ba981d86bef93fa9041e18e) Reviewed-on: http://git-master/r/829414 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu Tested-by: Seshendra Gadagottu GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h | 42 +++++++++++++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h index b8e236b8f..f442991e0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -114,6 +114,46 @@ static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) { return 0x00000001; } +static inline u32 flush_clean_comptags_r(void) +{ + return 0x0007000c; +} +static inline u32 flush_clean_comptags_pending_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 flush_clean_comptags_pending_empty_v(void) +{ + return 0x00000000; +} +static inline u32 flush_clean_comptags_pending_empty_f(void) +{ + return 0x0; +} +static inline u32 flush_clean_comptags_pending_busy_v(void) +{ + return 0x00000001; +} +static inline u32 flush_clean_comptags_pending_busy_f(void) +{ + return 0x1; +} +static inline u32 flush_clean_comptags_outstanding_v(u32 r) +{ + return (r >> 1) & 0x1; +} +static inline u32 flush_clean_comptags_outstanding_false_v(void) +{ + return 0x00000000; +} +static inline u32 flush_clean_comptags_outstanding_false_f(void) +{ + return 0x0; +} +static inline u32 flush_clean_comptags_outstanding_true_v(void) +{ + return 0x00000001; +} static inline u32 flush_fb_flush_r(void) { return 0x00070000; -- cgit v1.2.2 From 8d0d393b84f81055b28bec1af75507eced211edc Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Tue, 3 Nov 2015 11:44:14 -0500 Subject: gpu: nvgpu: gp10b: map GfxP buffers as GPU cacheable Some of the allocated buffers are used during normal graphics processing. Mark them as GPU cacheable to improve performance. Bug 1695718 Change-Id: I71d5d1538516e966526abe5e38a557776321597f Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/827087 (cherry picked from commit 60b40ac144c94e24a2c449c8be937edf8865e1ed) Reviewed-on: http://git-master/r/828493 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 51 +++++++++++++++++++++++----- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 2 ++ drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 21 +++++++----- 3 files changed, 57 insertions(+), 17 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index de6023b57..c801a2b89 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -18,6 +18,7 @@ #include #include "gk20a/gr_gk20a.h" +#include "gk20a/semaphore_gk20a.h" #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ #include "gp10b/gr_gp10b.h" @@ -492,6 +493,36 @@ static int gr_gp10b_init_ctx_state(struct gk20a *g) return 0; } +int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, + struct mem_desc *mem) +{ + int err; + + gk20a_dbg_fn(""); + + err = gk20a_gmmu_alloc_attr(vm->mm->g, 0, size, mem); + if (err) + return err; + + mem->gpu_va = gk20a_gmmu_map(vm, + &mem->sgt, + size, + NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, + gk20a_mem_flag_none, + false); + + if (!mem->gpu_va) { + err = -ENOMEM; + goto fail_free; + } + + return 0; + +fail_free: + gk20a_gmmu_free(vm->mm->g, mem); + return err; +} + static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, u32 class, @@ -530,32 +561,36 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size); gk20a_dbg_info("gfxp context attrib_cb_size=%d", attrib_cb_size); - err = gk20a_gmmu_alloc_map(vm, g->gr.t18x.ctx_vars.preempt_image_size, - &(*gr_ctx)->t18x.preempt_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &(*gr_ctx)->t18x.preempt_ctxsw_buffer); if (err) { gk20a_err(dev_from_gk20a(vm->mm->g), "cannot allocate preempt buffer"); goto fail_free_gk20a_ctx; } - err = gk20a_gmmu_alloc_map(vm, spill_size, - &(*gr_ctx)->t18x.spill_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + spill_size, + &(*gr_ctx)->t18x.spill_ctxsw_buffer); if (err) { gk20a_err(dev_from_gk20a(vm->mm->g), "cannot allocate spill buffer"); goto fail_free_preempt; } - err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, - &(*gr_ctx)->t18x.betacb_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + attrib_cb_size, + &(*gr_ctx)->t18x.betacb_ctxsw_buffer); if (err) { gk20a_err(dev_from_gk20a(vm->mm->g), "cannot allocate beta buffer"); goto fail_free_spill; } - err = gk20a_gmmu_alloc_map(vm, pagepool_size, - &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + pagepool_size, + &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); if (err) { gk20a_err(dev_from_gk20a(vm->mm->g), "cannot allocate page pool"); diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index bf49ba6f7..62b70a221 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -33,6 +33,8 @@ enum { #define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 void gp10b_init_gr(struct gpu_ops *ops); +int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, + struct mem_desc *mem); struct gr_t18x { struct { diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index 5edaa8192..c5c53b58e 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -84,9 +84,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, gk20a_dbg_info("gfxp context attrib cb size=%d", attrib_cb_size); - err = gk20a_gmmu_alloc_map(vm, - g->gr.t18x.ctx_vars.preempt_image_size, - &gr_ctx->t18x.preempt_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + g->gr.t18x.ctx_vars.preempt_image_size, + &gr_ctx->t18x.preempt_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; @@ -95,8 +95,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; - err = gk20a_gmmu_alloc_map(vm, spill_size, - &gr_ctx->t18x.spill_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + spill_size, + &gr_ctx->t18x.spill_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; @@ -105,8 +106,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; - err = gk20a_gmmu_alloc_map(vm, pagepool_size, - &gr_ctx->t18x.pagepool_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + pagepool_size, + &gr_ctx->t18x.pagepool_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; @@ -116,8 +118,9 @@ static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, desc->gpu_va; p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; - err = gk20a_gmmu_alloc_map(vm, attrib_cb_size, - &gr_ctx->t18x.betacb_ctxsw_buffer); + err = gr_gp10b_alloc_buffer(vm, + attrib_cb_size, + &gr_ctx->t18x.betacb_ctxsw_buffer); if (err) { err = -ENOMEM; goto fail; -- cgit v1.2.2 From dba641eac691e5002e88f4541126c8ad2a460b58 Mon Sep 17 00:00:00 2001 From: Alex Waterman Date: Tue, 29 Sep 2015 10:13:18 -0700 Subject: arm64: tegra: dts: Use new SID dt-bindings Use bindings more specific to the ARM SMMU. Change-Id: I0e2df8e8e7bfa51036a84e923fa06e42bbed3cd7 Signed-off-by: Alex Waterman Reviewed-on: http://git-master/r/812438 (cherry picked from commit 98cb259c87e9531b0a21dfd3132a3f3db07ff6f0) Reviewed-on: http://git-master/r/831515 Reviewed-by: Krishna Reddy Tested-by: Krishna Reddy --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index d6fca6e41..91a4964c9 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -15,6 +15,8 @@ #include +#include + #include "gk20a/gk20a.h" #include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" @@ -149,7 +151,7 @@ static void gp10b_ltc_init_fs_state(struct gk20a *g) gm20b_ltc_init_fs_state(g); gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), - ltc_ltca_g_axi_pctrl_user_sid_f(31)); + ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB)); } void gp10b_init_ltc(struct gpu_ops *gops) @@ -172,4 +174,3 @@ void gp10b_init_ltc(struct gpu_ops *gops) gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; #endif } - -- cgit v1.2.2 From 666831867617be32288213994810aeaa3f685e46 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 9 Nov 2015 10:23:02 -0800 Subject: Revert "gpu: nvgpu: gp10b: Force always SMMU bypass" This reverts commit cc9bd2dc24f562e97a87641e7436594fd3b469f2. Signed-off-by: Terje Bergstrom Change-Id: Ic4493bc7b71a2ebfb49644c91b34222dd15a9be1 Reviewed-on: http://git-master/r/830854 GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index c08202ec1..e7c55c97b 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -95,7 +95,7 @@ static int gp10b_tegra_probe(struct platform_device *pdev) } platform->g->host1x_dev = host1x_pdev; - platform->bypass_smmu = 1; + platform->bypass_smmu = !device_is_iommuable(&pdev->dev); platform->disable_bigpage = platform->bypass_smmu; platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close -- cgit v1.2.2 From b15e43d6400cf727e22f4c78d708dff135ff0f0f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 6 Nov 2015 09:46:57 -0800 Subject: gpu: nvgpu: ZBC update without idle Do ZBC updates without forcing engine idle first. Bug 1698013 Change-Id: I188563dd60ba511b087e9b9bdacd7f9445efd7a4 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/829146 --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index c801a2b89..defda1c39 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -210,14 +210,18 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, gr->zbc_col_tbl[index].format = color_val->format; gr->zbc_col_tbl[index].ref_cnt++; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), color_val->color_ds[0]); - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), color_val->color_ds[1]); - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), color_val->color_ds[2]); - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), color_val->color_ds[3]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), + color_val->color_ds[0]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), + color_val->color_ds[1]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), + color_val->color_ds[2]); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), + color_val->color_ds[3]); zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); zbc_c &= ~(0x7f << ((index % 4) * 7)); zbc_c |= color_val->format << ((index % 4) * 7); - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); + gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); return 0; } -- cgit v1.2.2 From 19d9465c83004d7e2966407dc66d7e035218024d Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 17 Nov 2015 12:13:03 -0800 Subject: gpu: nvgpu: gp10b: correct initial gpcclk rate Set initial gpcclk rate to 1GHz. Bug 200151332 Reviewed-on: http://git-master/r/834113 (cherry picked from commit 9ed69164da7afeec20c3a557885f74db4cbea9cb) Change-Id: I85107eb5852b25977b30663f6ae173b271ecafeb Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/834322 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index e7c55c97b..3476543d4 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -34,7 +34,7 @@ static struct { char *name; unsigned long default_rate; } tegra_gp10b_clocks[] = { - {"gpu", 1900000000}, + {"gpu", 1000000000}, {"gpu_sys", 204000000} }; /* -- cgit v1.2.2 From f03fa2c0ca48e90a69e55ee49b1141b8ac838dca Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 25 May 2015 14:51:56 +0300 Subject: gpu: nvgpu: User-space managed address space support (gp10b) Tell gk20a_init_vm() that bar2 VM is kernel-managed. Bug 200077571 Change-Id: I151c540a6dec76238e7959f745cfca280927f2d4 Signed-off-by: Sami Kiminki Reviewed-on: http://git-master/r/746803 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index d3297e316..d4a4e7f3d 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c @@ -76,7 +76,7 @@ static int gb10b_init_bar2_vm(struct gk20a *g) gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size); gk20a_init_vm(mm, vm, big_page_size, SZ_4K, mm->bar2.aperture_size - SZ_4K, - mm->bar2.aperture_size, false, "bar2"); + mm->bar2.aperture_size, false, false, "bar2"); /* allocate instance mem for bar2 */ err = gk20a_alloc_inst_block(g, inst_block); -- cgit v1.2.2 From f9d5381a940f0f645f13d38acd1c2cee10dd9249 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 13 Oct 2015 12:22:12 -0700 Subject: gpu: nvgpu: gp10b: add support for freq scaling Add support for gp10b freq scaling. Bug 200147662 Reviewed-on: http://git-master/r/816962 (cherry picked from commit 62de7dba758e46ee80c896dcfcbccb0f8b979438) Change-Id: I71ddfa394d490c002761d2a8bbb95090a4c0e799 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/834758 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 1 + drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 94 ++++++++++++++++++++++++++ 2 files changed, 95 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index f34d836d6..0542fd678 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -2,6 +2,7 @@ GCOV_PROFILE := y ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu ccflags-$(CONFIG_GK20A) += -I$(srctree)/include +ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/devfreq ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 3476543d4..48665ddb1 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -30,6 +30,9 @@ #include "gk20a/gk20a.h" #include "platform_tegra.h" +#define GP10B_MAX_SUPPORTED_FREQS 11 +unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; + static struct { char *name; unsigned long default_rate; @@ -130,7 +133,19 @@ static int gp10b_tegra_probe(struct platform_device *pdev) static int gp10b_tegra_late_probe(struct platform_device *pdev) { + /* Make gk20a power domain a subdomain of host1x */ + nvhost_register_client_domain(dev_to_genpd(&pdev->dev)); + + return 0; +} + +static int gp10b_tegra_remove(struct platform_device *pdev) +{ + /* remove gk20a power subdomain from host1x */ + nvhost_unregister_client_domain(dev_to_genpd(&pdev->dev)); + return 0; + } static bool gp10b_tegra_is_railgated(struct platform_device *pdev) @@ -206,6 +221,72 @@ static int gp10b_tegra_reset_deassert(struct platform_device *dev) return ret; } +static void gp10b_tegra_prescale(struct platform_device *pdev) +{ + struct gk20a *g = get_gk20a(pdev); + u32 avg = 0; + + gk20a_dbg_fn(""); + + gk20a_pmu_load_norm(g, &avg); + /* TBD - Notify EDP about changed constrains */ + + gk20a_dbg_fn("done"); +} + +static void gp10b_tegra_postscale(struct platform_device *pdev, + unsigned long freq) +{ + /* TBD - notify EMC about frequency change */ + gk20a_dbg_fn(""); +} + +static unsigned long gp10b_get_clk_rate(struct platform_device *dev) +{ + struct gk20a_platform *platform = gk20a_get_platform(dev); + + return clk_get_rate(platform->clk[0]); + +} + +static long gp10b_round_clk_rate(struct platform_device *dev, + unsigned long rate) +{ + struct gk20a_platform *platform = gk20a_get_platform(dev); + + return clk_round_rate(platform->clk[0], rate); +} + +static int gp10b_set_clk_rate(struct platform_device *dev, unsigned long rate) +{ + struct gk20a_platform *platform = gk20a_get_platform(dev); + + return clk_set_rate(platform->clk[0], rate); +} + +static int gp10b_clk_get_freqs(struct platform_device *pdev, + unsigned long **freqs, int *num_freqs) +{ + struct gk20a_platform *platform = gk20a_get_platform(pdev); + unsigned long min_rate, max_rate, freq_step, rate; + int i; + + min_rate = clk_round_rate(platform->clk[0], 0); + max_rate = clk_round_rate(platform->clk[0], (UINT_MAX - 1)); + freq_step = (max_rate - min_rate)/(GP10B_MAX_SUPPORTED_FREQS - 1); + gk20a_dbg_info("min rate: %ld max rate: %ld freq step %ld\n", + min_rate, max_rate, freq_step); + + for (i = 0; i < GP10B_MAX_SUPPORTED_FREQS; i++) { + rate = min_rate + i * freq_step; + gp10b_freq_table[i] = clk_round_rate(platform->clk[0], rate); + } + /* Fill freq table */ + *freqs = gp10b_freq_table; + *num_freqs = GP10B_MAX_SUPPORTED_FREQS; + return 0; +} + struct gk20a_platform t18x_gpu_tegra_platform = { .has_syncpoints = true, @@ -227,6 +308,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .probe = gp10b_tegra_probe, .late_probe = gp10b_tegra_late_probe, + .remove = gp10b_tegra_remove, /* power management callbacks */ .suspend = gp10b_tegra_suspend, @@ -243,6 +325,18 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .has_cde = true, + .clk_get_rate = gp10b_get_clk_rate, + .clk_round_rate = gp10b_round_clk_rate, + .clk_set_rate = gp10b_set_clk_rate, + .get_clk_freqs = gp10b_clk_get_freqs, + + /* frequency scaling configuration */ + .prescale = gp10b_tegra_prescale, + .postscale = gp10b_tegra_postscale, + + .devfreq_governor = "nvhost_podgov", + .qos_id = PM_QOS_GPU_FREQ_MIN, + .secure_alloc = gk20a_tegra_secure_alloc, .secure_page_alloc = gk20a_tegra_secure_page_alloc, -- cgit v1.2.2 From ca5145c934f424717b0801dff14de73d5fb31a71 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Tue, 24 Nov 2015 10:15:28 +0530 Subject: gpu: nvgpu: ELPG prod values update Bug 200151348 Change-Id: I44851b69adfe9c6bf5d4c897730d6da7df9bedd8 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/836877 (cherry picked from commit 69de3f3c439f544fd5f9223f5663010f5ec80193) Reviewed-on: http://git-master/r/837228 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 88 ++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 44 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 57accfb0c..dc7539a88 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -48,42 +48,42 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e06c, 0x00000087} , {0x0010e06c, 0x00000088} , {0x0010e06c, 0x0000008D} , - {0x0010e06c, 0x000000A00} , - {0x0010e06c, 0x000000A01} , - {0x0010e06c, 0x000000A02} , - {0x0010e06c, 0x000000A03} , - {0x0010e06c, 0x000000A04} , - {0x0010e06c, 0x000000A05} , - {0x0010e06c, 0x000000A06} , - {0x0010e06c, 0x000000A07} , - {0x0010e06c, 0x000000A08} , - {0x0010e06c, 0x000000A09} , - {0x0010e06c, 0x000000950} , - {0x0010e06c, 0x000000951} , - {0x0010e06c, 0x000000952} , - {0x0010e06c, 0x000000953} , - {0x0010e06c, 0x000000954} , - {0x0010e06c, 0x000000955} , - {0x0010e06c, 0x000000956} , - {0x0010e06c, 0x000000957} , + {0x0010e06c, 0x00000082} , + {0x0010e06c, 0x00000083} , + {0x0010e06c, 0x00000089} , + {0x0010e06c, 0x0000008A} , + {0x0010e06c, 0x000000A2} , + {0x0010e06c, 0x00000097} , + {0x0010e06c, 0x00000092} , + {0x0010e06c, 0x00000099} , + {0x0010e06c, 0x0000009B} , + {0x0010e06c, 0x0000009D} , + {0x0010e06c, 0x0000009F} , + {0x0010e06c, 0x000000A1} , + {0x0010e06c, 0x00000096} , + {0x0010e06c, 0x00000091} , + {0x0010e06c, 0x00000098} , + {0x0010e06c, 0x0000009A} , + {0x0010e06c, 0x0000009C} , + {0x0010e06c, 0x0000009E} , {0x0010ab14, 0x00000000} , {0x0010e024, 0x00000000} , {0x0010e028, 0x00000000} , {0x0010e11c, 0x00000000} , - {0x0010ab1c, 0x140B0B55} , - {0x0010e020, 0x0E262655} , - {0x0010e124, 0x25101055} , + {0x0010ab1c, 0x140B0BFF} , + {0x0010e020, 0x0E2626FF} , + {0x0010e124, 0x251010FF} , {0x0010ab20, 0x89abcdef} , {0x0010ab24, 0x00000000} , {0x0010e02c, 0x89abcdef} , {0x0010e030, 0x00000000} , {0x0010e128, 0x89abcdef} , {0x0010e12c, 0x00000000} , - {0x0010ab28, 0x75555555} , + {0x0010ab28, 0x7FFFFFFF} , {0x0010ab2c, 0x70000000} , - {0x0010e034, 0x75555555} , + {0x0010e034, 0x7FFFFFFF} , {0x0010e038, 0x70000000} , - {0x0010e130, 0x75555555} , + {0x0010e130, 0x7FFFFFFF} , {0x0010e134, 0x70000000} , {0x0010ab30, 0x00000000} , {0x0010ab34, 0x00000001} , @@ -97,8 +97,8 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e05c, 0x00000000} , {0x0010e044, 0x00000000} , {0x0010a644, 0x0000868B} , - {0x0010a648, 0x00000000 } , - {0x0010a64c, 0x00829493 } , + {0x0010a648, 0x00000000} , + {0x0010a64c, 0x00829493} , {0x0010a650, 0x00000000} , {0x0010e000, 0} , {0x0010e068, 0x000000A3} , @@ -111,24 +111,24 @@ static struct pg_init_sequence_list _pginitseq_gp10b[] = { {0x0010e068, 0x00000087} , {0x0010e068, 0x00000088} , {0x0010e068, 0x0000008D} , - {0x0010e068, 0x000000A00} , - {0x0010e068, 0x000000A01} , - {0x0010e068, 0x000000A02} , - {0x0010e068, 0x000000A03} , - {0x0010e068, 0x000000A04} , - {0x0010e068, 0x000000A05} , - {0x0010e068, 0x000000A06} , - {0x0010e068, 0x000000A07} , - {0x0010e068, 0x000000A08} , - {0x0010e068, 0x000000A09} , - {0x0010e068, 0x000000950} , - {0x0010e068, 0x000000951} , - {0x0010e068, 0x000000952} , - {0x0010e068, 0x000000953} , - {0x0010e068, 0x000000954} , - {0x0010e068, 0x000000955} , - {0x0010e068, 0x000000956} , - {0x0010e068, 0x000000957} , + {0x0010e068, 0x00000082} , + {0x0010e068, 0x00000083} , + {0x0010e068, 0x00000089} , + {0x0010e068, 0x0000008A} , + {0x0010e068, 0x000000A2} , + {0x0010e068, 0x00000097} , + {0x0010e068, 0x00000092} , + {0x0010e068, 0x00000099} , + {0x0010e068, 0x0000009B} , + {0x0010e068, 0x0000009D} , + {0x0010e068, 0x0000009F} , + {0x0010e068, 0x000000A1} , + {0x0010e068, 0x00000096} , + {0x0010e068, 0x00000091} , + {0x0010e068, 0x00000098} , + {0x0010e068, 0x0000009A} , + {0x0010e068, 0x0000009C} , + {0x0010e068, 0x0000009E} , {0x0010e000, 0} , {0x0010e004, 0x0000008E}, }; -- cgit v1.2.2 From ee6eef0d59a9178f76d3e7e9e75d29fbc3c309d4 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 23 Nov 2015 11:19:00 -0800 Subject: gpu: nvgpu: t18x: make gp10b_freq_table static Make gp10b_freq_table static to fix sparse warning Bug 200088648 Change-Id: Ibaaabd145e37685e049ac3a49e2b276fb6545d0e Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/837421 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 48665ddb1..6abb70c38 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -31,7 +31,7 @@ #include "platform_tegra.h" #define GP10B_MAX_SUPPORTED_FREQS 11 -unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; +static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; static struct { char *name; -- cgit v1.2.2 From 7db70bbd4e870d79230ca32943c01d07bb987b3f Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 6 Oct 2015 10:58:54 -0700 Subject: gpu: nvgpu: gp10b: Install gp10b access map Bug 1692373 Change-Id: I63bb1f8a40fe5d2c7b61440c989b78e4cb3ece98 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/812351 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index defda1c39..9c83030f7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1066,6 +1066,23 @@ static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); } +static void gr_gp10b_get_access_map(struct gk20a *g, + u32 **whitelist, int *num_entries) +{ + static u32 wl_addr_gp10b[] = { + /* this list must be sorted (low to high) */ + 0x404468, /* gr_pri_mme_max_instructions */ + 0x418800, /* gr_pri_gpcs_setup_debug */ + 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ + 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ + 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ + 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ + }; + + *whitelist = wl_addr_gp10b; + *num_entries = ARRAY_SIZE(wl_addr_gp10b); +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -1095,4 +1112,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.wait_empty = gr_gp10b_wait_empty; gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask; + gops->gr.get_access_map = gr_gp10b_get_access_map; } -- cgit v1.2.2 From 0646d39ca8ae2b428e23ff6b6821c925d7e468f1 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 6 Oct 2015 12:45:15 -0700 Subject: gpu: nvgpu: gp10b: Add tile caching registers Add tile caching registers to access map. Bug 1692373 Change-Id: Ic95fce02c564fa8d5556543a744c9828b542fb1f Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/812352 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9c83030f7..45befc516 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1072,7 +1072,31 @@ static void gr_gp10b_get_access_map(struct gk20a *g, static u32 wl_addr_gp10b[] = { /* this list must be sorted (low to high) */ 0x404468, /* gr_pri_mme_max_instructions */ + 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ 0x418800, /* gr_pri_gpcs_setup_debug */ + 0x418e00, /* gr_pri_gpcs_swdx_config */ + 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ + 0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr */ + 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ -- cgit v1.2.2 From d760512ade757355aadc882942808b72127cd397 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 30 Nov 2015 09:30:22 -0800 Subject: gpu: nvgpu: Recreate HW headers Add gradual slowdown registers, and fix names for L2 flush registers. Change-Id: If085c4febef494ae299d2147ca5201cd373bee0b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/839369 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu --- drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h | 20 +++--- drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 2 +- drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 120 +++++++++++++++++++++++++++++++ 3 files changed, 131 insertions(+), 11 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h index f442991e0..e2dff4909 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h @@ -114,43 +114,43 @@ static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) { return 0x00000001; } -static inline u32 flush_clean_comptags_r(void) +static inline u32 flush_l2_clean_comptags_r(void) { return 0x0007000c; } -static inline u32 flush_clean_comptags_pending_v(u32 r) +static inline u32 flush_l2_clean_comptags_pending_v(u32 r) { return (r >> 0) & 0x1; } -static inline u32 flush_clean_comptags_pending_empty_v(void) +static inline u32 flush_l2_clean_comptags_pending_empty_v(void) { return 0x00000000; } -static inline u32 flush_clean_comptags_pending_empty_f(void) +static inline u32 flush_l2_clean_comptags_pending_empty_f(void) { return 0x0; } -static inline u32 flush_clean_comptags_pending_busy_v(void) +static inline u32 flush_l2_clean_comptags_pending_busy_v(void) { return 0x00000001; } -static inline u32 flush_clean_comptags_pending_busy_f(void) +static inline u32 flush_l2_clean_comptags_pending_busy_f(void) { return 0x1; } -static inline u32 flush_clean_comptags_outstanding_v(u32 r) +static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) { return (r >> 1) & 0x1; } -static inline u32 flush_clean_comptags_outstanding_false_v(void) +static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) { return 0x00000000; } -static inline u32 flush_clean_comptags_outstanding_false_f(void) +static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) { return 0x0; } -static inline u32 flush_clean_comptags_outstanding_true_v(void) +static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) { return 0x00000001; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h index f66812d68..75bf59a30 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h index aed754817..17b1fb7ee 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h @@ -170,6 +170,18 @@ static inline u32 therm_config1_r(void) { return 0x00020050; } +static inline u32 therm_config2_r(void) +{ + return 0x00020130; +} +static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) +{ + return (v & 0x1) << 24; +} +static inline u32 therm_config2_grad_enable_f(u32 v) +{ + return (v & 0x1) << 31; +} static inline u32 therm_gate_ctrl_r(u32 i) { return 0x00020200 + i*4; @@ -278,4 +290,112 @@ static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) { return 0x0; } +static inline u32 therm_grad_stepping_table_r(u32 i) +{ + return 0x000202c8 + i*4; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) +{ + return (v & 0x3f) << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) +{ + return 0x3f << 0; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) +{ + return 0x2; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) +{ + return 0x6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) +{ + return 0xe; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) +{ + return (v & 0x3f) << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) +{ + return 0x3f << 6; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) +{ + return (v & 0x3f) << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) +{ + return 0x3f << 12; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) +{ + return (v & 0x3f) << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) +{ + return 0x3f << 18; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) +{ + return (v & 0x3f) << 24; +} +static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) +{ + return 0x3f << 24; +} +static inline u32 therm_grad_stepping0_r(void) +{ + return 0x000202c0; +} +static inline u32 therm_grad_stepping0_feature_s(void) +{ + return 1; +} +static inline u32 therm_grad_stepping0_feature_f(u32 v) +{ + return (v & 0x1) << 0; +} +static inline u32 therm_grad_stepping0_feature_m(void) +{ + return 0x1 << 0; +} +static inline u32 therm_grad_stepping0_feature_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 therm_grad_stepping0_feature_enable_f(void) +{ + return 0x1; +} +static inline u32 therm_grad_stepping1_r(void) +{ + return 0x000202c4; +} +static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) +{ + return (v & 0x1ffff) << 0; +} +static inline u32 therm_clk_timing_r(u32 i) +{ + return 0x000203c0 + i*4; +} +static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) +{ + return (v & 0x1) << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_m(void) +{ + return 0x1 << 16; +} +static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) +{ + return 0x10000; +} #endif -- cgit v1.2.2 From 5269b04c576161289a0169c214516d6489f82290 Mon Sep 17 00:00:00 2001 From: David Li Date: Wed, 30 Sep 2015 23:20:44 +0000 Subject: gpu: nvgpu: gp10b: fix set_circular_buffer_size It didn't set gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r causing a GPU MMU fault when used. Bug 200141640 Bug 200141981 Bug 200141640 Change-Id: I8b9f71e480553ead2827ff1f1dde2ba2e6efe697 Signed-off-by: David Li Reviewed-on: http://git-master/r/807694 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 45befc516..04856e444 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -415,17 +415,26 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) { struct gr_gk20a *gr = &g->gr; u32 gpc_index, ppc_index, stride, val; - u32 cb_size = data * 4; + u32 cb_size_steady = data * 4, cb_size; gk20a_dbg_fn(""); - if (cb_size > gr->attrib_cb_size) - cb_size = gr->attrib_cb_size; + if (cb_size_steady > gr->attrib_cb_size) + cb_size_steady = gr->attrib_cb_size; + if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != + gk20a_readl(g, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { + cb_size = cb_size_steady + + (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - + gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); + } else { + cb_size = cb_size_steady; + } gk20a_writel(g, gr_ds_tga_constraintlogic_beta_r(), (gk20a_readl(g, gr_ds_tga_constraintlogic_beta_r()) & ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) | - gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size)); + gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady)); for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { stride = proj_gpc_stride_v() * gpc_index; @@ -446,12 +455,19 @@ static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) stride + proj_ppc_in_gpc_stride_v() * ppc_index, val); + gk20a_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index + + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + + stride, + gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f( + cb_size_steady)); + val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r( ppc_index + gpc_index)); val = set_field(val, gr_gpcs_swdx_tc_beta_cb_size_v_m(), - gr_gpcs_swdx_tc_beta_cb_size_v_f(cb_size * + gr_gpcs_swdx_tc_beta_cb_size_v_f( + cb_size_steady * gr->gpc_ppc_count[gpc_index])); gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r( -- cgit v1.2.2 From 85ddd07fcbbe8134e5772804c760081a5a44f823 Mon Sep 17 00:00:00 2001 From: David Li Date: Fri, 4 Sep 2015 18:28:10 -0700 Subject: gpu: nvgpu: fix setting gr_pd_ab_dist_cfg1_r() gr_*__set_alpha_circular_buffer_size() left max_batches field of gr_pd_ab_dist_cfg1_r as 0 which results in too many alpha beta transitions and poor performance when tessellation or geometry shaders are used Change-Id: Ic3673f45b60674b3527641a6fdda0cedc6861db5 Signed-off-by: David Li Reviewed-on: http://git-master/r/840079 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 04856e444..6bdb9a7c4 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -388,7 +388,8 @@ static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) gr_pd_ab_dist_cfg1_max_output_granularity_v(); gk20a_writel(g, gr_pd_ab_dist_cfg1_r(), - gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output)); + gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | + gr_pd_ab_dist_cfg1_max_batches_init_f()); for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { stride = proj_gpc_stride_v() * gpc_index; -- cgit v1.2.2 From e0c5d873528d3c229bc71fe2bbff6582efaf150a Mon Sep 17 00:00:00 2001 From: Aingara Paramakuru Date: Mon, 14 Dec 2015 20:39:47 -0500 Subject: gpu: nvgpu: vgpu: update interface to free GR ctx The server only releases ownership of the ctxsw buffer mappings after the GR ctx has been released. Update the sequence to account for this. JIRA VFND-1117 Bug 1708163 Change-Id: I3aed015805b4ca51433e7d37ad32de2f8353999f Signed-off-by: Aingara Paramakuru Reviewed-on: http://git-master/r/922817 Reviewed-by: Richard Zhao GVS: Gerrit_Virtual_Submit Reviewed-by: Vladislav Buzov --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c index c5c53b58e..3023ef4b1 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c @@ -20,16 +20,30 @@ static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx) { + struct gk20a_platform *platform = gk20a_get_platform(g->dev); + struct tegra_vgpu_cmd_msg msg; + struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; + int err; + gk20a_dbg_fn(""); if (!gr_ctx || !gr_ctx->mem.gpu_va) return; + msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; + msg.handle = platform->virt_handle; + p->handle = gr_ctx->virt_ctx; + err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); + WARN_ON(err || msg.ret); + + gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, 0); + gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); - vgpu_gr_free_gr_ctx(g, vm, gr_ctx); + + kfree(gr_ctx); } static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, -- cgit v1.2.2 From 9a77be852b20c0af0ed239bbbbe49dc2ef08e449 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Mon, 11 Jan 2016 10:38:25 -0800 Subject: gpu: nvgpu: gp10b: Refresh regops whitelist Context & global whitelists are same, so delete second copy. Update the list. Bug 200164983 Change-Id: I440ce04316120b8128baeabc002c55436cf41d5b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/931178 GVS: Gerrit_Virtual_Submit Reviewed-by: Sandarbh Jain Tested-by: Sandarbh Jain --- drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 402 +++------------------------------ 1 file changed, 30 insertions(+), 372 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 0ab80b78c..48f6161d2 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c @@ -48,6 +48,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x00022450, 1}, { 0x0002245c, 1}, { 0x00070000, 5}, + { 0x000884e0, 1}, { 0x0008e00c, 1}, { 0x00100c18, 3}, { 0x00100c84, 1}, @@ -78,53 +79,53 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x0017e4a0, 1}, { 0x0017e550, 1}, { 0x00180040, 41}, - { 0x001800ec, 9}, + { 0x001800ec, 10}, { 0x00180240, 41}, - { 0x001802ec, 9}, + { 0x001802ec, 10}, { 0x00180440, 41}, - { 0x001804ec, 9}, + { 0x001804ec, 10}, { 0x00180640, 41}, - { 0x001806ec, 9}, + { 0x001806ec, 10}, { 0x00180840, 41}, - { 0x001808ec, 9}, + { 0x001808ec, 10}, { 0x00180a40, 41}, - { 0x00180aec, 9}, + { 0x00180aec, 10}, { 0x00180c40, 41}, - { 0x00180cec, 9}, + { 0x00180cec, 10}, { 0x00180e40, 41}, - { 0x00180eec, 9}, + { 0x00180eec, 10}, { 0x001a0040, 41}, - { 0x001a00ec, 9}, + { 0x001a00ec, 10}, { 0x001a0240, 41}, - { 0x001a02ec, 9}, + { 0x001a02ec, 10}, { 0x001a0440, 41}, - { 0x001a04ec, 9}, + { 0x001a04ec, 10}, { 0x001a0640, 41}, - { 0x001a06ec, 9}, + { 0x001a06ec, 10}, { 0x001a0840, 41}, - { 0x001a08ec, 9}, + { 0x001a08ec, 10}, { 0x001a0a40, 41}, - { 0x001a0aec, 9}, + { 0x001a0aec, 10}, { 0x001a0c40, 41}, - { 0x001a0cec, 9}, + { 0x001a0cec, 10}, { 0x001a0e40, 41}, - { 0x001a0eec, 9}, + { 0x001a0eec, 10}, { 0x001b0040, 41}, - { 0x001b00ec, 9}, + { 0x001b00ec, 10}, { 0x001b0240, 41}, - { 0x001b02ec, 9}, + { 0x001b02ec, 10}, { 0x001b0440, 41}, - { 0x001b04ec, 9}, + { 0x001b04ec, 10}, { 0x001b0640, 41}, - { 0x001b06ec, 9}, + { 0x001b06ec, 10}, { 0x001b0840, 41}, - { 0x001b08ec, 9}, + { 0x001b08ec, 10}, { 0x001b0a40, 41}, - { 0x001b0aec, 9}, + { 0x001b0aec, 10}, { 0x001b0c40, 41}, - { 0x001b0cec, 9}, + { 0x001b0cec, 10}, { 0x001b0e40, 41}, - { 0x001b0eec, 9}, + { 0x001b0eec, 10}, { 0x001b4000, 1}, { 0x001b4008, 1}, { 0x001b4010, 3}, @@ -176,7 +177,9 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x0041040c, 1}, { 0x00410510, 1}, { 0x00410584, 1}, - { 0x00418384, 1}, + { 0x00418000, 1}, + { 0x00418008, 1}, + { 0x00418380, 2}, { 0x00418400, 2}, { 0x004184a0, 1}, { 0x00418604, 1}, @@ -373,351 +376,6 @@ static const u32 gp10b_global_whitelist_ranges_count = /* context */ -static const struct regop_offset_range gp10b_context_whitelist_ranges[] = { - { 0x000004f0, 1}, - { 0x00001a00, 3}, - { 0x00002800, 128}, - { 0x00009400, 1}, - { 0x00009410, 1}, - { 0x00009480, 1}, - { 0x00020200, 24}, - { 0x00021c00, 4}, - { 0x00021c14, 3}, - { 0x00021c24, 1}, - { 0x00021c2c, 69}, - { 0x00021d44, 1}, - { 0x00021d4c, 1}, - { 0x00021d54, 1}, - { 0x00021d5c, 1}, - { 0x00021d64, 2}, - { 0x00021d70, 16}, - { 0x00022430, 7}, - { 0x00022450, 1}, - { 0x0002245c, 1}, - { 0x00070000, 5}, - { 0x0008e00c, 1}, - { 0x00100c18, 3}, - { 0x00100c84, 1}, - { 0x0010a0a8, 1}, - { 0x0010a4f0, 1}, - { 0x0013cc14, 1}, - { 0x00140028, 1}, - { 0x00140280, 1}, - { 0x001402a0, 1}, - { 0x00140350, 1}, - { 0x00140480, 1}, - { 0x001404a0, 1}, - { 0x00140550, 1}, - { 0x00142028, 1}, - { 0x00142280, 1}, - { 0x001422a0, 1}, - { 0x00142350, 1}, - { 0x00142480, 1}, - { 0x001424a0, 1}, - { 0x00142550, 1}, - { 0x0017e280, 1}, - { 0x0017e294, 1}, - { 0x0017e29c, 2}, - { 0x0017e2ac, 1}, - { 0x0017e350, 1}, - { 0x0017e39c, 1}, - { 0x0017e480, 1}, - { 0x0017e4a0, 1}, - { 0x0017e550, 1}, - { 0x00180040, 41}, - { 0x001800ec, 9}, - { 0x00180240, 41}, - { 0x001802ec, 9}, - { 0x00180440, 41}, - { 0x001804ec, 9}, - { 0x00180640, 41}, - { 0x001806ec, 9}, - { 0x00180840, 41}, - { 0x001808ec, 9}, - { 0x00180a40, 41}, - { 0x00180aec, 9}, - { 0x00180c40, 41}, - { 0x00180cec, 9}, - { 0x00180e40, 41}, - { 0x00180eec, 9}, - { 0x001a0040, 41}, - { 0x001a00ec, 9}, - { 0x001a0240, 41}, - { 0x001a02ec, 9}, - { 0x001a0440, 41}, - { 0x001a04ec, 9}, - { 0x001a0640, 41}, - { 0x001a06ec, 9}, - { 0x001a0840, 41}, - { 0x001a08ec, 9}, - { 0x001a0a40, 41}, - { 0x001a0aec, 9}, - { 0x001a0c40, 41}, - { 0x001a0cec, 9}, - { 0x001a0e40, 41}, - { 0x001a0eec, 9}, - { 0x001b0040, 41}, - { 0x001b00ec, 9}, - { 0x001b0240, 41}, - { 0x001b02ec, 9}, - { 0x001b0440, 41}, - { 0x001b04ec, 9}, - { 0x001b0640, 41}, - { 0x001b06ec, 9}, - { 0x001b0840, 41}, - { 0x001b08ec, 9}, - { 0x001b0a40, 41}, - { 0x001b0aec, 9}, - { 0x001b0c40, 41}, - { 0x001b0cec, 9}, - { 0x001b0e40, 41}, - { 0x001b0eec, 9}, - { 0x001b4000, 1}, - { 0x001b4008, 1}, - { 0x001b4010, 3}, - { 0x001b4020, 3}, - { 0x001b4030, 3}, - { 0x001b4040, 3}, - { 0x001b4050, 3}, - { 0x001b4060, 4}, - { 0x001b4074, 7}, - { 0x001b4094, 3}, - { 0x001b40a4, 1}, - { 0x001b4100, 6}, - { 0x001b4124, 1}, - { 0x001b8000, 1}, - { 0x001b8008, 1}, - { 0x001b8010, 3}, - { 0x001bc000, 1}, - { 0x001bc008, 1}, - { 0x001bc010, 3}, - { 0x001be000, 1}, - { 0x001be008, 1}, - { 0x001be010, 3}, - { 0x00400500, 1}, - { 0x0040415c, 1}, - { 0x00404468, 1}, - { 0x00404498, 1}, - { 0x00405800, 1}, - { 0x00405840, 2}, - { 0x00405850, 1}, - { 0x00405908, 1}, - { 0x00405b40, 1}, - { 0x00405b50, 1}, - { 0x00406024, 5}, - { 0x00407010, 1}, - { 0x00407808, 1}, - { 0x0040803c, 1}, - { 0x00408804, 1}, - { 0x0040880c, 1}, - { 0x00408900, 2}, - { 0x00408910, 1}, - { 0x00408944, 1}, - { 0x00408984, 1}, - { 0x004090a8, 1}, - { 0x004098a0, 1}, - { 0x00409b00, 1}, - { 0x0041000c, 1}, - { 0x00410110, 1}, - { 0x00410184, 1}, - { 0x0041040c, 1}, - { 0x00410510, 1}, - { 0x00410584, 1}, - { 0x00418384, 1}, - { 0x00418400, 2}, - { 0x004184a0, 1}, - { 0x00418604, 1}, - { 0x00418680, 1}, - { 0x00418704, 1}, - { 0x00418714, 1}, - { 0x00418800, 1}, - { 0x0041881c, 1}, - { 0x00418830, 1}, - { 0x00418884, 1}, - { 0x004188b0, 1}, - { 0x004188c8, 3}, - { 0x004188fc, 1}, - { 0x00418b04, 1}, - { 0x00418c04, 1}, - { 0x00418c10, 8}, - { 0x00418c88, 1}, - { 0x00418d00, 1}, - { 0x00418e00, 1}, - { 0x00418e08, 1}, - { 0x00418e34, 1}, - { 0x00418e40, 4}, - { 0x00418e58, 16}, - { 0x00418f08, 1}, - { 0x00419000, 1}, - { 0x0041900c, 1}, - { 0x00419018, 1}, - { 0x00419854, 1}, - { 0x00419864, 1}, - { 0x00419a04, 2}, - { 0x00419a14, 1}, - { 0x00419ab0, 1}, - { 0x00419ab8, 3}, - { 0x00419c0c, 1}, - { 0x00419c8c, 2}, - { 0x00419d00, 1}, - { 0x00419d08, 2}, - { 0x00419e00, 11}, - { 0x00419e34, 2}, - { 0x00419e44, 11}, - { 0x00419e74, 10}, - { 0x00419ea4, 1}, - { 0x00419eac, 2}, - { 0x00419ee8, 1}, - { 0x00419ef0, 28}, - { 0x00419f70, 1}, - { 0x00419f78, 2}, - { 0x00419f98, 2}, - { 0x00419fdc, 1}, - { 0x0041a02c, 2}, - { 0x0041a0a0, 1}, - { 0x0041a0a8, 1}, - { 0x0041a890, 2}, - { 0x0041a8a0, 3}, - { 0x0041a8b0, 2}, - { 0x0041b014, 1}, - { 0x0041b0cc, 1}, - { 0x0041b1dc, 1}, - { 0x0041be0c, 3}, - { 0x0041becc, 1}, - { 0x0041bfdc, 1}, - { 0x0041c054, 1}, - { 0x0041c2b0, 1}, - { 0x0041c2b8, 3}, - { 0x0041c40c, 1}, - { 0x0041c48c, 2}, - { 0x0041c500, 1}, - { 0x0041c508, 2}, - { 0x0041c600, 11}, - { 0x0041c634, 2}, - { 0x0041c644, 11}, - { 0x0041c674, 10}, - { 0x0041c6a4, 1}, - { 0x0041c6ac, 2}, - { 0x0041c6e8, 1}, - { 0x0041c6f0, 28}, - { 0x0041c770, 1}, - { 0x0041c778, 2}, - { 0x0041c798, 2}, - { 0x0041c7dc, 1}, - { 0x0041c854, 1}, - { 0x0041cab0, 1}, - { 0x0041cab8, 3}, - { 0x0041cc0c, 1}, - { 0x0041cc8c, 2}, - { 0x0041cd00, 1}, - { 0x0041cd08, 2}, - { 0x0041ce00, 11}, - { 0x0041ce34, 2}, - { 0x0041ce44, 11}, - { 0x0041ce74, 10}, - { 0x0041cea4, 1}, - { 0x0041ceac, 2}, - { 0x0041cee8, 1}, - { 0x0041cef0, 28}, - { 0x0041cf70, 1}, - { 0x0041cf78, 2}, - { 0x0041cf98, 2}, - { 0x0041cfdc, 1}, - { 0x00500384, 1}, - { 0x005004a0, 1}, - { 0x00500604, 1}, - { 0x00500680, 1}, - { 0x00500714, 1}, - { 0x0050081c, 1}, - { 0x00500884, 1}, - { 0x005008b0, 1}, - { 0x005008c8, 3}, - { 0x005008fc, 1}, - { 0x00500b04, 1}, - { 0x00500c04, 1}, - { 0x00500c10, 8}, - { 0x00500c88, 1}, - { 0x00500d00, 1}, - { 0x00500e08, 1}, - { 0x00500f08, 1}, - { 0x00501000, 1}, - { 0x0050100c, 1}, - { 0x00501018, 1}, - { 0x00501854, 1}, - { 0x00501ab0, 1}, - { 0x00501ab8, 3}, - { 0x00501c0c, 1}, - { 0x00501c8c, 2}, - { 0x00501d00, 1}, - { 0x00501d08, 2}, - { 0x00501e00, 11}, - { 0x00501e34, 2}, - { 0x00501e44, 11}, - { 0x00501e74, 10}, - { 0x00501ea4, 1}, - { 0x00501eac, 2}, - { 0x00501ee8, 1}, - { 0x00501ef0, 28}, - { 0x00501f70, 1}, - { 0x00501f78, 2}, - { 0x00501f98, 2}, - { 0x00501fdc, 1}, - { 0x0050202c, 2}, - { 0x005020a0, 1}, - { 0x005020a8, 1}, - { 0x00502890, 2}, - { 0x005028a0, 3}, - { 0x005028b0, 2}, - { 0x00503014, 1}, - { 0x005030cc, 1}, - { 0x005031dc, 1}, - { 0x00503e14, 1}, - { 0x00503ecc, 1}, - { 0x00503fdc, 1}, - { 0x00504054, 1}, - { 0x005042b0, 1}, - { 0x005042b8, 3}, - { 0x0050440c, 1}, - { 0x0050448c, 2}, - { 0x00504500, 1}, - { 0x00504508, 2}, - { 0x00504600, 11}, - { 0x00504634, 2}, - { 0x00504644, 11}, - { 0x00504674, 10}, - { 0x005046a4, 1}, - { 0x005046ac, 2}, - { 0x005046e8, 1}, - { 0x005046f0, 28}, - { 0x00504770, 1}, - { 0x00504778, 2}, - { 0x00504798, 2}, - { 0x005047dc, 1}, - { 0x00504854, 1}, - { 0x00504ab0, 1}, - { 0x00504ab8, 3}, - { 0x00504c0c, 1}, - { 0x00504c8c, 2}, - { 0x00504d00, 1}, - { 0x00504d08, 2}, - { 0x00504e00, 11}, - { 0x00504e34, 2}, - { 0x00504e44, 11}, - { 0x00504e74, 10}, - { 0x00504ea4, 1}, - { 0x00504eac, 2}, - { 0x00504ee8, 1}, - { 0x00504ef0, 28}, - { 0x00504f70, 1}, - { 0x00504f78, 2}, - { 0x00504f98, 2}, - { 0x00504fdc, 1}, - { 0x00900100, 1}, - { 0x009a0100, 1}, -}; -static const u32 gp10b_context_whitelist_ranges_count = - ARRAY_SIZE(gp10b_context_whitelist_ranges); - /* runcontrol */ static const u32 gp10b_runcontrol_whitelist[] = { }; @@ -753,12 +411,12 @@ static int gp10b_get_global_whitelist_ranges_count(void) static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void) { - return gp10b_context_whitelist_ranges; + return gp10b_global_whitelist_ranges; } static int gp10b_get_context_whitelist_ranges_count(void) { - return gp10b_context_whitelist_ranges_count; + return gp10b_global_whitelist_ranges_count; } static const u32 *gp10b_get_runcontrol_whitelist(void) -- cgit v1.2.2 From b836a445d4bb3804218526e6420c36ca693835aa Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Mon, 4 Jan 2016 16:27:33 -0800 Subject: gpu: nvgpu: enable semaphore acquire timeout for gp10b It'll detect dead semaphore acquire. The worst case is when ACQUIRE_SWITCH is disabled, semaphore acquire will poll and consume full gpu timeslicees. The timeout value is set to half of channel WDT. Bug 1636800 Change-Id: Idbd4bfa52981e8a849b62a168e3a6828330112f5 Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/928830 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 8 ++------ drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 22 +++++++++++++++++++++- 2 files changed, 23 insertions(+), 7 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 8c53978bd..ade6ff0a0 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B fifo * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -122,11 +122,7 @@ static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, gk20a_mem_wr32(inst_ptr, ram_fc_target_w(), pbdma_target_engine_sw_f()); gk20a_mem_wr32(inst_ptr, ram_fc_acquire_w(), - pbdma_acquire_retry_man_2_f() | - pbdma_acquire_retry_exp_2_f() | - pbdma_acquire_timeout_exp_max_f() | - pbdma_acquire_timeout_man_max_f() | - pbdma_acquire_timeout_en_disable_f()); + channel_gk20a_pbdma_acquire_val(c)); gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(), pbdma_runlist_timeslice_timeout_128_f() | diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h index d3f97a440..f66fa9345 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -262,14 +262,34 @@ static inline u32 pbdma_acquire_retry_exp_2_f(void) { return 0x100; } +static inline u32 pbdma_acquire_timeout_exp_f(u32 v) +{ + return (v & 0xf) << 11; +} +static inline u32 pbdma_acquire_timeout_exp_max_v(void) +{ + return 0x0000000f; +} static inline u32 pbdma_acquire_timeout_exp_max_f(void) { return 0x7800; } +static inline u32 pbdma_acquire_timeout_man_f(u32 v) +{ + return (v & 0xffff) << 15; +} +static inline u32 pbdma_acquire_timeout_man_max_v(void) +{ + return 0x0000ffff; +} static inline u32 pbdma_acquire_timeout_man_max_f(void) { return 0x7fff8000; } +static inline u32 pbdma_acquire_timeout_en_enable_f(void) +{ + return 0x80000000; +} static inline u32 pbdma_acquire_timeout_en_disable_f(void) { return 0x0; -- cgit v1.2.2 From f47df044026b190299c0118f78aefa6c044af946 Mon Sep 17 00:00:00 2001 From: Konsta Holtta Date: Mon, 30 Nov 2015 12:51:13 +0200 Subject: gpu: nvgpu: bitmap allocator for comptags Restore comptags to be bitmap-allocated, like they were before we had the buddy allocator. Bug 200145635 Change-Id: I681493871096f437014b7eca1182fefbaf7f6a74 Signed-off-by: Konsta Holtta Reviewed-on: http://git-master/r/839240 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 91a4964c9..479929885 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -18,7 +18,6 @@ #include #include "gk20a/gk20a.h" -#include "gk20a/gk20a_allocator.h" #include "gm20b/ltc_gm20b.h" #include "hw_proj_gp10b.h" #include "hw_mc_gp10b.h" @@ -110,8 +109,9 @@ static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) if (err) return err; - __gk20a_allocator_init(&gr->comp_tags, NULL, "comptag", - 1, max_comptag_lines - 1, 1, 10, 0); + err = gk20a_comptag_allocator_init(&gr->comp_tags, max_comptag_lines); + if (err) + return err; gr->comptags_per_cacheline = comptags_per_cacheline; gr->slices_per_ltc = slices_per_ltc; -- cgit v1.2.2 From 975c13c35fd386593f6b8315b035efb5868fddf3 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 15 Jan 2016 12:33:16 -0800 Subject: gpu: nvgpu: gp10b: enable gradual slowdown Enable gradual slowdown for gp10b and also correct thermal slowdown factors with extended mode. Bug 1719974 Change-Id: I31a5d7df71c98135273a980c49b70bc76fac0b40 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/933279 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/therm_gp10b.c | 53 ++++++++++++++++++++++++++++++----- 1 file changed, 46 insertions(+), 7 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c index 471edb872..7bf0c0e54 100644 --- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c @@ -3,7 +3,7 @@ * * GP10B Therm * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,6 +20,8 @@ static int gp10b_init_therm_setup_hw(struct gk20a *g) { + u32 v; + gk20a_dbg_fn(""); /* program NV_THERM registers */ @@ -27,14 +29,51 @@ static int gp10b_init_therm_setup_hw(struct gk20a *g) therm_use_a_ext_therm_1_enable_f() | therm_use_a_ext_therm_2_enable_f()); gk20a_writel(g, therm_evt_ext_therm_0_r(), - therm_evt_ext_therm_0_slow_factor_f( - therm_evt_ext_therm_0_slow_factor_init_v())); + therm_evt_ext_therm_0_slow_factor_f(0x2)); gk20a_writel(g, therm_evt_ext_therm_1_r(), - therm_evt_ext_therm_1_slow_factor_f( - therm_evt_ext_therm_1_slow_factor_init_v())); + therm_evt_ext_therm_1_slow_factor_f(0x6)); gk20a_writel(g, therm_evt_ext_therm_2_r(), - therm_evt_ext_therm_2_slow_factor_f( - therm_evt_ext_therm_2_slow_factor_init_v())); + therm_evt_ext_therm_2_slow_factor_f(0xe)); + + gk20a_writel(g, therm_grad_stepping_table_r(0), + therm_grad_stepping_table_slowdown_factor0_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) | + therm_grad_stepping_table_slowdown_factor1_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) | + therm_grad_stepping_table_slowdown_factor2_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) | + therm_grad_stepping_table_slowdown_factor3_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | + therm_grad_stepping_table_slowdown_factor4_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); + + gk20a_writel(g, therm_grad_stepping_table_r(1), + therm_grad_stepping_table_slowdown_factor0_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | + therm_grad_stepping_table_slowdown_factor1_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | + therm_grad_stepping_table_slowdown_factor2_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | + therm_grad_stepping_table_slowdown_factor3_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | + therm_grad_stepping_table_slowdown_factor4_f( + therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); + + v = gk20a_readl(g, therm_clk_timing_r(0)); + v |= therm_clk_timing_grad_slowdown_enabled_f(); + gk20a_writel(g, therm_clk_timing_r(0), v); + + v = gk20a_readl(g, therm_config2_r()); + v |= therm_config2_grad_enable_f(1); + v |= therm_config2_slowdown_factor_extended_f(1); + gk20a_writel(g, therm_config2_r(), v); + + gk20a_writel(g, therm_grad_stepping1_r(), + therm_grad_stepping1_pdiv_duration_f(32)); + + v = gk20a_readl(g, therm_grad_stepping0_r()); + v |= therm_grad_stepping0_feature_enable_f(); + gk20a_writel(g, therm_grad_stepping0_r(), v); return 0; } -- cgit v1.2.2 From 42c7d7435f2731fa57ce3bafb58f11d923b07843 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 26 Jan 2016 17:53:12 -0800 Subject: gpu: nvgpu: gp10b: add delay cycles before engine gating For copy engine, add 16 clock cycle delay before engine clock gating. Bug 1717152 Change-Id: Ife92299c052f44000bc0d900f0129a2eab13f3b5 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/998408 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 10 +++++++++- drivers/gpu/nvgpu/gp10b/therm_gp10b.c | 14 ++++++++++++++ 2 files changed, 23 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h index 17b1fb7ee..8a587b7c5 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -246,6 +246,14 @@ static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) { return 0x7 << 13; } +static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) +{ + return (v & 0xf) << 16; +} +static inline u32 therm_gate_ctrl_eng_delay_before_m(void) +{ + return 0xf << 16; +} static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) { return (v & 0xf) << 20; diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c index 7bf0c0e54..687593b05 100644 --- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c @@ -78,8 +78,22 @@ static int gp10b_init_therm_setup_hw(struct gk20a *g) return 0; } +static int gp10b_update_therm_gate_ctrl(struct gk20a *g) +{ + u32 gate_ctrl; + + gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A)); + gate_ctrl = set_field(gate_ctrl, + therm_gate_ctrl_eng_delay_before_m(), + therm_gate_ctrl_eng_delay_before_f(4)); + gk20a_writel(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A), gate_ctrl); + + return 0; +} + void gp10b_init_therm_ops(struct gpu_ops *gops) { gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw; + gops->therm.update_therm_gate_ctrl = gp10b_update_therm_gate_ctrl; } -- cgit v1.2.2 From a7726249433ed27f938df1552bb5356a7a8b19f4 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Thu, 8 Oct 2015 09:43:26 -0700 Subject: gpu: nvgpu: gp10b: enable power gating Enable engine level power gating(elpg) Bug 200144583 Change-Id: I66f3be841625c2c9e07cafbf19af8f1dbdbfd390 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/818637 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 6abb70c38..8bddff3d2 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -3,7 +3,7 @@ * * GK20A Tegra Platform Interface * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -296,7 +296,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { /* power management configuration */ .can_railgate = false, - .enable_elpg = false, + .enable_elpg = true, .enable_blcg = true, .enable_slcg = true, .enable_elcg = true, -- cgit v1.2.2 From 41e82ba8c358abd8165c1a11017e6f355c809731 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 8 Dec 2015 15:43:39 -0800 Subject: gpu: nvgpu: gp10b: clean-up pmu init operations Removed unwanted initlization of function pointer. Bug 200157852 Change-Id: I3b44ccce366f1b72c3ff769a7b9ab350bb2c0066 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/843218 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index dc7539a88..00701a50f 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B PMU * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -332,8 +332,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; } else { gk20a_init_pmu_ops(gops); - gops->pmu.pmu_setup_hw_and_bootstrap = - gm20b_init_nspmu_setup_hw1; gops->pmu.load_lsfalcon_ucode = NULL; gops->pmu.init_wpr_region = NULL; gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; -- cgit v1.2.2 From 59feaed89c828b347c79dae213f1cbe9db35415c Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Thu, 18 Jun 2015 16:31:50 -0700 Subject: gpu: nvgpu: gp10b: add ECC support Add ECC exception handling support for SM, TEX, and LTC. Bug 1635727 Bug 1637486 Change-Id: I8862ead5784f48742355432ec07c71a82b1b6735 Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/935362 Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 102 ++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 110 ++++++++++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 16 +++++ drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 23 +++++++ 4 files changed, 250 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 6bdb9a7c4..f8c31bd32 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -55,6 +55,106 @@ static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) return valid; } +static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event, struct channel_gk20a *fault_ch) +{ + int ret = 0; + u32 offset = proj_gpc_stride_v() * gpc + + proj_tpc_in_gpc_stride_v() * tpc; + u32 lrf_ecc_status, shm_ecc_status; + + gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, NULL); + + /* Check for LRF ECC errors. */ + lrf_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); + if ( (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) { + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Single bit error detected in SM LRF!"); + } + if ( (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || + (lrf_ecc_status & + gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) { + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Double bit error detected in SM LRF!"); + } + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, + lrf_ecc_status); + + /* Check for SHM ECC errors. */ + shm_ecc_status = gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); + if ((shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) { + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Single bit error detected in SM SHM!"); + } + if ( (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || + (shm_ecc_status & + gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) { + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Double bit error detected in SM SHM!"); + } + gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset, + shm_ecc_status); + + + return ret; +} + +static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, + bool *post_event) +{ + int ret = 0; + u32 offset = proj_gpc_stride_v() * gpc + + proj_tpc_in_gpc_stride_v() * tpc; + u32 esr; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); + + esr = gk20a_readl(g, + gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); + gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); + + if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Single bit error detected in TEX!"); + } + if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, + "Double bit error detected in TEX!"); + } + + gk20a_writel(g, + gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, + esr); + + return ret; +} + static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, struct channel_gk20a *c, bool patch) { @@ -1154,4 +1254,6 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask; gops->gr.get_access_map = gr_gp10b_get_access_map; + gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; + gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 347e530d9..9569bb9c0 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -466,6 +466,70 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) { return 0x00504238; } +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) +{ + return 0x005046b8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) +{ + return 0x40; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) +{ + return 0x80; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) +{ + return 0x200; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) +{ + return 0x400; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) +{ + return 0x800; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) +{ + return 0x005044a0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) +{ + return 0x10; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) +{ + return 0x20; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) +{ + return 0x100; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) +{ + return 0x200; +} static inline u32 gr_pri_be0_crop_status1_r(void) { return 0x00410134; @@ -3158,6 +3222,14 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(vo { return 0x10; } +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) +{ + return 0x20000000; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) +{ + return 0x40000000; +} static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) { return 0x20; @@ -3174,6 +3246,10 @@ static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) { return 0x2; } +static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) +{ + return 0x1; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) { return 0x0050450c; @@ -3210,6 +3286,14 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) { return 0x00504508; } +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) +{ + return 0x00000001; +} static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) { return (r >> 1) & 0x1; @@ -3322,6 +3406,14 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) { return 0x10; } +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) +{ + return 0x20000000; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) +{ + return 0x40000000; +} static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) { return 0x20; @@ -3330,6 +3422,22 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( { return 0x40; } +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) +{ + return 0x00504224; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) +{ + return 0x80; +} +static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) +{ + return 0x100; +} static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) { return 0x00504648; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index ea96a9aaa..302c2243d 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -286,6 +286,14 @@ static inline u32 ltc_ltcs_ltss_intr_r(void) { return 0x0017e20c; } +static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) +{ + return 0x100; +} +static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) +{ + return 0x200; +} static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) { return 0x1 << 20; @@ -294,6 +302,14 @@ static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) { return 0x1 << 30; } +static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) +{ + return 0x1000000; +} +static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) +{ + return 0x2000000; +} static inline u32 ltc_ltc0_lts0_intr_r(void) { return 0x0014040c; diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index 479929885..d0be86a4f 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -136,6 +136,20 @@ static void gp10b_ltc_isr(struct gk20a *g) ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + proj_ltc_stride_v() * ltc + proj_lts_stride_v() * slice); + + /* Detect and handle ECC errors */ + if (ltc_intr & + ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) { + gk20a_err(dev_from_gk20a(g), + "Single bit error detected in GPU L2!"); + g->ops.mm.l2_flush(g, true); + } + if (ltc_intr & + ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) { + gk20a_err(dev_from_gk20a(g), + "Double bit error detected in GPU L2!"); + } + gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", ltc, slice, ltc_intr); gk20a_writel(g, ltc_ltc0_lts0_intr_r() + @@ -148,10 +162,19 @@ static void gp10b_ltc_isr(struct gk20a *g) static void gp10b_ltc_init_fs_state(struct gk20a *g) { + u32 ltc_intr; + gm20b_ltc_init_fs_state(g); gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB)); + + /* Enable ECC interrupts */ + ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); + ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | + ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); + gk20a_writel(g, ltc_ltcs_ltss_intr_r(), + ltc_intr); } void gp10b_init_ltc(struct gpu_ops *gops) -- cgit v1.2.2 From e2df20c1cb17c9c1cd3ae717a9dddfcac000d09e Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 28 Dec 2015 16:21:58 +0530 Subject: gpu: nvgpu: mask hww_warp_esr for gp10b Add API gp10b_mask_hww_warp_esr() to mask hww_warp_esr appropriately on gp10b Bug 200156699 Change-Id: I451b5e949bd4e6d286e5d0c7cd7616e6cfaf3ea9 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/927129 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 11 +++++++++++ 1 file changed, 11 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f8c31bd32..a13b9a2c0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1224,6 +1224,16 @@ static void gr_gp10b_get_access_map(struct gk20a *g, *num_entries = ARRAY_SIZE(wl_addr_gp10b); } +static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) +{ + if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) + hww_warp_esr = set_field(hww_warp_esr, + gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), + gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); + + return hww_warp_esr; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -1256,4 +1266,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.get_access_map = gr_gp10b_get_access_map; gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; + gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr; } -- cgit v1.2.2 From 654271a675364f9b69edce9871693aac2a1603ff Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 18 Dec 2015 12:35:04 +0530 Subject: gpu: nvgpu: add CILP support for gp10b Add CILP support for gp10b by defining below function pointers (with detailed explanation) pre_process_sm_exception() - for CILP enabled channels, get the mask of errors - if we need to broadcast the stop_trigger, suspend all SMs - otherwise suspend only current SM - clear hww_global_esr values in h/w - gr_gp10b_set_cilp_preempt_pending() - get ctx_id - using sideband method, program FECS to generate interrupt on next ctxsw - disable and preempt the channel/TSG - set cilp_preempt_pending = true - clear single step mode - resume current SM handle_fecs_error() - we get ctxsw_intr1 upon next ctxsw - clear this interrupt - get handle of channel on which we first triggered SM exception - gr_gp10b_clear_cilp_preempt_pending() - set cilp_preempt_pending = false - send events to channel and debug session fd Bug 200156699 Change-Id: Ia765db47e68fb968fada6409609af505c079df53 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/925897 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 314 ++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 5 + drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 6 +- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 100 ++++++++ 4 files changed, 424 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a13b9a2c0..91adf20c7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -19,6 +19,7 @@ #include "gk20a/gr_gk20a.h" #include "gk20a/semaphore_gk20a.h" +#include "gk20a/dbg_gpu_gk20a.h" #include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ #include "gp10b/gr_gp10b.h" @@ -657,6 +658,8 @@ static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, if (err) return err; + (*gr_ctx)->t18x.ctx_id_valid = false; + if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; @@ -1224,6 +1227,314 @@ static void gr_gp10b_get_access_map(struct gk20a *g, *num_entries = ARRAY_SIZE(wl_addr_gp10b); } +static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) +{ + int ret = 0; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + ret = gk20a_disable_channel_tsg(g, fault_ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to disable channel/TSG!\n"); + return ret; + } + + ret = g->ops.fifo.update_runlist(g, 0, ~0, true, false); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to restart runlist 0!"); + return ret; + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); + + if (gk20a_is_channel_marked_as_tsg(fault_ch)) + gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); + else + gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg"); + + return ret; +} + +static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch) +{ + int ret; + struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + if (!gr_ctx) + return -EINVAL; + + if (gr_ctx->t18x.cilp_preempt_pending) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP is already pending for chid %d", + fault_ch->hw_chid); + return 0; + } + + /* get ctx_id from the ucode image */ + if (!gr_ctx->t18x.ctx_id_valid) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: looking up ctx id"); + ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); + if (ret) { + gk20a_err(dev_from_gk20a(g), "CILP: error looking up ctx id!\n"); + return ret; + } + gr_ctx->t18x.ctx_id_valid = true; + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id); + + /* send ucode method to set ctxsw interrupt */ + ret = gr_gk20a_submit_fecs_sideband_method_op(g, + (struct fecs_method_op_gk20a) { + .method.data = gr_ctx->t18x.ctx_id, + .method.addr = + gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), + .mailbox = { + .id = 1 /* sideband */, .data = 0, + .clr = ~0, .ret = NULL, + .ok = gr_fecs_ctxsw_mailbox_value_pass_v(), + .fail = 0}, + .cond.ok = GR_IS_UCODE_OP_EQUAL, + .cond.fail = GR_IS_UCODE_OP_SKIP}); + + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to enable ctxsw interrupt!"); + return ret; + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: enabled ctxsw completion interrupt"); + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: disabling channel %d", + fault_ch->hw_chid); + + ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), + "CILP: failed to disable channel!!"); + return ret; + } + + /* set cilp_preempt_pending = true and record the channel */ + gr_ctx->t18x.cilp_preempt_pending = true; + g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; + + return 0; +} + +static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, + struct channel_gk20a *fault_ch) +{ + struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + if (!gr_ctx) + return -EINVAL; + + /* The ucode is self-clearing, so all we need to do here is + to clear cilp_preempt_pending. */ + if (!gr_ctx->t18x.cilp_preempt_pending) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP is already cleared for chid %d\n", + fault_ch->hw_chid); + return 0; + } + + gr_ctx->t18x.cilp_preempt_pending = false; + g->gr.t18x.cilp_preempt_pending_chid = -1; + + return 0; +} + +/* @brief pre-process work on the SM exceptions to determine if we clear them or not. + * + * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing + */ +int gr_gp10b_pre_process_sm_exception(struct gk20a *g, + u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, + bool sm_debugger_attached, struct channel_gk20a *fault_ch, + bool *early_exit, bool *ignore_debugger) +{ + int ret; + bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode == + NVGPU_GR_PREEMPTION_MODE_CILP) ; + u32 global_mask = 0, dbgr_control0, global_esr_copy; + u32 offset = proj_gpc_stride_v() * gpc + + proj_tpc_in_gpc_stride_v() * tpc; + + *early_exit = false; + *ignore_debugger = false; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", + gpc, tpc, global_esr); + + if (cilp_enabled && sm_debugger_attached) { + if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); + + if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) + gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, + gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); + + global_mask = gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() | + gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() | + gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() | + gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f() | + gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() | + gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(); + + if (warp_esr != 0 || (global_esr & global_mask) != 0) { + *ignore_debugger = true; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n", + gpc, tpc); + + if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", + gpc, tpc); + gk20a_suspend_all_sms(g, global_mask, false); + + gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); + } else { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: STOP_TRIGGER from gpc %d tpc %d\n", + gpc, tpc); + gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); + } + + /* reset the HWW errors after locking down */ + global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); + gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: HWWs cleared for gpc %d tpc %d\n", + gpc, tpc); + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); + ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), "CILP: error while setting CILP preempt pending!\n"); + return ret; + } + + dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); + if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", + gpc, tpc); + dbgr_control0 = set_field(dbgr_control0, + gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), + gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); + gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); + } + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, + "CILP: resume for gpc %d tpc %d\n", + gpc, tpc); + gk20a_resume_single_sm(g, gpc, tpc); + + *ignore_debugger = true; + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); + } + + *early_exit = true; + } + return 0; +} + +static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) +{ + struct gr_ctx_desc *gr_ctx; + struct channel_gk20a *ch; + int chid; + int ret = -EINVAL; + + chid = g->gr.t18x.cilp_preempt_pending_chid; + + ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid)); + if (!ch) + return ret; + + gr_ctx = ch->ch_ctx.gr_ctx; + + if (gr_ctx->t18x.cilp_preempt_pending) { + *__chid = chid; + ret = 0; + } + + gk20a_channel_put(ch); + + return ret; +} + +static int gr_gp10b_handle_fecs_error(struct gk20a *g, + struct channel_gk20a *__ch, + struct gr_gk20a_isr_data *isr_data) +{ + u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); + struct channel_gk20a *ch; + int chid = -1; + int ret = 0; + + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); + + /* + * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) + * indicates that a CILP ctxsw save has finished + */ + if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) { + gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, + "CILP: ctxsw save completed!\n"); + + /* now clear the interrupt */ + gk20a_writel(g, gr_fecs_host_int_clear_r(), + gr_fecs_host_int_clear_ctxsw_intr1_clear_f()); + + ret = gr_gp10b_get_cilp_preempt_pending_chid(g, &chid); + if (ret) + goto clean_up; + + ch = gk20a_channel_get( + gk20a_fifo_channel_from_hw_chid(g, chid)); + if (!ch) + goto clean_up; + + + /* set preempt_pending to false */ + ret = gr_gp10b_clear_cilp_preempt_pending(g, ch); + if (ret) { + gk20a_err(dev_from_gk20a(g), "CILP: error while unsetting CILP preempt pending!\n"); + gk20a_channel_put(ch); + goto clean_up; + } + + if (gk20a_gr_sm_debugger_attached(g)) { + gk20a_err(dev_from_gk20a(g), "CILP: posting usermode event"); + gk20a_dbg_gpu_post_events(ch); + gk20a_channel_post_event(ch); + } + + gk20a_channel_put(ch); + } + +clean_up: + /* handle any remaining interrupts */ + return gk20a_gr_handle_fecs_error(g, __ch, isr_data); +} + static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) { if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) @@ -1267,4 +1578,7 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr; + gops->gr.pre_process_sm_exception = + gr_gp10b_pre_process_sm_exception; + gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 62b70a221..c35fb384f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -46,6 +46,8 @@ struct gr_t18x { struct dentry *debugfs_force_preemption_gfxp; struct dentry *debugfs_dump_ctxsw_stats; } ctx_vars; + + int cilp_preempt_pending_chid; }; struct gr_ctx_desc_t18x { @@ -53,6 +55,9 @@ struct gr_ctx_desc_t18x { struct mem_desc spill_ctxsw_buffer; struct mem_desc betacb_ctxsw_buffer; struct mem_desc pagepool_ctxsw_buffer; + u32 ctx_id; + bool ctx_id_valid; + bool cilp_preempt_pending; }; #define NVGPU_GR_PREEMPTION_MODE_GFXP 1 diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index f358d4054..49e92df94 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -286,4 +286,8 @@ static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_ { return 0x2; } +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 9569bb9c0..b494482ac 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1010,6 +1010,10 @@ static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) { return 0x00000004; } +static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) +{ + return 0x0000003a; +} static inline u32 gr_fecs_host_int_status_r(void) { return 0x00409c18; @@ -1022,14 +1026,30 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) { return (v & 0x1) << 18; } +static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) +{ + return (v & 0xffff) << 0; +} static inline u32 gr_fecs_host_int_clear_r(void) { return 0x00409c20; } +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) +{ + return (v & 0x1) << 1; +} +static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) +{ + return 0x2; +} static inline u32 gr_fecs_host_int_enable_r(void) { return 0x00409c24; } +static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) +{ + return 0x2; +} static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) { return 0x10000; @@ -2182,6 +2202,10 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) { return (v & 0xffff) << 0; } +static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) +{ + return (r >> 0) & 0xffff; +} static inline u32 gr_gpc0_tpc0_sm_arch_r(void) { return 0x0050469c; @@ -3326,6 +3350,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) { return 0x40000000; @@ -3398,6 +3430,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f( { return 0x40; } +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) +{ + return 0x80000000; +} static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) { return 0x00504650; @@ -3438,6 +3490,26 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) { return 0x100; } +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) +{ + return 0x1; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) +{ + return 0x2; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) +{ + return 0x4; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) +{ + return 0x8; +} +static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) +{ + return 0x80000000; +} static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) { return 0x00504648; @@ -3454,6 +3526,22 @@ static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) { return 0x0; } +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) +{ + return 0x1 << 24; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) +{ + return 0x7 << 25; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) +{ + return 0x0; +} +static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) +{ + return 0x00504654; +} static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) { return 0x00504770; @@ -3850,6 +3938,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) { return 0x0; } +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) +{ + return 0x1 << 3; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) +{ + return 0x8; +} +static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) +{ + return 0x0; +} static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) { return 0x1 << 30; -- cgit v1.2.2 From 4720ae6679db6ce0b87b185ea48d5d02a19a713e Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 2 Feb 2016 19:18:10 +0530 Subject: gpu: nvgpu: post events on all channels of TSG While posting CILP preemption complete event to user space, raise the event to all channels of TSG (if channel is part of TSG) This is a WAR until we have proper sync mechanism with user space to raise CILP events Bug 200156699 Change-Id: Ieedc866498a8c5464cf65962257a803b37da6826 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1001696 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 91adf20c7..6ed91bb17 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1523,8 +1523,21 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g, if (gk20a_gr_sm_debugger_attached(g)) { gk20a_err(dev_from_gk20a(g), "CILP: posting usermode event"); - gk20a_dbg_gpu_post_events(ch); - gk20a_channel_post_event(ch); + + if (gk20a_is_channel_marked_as_tsg(ch)) { + struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; + struct channel_gk20a *__ch; + + mutex_lock(&tsg->ch_list_lock); + list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { + gk20a_dbg_gpu_post_events(__ch); + gk20a_channel_post_event(__ch); + } + mutex_unlock(&tsg->ch_list_lock); + } else { + gk20a_dbg_gpu_post_events(ch); + gk20a_channel_post_event(ch); + } } gk20a_channel_put(ch); -- cgit v1.2.2 From de8d4d127cfa30daad9584448cd0553c2188a4ff Mon Sep 17 00:00:00 2001 From: Richard Zhao Date: Fri, 29 Jan 2016 11:32:44 -0800 Subject: gpu: nvgpu: vgpu: fix sparse warnings Bug 200088648 Change-Id: I61be7b4787e9bc9bac310a8739977f43c38a67ee Signed-off-by: Richard Zhao Reviewed-on: http://git-master/r/1000174 Reviewed-by: Aingara Paramakuru GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 14a7768a8..b665a8dd6 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c @@ -16,6 +16,7 @@ #include "vgpu_gr_gp10b.h" #include "vgpu_fifo_gp10b.h" #include "vgpu_mm_gp10b.h" +#include "nvgpu_gpuid_t18x.h" int vgpu_gp10b_init_hal(struct gk20a *g) { -- cgit v1.2.2 From 32e22e9f3c053c4b8b86f52b57d6700522494f1a Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 9 Feb 2016 18:32:35 +0530 Subject: gpu: nvgpu: fix sparse warning fix below sparse warning : drivers/gpu/nvgpu/gp10b/gr_gp10b.c:1364:5: warning: symbol 'gr_gp10b_pre_process_sm_exception' was not declared. Should it be static? Bug 200088648 Change-Id: Ie55ffc12eb653b10358001e2aef8766562fd0df9 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1009938 Reviewed-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 6ed91bb17..ae2ffc0ab 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B GPU GR * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -1361,7 +1361,7 @@ static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, * * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing */ -int gr_gp10b_pre_process_sm_exception(struct gk20a *g, +static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, bool sm_debugger_attached, struct channel_gk20a *fault_ch, bool *early_exit, bool *ignore_debugger) -- cgit v1.2.2 From 86a91ec164eef01cde6696c5537763b3d3e6af71 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Fri, 12 Feb 2016 16:28:28 +0530 Subject: gpu: nvgpu: pass channel pointer to handle sm exception Pass faulting channel pointer to gr_gk20a_handle_sm_exception() instead of NULL Bug 200156699 Change-Id: I909327e2a000bea8bc91cfd0820a759960664b46 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1011289 GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index ae2ffc0ab..c66dea927 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -64,7 +64,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, proj_tpc_in_gpc_stride_v() * tpc; u32 lrf_ecc_status, shm_ecc_status; - gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, NULL); + gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch); /* Check for LRF ECC errors. */ lrf_ecc_status = gk20a_readl(g, -- cgit v1.2.2 From 05af10a367123c221e4acccec020cf0b275204d3 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Fri, 11 Dec 2015 16:16:21 -0800 Subject: gpu: nvgpu: gp10b: add ECC stats sysfs nodes Add sysfs nodes for querying ECC single/double bit error counts. Bug 1699676 Change-Id: I6d5219facadaa17207ac759b88fe19077207d8f1 Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/935363 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 145 +++++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 28 +++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 92 +++++++ drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 22 +- drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 33 ++- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 328 +++++++++++++++++++++++++ 6 files changed, 644 insertions(+), 4 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index c66dea927..90d0ce8d7 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -80,6 +80,13 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Single bit error detected in SM LRF!"); + + g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, + 0); } if ( (lrf_ecc_status & gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || @@ -92,6 +99,13 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Double bit error detected in SM LRF!"); + + g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, + 0); } gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, lrf_ecc_status); @@ -107,17 +121,42 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || (shm_ecc_status & gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) { + u32 ecc_stats_reg_val; gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Single bit error detected in SM SHM!"); + + ecc_stats_reg_val = + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); + g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); + g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, + ecc_stats_reg_val); } if ( (shm_ecc_status & gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || (shm_ecc_status & gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) { + u32 ecc_stats_reg_val; gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Double bit error detected in SM SHM!"); + + ecc_stats_reg_val = + gk20a_readl(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); + g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); + gk20a_writel(g, + gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, + ecc_stats_reg_val); } gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset, shm_ecc_status); @@ -133,6 +172,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 offset = proj_gpc_stride_v() * gpc + proj_tpc_in_gpc_stride_v() * tpc; u32 esr; + u32 ecc_stats_reg_val; gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); @@ -143,10 +183,114 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Single bit error detected in TEX!"); + + /* Pipe 0 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + /* Pipe 1 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); } if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) { gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, "Double bit error detected in TEX!"); + + /* Pipe 0 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + /* Pipe 1 counters */ + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); + g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, + ecc_stats_reg_val); + + ecc_stats_reg_val = gk20a_readl(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); + g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); + ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, + ecc_stats_reg_val); + + + gk20a_writel(g, + gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, + gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); } gk20a_writel(g, @@ -1594,4 +1738,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gops->gr.pre_process_sm_exception = gr_gp10b_pre_process_sm_exception; gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; + gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs; } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index c35fb384f..bd4b5879a 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h @@ -35,6 +35,13 @@ enum { void gp10b_init_gr(struct gpu_ops *ops); int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, struct mem_desc *mem); +void gr_gp10b_create_sysfs(struct platform_device *dev); + +struct ecc_stat { + char **names; + u32 *counters; + struct hlist_node hash_node; +}; struct gr_t18x { struct { @@ -47,6 +54,27 @@ struct gr_t18x { struct dentry *debugfs_dump_ctxsw_stats; } ctx_vars; + struct { + struct ecc_stat sm_lrf_single_err_count; + struct ecc_stat sm_lrf_double_err_count; + + struct ecc_stat sm_shm_sec_count; + struct ecc_stat sm_shm_sed_count; + struct ecc_stat sm_shm_ded_count; + + struct ecc_stat tex_total_sec_pipe0_count; + struct ecc_stat tex_total_ded_pipe0_count; + struct ecc_stat tex_unique_sec_pipe0_count; + struct ecc_stat tex_unique_ded_pipe0_count; + struct ecc_stat tex_total_sec_pipe1_count; + struct ecc_stat tex_total_ded_pipe1_count; + struct ecc_stat tex_unique_sec_pipe1_count; + struct ecc_stat tex_unique_ded_pipe1_count; + + struct ecc_stat l2_sec_count; + struct ecc_stat l2_ded_count; + } ecc_stats; + int cilp_preempt_pending_chid; }; diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index b494482ac..0480527c9 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -530,6 +530,98 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe { return 0x200; } +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) +{ + return 0x005046bc; +} +static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) +{ + return 0x005046c0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) +{ + return 0x005044a4; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) +{ + return 0xff << 0; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) +{ + return 0xff << 8; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) +{ + return (r >> 8) & 0xff; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) +{ + return 0xff << 16; +} +static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) +{ + return (r >> 16) & 0xff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) +{ + return 0x005042c4; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) +{ + return 0x0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) +{ + return 0x1; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) +{ + return 0x2; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) +{ + return 0x00504218; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) +{ + return (r >> 16) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) +{ + return 0x005042ec; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) +{ + return 0xffff << 0; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) +{ + return (r >> 0) & 0xffff; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) +{ + return 0xffff << 16; +} +static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) +{ + return (r >> 16) & 0xffff; +} static inline u32 gr_pri_be0_crop_status1_r(void) { return 0x00410134; diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h index 302c2243d..5916f6952 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -314,6 +314,26 @@ static inline u32 ltc_ltc0_lts0_intr_r(void) { return 0x0014040c; } +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) +{ + return 0x0014051c; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) +{ + return 0xff << 0; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) +{ + return (r >> 0) & 0xff; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) +{ + return 0xff << 16; +} +static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) +{ + return (r >> 16) & 0xff; +} static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) { return 0x0017e2a0; diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index d0be86a4f..e68e762d3 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c @@ -133,21 +133,48 @@ static void gp10b_ltc_isr(struct gk20a *g) if ((mc_intr & 1 << ltc) == 0) continue; for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + - proj_ltc_stride_v() * ltc + - proj_lts_stride_v() * slice); + u32 offset = proj_ltc_stride_v() * ltc + + proj_lts_stride_v() * slice; + ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset); /* Detect and handle ECC errors */ if (ltc_intr & ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) { + u32 ecc_stats_reg_val; + gk20a_err(dev_from_gk20a(g), "Single bit error detected in GPU L2!"); + + ecc_stats_reg_val = + gk20a_readl(g, + ltc_ltc0_lts0_dstg_ecc_report_r() + offset); + g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] += + ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); + ecc_stats_reg_val &= + ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); + gk20a_writel(g, + ltc_ltc0_lts0_dstg_ecc_report_r() + offset, + ecc_stats_reg_val); + g->ops.mm.l2_flush(g, true); } if (ltc_intr & ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) { + u32 ecc_stats_reg_val; + gk20a_err(dev_from_gk20a(g), "Double bit error detected in GPU L2!"); + + ecc_stats_reg_val = + gk20a_readl(g, + ltc_ltc0_lts0_dstg_ecc_report_r() + offset); + g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] += + ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); + ecc_stats_reg_val &= + ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); + gk20a_writel(g, + ltc_ltc0_lts0_dstg_ecc_report_r() + offset, + ecc_stats_reg_val); } gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 8bddff3d2..0cfb1d91e 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -26,9 +26,14 @@ #include #include #include +#include #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" #include "platform_tegra.h" +#include "gr_gp10b.h" +#include "ltc_gp10b.h" +#include "hw_gr_gp10b.h" +#include "hw_ltc_gp10b.h" #define GP10B_MAX_SUPPORTED_FREQS 11 static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; @@ -40,6 +45,8 @@ static struct { {"gpu", 1000000000}, {"gpu_sys", 204000000} }; +static void gr_gp10b_remove_sysfs(struct device *dev); + /* * gp10b_tegra_get_clocks() * @@ -144,6 +151,8 @@ static int gp10b_tegra_remove(struct platform_device *pdev) /* remove gk20a power subdomain from host1x */ nvhost_unregister_client_domain(dev_to_genpd(&pdev->dev)); + gr_gp10b_remove_sysfs(&pdev->dev); + return 0; } @@ -345,3 +354,322 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .force_reset_in_do_idle = true, }; + + +#define ECC_STAT_NAME_MAX_SIZE 100 + + +DEFINE_HASHTABLE(ecc_hash_table, 5); + +static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array; +static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array; + +static struct device_attribute *dev_attr_sm_shm_ecc_sec_count_array; +static struct device_attribute *dev_attr_sm_shm_ecc_sed_count_array; +static struct device_attribute *dev_attr_sm_shm_ecc_ded_count_array; + +static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe0_count_array; +static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe0_count_array; +static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe0_count_array; +static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe0_count_array; +static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe1_count_array; +static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe1_count_array; +static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe1_count_array; +static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe1_count_array; + +static struct device_attribute *dev_attr_l2_ecc_sec_count_array; +static struct device_attribute *dev_attr_l2_ecc_ded_count_array; + + +static u32 gen_ecc_hash_key(char *str) +{ + int i = 0; + u32 hash_key = 0; + + while (str[i]) { + hash_key += (u32)(str[i]); + i++; + }; + + return hash_key; +} + +static ssize_t ecc_stat_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + const char *ecc_stat_full_name = attr->attr.name; + const char *ecc_stat_base_name; + unsigned int hw_unit; + struct ecc_stat *ecc_stat; + u32 hash_key; + + if (sscanf(ecc_stat_full_name, "ltc%u", &hw_unit) == 1) { + ecc_stat_base_name = &(ecc_stat_full_name[strlen("ltc0_")]); + } else if (sscanf(ecc_stat_full_name, "gpc0_tpc%u", &hw_unit) == 1) { + ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_tpc0_")]); + } else { + return snprintf(buf, + PAGE_SIZE, + "Error: Invalid ECC stat name!\n"); + } + + hash_key = gen_ecc_hash_key((char *)ecc_stat_base_name); + hash_for_each_possible(ecc_hash_table, + ecc_stat, + hash_node, + hash_key) { + if (!strcmp(ecc_stat_full_name, ecc_stat->names[hw_unit])) + return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stat->counters[hw_unit]); + } + + return snprintf(buf, PAGE_SIZE, "Error: No ECC stat found!\n"); +} + +static int ecc_stat_create(struct platform_device *dev, + int is_l2, + char *ecc_stat_name, + struct ecc_stat *ecc_stat, + struct device_attribute *dev_attr_array) +{ + int error = 0; + struct gk20a *g = get_gk20a(dev); + int num_hw_units = 0; + int hw_unit = 0; + u32 hash_key = 0; + + if (is_l2) + num_hw_units = g->ltc_count; + else + num_hw_units = g->gr.tpc_count; + + /* Allocate arrays */ + dev_attr_array = kzalloc(sizeof(struct device_attribute) * num_hw_units, GFP_KERNEL); + ecc_stat->counters = kzalloc(sizeof(u32) * num_hw_units, GFP_KERNEL); + ecc_stat->names = kzalloc(sizeof(char *) * num_hw_units, GFP_KERNEL); + for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { + ecc_stat->names[hw_unit] = kzalloc(sizeof(char) * ECC_STAT_NAME_MAX_SIZE, GFP_KERNEL); + } + + for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { + /* Fill in struct device_attribute members */ + if (is_l2) + snprintf(ecc_stat->names[hw_unit], + ECC_STAT_NAME_MAX_SIZE, + "ltc%d_%s", + hw_unit, + ecc_stat_name); + else + snprintf(ecc_stat->names[hw_unit], + ECC_STAT_NAME_MAX_SIZE, + "gpc0_tpc%d_%s", + hw_unit, + ecc_stat_name); + dev_attr_array[hw_unit].attr.name = ecc_stat->names[hw_unit]; + dev_attr_array[hw_unit].attr.mode = VERIFY_OCTAL_PERMISSIONS(S_IRUGO); + dev_attr_array[hw_unit].show = ecc_stat_show; + dev_attr_array[hw_unit].store = NULL; + + /* Create sysfs file */ + error |= device_create_file(&dev->dev, + &dev_attr_array[hw_unit]); + } + + /* Add hash table entry */ + hash_key = gen_ecc_hash_key(ecc_stat_name); + hash_add(ecc_hash_table, + &ecc_stat->hash_node, + hash_key); + + return error; +} + +static void ecc_stat_remove(struct device *dev, + int is_l2, + struct ecc_stat *ecc_stat, + struct device_attribute *dev_attr_array) +{ + struct platform_device *ndev = to_platform_device(dev); + struct gk20a *g = get_gk20a(ndev); + int num_hw_units = 0; + int hw_unit = 0; + + if (is_l2) + num_hw_units = g->ltc_count; + else + num_hw_units = g->gr.tpc_count; + + /* Remove sysfs files */ + for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { + device_remove_file(dev, &dev_attr_array[hw_unit]); + } + + /* Remove hash table entry */ + hash_del(&ecc_stat->hash_node); + + /* Free arrays */ + kfree(ecc_stat->counters); + for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { + kfree(ecc_stat->names[hw_unit]); + } + kfree(ecc_stat->names); + kfree(dev_attr_array); +} + +void gr_gp10b_create_sysfs(struct platform_device *dev) +{ + int error = 0; + struct gk20a *g = get_gk20a(dev); + + error |= ecc_stat_create(dev, + 0, + "sm_lrf_ecc_single_err_count", + &g->gr.t18x.ecc_stats.sm_lrf_single_err_count, + dev_attr_sm_lrf_ecc_single_err_count_array); + error |= ecc_stat_create(dev, + 0, + "sm_lrf_ecc_double_err_count", + &g->gr.t18x.ecc_stats.sm_lrf_double_err_count, + dev_attr_sm_lrf_ecc_double_err_count_array); + + error |= ecc_stat_create(dev, + 0, + "sm_shm_ecc_sec_count", + &g->gr.t18x.ecc_stats.sm_shm_sec_count, + dev_attr_sm_shm_ecc_sec_count_array); + error |= ecc_stat_create(dev, + 0, + "sm_shm_ecc_sed_count", + &g->gr.t18x.ecc_stats.sm_shm_sed_count, + dev_attr_sm_shm_ecc_sed_count_array); + error |= ecc_stat_create(dev, + 0, + "sm_shm_ecc_ded_count", + &g->gr.t18x.ecc_stats.sm_shm_ded_count, + dev_attr_sm_shm_ecc_ded_count_array); + + error |= ecc_stat_create(dev, + 0, + "tex_ecc_total_sec_pipe0_count", + &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count, + dev_attr_tex_ecc_total_sec_pipe0_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_total_ded_pipe0_count", + &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count, + dev_attr_tex_ecc_total_ded_pipe0_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_unique_sec_pipe0_count", + &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count, + dev_attr_tex_ecc_unique_sec_pipe0_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_unique_ded_pipe0_count", + &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count, + dev_attr_tex_ecc_unique_ded_pipe0_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_total_sec_pipe1_count", + &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count, + dev_attr_tex_ecc_total_sec_pipe1_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_total_ded_pipe1_count", + &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count, + dev_attr_tex_ecc_total_ded_pipe1_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_unique_sec_pipe1_count", + &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count, + dev_attr_tex_ecc_unique_sec_pipe1_count_array); + error |= ecc_stat_create(dev, + 0, + "tex_ecc_unique_ded_pipe1_count", + &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count, + dev_attr_tex_ecc_unique_ded_pipe1_count_array); + + error |= ecc_stat_create(dev, + 1, + "lts0_ecc_sec_count", + &g->gr.t18x.ecc_stats.l2_sec_count, + dev_attr_l2_ecc_sec_count_array); + error |= ecc_stat_create(dev, + 1, + "lts0_ecc_ded_count", + &g->gr.t18x.ecc_stats.l2_ded_count, + dev_attr_l2_ecc_ded_count_array); + + if (error) + dev_err(&dev->dev, "Failed to create sysfs attributes!\n"); +} + +static void gr_gp10b_remove_sysfs(struct device *dev) +{ + struct platform_device *ndev = to_platform_device(dev); + struct gk20a *g = get_gk20a(ndev); + + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.sm_lrf_single_err_count, + dev_attr_sm_lrf_ecc_single_err_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.sm_lrf_double_err_count, + dev_attr_sm_lrf_ecc_double_err_count_array); + + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.sm_shm_sec_count, + dev_attr_sm_shm_ecc_sec_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.sm_shm_sed_count, + dev_attr_sm_shm_ecc_sed_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.sm_shm_ded_count, + dev_attr_sm_shm_ecc_ded_count_array); + + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count, + dev_attr_tex_ecc_total_sec_pipe0_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count, + dev_attr_tex_ecc_total_ded_pipe0_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count, + dev_attr_tex_ecc_unique_sec_pipe0_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count, + dev_attr_tex_ecc_unique_ded_pipe0_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count, + dev_attr_tex_ecc_total_sec_pipe1_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count, + dev_attr_tex_ecc_total_ded_pipe1_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count, + dev_attr_tex_ecc_unique_sec_pipe1_count_array); + ecc_stat_remove(dev, + 0, + &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count, + dev_attr_tex_ecc_unique_ded_pipe1_count_array); + + ecc_stat_remove(dev, + 1, + &g->gr.t18x.ecc_stats.l2_sec_count, + dev_attr_l2_ecc_sec_count_array); + ecc_stat_remove(dev, + 1, + &g->gr.t18x.ecc_stats.l2_ded_count, + dev_attr_l2_ecc_ded_count_array); +} -- cgit v1.2.2 From b8c0739d4d00e1474fd267c7e5fe200791486ba9 Mon Sep 17 00:00:00 2001 From: Mahantesh Kumbar Date: Fri, 19 Feb 2016 15:23:30 +0530 Subject: gpu: nvgpu: gp10b: Enable adaptive ELPG ELPG is enabled on TOT. Bug 200144583 Change-Id: Icbdcb5f575a4ca37becf47b098fbd6a1f89feec7 Signed-off-by: Mahantesh Kumbar Reviewed-on: http://git-master/r/1013845 Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 0cfb1d91e..3221e4233 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -309,6 +309,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .enable_blcg = true, .enable_slcg = true, .enable_elcg = true, + .enable_aelpg = true, /* ptimer src frequency in hz*/ .ptimer_src_freq = 31250000, -- cgit v1.2.2 From 71b59d75fc49e2159830026bce387ef4d829faa8 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 22 Sep 2015 12:40:24 -0700 Subject: gpu: nvgpu: gp10b: enable gpu rail gating Bug 1698618 Change-Id: Iabfd726891165d7879376ab96445b7b81b907153 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/841856 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 3221e4233..65e11d37b 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -304,7 +304,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .clockgate_delay = 50, /* power management configuration */ - .can_railgate = false, + .can_railgate = true, .enable_elpg = true, .enable_blcg = true, .enable_slcg = true, -- cgit v1.2.2 From 7c1f6f0b2998c354f315b431e00f3c8f861cb190 Mon Sep 17 00:00:00 2001 From: Prashant Gaikwad Date: Wed, 24 Feb 2016 11:47:28 +0530 Subject: Revert "gpu: nvgpu: gp10b: enable gpu rail gating" This reverts commit 71b59d75fc49e2159830026bce387ef4d829faa8 since it causes suspend_sanity to fail on quill platform. On system resume, we see the following error dump from GPU gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 501 timed out gk20a 17000000.gp10b: gk20a_fifo_set_ctx_mmu_error_ch: channel 501 generated a mmu fault gk20a 17000000.gp10b: gk20a_set_error_notifier: error notifier set to 31 for ch 501 gk20a 17000000.gp10b: gk20a_channel_timeout_handler: Job on channel 509 timed out Change-Id: I61bc3b0745fe136675ab79b13f54e9126602f51c Signed-off-by: Prashant Gaikwad Reviewed-on: http://git-master/r/1017967 Reviewed-by: Bharat Nihalani --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 65e11d37b..3221e4233 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -304,7 +304,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .clockgate_delay = 50, /* power management configuration */ - .can_railgate = true, + .can_railgate = false, .enable_elpg = true, .enable_blcg = true, .enable_slcg = true, -- cgit v1.2.2 From a0b75eba5e9ac8869911af445ca7fe3b29c694df Mon Sep 17 00:00:00 2001 From: Supriya Date: Thu, 10 Dec 2015 12:54:38 +0530 Subject: gpu: nvgpu: ECC override -sysfs functions to call into LS PMU and modify ECC overide register Bug 1699676 Change-Id: Iaf6cc3a86160b806e52ab168577caad42b2c5d22 Signed-off-by: Supriya Reviewed-on: http://git-master/r/921252 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Vijayakumar Subbu GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom Tested-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | 66 ++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h | 25 +++++++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 10 ++++ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 ++ drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 8 ++- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 76 +++++++++++++++++++++++++- 7 files changed, 187 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c create mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 0542fd678..8b930bca4 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_GK20A) += \ gp10b_gating_reglist.o \ regops_gp10b.o \ cde_gp10b.o \ - therm_gp10b.o + therm_gp10b.o \ + gp10b_sysfs.o obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c new file mode 100644 index 000000000..800f39c3e --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c @@ -0,0 +1,66 @@ +/* + * GP10B specific sysfs files + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include + +#include "gk20a/gk20a.h" +#include "gp10b_sysfs.h" + +#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) + +static ssize_t ecc_enable_store(struct device *device, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct platform_device *ndev = to_platform_device(device); + struct gk20a *g = get_gk20a(ndev); + u32 ecc_mask; + u32 err = 0; + + err = sscanf(buf, "%d", &ecc_mask); + if (err == 1) { + err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd + (g, ecc_mask); + if (err) + dev_err(device, "ECC override did not happen\n"); + } else + return -EINVAL; + return count; +} + +static ssize_t ecc_enable_read(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct platform_device *ndev = to_platform_device(device); + struct gk20a *g = get_gk20a(ndev); + + return sprintf(buf, "ecc override =0x%x\n", + g->ops.gr.get_lrf_tex_ltc_dram_override(g)); +} + +static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store); + +void gp10b_create_sysfs(struct platform_device *dev) +{ + int error = 0; + + error |= device_create_file(&dev->dev, &dev_attr_ecc_enable); + if (error) + dev_err(&dev->dev, "Failed to create sysfs attributes!\n"); +} + +void gp10b_remove_sysfs(struct device *dev) +{ + device_remove_file(dev, &dev_attr_ecc_enable); +} diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h new file mode 100644 index 000000000..c1d101daf --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h @@ -0,0 +1,25 @@ +/* + * GP10B specific sysfs files + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _GP10B_SYSFS_H_ +#define _GP10B_SYSFS_H_ + +/*ECC Fuse*/ +#define FUSE_OPT_ECC_EN 0x358 + +void gp10b_create_sysfs(struct platform_device *dev); +void gp10b_remove_sysfs(struct device *dev); + +#endif /*_GP10B_SYSFS_H_*/ diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 90d0ce8d7..9eea7d436 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -28,6 +28,7 @@ #include "hw_proj_gp10b.h" #include "hw_ctxsw_prog_gp10b.h" #include "hw_mc_gp10b.h" +#include "gp10b_sysfs.h" #include static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) @@ -1702,6 +1703,14 @@ static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) return hww_warp_esr; } +static u32 get_ecc_override_val(struct gk20a *g) +{ + if (tegra_fuse_readl(FUSE_OPT_ECC_EN)) + return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); + else + return 0; +} + void gp10b_init_gr(struct gpu_ops *gops) { gm20b_init_gr(gops); @@ -1739,4 +1748,5 @@ void gp10b_init_gr(struct gpu_ops *gops) gr_gp10b_pre_process_sm_exception; gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs; + gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val; } diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 0480527c9..62ac13274 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1478,6 +1478,10 @@ static inline u32 gr_fecs_ctxsw_idlestate_r(void) { return 0x00409420; } +static inline u32 gr_fecs_feature_override_ecc_r(void) +{ + return 0x00409658; +} static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { return 0x00502420; diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 3221e4233..c4a5179a0 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -34,6 +34,7 @@ #include "ltc_gp10b.h" #include "hw_gr_gp10b.h" #include "hw_ltc_gp10b.h" +#include "gp10b_sysfs.h" #define GP10B_MAX_SUPPORTED_FREQS 11 static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; @@ -142,7 +143,8 @@ static int gp10b_tegra_late_probe(struct platform_device *pdev) { /* Make gk20a power domain a subdomain of host1x */ nvhost_register_client_domain(dev_to_genpd(&pdev->dev)); - + /*Create GP10B specific sysfs*/ + gp10b_create_sysfs(pdev); return 0; } @@ -150,9 +152,9 @@ static int gp10b_tegra_remove(struct platform_device *pdev) { /* remove gk20a power subdomain from host1x */ nvhost_unregister_client_domain(dev_to_genpd(&pdev->dev)); - gr_gp10b_remove_sysfs(&pdev->dev); - + /*Remove GP10B specific sysfs*/ + gp10b_remove_sysfs(&pdev->dev); return 0; } diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 00701a50f..6a7048130 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c @@ -2,7 +2,7 @@ * GP10B PMU * * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. -* + * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, * version 2, as published by the Free Software Foundation. @@ -14,6 +14,7 @@ */ #include /* for udelay */ +#include #include "gk20a/gk20a.h" #include "gk20a/pmu_gk20a.h" #include "gm20b/acr_gm20b.h" @@ -21,6 +22,7 @@ #include "pmu_gp10b.h" #include "hw_pwr_gp10b.h" +#include "gp10b_sysfs.h" #define gp10b_dbg_pmu(fmt, arg...) \ gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) @@ -324,6 +326,76 @@ static int gp10b_init_pmu_setup_hw1(struct gk20a *g) } +static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg, + void *param, u32 handle, u32 status) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc = + &msg->msg.lrf_tex_ltc_dram.en_dis; + gk20a_dbg_fn(""); + + if (status != 0) { + gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted"); + return; + } + if (msg->msg.lrf_tex_ltc_dram.msg_type != + PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) { + gk20a_err(dev_from_gk20a(g), + "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd"); + return; + } else if (ecc->pmu_status != 0) { + gk20a_err(dev_from_gk20a(g), + "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x", + ecc->pmu_status); + gk20a_err(dev_from_gk20a(g), + "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x", + ecc->en_fail_mask); + gk20a_err(dev_from_gk20a(g), + "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x", + ecc->dis_fail_mask); + } else + pmu->override_done = 1; + gk20a_dbg_fn("done"); +} + +static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) +{ + struct pmu_gk20a *pmu = &g->pmu; + struct pmu_cmd cmd; + u32 seq; + int status; + gk20a_dbg_fn(""); + + if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) { + gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); + return -1; + } + if (!(g->acr.capabilities & + ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) { + gk20a_err(dev_from_gk20a(g), "check ACR capabilities"); + return -1; + } + memset(&cmd, 0, sizeof(struct pmu_cmd)); + cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE; + cmd.hdr.size = PMU_CMD_HDR_SIZE + + sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis); + cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type = + PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS; + cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff); + + gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC"); + pmu->override_done = 0; + status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, + pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0); + if (status) + gk20a_err(dev_from_gk20a(g), "ECC override failed"); + else + pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), + &pmu->override_done, 1); + gk20a_dbg_fn("done"); + return status; +} + void gp10b_init_pmu_ops(struct gpu_ops *gops) { if (gops->privsecurity) { @@ -342,4 +414,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; + gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = + send_ecc_overide_en_dis_cmd; } -- cgit v1.2.2 From d27275cea206a0a968727fc8f85e8e872a6a7a60 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Fri, 26 Feb 2016 10:12:49 -0800 Subject: Revert "Revert "gpu: nvgpu: gp10b: enable gpu rail gating"" This reverts commit 7c1f6f0b2998c354f315b431e00f3c8f861cb190. Bug 200176691 Change-Id: Ia546513ec5c61999f6eb4d56ccd7e45ae072167c Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1020813 Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index c4a5179a0..43d905287 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -306,7 +306,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { .clockgate_delay = 50, /* power management configuration */ - .can_railgate = false, + .can_railgate = true, .enable_elpg = true, .enable_blcg = true, .enable_slcg = true, -- cgit v1.2.2 From dcb41e1909cf7d7d610181e7b0f71350cb7c40cd Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 1 Mar 2016 13:32:42 -0800 Subject: gpu: nvgpu: t18x: update slcg prod settings Update prod settings to disable slcg pbdma related domains. Bug 1703083 Change-Id: I9f9192da69d07c5cea5bc7d79a031e5d2428b685 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1022219 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c index fbf146a2a..7be9b60ff 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -54,7 +54,7 @@ static const struct gating_desc gp10b_slcg_fb[] = { /* slcg fifo */ static const struct gating_desc gp10b_slcg_fifo[] = { - {.addr = 0x000026ac, .prod = 0x00000100, .disable = 0x0001fffe}, + {.addr = 0x000026ac, .prod = 0x00000f00, .disable = 0x0001fffe}, }; /* slcg gr */ -- cgit v1.2.2 From d391cce5650c3a0f592f4469be14f2c0b6d81567 Mon Sep 17 00:00:00 2001 From: Amit Sharma Date: Wed, 2 Mar 2016 10:00:44 +0530 Subject: gpu: nvgpu: gp10b: make local symbol static Fixed the following sparse warning by making local symbol static: - platform_gp10b_tegra.c:365: warning: symbol 'ecc_hash_table' was not declared. Should it be static? Bug 200088648 Change-Id: Iea1a682c3ee0609730366d44fab91849cd59c9ad Signed-off-by: Amit Sharma Reviewed-on: http://git-master/r/1022410 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam Tested-by: Sachin Nikam --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index 43d905287..dfeba9c42 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -362,7 +362,7 @@ struct gk20a_platform t18x_gpu_tegra_platform = { #define ECC_STAT_NAME_MAX_SIZE 100 -DEFINE_HASHTABLE(ecc_hash_table, 5); +static DEFINE_HASHTABLE(ecc_hash_table, 5); static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array; static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array; -- cgit v1.2.2 From 063e3d5ae87612e3f896735d6b39240f49d48941 Mon Sep 17 00:00:00 2001 From: Adeel Raza Date: Mon, 29 Feb 2016 14:25:15 -0800 Subject: gpu: nvgpu: gp10b: only create ECC stats once The ECC sysfs stat creation function is called on GR init. GR can get initialized multiple times but we only need to create the ECC stats once. Therefore, add a check to avoid creating duplicate stat sysfs nodes. Change-Id: Ifb338e57643f2f15492df137d2a7521e0c990cf2 Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/1021660 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index dfeba9c42..e1a96e4c0 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -524,6 +524,13 @@ void gr_gp10b_create_sysfs(struct platform_device *dev) int error = 0; struct gk20a *g = get_gk20a(dev); + /* This stat creation function is called on GR init. GR can get + initialized multiple times but we only need to create the ECC + stats once. Therefore, add the following check to avoid + creating duplicate stat sysfs nodes. */ + if (g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters != NULL) + return; + error |= ecc_stat_create(dev, 0, "sm_lrf_ecc_single_err_count", -- cgit v1.2.2 From 9a8a533e18d81964df148c225773eea2b76039e1 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 29 Feb 2016 16:04:16 +0530 Subject: gpu: host1x: add T186 support Add host1x05 version and fill in the h/w details in host1x05_info Add all the hardware accessors for T186 (channel, sync, uclass accessors) Add hardware support files for host1x channel, syncpoints, cdma, pushbuffer, interrupt, and debug support Keep gather filter disabled Things working with this : - cdma operations - basic channel job submit path - syncpoint support - syncpoint interrupt mechanism - debug dump With this support, below tests pass for VIC client $nvrm_channel channel_Basic $nvrm_channel --module=vic Bug 1704301 Change-Id: I7d97560cb1e3a57733fa0853936b0783c71b7060 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1021434 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen Reviewed-by: Shridhar Rasal --- drivers/gpu/host1x/Makefile | 8 + drivers/gpu/host1x/dev_t186.c | 40 ++++ drivers/gpu/host1x/dev_t186.h | 34 +++ drivers/gpu/host1x/hw/cdma_hw_t186.c | 340 ++++++++++++++++++++++++++++ drivers/gpu/host1x/hw/channel_hw_t186.c | 297 ++++++++++++++++++++++++ drivers/gpu/host1x/hw/debug_hw_t186.c | 288 +++++++++++++++++++++++ drivers/gpu/host1x/hw/host1x05.c | 40 ++++ drivers/gpu/host1x/hw/host1x05.h | 24 ++ drivers/gpu/host1x/hw/host1x05_hardware.h | 128 +++++++++++ drivers/gpu/host1x/hw/hw_host1x05_channel.h | 169 ++++++++++++++ drivers/gpu/host1x/hw/hw_host1x05_sync.h | 321 ++++++++++++++++++++++++++ drivers/gpu/host1x/hw/hw_host1x05_uclass.h | 157 +++++++++++++ drivers/gpu/host1x/hw/intr_hw_t186.c | 247 ++++++++++++++++++++ drivers/gpu/host1x/hw/syncpt_hw_t186.c | 126 +++++++++++ 14 files changed, 2219 insertions(+) create mode 100644 drivers/gpu/host1x/Makefile create mode 100644 drivers/gpu/host1x/dev_t186.c create mode 100644 drivers/gpu/host1x/dev_t186.h create mode 100644 drivers/gpu/host1x/hw/cdma_hw_t186.c create mode 100644 drivers/gpu/host1x/hw/channel_hw_t186.c create mode 100644 drivers/gpu/host1x/hw/debug_hw_t186.c create mode 100644 drivers/gpu/host1x/hw/host1x05.c create mode 100644 drivers/gpu/host1x/hw/host1x05.h create mode 100644 drivers/gpu/host1x/hw/host1x05_hardware.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x05_channel.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x05_sync.h create mode 100644 drivers/gpu/host1x/hw/hw_host1x05_uclass.h create mode 100644 drivers/gpu/host1x/hw/intr_hw_t186.c create mode 100644 drivers/gpu/host1x/hw/syncpt_hw_t186.c (limited to 'drivers/gpu') diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile new file mode 100644 index 000000000..9c8c6467b --- /dev/null +++ b/drivers/gpu/host1x/Makefile @@ -0,0 +1,8 @@ +ccflags-y += -Idrivers/gpu/host1x +ccflags-y += -I../kernel-t18x/drivers/gpu/host1x + +host1x-t186-y = \ + dev_t186.o \ + hw/host1x05.o + +obj-$(CONFIG_TEGRA_HOST1X) += host1x-t186.o diff --git a/drivers/gpu/host1x/dev_t186.c b/drivers/gpu/host1x/dev_t186.c new file mode 100644 index 000000000..e4d148760 --- /dev/null +++ b/drivers/gpu/host1x/dev_t186.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "dev.h" +#include "dev_t186.h" + +#include "hw/host1x05.h" + +struct host1x_info host1x05_info = { + .nb_channels = 63, + .nb_pts = 576, + .nb_mlocks = 24, + .nb_bases = 16, + .init = host1x05_init, + .sync_offset = 0x0, + .gather_filter_enabled = false, +}; + +void host1x_writel(struct host1x *host1x, u32 v, u32 r) +{ + writel(v, host1x->regs + r); +} + +u32 host1x_readl(struct host1x *host1x, u32 r) +{ + return readl(host1x->regs + r); +} diff --git a/drivers/gpu/host1x/dev_t186.h b/drivers/gpu/host1x/dev_t186.h new file mode 100644 index 000000000..be9726e88 --- /dev/null +++ b/drivers/gpu/host1x/dev_t186.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HOST1X_DEV_T186_H +#define HOST1X_DEV_T186_H + +#include "dev.h" + +extern struct host1x_info host1x05_info; + +void host1x_writel(struct host1x *host1x, u32 v, u32 r); +u32 host1x_readl(struct host1x *host1x, u32 r); + +static inline void host1x_hw_sync_get_mutex_owner(struct host1x *host, + struct host1x_syncpt *sp, + unsigned int mutex_id, bool *cpu, bool *ch, + unsigned int *chid) +{ + host->syncpt_op->get_mutex_owner(sp, mutex_id, cpu, ch, chid); +} +#endif diff --git a/drivers/gpu/host1x/hw/cdma_hw_t186.c b/drivers/gpu/host1x/hw/cdma_hw_t186.c new file mode 100644 index 000000000..e903f3e8b --- /dev/null +++ b/drivers/gpu/host1x/hw/cdma_hw_t186.c @@ -0,0 +1,340 @@ +/* + * Tegra host1x Command DMA + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include "cdma.h" +#include "channel.h" +#include "dev.h" +#include "debug.h" + +/* + * Put the restart at the end of pushbuffer memory + */ +static void push_buffer_init(struct push_buffer *pb) +{ + *(u32 *)(pb->mapped + pb->size_bytes) = host1x_opcode_restart(0); +} + +/* + * Increment timedout buffer's syncpt via CPU. + */ +static void cdma_timeout_handle(struct host1x_cdma *cdma, u32 getptr, + u32 nr_slots) +{ + struct host1x *host1x = cdma_to_host1x(cdma); + struct push_buffer *pb = &cdma->push_buffer; + + /* NOP all the PB slots */ + while (nr_slots--) { + u32 *p = (u32 *)(pb->mapped + getptr); + *(p++) = HOST1X_OPCODE_NOP; + *(p++) = HOST1X_OPCODE_NOP; + dev_dbg(host1x->dev, "%s: NOP at %pad+%#x\n", __func__, + &pb->phys, getptr); + getptr = (getptr + 8) & (pb->size_bytes - 1); + } + wmb(); +} + +/* + * Start channel DMA + */ +static void cdma_start(struct host1x_cdma *cdma) +{ + struct host1x_channel *ch = cdma_to_channel(cdma); + + if (cdma->running) + return; + + cdma->last_pos = cdma->push_buffer.pos; + + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, + HOST1X_CHANNEL_DMACTRL); + + /* set base, put and end pointer */ + host1x_ch_writel(ch, cdma->push_buffer.phys, HOST1X_CHANNEL_DMASTART); + host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); + host1x_ch_writel(ch, cdma->push_buffer.phys + + cdma->push_buffer.size_bytes + 4, + HOST1X_CHANNEL_DMAEND); + + /* reset GET */ + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | + HOST1X_CHANNEL_DMACTRL_DMAGETRST | + HOST1X_CHANNEL_DMACTRL_DMAINITGET, + HOST1X_CHANNEL_DMACTRL); + + host1x_channel_enable_gather_filter(ch); + + /* start the command DMA */ + host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL); + + cdma->running = true; +} + +/* + * Similar to cdma_start(), but rather than starting from an idle + * state (where DMA GET is set to DMA PUT), on a timeout we restore + * DMA GET from an explicit value (so DMA may again be pending). + */ +static void cdma_timeout_restart(struct host1x_cdma *cdma, u32 getptr) +{ + struct host1x *host1x = cdma_to_host1x(cdma); + struct host1x_channel *ch = cdma_to_channel(cdma); + + if (cdma->running) + return; + + cdma->last_pos = cdma->push_buffer.pos; + + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, + HOST1X_CHANNEL_DMACTRL); + + /* set base, end pointer (all of memory) */ + host1x_ch_writel(ch, cdma->push_buffer.phys, HOST1X_CHANNEL_DMASTART); + host1x_ch_writel(ch, cdma->push_buffer.phys + + cdma->push_buffer.size_bytes, + HOST1X_CHANNEL_DMAEND); + + /* set GET, by loading the value in PUT (then reset GET) */ + host1x_ch_writel(ch, getptr, HOST1X_CHANNEL_DMAPUT); + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP | + HOST1X_CHANNEL_DMACTRL_DMAGETRST | + HOST1X_CHANNEL_DMACTRL_DMAINITGET, + HOST1X_CHANNEL_DMACTRL); + + dev_dbg(host1x->dev, + "%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n", __func__, + host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET), + host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT), + cdma->last_pos); + + /* deassert GET reset and set PUT */ + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, + HOST1X_CHANNEL_DMACTRL); + host1x_ch_writel(ch, cdma->push_buffer.pos, HOST1X_CHANNEL_DMAPUT); + + host1x_channel_enable_gather_filter(ch); + + /* start the command DMA */ + host1x_ch_writel(ch, 0, HOST1X_CHANNEL_DMACTRL); + + cdma->running = true; +} + +/* + * Kick channel DMA into action by writing its PUT offset (if it has changed) + */ +static void cdma_flush(struct host1x_cdma *cdma) +{ + struct host1x_channel *ch = cdma_to_channel(cdma); + + if (cdma->push_buffer.pos != cdma->last_pos) { + host1x_ch_writel(ch, cdma->push_buffer.pos, + HOST1X_CHANNEL_DMAPUT); + cdma->last_pos = cdma->push_buffer.pos; + } +} + +static void cdma_stop(struct host1x_cdma *cdma) +{ + struct host1x_channel *ch = cdma_to_channel(cdma); + + mutex_lock(&cdma->lock); + if (cdma->running) { + host1x_cdma_wait_locked(cdma, CDMA_EVENT_SYNC_QUEUE_EMPTY); + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, + HOST1X_CHANNEL_DMACTRL); + cdma->running = false; + } + mutex_unlock(&cdma->lock); +} + +/* + * Stops both channel's command processor and CDMA immediately. + * Also, tears down the channel and resets corresponding module. + */ +static void cdma_freeze(struct host1x_cdma *cdma) +{ + struct host1x *host = cdma_to_host1x(cdma); + struct host1x_channel *ch = cdma_to_channel(cdma); + u32 cmdproc_stop; + + if (cdma->torndown && !cdma->running) { + dev_warn(host->dev, "Already torn down\n"); + return; + } + + dev_dbg(host->dev, "freezing channel (id %d)\n", ch->id); + + cmdproc_stop = host1x_ch_readl(ch, HOST1X_SYNC_CMDPROC_STOP); + cmdproc_stop |= BIT(0); + host1x_ch_writel(ch, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP); + + dev_dbg(host->dev, "%s: DMA GET 0x%x, PUT HW 0x%x / shadow 0x%x\n", + __func__, host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET), + host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT), + cdma->last_pos); + + host1x_ch_writel(ch, HOST1X_CHANNEL_DMACTRL_DMASTOP, + HOST1X_CHANNEL_DMACTRL); + + host1x_ch_writel(ch, BIT(0), HOST1X_SYNC_CH_TEARDOWN); + + cdma->running = false; + cdma->torndown = true; +} + +static void cdma_resume(struct host1x_cdma *cdma, u32 getptr) +{ + struct host1x *host1x = cdma_to_host1x(cdma); + struct host1x_channel *ch = cdma_to_channel(cdma); + u32 cmdproc_stop; + + dev_dbg(host1x->dev, + "resuming channel (id %d, DMAGET restart = 0x%x)\n", + ch->id, getptr); + + cmdproc_stop = host1x_ch_readl(ch, HOST1X_SYNC_CMDPROC_STOP); + cmdproc_stop &= ~(BIT(0)); + host1x_ch_writel(ch, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP); + + cdma->torndown = false; + cdma_timeout_restart(cdma, getptr); +} + +/* + * If this timeout fires, it indicates the current sync_queue entry has + * exceeded its TTL and the userctx should be timed out and remaining + * submits already issued cleaned up (future submits return an error). + */ +static void cdma_timeout_handler(struct work_struct *work) +{ + struct host1x_cdma *cdma; + struct host1x *host1x; + struct host1x_channel *ch; + bool has_timedout = 0; + + u32 prev_cmdproc, cmdproc_stop; + + unsigned int i; + + cdma = container_of(to_delayed_work(work), struct host1x_cdma, + timeout.wq); + host1x = cdma_to_host1x(cdma); + ch = cdma_to_channel(cdma); + + host1x_debug_dump(cdma_to_host1x(cdma)); + + mutex_lock(&cdma->lock); + + if (!cdma->timeout.client) { + dev_dbg(host1x->dev, + "cdma_timeout: expired, but has no clientid\n"); + mutex_unlock(&cdma->lock); + return; + } + + /* stop processing to get a clean snapshot */ + prev_cmdproc = host1x_ch_readl(ch, HOST1X_SYNC_CMDPROC_STOP); + cmdproc_stop = prev_cmdproc | BIT(0); + host1x_ch_writel(ch, cmdproc_stop, HOST1X_SYNC_CMDPROC_STOP); + + dev_dbg(host1x->dev, "cdma_timeout: cmdproc was 0x%x is 0x%x\n", + prev_cmdproc, cmdproc_stop); + + for (i = 0; i < cdma->timeout.num_syncpts; ++i) { + u32 id = cdma->timeout.syncpts[i].id; + u32 end = cdma->timeout.syncpts[i].end; + struct host1x_syncpt *syncpt = host1x_syncpt_get(host1x, id); + + host1x_syncpt_load(syncpt); + + has_timedout = !host1x_syncpt_is_expired(syncpt, end); + if (has_timedout) + break; + } + + /* has buffer actually completed? */ + if (!has_timedout) { + dev_dbg(host1x->dev, + "cdma_timeout: expired, but buffer had completed\n"); + /* restore */ + cmdproc_stop = prev_cmdproc & ~(BIT(0)); + host1x_ch_writel(ch, cmdproc_stop, + HOST1X_SYNC_CMDPROC_STOP); + mutex_unlock(&cdma->lock); + return; + } + + for (i = 0; i < cdma->timeout.num_syncpts; ++i) { + u32 id = cdma->timeout.syncpts[i].id; + struct host1x_syncpt *syncpt = host1x_syncpt_get(host1x, id); + u32 syncpt_val = host1x_syncpt_read_min(syncpt); + + dev_warn(host1x->dev, "%s: timeout: %d (%s), HW thresh %d, done %d\n", + __func__, syncpt->id, syncpt->name, + syncpt_val, syncpt_val); + } + + /* stop HW, resetting channel/module */ + host1x_hw_cdma_freeze(host1x, cdma); + + host1x_cdma_update_sync_queue(cdma, ch->dev); + mutex_unlock(&cdma->lock); +} + +/* + * Init timeout resources + */ +static int cdma_timeout_init(struct host1x_cdma *cdma) +{ + INIT_DELAYED_WORK(&cdma->timeout.wq, cdma_timeout_handler); + cdma->timeout.initialized = true; + + return 0; +} + +/* + * Clean up timeout resources + */ +static void cdma_timeout_destroy(struct host1x_cdma *cdma) +{ + if (cdma->timeout.initialized) + cancel_delayed_work(&cdma->timeout.wq); + cdma->timeout.initialized = false; +} + +static const struct host1x_cdma_ops host1x_cdma_t186_ops = { + .start = cdma_start, + .stop = cdma_stop, + .flush = cdma_flush, + + .timeout_init = cdma_timeout_init, + .timeout_destroy = cdma_timeout_destroy, + .freeze = cdma_freeze, + .resume = cdma_resume, + .timeout_handle = cdma_timeout_handle, +}; + +static const struct host1x_pushbuffer_ops host1x_pushbuffer_t186_ops = { + .init = push_buffer_init, +}; diff --git a/drivers/gpu/host1x/hw/channel_hw_t186.c b/drivers/gpu/host1x/hw/channel_hw_t186.c new file mode 100644 index 000000000..2b90ba638 --- /dev/null +++ b/drivers/gpu/host1x/hw/channel_hw_t186.c @@ -0,0 +1,297 @@ +/* + * Tegra host1x Channel + * + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include + +#include "dev_t186.h" +#include "channel.h" +#include "intr.h" +#include "job.h" + +#define TRACE_MAX_LENGTH 128U + +static void trace_write_gather(struct host1x_cdma *cdma, struct host1x_bo *bo, + u32 offset, u32 words) +{ + struct device *dev = cdma_to_channel(cdma)->dev; + void *mem = NULL; + + if (host1x_debug_trace_cmdbuf) + mem = host1x_bo_mmap(bo); + + if (mem) { + u32 i; + /* + * Write in batches of 128 as there seems to be a limit + * of how much you can output to ftrace at once. + */ + for (i = 0; i < words; i += TRACE_MAX_LENGTH) { + u32 num_words = min(words - i, TRACE_MAX_LENGTH); + u32 next_offset = offset + i * sizeof(u32); + + trace_host1x_cdma_push_gather(dev_name(dev), bo, + num_words, + next_offset, + mem); + } + + host1x_bo_munmap(bo, mem); + } +} + +static void channel_push_wait(struct host1x_channel *channel, + u32 id, u32 thresh) +{ + host1x_cdma_push(&channel->cdma, + host1x_opcode_setclass(HOST1X_CLASS_HOST1X, + HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32, 1), + thresh); + host1x_cdma_push(&channel->cdma, + host1x_opcode_setclass(HOST1X_CLASS_HOST1X, + HOST1X_UCLASS_WAIT_SYNCPT_32, 1), + id); +} + +static inline void serialize(struct host1x_job *job) +{ + struct host1x_channel *ch = job->channel; + struct host1x *host = dev_get_drvdata(ch->dev->parent); + unsigned int i; + + for (i = 0; i < job->num_syncpts; ++i) { + u32 syncpt_id = job->syncpts[i].id; + struct host1x_syncpt *syncpt = + host1x_syncpt_get(host, syncpt_id); + + /* + * Force serialization by inserting a host wait for the + * previous job to finish before this one can commence. + */ + channel_push_wait(ch, syncpt_id, host1x_syncpt_read_max(syncpt)); + } +} + +static void add_sync_waits(struct host1x_job *job) +{ + struct host1x *host = dev_get_drvdata(job->channel->dev->parent); + unsigned int i; + + for (i = 0; i < job->num_gathers; i++) { + struct host1x_job_gather *g = &job->gathers[i]; + + if (g->pre_fence) + host1x_sync_fence_wait(g->pre_fence, host, + job->channel); + } +} + +static void submit_gathers(struct host1x_job *job) +{ + struct host1x_cdma *cdma = &job->channel->cdma; + unsigned int i; + u32 cur_class = 0; + + cur_class = HOST1X_CLASS_HOST1X; + host1x_cdma_push(cdma, + host1x_opcode_acquire_mlock(cur_class), + host1x_opcode_setclass(cur_class, 0, 0)); + + add_sync_waits(job); + + for (i = 0; i < job->num_gathers; i++) { + struct host1x_job_gather *g = &job->gathers[i]; + u32 op1 = host1x_opcode_gather(g->words); + u32 op2 = g->base + g->offset; + + /* add a setclass for modules that require it */ + if (cur_class != g->class_id) { + if (cur_class) + host1x_cdma_push(cdma, + HOST1X_OPCODE_NOP, + host1x_opcode_release_mlock(cur_class)); + + host1x_cdma_push(cdma, + host1x_opcode_acquire_mlock(g->class_id), + host1x_opcode_setclass(g->class_id, 0, 0)); + cur_class = g->class_id; + } + + trace_write_gather(cdma, g->bo, g->offset, op1 & 0xffff); + host1x_cdma_push(cdma, op1, op2); + } + + if (job->serialize) + serialize(job); + + if (cur_class) + host1x_cdma_push(cdma, + HOST1X_OPCODE_NOP, + host1x_opcode_release_mlock(cur_class)); +} + +static inline void synchronize_syncpt_base(struct host1x_job *job) +{ + struct host1x_channel *ch = job->channel; + struct host1x *host = dev_get_drvdata(ch->dev->parent); + unsigned int i; + + for (i = 0; i < job->num_syncpts; ++i) { + u32 syncpt_id = job->syncpts[i].id; + struct host1x_syncpt *syncpt = + host1x_syncpt_get(host, syncpt_id); + u32 base_id, value; + + if (!syncpt->base) + continue; + + value = host1x_syncpt_read_max(syncpt); + base_id = syncpt->base->id; + + host1x_cdma_push(&job->channel->cdma, + host1x_opcode_setclass(HOST1X_CLASS_HOST1X, + HOST1X_UCLASS_LOAD_SYNCPT_BASE, 1), + HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(base_id) | + HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(value)); + } +} + +static int channel_submit(struct host1x_job *job) +{ + struct host1x_channel *ch = job->channel; + struct host1x_syncpt *syncpt; + u32 prev_max = 0; + int err; + struct host1x_waitlist *completed_waiter[job->num_syncpts]; + struct host1x *host = dev_get_drvdata(ch->dev->parent); + unsigned int i; + int streamid = 0; + + trace_host1x_channel_submit(dev_name(ch->dev), + job->num_gathers, job->num_relocs, + job->num_waitchk, job->syncpts[0].id, + job->syncpts[0].incrs); + + /* before error checks, return current max */ + syncpt = host1x_syncpt_get(host, job->syncpts[0].id); + prev_max = host1x_syncpt_read_max(syncpt); + + /* get submit lock */ + err = mutex_lock_interruptible(&ch->submitlock); + if (err) + goto error; + + for (i = 0; i < job->num_syncpts; i++) { + completed_waiter[i] = kzalloc(sizeof(*completed_waiter[i]), + GFP_KERNEL); + if (!completed_waiter[i]) { + mutex_unlock(&ch->submitlock); + err = -ENOMEM; + goto error; + } + } + + streamid = iommu_get_hwid(host->dev->archdata.iommu, host->dev, 0); + if (streamid >= 0) + host1x_ch_writel(ch, streamid, HOST1X_CHANNEL_SMMU_STREAMID); + + /* begin a CDMA submit */ + err = host1x_cdma_begin(&ch->cdma, job); + if (err) { + mutex_unlock(&ch->submitlock); + goto error; + } + + /* Synchronize base register to allow using it for relative waiting */ + synchronize_syncpt_base(job); + + /* Increment syncpoint maximum values */ + for (i = 0; i < job->num_syncpts; ++i) { + u32 id; + u32 incrs; + + id = job->syncpts[i].id; + incrs = job->syncpts[i].incrs; + syncpt = host1x_syncpt_get(host, id); + job->syncpts[i].end = host1x_syncpt_incr_max(syncpt, incrs); + } + + submit_gathers(job); + + /* end CDMA submit & stash pinned hMems into sync queue */ + host1x_cdma_end(&ch->cdma, job); + + trace_host1x_channel_submitted(dev_name(ch->dev), prev_max, + job->syncpts[0].end); + + /* schedule submit complete interrupts */ + for (i = 0; i < job->num_syncpts; ++i) { + u32 syncpt_id = job->syncpts[i].id; + u32 syncpt_end = job->syncpts[i].end; + + err = host1x_intr_add_action(host, syncpt_id, syncpt_end, + HOST1X_INTR_ACTION_SUBMIT_COMPLETE, + ch, completed_waiter[i], NULL); + completed_waiter[i] = NULL; + WARN(err, "Failed to set submit complete interrupt"); + } + + mutex_unlock(&ch->submitlock); + + return 0; + +error: + for (i = 0; i < job->num_syncpts; i++) + kfree(completed_waiter[i]); + return err; +} + +static int host1x_channel_init(struct host1x_channel *ch, struct host1x *dev, + unsigned int index) +{ + ch->id = index; + mutex_init(&ch->reflock); + mutex_init(&ch->submitlock); + + ch->regs = dev->regs + (HOST1X_CHANNEL_CH_APERTURE_START + + index * HOST1X_CHANNEL_CH_APERTURE_SIZE); + return 0; +} + +static void channel_enable_gather_filter(struct host1x_channel *ch) +{ + struct host1x *host = dev_get_drvdata(ch->dev->parent); + u32 val; + + val = host1x_readl(host, HOST1X_CHANNEL_FILTER_GBUFFER + + BIT_WORD(ch->id) * sizeof(u32)); + + host1x_writel(host, val | BIT_MASK(ch->id), + HOST1X_CHANNEL_FILTER_GBUFFER + + BIT_WORD(ch->id) * sizeof(u32)); +} + +static const struct host1x_channel_ops host1x_channel_t186_ops = { + .init = host1x_channel_init, + .submit = channel_submit, + .push_wait = channel_push_wait, + .enable_gather_filter = channel_enable_gather_filter, +}; diff --git a/drivers/gpu/host1x/hw/debug_hw_t186.c b/drivers/gpu/host1x/hw/debug_hw_t186.c new file mode 100644 index 000000000..d6111668e --- /dev/null +++ b/drivers/gpu/host1x/hw/debug_hw_t186.c @@ -0,0 +1,288 @@ +/* + * Copyright (C) 2010 Google, Inc. + * Author: Erik Gilling + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include "dev.h" +#include "debug.h" +#include "cdma.h" +#include "channel.h" + +#define HOST1X_DEBUG_MAX_PAGE_OFFSET 102400 + +enum { + HOST1X_OPCODE_SETCLASS = 0x00, + HOST1X_OPCODE_INCR = 0x01, + HOST1X_OPCODE_NONINCR = 0x02, + HOST1X_OPCODE_MASK = 0x03, + HOST1X_OPCODE_IMM = 0x04, + HOST1X_OPCODE_RESTART = 0x05, + HOST1X_OPCODE_GATHER = 0x06, + HOST1X_OPCODE_EXTEND = 0x0e, +}; + +enum { + HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK = 0x00, + HOST1X_OPCODE_EXTEND_RELEASE_MLOCK = 0x01, +}; + +static unsigned int show_channel_command(struct output *o, u32 val) +{ + unsigned mask; + unsigned subop; + + switch (val >> 28) { + case HOST1X_OPCODE_SETCLASS: + mask = val & 0x3f; + if (mask) { + host1x_debug_output(o, "SETCL(class=%03x, offset=%03x, mask=%02x, [", + val >> 6 & 0x3ff, + val >> 16 & 0xfff, mask); + return hweight8(mask); + } else { + host1x_debug_output(o, "SETCL(class=%03x)\n", + val >> 6 & 0x3ff); + return 0; + } + + case HOST1X_OPCODE_INCR: + host1x_debug_output(o, "INCR(offset=%03x, [", + val >> 16 & 0xfff); + return val & 0xffff; + + case HOST1X_OPCODE_NONINCR: + host1x_debug_output(o, "NONINCR(offset=%03x, [", + val >> 16 & 0xfff); + return val & 0xffff; + + case HOST1X_OPCODE_MASK: + mask = val & 0xffff; + host1x_debug_output(o, "MASK(offset=%03x, mask=%03x, [", + val >> 16 & 0xfff, mask); + return hweight16(mask); + + case HOST1X_OPCODE_IMM: + host1x_debug_output(o, "IMM(offset=%03x, data=%03x)\n", + val >> 16 & 0xfff, val & 0xffff); + return 0; + + case HOST1X_OPCODE_RESTART: + host1x_debug_output(o, "RESTART(offset=%08x)\n", val << 4); + return 0; + + case HOST1X_OPCODE_GATHER: + host1x_debug_output(o, "GATHER(offset=%03x, insert=%d, type=%d, count=%04x, addr=[", + val >> 16 & 0xfff, val >> 15 & 0x1, + val >> 14 & 0x1, val & 0x3fff); + return 1; + + case HOST1X_OPCODE_EXTEND: + subop = val >> 24 & 0xf; + if (subop == HOST1X_OPCODE_EXTEND_ACQUIRE_MLOCK) + host1x_debug_output(o, "ACQUIRE_MLOCK(index=%d)\n", + val & 0xff); + else if (subop == HOST1X_OPCODE_EXTEND_RELEASE_MLOCK) + host1x_debug_output(o, "RELEASE_MLOCK(index=%d)\n", + val & 0xff); + else + host1x_debug_output(o, "EXTEND_UNKNOWN(%08x)\n", val); + return 0; + + default: + return 0; + } +} + +static void show_gather(struct output *o, phys_addr_t phys_addr, + unsigned int words, struct host1x_cdma *cdma, + phys_addr_t pin_addr, u32 *map_addr) +{ + /* Map dmaget cursor to corresponding mem handle */ + u32 offset = phys_addr - pin_addr; + unsigned int data_count = 0, i; + + /* + * Sometimes we're given different hardware address to the same + * page - in these cases the offset will get an invalid number and + * we just have to bail out. + */ + if (offset > HOST1X_DEBUG_MAX_PAGE_OFFSET) { + host1x_debug_output(o, "[address mismatch]\n"); + return; + } + + for (i = 0; i < words; i++) { + u32 addr = phys_addr + i * 4; + u32 val = *(map_addr + offset / 4 + i); + + if (!data_count) { + host1x_debug_output(o, "%08x: %08x:", addr, val); + data_count = show_channel_command(o, val); + } else { + host1x_debug_output(o, "%08x%s", val, + data_count > 0 ? ", " : "])\n"); + data_count--; + } + } +} + +static void show_channel_gathers(struct output *o, struct host1x_cdma *cdma) +{ + struct host1x_job *job; + + list_for_each_entry(job, &cdma->sync_queue, list) { + int i; + host1x_debug_output(o, "\n%p: JOB, syncpt_id=%d, syncpt_val=%d, first_get=%08x, timeout=%d num_slots=%d, num_handles=%d\n", + job, + (job->syncpts ? job->syncpts[0].id : 0), + (job->syncpts ? job->syncpts[0].end : 0), + job->first_get, job->timeout, + job->num_slots, job->num_unpins); + + for (i = 0; i < job->num_gathers; i++) { + struct host1x_job_gather *g = &job->gathers[i]; + u32 *mapped; + + if (job->gather_copy_mapped) + mapped = (u32 *)job->gather_copy_mapped; + else + mapped = host1x_bo_mmap(g->bo); + + if (!mapped) { + host1x_debug_output(o, "[could not mmap]\n"); + continue; + } + + host1x_debug_output(o, " GATHER at %pad+%#x, %d words\n", + &g->base, g->offset, g->words); + + show_gather(o, g->base + g->offset, g->words, cdma, + g->base, mapped); + + if (!job->gather_copy_mapped) + host1x_bo_munmap(g->bo, mapped); + } + } +} + +static void host1x_debug_show_channel_cdma(struct host1x *host, + struct host1x_channel *ch, + struct output *o) +{ + struct host1x_cdma *cdma = &ch->cdma; + u32 val; + + host1x_debug_output(o, "Host1x basic channel registers: \n"); + + val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT); + host1x_debug_output(o, "CMDFIFO_STAT_0: %08x\n", val); + val = host1x_ch_readl(ch, HOST1X_CHANNEL_RDATA); + host1x_debug_output(o, "CMDFIFO_RDATA_0: %08x\n", val); + val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET); + host1x_debug_output(o, "CMDP_OFFSET_0: %08x\n", val); + val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS); + host1x_debug_output(o, "CMDP_CLASS_0: %08x\n", val); + val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CHANNELSTAT); + host1x_debug_output(o, "CHANNELSTAT_0: %08x\n", val); + + show_channel_gathers(o, cdma); + host1x_debug_output(o, "\n"); +} + +static void host1x_debug_show_channel_fifo(struct host1x *host, + struct host1x_channel *ch, + struct output *o) +{ + u32 val, rd_ptr, wr_ptr, start, end, temp; + unsigned int data_count = 0; + + host1x_debug_output(o, "%d: fifo:\n", ch->id); + + temp = host1x_sync_readl(host, HOST1X_THOST_COMMON_ICG_EN_OVERRIDE_0); + host1x_sync_writel(host, 0x1, HOST1X_THOST_COMMON_ICG_EN_OVERRIDE_0); + + val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT); + host1x_debug_output(o, "FIFOSTAT %08x\n", val); + if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) { + host1x_debug_output(o, "[empty]\n"); + return; + } + + host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL); + host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) | + HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id), + HOST1X_SYNC_CFPEEK_CTRL); + + val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS); + rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val); + wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val); + + val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id)); + start = HOST1X_SYNC_CF_SETUP_BASE_V(val); + end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val); + + do { + host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL); + host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) | + HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) | + HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr), + HOST1X_SYNC_CFPEEK_CTRL); + val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ); + + if (!data_count) { + host1x_debug_output(o, "%08x:", val); + data_count = show_channel_command(o, val); + } else { + host1x_debug_output(o, "%08x%s", val, + data_count > 0 ? ", " : "])\n"); + data_count--; + } + + if (rd_ptr == end) + rd_ptr = start; + else + rd_ptr++; + } while (rd_ptr != wr_ptr); + + if (data_count) + host1x_debug_output(o, ", ...])\n"); + host1x_debug_output(o, "\n"); + + host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL); + + host1x_sync_writel(host, temp, HOST1X_THOST_COMMON_ICG_EN_OVERRIDE_0); +} + +static void host1x_debug_show_mlocks(struct host1x *host, struct output *o) +{ + int i; + unsigned int chid; + bool cpu, ch; + + host1x_debug_output(o, "---- mlocks ----\n"); + for (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) { + host1x_hw_sync_get_mutex_owner(host, host->syncpt, + i, &cpu, &ch, &chid); + if (ch) + host1x_debug_output(o, "%d: locked by channel %d\n", i, chid); + } + host1x_debug_output(o, "\n"); +} + +static const struct host1x_debug_ops host1x_debug_t186_ops = { + .show_channel_cdma = host1x_debug_show_channel_cdma, + .show_channel_fifo = host1x_debug_show_channel_fifo, + .show_mlocks = host1x_debug_show_mlocks, +}; diff --git a/drivers/gpu/host1x/hw/host1x05.c b/drivers/gpu/host1x/hw/host1x05.c new file mode 100644 index 000000000..db64e7cfe --- /dev/null +++ b/drivers/gpu/host1x/hw/host1x05.c @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* include hw specification */ +#include "host1x05.h" +#include "host1x05_hardware.h" + +/* include code */ +#include "cdma_hw_t186.c" +#include "channel_hw_t186.c" +#include "debug_hw_t186.c" +#include "intr_hw_t186.c" +#include "syncpt_hw_t186.c" + +#include "dev.h" + +int host1x05_init(struct host1x *host) +{ + host->channel_op = &host1x_channel_t186_ops; + host->cdma_op = &host1x_cdma_t186_ops; + host->cdma_pb_op = &host1x_pushbuffer_t186_ops; + host->syncpt_op = &host1x_syncpt_t186_ops; + host->intr_op = &host1x_intr_t186_ops; + host->debug_op = &host1x_debug_t186_ops; + + return 0; +} diff --git a/drivers/gpu/host1x/hw/host1x05.h b/drivers/gpu/host1x/hw/host1x05.h new file mode 100644 index 000000000..e1b842146 --- /dev/null +++ b/drivers/gpu/host1x/hw/host1x05.h @@ -0,0 +1,24 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef HOST1X_HOST1X05_H +#define HOST1X_HOST1X05_H + +struct host1x; + +int host1x05_init(struct host1x *host); + +#endif diff --git a/drivers/gpu/host1x/hw/host1x05_hardware.h b/drivers/gpu/host1x/hw/host1x05_hardware.h new file mode 100644 index 000000000..add00014e --- /dev/null +++ b/drivers/gpu/host1x/hw/host1x05_hardware.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __HOST1X_HOST1X05_HARDWARE_H +#define __HOST1X_HOST1X05_HARDWARE_H + +#include +#include + +#include "hw_host1x05_channel.h" +#include "hw_host1x05_sync.h" +#include "hw_host1x05_uclass.h" + +static inline u32 host1x_class_host_wait_syncpt( + unsigned indx, unsigned threshold) +{ + return host1x_uclass_wait_syncpt_indx_f(indx) + | host1x_uclass_wait_syncpt_thresh_f(threshold); +} + +static inline u32 host1x_class_host_load_syncpt_base( + unsigned indx, unsigned threshold) +{ + return host1x_uclass_load_syncpt_base_base_indx_f(indx) + | host1x_uclass_load_syncpt_base_value_f(threshold); +} + +static inline u32 host1x_class_host_wait_syncpt_base( + unsigned indx, unsigned base_indx, unsigned offset) +{ + return host1x_uclass_wait_syncpt_base_indx_f(indx) + | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx) + | host1x_uclass_wait_syncpt_base_offset_f(offset); +} + +static inline u32 host1x_class_host_incr_syncpt_base( + unsigned base_indx, unsigned offset) +{ + return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx) + | host1x_uclass_incr_syncpt_base_offset_f(offset); +} + +static inline u32 host1x_class_host_incr_syncpt( + unsigned cond, unsigned indx) +{ + return host1x_uclass_incr_syncpt_cond_f(cond) + | host1x_uclass_incr_syncpt_indx_f(indx); +} + +/* cdma opcodes */ +static inline u32 host1x_opcode_setclass( + unsigned class_id, unsigned offset, unsigned mask) +{ + return (0 << 28) | (offset << 16) | (class_id << 6) | mask; +} + +static inline u32 host1x_opcode_incr(unsigned offset, unsigned count) +{ + return (1 << 28) | (offset << 16) | count; +} + +static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count) +{ + return (2 << 28) | (offset << 16) | count; +} + +static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask) +{ + return (3 << 28) | (offset << 16) | mask; +} + +static inline u32 host1x_opcode_imm(unsigned offset, unsigned value) +{ + return (4 << 28) | (offset << 16) | value; +} + +static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx) +{ + return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(), + host1x_class_host_incr_syncpt(cond, indx)); +} + +static inline u32 host1x_opcode_restart(unsigned address) +{ + return (5 << 28) | (address >> 4); +} + +static inline u32 host1x_opcode_gather(unsigned count) +{ + return (6 << 28) | count; +} + +static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count) +{ + return (6 << 28) | (offset << 16) | BIT(15) | count; +} + +static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count) +{ + return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count; +} + +static inline u32 host1x_opcode_acquire_mlock(unsigned id) +{ + return (14 << 28) | id; +} + +static inline u32 host1x_opcode_release_mlock(unsigned id) +{ + return (14 << 28) | (1 << 24) | id; +} + +#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0) + +#endif diff --git a/drivers/gpu/host1x/hw/hw_host1x05_channel.h b/drivers/gpu/host1x/hw/hw_host1x05_channel.h new file mode 100644 index 000000000..8c3499f91 --- /dev/null +++ b/drivers/gpu/host1x/hw/hw_host1x05_channel.h @@ -0,0 +1,169 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + + /* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ + +#ifndef HOST1X_HW_HOST1X05_CHANNEL_H +#define HOST1X_HW_HOST1X05_CHANNEL_H + +static inline u32 host1x_channel_ch_aperture_start_r(void) +{ + return 0x10000; +} +#define HOST1X_CHANNEL_CH_APERTURE_START \ + host1x_channel_ch_aperture_start_r() +static inline u32 host1x_channel_ch_aperture_size_r(void) +{ + return 0x100; +} +#define HOST1X_CHANNEL_CH_APERTURE_SIZE \ + host1x_channel_ch_aperture_size_r() +static inline u32 host1x_channel_fifostat_r(void) +{ + return 0x24; +} +#define HOST1X_CHANNEL_FIFOSTAT \ + host1x_channel_fifostat_r() +static inline u32 host1x_channel_fifostat_cfempty_v(u32 r) +{ + return (r >> 13) & 0x1; +} +#define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \ + host1x_channel_fifostat_cfempty_v(r) +static inline u32 host1x_channel_rdata_r(void) +{ + return 0x28; +} +#define HOST1X_CHANNEL_RDATA \ + host1x_channel_rdata_r() +static inline u32 host1x_channel_cmdp_offset_r(void) +{ + return 0x30; +} +#define HOST1X_CHANNEL_CMDP_OFFSET \ + host1x_channel_cmdp_offset_r() +static inline u32 host1x_channel_cmdp_class_r(void) +{ + return 0x34; +} +#define HOST1X_CHANNEL_CMDP_CLASS \ + host1x_channel_cmdp_class_r() +static inline u32 host1x_channel_cmdp_channelstat_r(void) +{ + return 0x38; +} +#define HOST1X_CHANNEL_CMDP_CHANNELSTAT \ + host1x_channel_cmdp_channelstat_r() +static inline u32 host1x_channel_dmastart_r(void) +{ + return 0x0; +} +#define HOST1X_CHANNEL_DMASTART \ + host1x_channel_dmastart_r() +static inline u32 host1x_channel_dmaput_r(void) +{ + return 0x8; +} +#define HOST1X_CHANNEL_DMAPUT \ + host1x_channel_dmaput_r() +static inline u32 host1x_channel_dmaget_r(void) +{ + return 0x10; +} +#define HOST1X_CHANNEL_DMAGET \ + host1x_channel_dmaget_r() +static inline u32 host1x_channel_dmaend_r(void) +{ + return 0x18; +} +#define HOST1X_CHANNEL_DMAEND \ + host1x_channel_dmaend_r() +static inline u32 host1x_channel_dmactrl_r(void) +{ + return 0x20; +} +#define HOST1X_CHANNEL_DMACTRL \ + host1x_channel_dmactrl_r() +static inline u32 host1x_channel_dmactrl_dmastop(void) +{ + return 1 << 0; +} +#define HOST1X_CHANNEL_DMACTRL_DMASTOP \ + host1x_channel_dmactrl_dmastop() +static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r) +{ + return (r >> 0) & 0x1; +} +#define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \ + host1x_channel_dmactrl_dmastop_v(r) +static inline u32 host1x_channel_dmactrl_dmagetrst(void) +{ + return 1 << 1; +} +#define HOST1X_CHANNEL_DMACTRL_DMAGETRST \ + host1x_channel_dmactrl_dmagetrst() +static inline u32 host1x_channel_dmactrl_dmainitget(void) +{ + return 1 << 2; +} +#define HOST1X_CHANNEL_DMACTRL_DMAINITGET \ + host1x_channel_dmactrl_dmainitget() +static inline u32 host1x_channel_smmu_streamid_r(void) +{ + return 0x84; +} +#define HOST1X_CHANNEL_SMMU_STREAMID \ + host1x_channel_smmu_streamid_r() +static inline u32 host1x_channel_filter_gbuffer_r(void) +{ + return 0x2020; +} +#define HOST1X_CHANNEL_FILTER_GBUFFER \ + host1x_channel_filter_gbuffer_r() + +#endif diff --git a/drivers/gpu/host1x/hw/hw_host1x05_sync.h b/drivers/gpu/host1x/hw/hw_host1x05_sync.h new file mode 100644 index 000000000..55fe98859 --- /dev/null +++ b/drivers/gpu/host1x/hw/hw_host1x05_sync.h @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + + /* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ + +#ifndef HOST1X_HW_HOST1X05_SYNC_H +#define HOST1X_HW_HOST1X05_SYNC_H + +#define REGISTER_STRIDE 4 + +static inline u32 host1x_sync_intstatus_r(void) +{ + return 0x1c; +} +#define HOST1X_SYNC_INTSTATUS \ + host1x_sync_intstatus_r() +static inline u32 host1x_sync_intmask_r(void) +{ + return 0x30; +} +#define HOST1X_SYNC_INTMASK \ + host1x_sync_intmask_r() +static inline u32 host1x_sync_intc0mask_r(void) +{ + return 0x4; +} +#define HOST1X_SYNC_INTC0MASK \ + host1x_sync_intc0mask_r() +static inline u32 host1x_sync_intgmask_r(void) +{ + return 0x44; +} +#define HOST1X_SYNC_INTGMASK \ + host1x_sync_intgmask_r() +static inline u32 host1x_sync_syncpt_intgmask_r(void) +{ + return 0x50; +} +#define HOST1X_SYNC_SYNCPT_INTGMASK \ + host1x_sync_syncpt_intgmask_r() +static inline u32 host1x_sync_intstatus_ip_read_int_v(u32 r) +{ + return (r >> 0) & 0x1; +} +#define HOST1X_SYNC_INTSTATUS_IP_READ_INT_V(r) \ + host1x_sync_intstatus_ip_read_int_v(r) +static inline u32 host1x_sync_intstatus_ip_write_int_v(u32 r) +{ + return (r >> 1) & 0x1; +} +#define HOST1X_SYNC_INTSTATUS_IP_WRITE_INT_V(r) \ + host1x_sync_intstatus_ip_write_int_v(r) +static inline u32 host1x_sync_intstatus_illegal_pb_access_v(u32 r) +{ + return (r >> 28) & 0x1; +} +#define HOST1X_SYNC_INTSTATUS_ILLEGAL_PB_ACCESS_V(r) \ + host1x_sync_intstatus_illegal_pb_access_v(r) +static inline u32 host1x_sync_illegal_syncpt_access_frm_pb_r(void) +{ + return 0x2270; +} +#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB \ + host1x_sync_illegal_syncpt_access_frm_pb_r() +static inline u32 host1x_sync_illegal_syncpt_access_frm_pb_syncpt_v(u32 r) +{ + return (r >> 16) & 0x3ff; +} +#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB_SYNCPT_V(r) \ + host1x_sync_illegal_syncpt_access_frm_pb_syncpt_v(r) +static inline u32 host1x_sync_illegal_syncpt_access_frm_pb_ch_v(u32 r) +{ + return (r >> 10) & 0x3f; +} +#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB_CH_V(r) \ + host1x_sync_illegal_syncpt_access_frm_pb_ch_v(r) +static inline u32 host1x_sync_intstatus_illegal_client_access_v(u32 r) +{ + return (r >> 30) & 0x1; +} +#define HOST1X_SYNC_INTSTATUS_ILLEGAL_CLIENT_ACCESS_V(r) \ + host1x_sync_intstatus_illegal_client_access_v(r) +static inline u32 host1x_sync_illegal_syncpt_access_frm_client_r(void) +{ + return 0x2268; +} +#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT \ + host1x_sync_illegal_syncpt_access_frm_client_r() +static inline u32 host1x_sync_illegal_syncpt_access_frm_client_syncpt_v(u32 r) +{ + return (r >> 16) & 0x3ff; +} +#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT_SYNCPT_V(r) \ + host1x_sync_illegal_syncpt_access_frm_client_syncpt_v(r) +static inline u32 host1x_sync_illegal_syncpt_access_frm_client_ch_v(u32 r) +{ + return (r >> 10) & 0x3f; +} +#define HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT_CH_V(r) \ + host1x_sync_illegal_syncpt_access_frm_client_ch_v(r) +static inline u32 host1x_sync_syncpt_r(unsigned int id) +{ + return 0x18080 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT(id) \ + host1x_sync_syncpt_r(id) +static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id) +{ + return 0x16464 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \ + host1x_sync_syncpt_thresh_cpu0_int_status_r(id) +static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id) +{ + return 0x16590 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \ + host1x_sync_syncpt_thresh_int_disable_r(id) +static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id) +{ + return 0x1652c + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \ + host1x_sync_syncpt_thresh_int_enable_cpu0_r(id) +static inline u32 host1x_sync_cf_setup_r(unsigned int channel) +{ + return 0x2588 + channel * REGISTER_STRIDE; +} +#define HOST1X_SYNC_CF_SETUP(channel) \ + host1x_sync_cf_setup_r(channel) +static inline u32 host1x_sync_cf_setup_base_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +#define HOST1X_SYNC_CF_SETUP_BASE_V(r) \ + host1x_sync_cf_setup_base_v(r) +static inline u32 host1x_sync_cf_setup_limit_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +#define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \ + host1x_sync_cf_setup_limit_v(r) +static inline u32 host1x_sync_cmdproc_stop_r(void) +{ + return 0x48; +} +#define HOST1X_SYNC_CMDPROC_STOP \ + host1x_sync_cmdproc_stop_r() +static inline u32 host1x_sync_ch_teardown_r(void) +{ + return 0x4c; +} +#define HOST1X_SYNC_CH_TEARDOWN \ + host1x_sync_ch_teardown_r() +static inline u32 host1x_sync_usec_clk_r(void) +{ + return 0x2244; +} +#define HOST1X_SYNC_USEC_CLK \ + host1x_sync_usec_clk_r() +static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void) +{ + return 0x2248; +} +#define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \ + host1x_sync_ctxsw_timeout_cfg_r() +static inline u32 host1x_sync_ip_busy_timeout_r(void) +{ + return 0x2250; +} +#define HOST1X_SYNC_IP_BUSY_TIMEOUT \ + host1x_sync_ip_busy_timeout_r() +static inline u32 host1x_sync_ip_read_timeout_addr_r(void) +{ + return 0x2254; +} +#define HOST1X_SYNC_IP_READ_TIMEOUT_ADDR \ + host1x_sync_ip_read_timeout_addr_r() +static inline u32 host1x_sync_ip_write_timeout_addr_r(void) +{ + return 0x225c; +} +#define HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR \ + host1x_sync_ip_write_timeout_addr_r() +static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id) +{ + return 0x18a00 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \ + host1x_sync_syncpt_int_thresh_r(id) +static inline u32 host1x_sync_syncpt_base_r(unsigned int id) +{ + return 0x18000 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT_BASE(id) \ + host1x_sync_syncpt_base_r(id) +static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id) +{ + return 0x16400 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \ + host1x_sync_syncpt_cpu_incr_r(id) +static inline u32 host1x_sync_cfpeek_ctrl_r(void) +{ + return 0x233c; +} +#define HOST1X_SYNC_CFPEEK_CTRL \ + host1x_sync_cfpeek_ctrl_r() +static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v) +{ + return (v & 0xfff) << 0; +} +#define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \ + host1x_sync_cfpeek_ctrl_addr_f(v) +static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v) +{ + return (v & 0x3f) << 16; +} +#define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \ + host1x_sync_cfpeek_ctrl_channr_f(v) +static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v) +{ + return (v & 0x1) << 31; +} +#define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \ + host1x_sync_cfpeek_ctrl_ena_f(v) +static inline u32 host1x_sync_cfpeek_read_r(void) +{ + return 0x2340; +} +#define HOST1X_SYNC_CFPEEK_READ \ + host1x_sync_cfpeek_read_r() +static inline u32 host1x_sync_cfpeek_ptrs_r(void) +{ + return 0x2344; +} +#define HOST1X_SYNC_CFPEEK_PTRS \ + host1x_sync_cfpeek_ptrs_r() +static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r) +{ + return (r >> 0) & 0xfff; +} +#define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \ + host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r) +static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r) +{ + return (r >> 16) & 0xfff; +} +#define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \ + host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r) +static inline u32 host1x_sync_common_mlock_r(unsigned long id) +{ + return 0x2030 + id * REGISTER_STRIDE; +} +#define HOST1X_SYNC_COMMON_MLOCK \ + host1x_sync_common_mlock_r() +static inline u32 host1x_sync_common_mlock_ch_v(u32 r) +{ + return (r >> 2) & 0x3f; +} +#define HOST1X_SYNC_COMMON_MLOCK_CH_V(r) \ + host1x_sync_common_mlock_ch_v(r) +static inline u32 host1x_sync_common_mlock_locked_v(u32 r) +{ + return (r >> 0) & 0x1; +} +#define HOST1X_SYNC_COMMON_MLOCK_LOCKED_V(r) \ + host1x_sync_common_mlock_locked_v(r) +static inline u32 host1x_thost_common_icg_en_override_0_r(void) +{ + return 0x2aa8; +} +#define HOST1X_THOST_COMMON_ICG_EN_OVERRIDE_0 \ + host1x_thost_common_icg_en_override_0_r() + +#endif diff --git a/drivers/gpu/host1x/hw/hw_host1x05_uclass.h b/drivers/gpu/host1x/hw/hw_host1x05_uclass.h new file mode 100644 index 000000000..01145f610 --- /dev/null +++ b/drivers/gpu/host1x/hw/hw_host1x05_uclass.h @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + * + */ + + /* + * Function naming determines intended use: + * + * _r(void) : Returns the offset for register . + * + * _w(void) : Returns the word offset for word (4 byte) element . + * + * __s(void) : Returns size of field of register in bits. + * + * __f(u32 v) : Returns a value based on 'v' which has been shifted + * and masked to place it at field of register . This value + * can be |'d with others to produce a full register value for + * register . + * + * __m(void) : Returns a mask for field of register . This + * value can be ~'d and then &'d to clear the value of field for + * register . + * + * ___f(void) : Returns the constant value after being shifted + * to place it at field of register . This value can be |'d + * with others to produce a full register value for . + * + * __v(u32 r) : Returns the value of field from a full register + * value 'r' after being shifted to place its LSB at bit 0. + * This value is suitable for direct comparison with other unshifted + * values appropriate for use in field of register . + * + * ___v(void) : Returns the constant value for defined for + * field of register . This value is suitable for direct + * comparison with unshifted values appropriate for use in field + * of register . + */ + +#ifndef HOST1X_HW_HOST1X05_UCLASS_H +#define HOST1X_HW_HOST1X05_UCLASS_H + +static inline u32 host1x_uclass_incr_syncpt_r(void) +{ + return 0x0; +} +#define HOST1X_UCLASS_INCR_SYNCPT \ + host1x_uclass_incr_syncpt_r() +static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v) +{ + return (v & 0xff) << 10; +} +#define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \ + host1x_uclass_incr_syncpt_cond_f(v) +static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v) +{ + return (v & 0x3ff) << 0; +} +#define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \ + host1x_uclass_incr_syncpt_indx_f(v) +static inline u32 host1x_uclass_load_syncpt_payload_32_r(void) +{ + return 0x4e; +} +#define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \ + host1x_uclass_load_syncpt_payload_32_r() +static inline u32 host1x_uclass_wait_syncpt_32_r(void) +{ + return 0x50; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_32 \ + host1x_uclass_wait_syncpt_32_r() +static inline u32 host1x_uclass_wait_syncpt_r(void) +{ + return 0x8; +} +#define HOST1X_UCLASS_WAIT_SYNCPT \ + host1x_uclass_wait_syncpt_r() +static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \ + host1x_uclass_wait_syncpt_indx_f(v) +static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \ + host1x_uclass_wait_syncpt_thresh_f(v) +static inline u32 host1x_uclass_wait_syncpt_base_r(void) +{ + return 0x9; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE \ + host1x_uclass_wait_syncpt_base_r() +static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v) +{ + return (v & 0x3ff) << 22; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \ + host1x_uclass_wait_syncpt_base_indx_f(v) +static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v) +{ + return (v & 0x3f) << 16; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \ + host1x_uclass_wait_syncpt_base_base_indx_f(v) +static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v) +{ + return (v & 0xffff) << 0; +} +#define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \ + host1x_uclass_wait_syncpt_base_offset_f(v) +static inline u32 host1x_uclass_load_syncpt_base_r(void) +{ + return 0xb; +} +#define HOST1X_UCLASS_LOAD_SYNCPT_BASE \ + host1x_uclass_load_syncpt_base_r() +static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \ + host1x_uclass_load_syncpt_base_base_indx_f(v) +static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +#define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \ + host1x_uclass_load_syncpt_base_value_f(v) +static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v) +{ + return (v & 0xff) << 24; +} +#define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \ + host1x_uclass_incr_syncpt_base_base_indx_f(v) +static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +#define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \ + host1x_uclass_incr_syncpt_base_offset_f(v) + +#endif diff --git a/drivers/gpu/host1x/hw/intr_hw_t186.c b/drivers/gpu/host1x/hw/intr_hw_t186.c new file mode 100644 index 000000000..48bd1150f --- /dev/null +++ b/drivers/gpu/host1x/hw/intr_hw_t186.c @@ -0,0 +1,247 @@ +/* + * Tegra host1x Interrupt Management + * + * Copyright (C) 2010 Google, Inc. + * Copyright (C) 2016 NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include + +#include "intr.h" +#include "dev.h" + + +static inline u32 bit_mask(u32 nr) +{ + return 1UL << (nr % 32); +} +static inline u32 bit_word(u32 nr) +{ + return nr / 32; +} + +/* + * Sync point threshold interrupt service function + * Handles sync point threshold triggers, in interrupt context + */ +static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt) +{ + unsigned int id = syncpt->id; + struct host1x *host = syncpt->host; + + host1x_sync_writel(host, bit_mask(id), + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(bit_word(id))); + host1x_sync_writel(host, bit_mask(id), + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(bit_word(id))); + + queue_work(host->intr_wq, &syncpt->intr.work); +} + +static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id) +{ + struct host1x *host = dev_id; + unsigned long reg; + int i, set_bit; + + for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) { + reg = host1x_sync_readl(host, + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); + for_each_set_bit(set_bit, ®, 32) { + struct host1x_syncpt *syncpt; + int id = i * 32 + set_bit; + + if (unlikely(id < 0 || id >= host->info->nb_pts)) { + dev_err(host->dev, + "%s(): unexptected syncpt id %d\n", + __func__, id); + goto out; + } + syncpt = host->syncpt + id; + host1x_intr_syncpt_handle(syncpt); + } + } +out: + return IRQ_HANDLED; +} + +static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host) +{ + u32 i; + + for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) { + host1x_sync_writel(host, 0xffffffffu, + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i)); + host1x_sync_writel(host, 0xffffffffu, + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i)); + } +} + +static int _host1x_intr_init_host_sync(struct host1x *host, u32 cpm, + void (*syncpt_thresh_work)(struct work_struct *)) +{ + int i, err; + + host1x_hw_intr_disable_all_syncpt_intrs(host); + + for (i = 0; i < host->info->nb_pts; i++) + INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work); + + err = devm_request_irq(host->dev, host->intr_syncpt_irq, + syncpt_thresh_isr, IRQF_SHARED, + "host1x_syncpt", host); + if (IS_ERR_VALUE(err)) { + WARN_ON(1); + return err; + } + + /* disable the ip_busy_timeout. this prevents write drops */ + host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT); + + /* + * increase the auto-ack timout to the maximum value. 2d will hang + * otherwise on Tegra2. + */ + host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG); + + /* update host clocks per usec */ + host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK); + + return 0; +} + +static void _host1x_intr_set_syncpt_threshold(struct host1x *host, + u32 id, u32 thresh) +{ + host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id)); +} + +static void _host1x_intr_enable_syncpt_intr(struct host1x *host, u32 id) +{ + host1x_sync_writel(host, bit_mask(id), + HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(bit_word(id))); +} + +static void _host1x_intr_disable_syncpt_intr(struct host1x *host, u32 id) +{ + host1x_sync_writel(host, bit_mask(id), + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(bit_word(id))); + host1x_sync_writel(host, bit_mask(id), + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(bit_word(id))); +} + +static int _host1x_free_syncpt_irq(struct host1x *host) +{ + devm_free_irq(host->dev, host->intr_syncpt_irq, host); + flush_workqueue(host->intr_wq); + return 0; +} + +/** + * Host general interrupt service function + * Handles read / write failures + */ +static irqreturn_t general_isr(int irq, void *dev_id) +{ + struct host1x *host = dev_id; + u32 intstatus, addr; + + /* Handle host1x interrupt in ISR */ + intstatus = host1x_sync_readl(host, HOST1X_SYNC_INTSTATUS); + + if (HOST1X_SYNC_INTSTATUS_IP_READ_INT_V(intstatus)) { + addr = host1x_sync_readl(host, + HOST1X_SYNC_IP_READ_TIMEOUT_ADDR); + pr_err("Host read timeout at address %x\n", addr); + } + + if (HOST1X_SYNC_INTSTATUS_IP_WRITE_INT_V(intstatus)) { + addr = host1x_sync_readl(host, + HOST1X_SYNC_IP_WRITE_TIMEOUT_ADDR); + pr_err("Host write timeout at address %x\n", addr); + } + + if (HOST1X_SYNC_INTSTATUS_ILLEGAL_PB_ACCESS_V(intstatus)) { + u32 stat = host1x_sync_readl(host, HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB); + u32 ch = HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB_CH_V(stat); + u32 id = HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_PB_SYNCPT_V(stat); + pr_err("Host illegal syncpoint pb access (ch=%u, id=%u)\n", ch, id); + } + + if (HOST1X_SYNC_INTSTATUS_ILLEGAL_CLIENT_ACCESS_V(intstatus)) { + u32 stat = host1x_sync_readl(host, HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT); + u32 ch = HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT_CH_V(stat); + u32 id = HOST1X_SYNC_ILLEGAL_SYNCPT_ACCESS_FRM_CLIENT_SYNCPT_V(stat); + pr_err("Host illegal syncpoint client access (ch=%u, id=%u)\n", ch, id); + } + + host1x_sync_writel(host, intstatus, HOST1X_SYNC_INTSTATUS); + + return IRQ_HANDLED; +} + +static int _host1x_intr_request_host_general_irq(struct host1x *host) +{ + int err; + + /* master disable for general (not syncpt) host interrupts */ + host1x_sync_writel(host, 0, HOST1X_SYNC_INTC0MASK); + host1x_sync_writel(host, 0, HOST1X_SYNC_INTGMASK); + host1x_sync_writel(host, 0, HOST1X_SYNC_INTMASK); + + err = devm_request_irq(host->dev, host->intr_general_irq, + general_isr, 0, + "host1x_general", host); + if (IS_ERR_VALUE(err)) { + WARN_ON(1); + return err; + } + + /* enable host module interrupt to CPU0 */ + host1x_sync_writel(host, BIT(0), HOST1X_SYNC_INTC0MASK); + host1x_sync_writel(host, BIT(0), HOST1X_SYNC_INTGMASK); + host1x_sync_writel(host, 0xff << 8, HOST1X_SYNC_SYNCPT_INTGMASK); + + /* master enable for general (not syncpt) host interrupts + * (AXIREAD, AXIWRITE, Syncpoint protection */ + host1x_sync_writel(host, BIT(0) | BIT(1) | BIT(28) | BIT(30), + HOST1X_SYNC_INTMASK); + + return err; +} + +static void _host1x_intr_free_host_general_irq(struct host1x *host) +{ + /* master disable for general (not syncpt) host interrupts */ + host1x_sync_writel(host, 0, HOST1X_SYNC_INTMASK); + host1x_sync_writel(host, 0, HOST1X_SYNC_SYNCPT_INTGMASK); + + devm_free_irq(host->dev, host->intr_general_irq, host); +} + +static const struct host1x_intr_ops host1x_intr_t186_ops = { + /* Syncpt interrupts */ + .init_host_sync = _host1x_intr_init_host_sync, + .set_syncpt_threshold = _host1x_intr_set_syncpt_threshold, + .enable_syncpt_intr = _host1x_intr_enable_syncpt_intr, + .disable_syncpt_intr = _host1x_intr_disable_syncpt_intr, + .disable_all_syncpt_intrs = _host1x_intr_disable_all_syncpt_intrs, + .free_syncpt_irq = _host1x_free_syncpt_irq, + + /* Host general interrupts */ + .request_host_general_irq = _host1x_intr_request_host_general_irq, + .free_host_general_irq = _host1x_intr_free_host_general_irq, +}; diff --git a/drivers/gpu/host1x/hw/syncpt_hw_t186.c b/drivers/gpu/host1x/hw/syncpt_hw_t186.c new file mode 100644 index 000000000..9b196854a --- /dev/null +++ b/drivers/gpu/host1x/hw/syncpt_hw_t186.c @@ -0,0 +1,126 @@ +/* + * Tegra host1x Syncpoints + * + * Copyright (c) 2016, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include "dev.h" +#include "syncpt.h" + +/* + * Write the current syncpoint value back to hw. + */ +static void syncpt_restore(struct host1x_syncpt *sp) +{ + struct host1x *host = sp->host; + int min = host1x_syncpt_read_min(sp); + host1x_sync_writel(host, min, HOST1X_SYNC_SYNCPT(sp->id)); +} + +/* + * Write the current waitbase value back to hw. + */ +static void syncpt_restore_wait_base(struct host1x_syncpt *sp) +{ + struct host1x *host = sp->host; + host1x_sync_writel(host, sp->base_val, + HOST1X_SYNC_SYNCPT_BASE(sp->id)); +} + +/* + * Read waitbase value from hw. + */ +static void syncpt_read_wait_base(struct host1x_syncpt *sp) +{ + struct host1x *host = sp->host; + sp->base_val = + host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id)); +} + +/* + * Updates the last value read from hardware. + */ +static u32 syncpt_load(struct host1x_syncpt *sp) +{ + struct host1x *host = sp->host; + u32 old, live; + + /* Loop in case there's a race writing to min_val */ + do { + old = host1x_syncpt_read_min(sp); + live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id)); + } while ((u32)atomic_cmpxchg(&sp->min_val, old, live) != old); + + if (!host1x_syncpt_check_max(sp, live)) + dev_err(host->dev, "%s failed: id=%u, min=%d, max=%d\n", + __func__, sp->id, host1x_syncpt_read_min(sp), + host1x_syncpt_read_max(sp)); + + return live; +} + +/* + * Write a cpu syncpoint increment to the hardware, without touching + * the cache. + */ +static int syncpt_cpu_incr(struct host1x_syncpt *sp) +{ + struct host1x *host = sp->host; + u32 reg_offset = sp->id / 32; + + if (!host1x_syncpt_client_managed(sp) && + host1x_syncpt_idle(sp)) + return -EINVAL; + host1x_sync_writel(host, BIT_MASK(sp->id), + HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset)); + wmb(); + + return 0; +} + +/* remove a wait pointed to by patch_addr */ +static int syncpt_patch_wait(struct host1x_syncpt *sp, void *patch_addr) +{ + u32 override = host1x_class_host_wait_syncpt( + HOST1X_SYNCPT_RESERVED, 0); + + *((u32 *)patch_addr) = override; + return 0; +} + +static void syncpt_get_mutex_owner(struct host1x_syncpt *sp, + unsigned int mutex_id, bool *cpu, bool *ch, + unsigned int *chid) +{ + struct host1x *host = sp->host; + u32 owner; + + owner = host1x_sync_readl(host, host1x_sync_common_mlock_r(mutex_id)); + *chid = HOST1X_SYNC_COMMON_MLOCK_CH_V(owner); + *ch = HOST1X_SYNC_COMMON_MLOCK_LOCKED_V(owner); + *cpu = false; +} + +static const struct host1x_syncpt_ops host1x_syncpt_t186_ops = { + .restore = syncpt_restore, + .restore_wait_base = syncpt_restore_wait_base, + .load_wait_base = syncpt_read_wait_base, + .load = syncpt_load, + .cpu_incr = syncpt_cpu_incr, + .patch_wait = syncpt_patch_wait, + .get_mutex_owner = syncpt_get_mutex_owner, +}; -- cgit v1.2.2 From 0d38894a0fb6c165ce786ce60857e4f6ee9c1708 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 3 Mar 2016 14:15:16 +0530 Subject: gpu: host1x: API to load streamid registers Define host1x_dev_ops for T186 Add API load_streamid_regs() to load streamid registers Set this API to host1x_dev_ops.load_regs so that we set streamid registers during host1x_probe() Add a static table which includes streamid mappings for all the clients Bug 1704301 Change-Id: I7aeefc43776472a7ccf868bfa18c810f3b80b52b Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1023438 Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/host1x/hw/host1x05.c | 2 + drivers/gpu/host1x/hw/stremid_hw_t186.c | 95 +++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 drivers/gpu/host1x/hw/stremid_hw_t186.c (limited to 'drivers/gpu') diff --git a/drivers/gpu/host1x/hw/host1x05.c b/drivers/gpu/host1x/hw/host1x05.c index db64e7cfe..3a790bee4 100644 --- a/drivers/gpu/host1x/hw/host1x05.c +++ b/drivers/gpu/host1x/hw/host1x05.c @@ -24,11 +24,13 @@ #include "debug_hw_t186.c" #include "intr_hw_t186.c" #include "syncpt_hw_t186.c" +#include "stremid_hw_t186.c" #include "dev.h" int host1x05_init(struct host1x *host) { + host->dev_op = &host1x_dev_t186_ops; host->channel_op = &host1x_channel_t186_ops; host->cdma_op = &host1x_cdma_t186_ops; host->cdma_pb_op = &host1x_pushbuffer_t186_ops; diff --git a/drivers/gpu/host1x/hw/stremid_hw_t186.c b/drivers/gpu/host1x/hw/stremid_hw_t186.c new file mode 100644 index 000000000..9f4c36852 --- /dev/null +++ b/drivers/gpu/host1x/hw/stremid_hw_t186.c @@ -0,0 +1,95 @@ +/* + * Copyright (c) 2016, NVIDIA Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + + +#include "dev_t186.h" + +struct host1x_streamid_mapping { + u32 host1x_offset; + u32 client_offset; + u32 client_limit; +}; + +static struct host1x_streamid_mapping __attribute__((__unused__)) + t18x_host1x_streamid_mapping[] = { + /* HOST1X_THOST_COMMON_SE1_STRMID_0_OFFSET_BASE_0 */ + { 0x00001ac8, 0x00000090, 0x00000090}, + /* HOST1X_THOST_COMMON_SE2_STRMID_0_OFFSET_BASE_0 */ + { 0x00001ad0, 0x00000090, 0x00000090}, + /* HOST1X_THOST_COMMON_SE3_STRMID_0_OFFSET_BASE_0 */ + { 0x00001ad8, 0x00000090, 0x00000090}, + /* HOST1X_THOST_COMMON_SE4_STRMID_0_OFFSET_BASE_0 */ + { 0x00001ae0, 0x00000090, 0x00000090}, + /* HOST1X_THOST_COMMON_ISP_STRMID_0_OFFSET_BASE_0 */ + { 0x00001ae8, 0x00000050, 0x00000050}, + /* HOST1X_THOST_COMMON_VIC_STRMID_0_OFFSET_BASE_0 */ + { 0x00001af0, 0x00000030, 0x00000034}, + /* HOST1X_THOST_COMMON_NVENC_STRMID_0_OFFSET_BASE_0 */ + { 0x00001af8, 0x00000030, 0x00000034}, + /* HOST1X_THOST_COMMON_NVDEC_STRMID_0_OFFSET_BASE_0 */ + { 0x00001b00, 0x00000030, 0x00000034}, + /* HOST1X_THOST_COMMON_NVJPG_STRMID_0_OFFSET_BASE_0 */ + { 0x00001b08, 0x00000030, 0x00000034}, + /* HOST1X_THOST_COMMON_TSEC_STRMID_0_OFFSET_BASE_0 */ + { 0x00001b10, 0x00000030, 0x00000034}, + /* HOST1X_THOST_COMMON_TSECB_STRMID_0_OFFSET_BASE_0 */ + { 0x00001b18, 0x00000030, 0x00000034}, + /* HOST1X_THOST_COMMON_VI_STRMID_0_OFFSET_BASE_0 */ + { 0x00001b80, 0x00010000, 0x00010000}, + /* HOST1X_THOST_COMMON_VI_STRMID_1_OFFSET_BASE_0 */ + { 0x00001b88, 0x00020000, 0x00020000}, + /* HOST1X_THOST_COMMON_VI_STRMID_2_OFFSET_BASE_0 */ + { 0x00001b90, 0x00030000, 0x00030000}, + /* HOST1X_THOST_COMMON_VI_STRMID_3_OFFSET_BASE_0 */ + { 0x00001b98, 0x00040000, 0x00040000}, + /* HOST1X_THOST_COMMON_VI_STRMID_4_OFFSET_BASE_0 */ + { 0x00001ba0, 0x00050000, 0x00050000}, + /* HOST1X_THOST_COMMON_VI_STRMID_5_OFFSET_BASE_0 */ + { 0x00001ba8, 0x00060000, 0x00060000}, + /* HOST1X_THOST_COMMON_VI_STRMID_6_OFFSET_BASE_0 */ + { 0x00001bb0, 0x00070000, 0x00070000}, + /* HOST1X_THOST_COMMON_VI_STRMID_7_OFFSET_BASE_0 */ + { 0x00001bb8, 0x00080000, 0x00080000}, + /* HOST1X_THOST_COMMON_VI_STRMID_8_OFFSET_BASE_0 */ + { 0x00001bc0, 0x00090000, 0x00090000}, + /* HOST1X_THOST_COMMON_VI_STRMID_9_OFFSET_BASE_0 */ + { 0x00001bc8, 0x000a0000, 0x000a0000}, + /* HOST1X_THOST_COMMON_VI_STRMID_10_OFFSET_BASE_0 */ + { 0x00001bd0, 0x000b0000, 0x000b0000}, + /* HOST1X_THOST_COMMON_VI_STRMID_11_OFFSET_BASE_0 */ + { 0x00001bd8, 0x000c0000, 0x000c0000}, + {}, +}; + +static int load_streamid_regs(struct host1x *host) +{ + struct host1x_streamid_mapping *map_regs = t18x_host1x_streamid_mapping; + + while (map_regs->host1x_offset) { + host1x_writel(host, map_regs->client_offset, + map_regs->host1x_offset); + host1x_writel(host, map_regs->client_limit, + map_regs->host1x_offset + sizeof(u32)); + + map_regs++; + } + + return 0; +} + +static const struct host1x_dev_ops host1x_dev_t186_ops = { + .load_regs = load_streamid_regs, +}; -- cgit v1.2.2 From a05ad4e23fe34423488e14e216f79cd185507cb6 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 3 Mar 2016 19:15:24 +0530 Subject: drm/tegra: add T186 support to VIC Define vic_t186_config and vic_t186_ops for VIC Define .load_regs = vic_load_streamid_regs() for VIC streamid support Bug 1704301 Change-Id: Ib364c773c6c340c30e2644ef0baca500d89de55c Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1023439 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/drm/tegra/Makefile | 7 ++++++ drivers/gpu/drm/tegra/vic_t186.c | 48 ++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/vic_t186.h | 27 ++++++++++++++++++++++ 3 files changed, 82 insertions(+) create mode 100644 drivers/gpu/drm/tegra/Makefile create mode 100644 drivers/gpu/drm/tegra/vic_t186.c create mode 100644 drivers/gpu/drm/tegra/vic_t186.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile new file mode 100644 index 000000000..7b2ba155c --- /dev/null +++ b/drivers/gpu/drm/tegra/Makefile @@ -0,0 +1,7 @@ +ccflags-y += -Idrivers/gpu/drm/tegra +ccflags-y += -I../kernel-t18x/drivers/gpu/drm/tegra + +tegra-drm-t186-y = \ + vic_t186.o + +obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/drm/tegra/vic_t186.c b/drivers/gpu/drm/tegra/vic_t186.c new file mode 100644 index 000000000..c6efe1e86 --- /dev/null +++ b/drivers/gpu/drm/tegra/vic_t186.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "drm.h" +#include "vic_t186.h" + +#include + +static int vic_load_streamid_regs(struct tegra_drm_client *client) +{ + struct vic *vic = to_vic(client); + int streamid = -EINVAL; + + streamid = iommu_get_hwid(vic->dev->archdata.iommu, vic->dev, 0); + + if (streamid >= 0) { + vic_writel(vic, streamid, VIC_THI_STREAMID0); + vic_writel(vic, streamid, VIC_THI_STREAMID1); + } + + return 0; +} + +static const struct tegra_drm_client_ops vic_t186_ops = { + .open_channel = vic_open_channel, + .close_channel = vic_close_channel, + .is_addr_reg = vic_is_addr_reg, + .submit = tegra_drm_submit, + .load_regs = vic_load_streamid_regs, +}; + +const struct vic_config vic_t186_config = { + .ucode_name = "tegra18x/vic04_ucode.bin", + .drm_client_ops = &vic_t186_ops, +}; diff --git a/drivers/gpu/drm/tegra/vic_t186.h b/drivers/gpu/drm/tegra/vic_t186.h new file mode 100644 index 000000000..e819dd49d --- /dev/null +++ b/drivers/gpu/drm/tegra/vic_t186.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TEGRA_VIC_T186_H +#define TEGRA_VIC_T186_H + +#include "vic.h" + +#define VIC_THI_STREAMID0 0x30 +#define VIC_THI_STREAMID1 0x34 + +extern const struct vic_config vic_t186_config; + +#endif -- cgit v1.2.2 From 368db829f3d9bf6d6e1a7905aee449a82bfa08df Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Tue, 8 Mar 2016 11:01:47 -0800 Subject: gpu: nvgpu: t18x: update blcg prod settings Update prod settings to disable stall blcg. Bug 1729471 Change-Id: I1123bf47159fc9dbb1223aebcacf37361b90743f Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1026611 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Mahantesh Kumbar Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c index 7be9b60ff..6bcd9f358 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c @@ -207,7 +207,7 @@ static const struct gating_desc gp10b_blcg_gr[] = { {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x0000c444, .disable = 0x00000000}, + {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, -- cgit v1.2.2 From 41957a658ef65a711479a403098c7079a58d61e2 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Tue, 8 Mar 2016 10:54:02 -0800 Subject: gpu: nvgpu: gp10b: Allow importing makefile via include Refactor makefiles so that there is one makefile, and that file can be included in the main nvgpu build. Bug 1476801 Change-Id: I23ac451d695fc64064de2300e83b9d9487c52743 Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1028353 Reviewed-by: Konsta Holtta GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile | 33 +++++++++++++++++++++++++-------- drivers/gpu/nvgpu/gp10b/Makefile | 31 ------------------------------- drivers/gpu/nvgpu/vgpu/gp10b/Makefile | 16 ---------------- 3 files changed, 25 insertions(+), 55 deletions(-) delete mode 100644 drivers/gpu/nvgpu/gp10b/Makefile delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/Makefile (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 37cc15a59..c4873257c 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -1,10 +1,27 @@ -GCOV_PROFILE := y +nvgpu-t18x := ../../../../kernel-t18x/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/include/linux -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include -ccflags-$(CONFIG_GK20A) += -Wno-multichar -ccflags-$(CONFIG_GK20A) += -Werror +nvgpu-y += \ + $(nvgpu-t18x)/gp10b/gr_gp10b.o \ + $(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \ + $(nvgpu-t18x)/gp10b/ce2_gp10b.o \ + $(nvgpu-t18x)/gp10b/mc_gp10b.o \ + $(nvgpu-t18x)/gp10b/fifo_gp10b.o \ + $(nvgpu-t18x)/gp10b/ltc_gp10b.o \ + $(nvgpu-t18x)/gp10b/mm_gp10b.o \ + $(nvgpu-t18x)/gp10b/fb_gp10b.o \ + $(nvgpu-t18x)/gp10b/pmu_gp10b.o \ + $(nvgpu-t18x)/gp10b/hal_gp10b.o \ + $(nvgpu-t18x)/gp10b/rpfb_gp10b.o \ + $(nvgpu-t18x)/gp10b/gp10b_gating_reglist.o \ + $(nvgpu-t18x)/gp10b/regops_gp10b.o \ + $(nvgpu-t18x)/gp10b/cde_gp10b.o \ + $(nvgpu-t18x)/gp10b/therm_gp10b.o \ + $(nvgpu-t18x)/gp10b/gp10b_sysfs.o -obj-$(CONFIG_GK20A) += gp10b/ -obj-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += vgpu/gp10b/ +nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o + +nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ + $(nvgpu-t18x)/vgpu/gp10b/vgpu_hal_gp10b.o \ + $(nvgpu-t18x)/vgpu/gp10b/vgpu_gr_gp10b.o \ + $(nvgpu-t18x)/vgpu/gp10b/vgpu_mm_gp10b.o \ + $(nvgpu-t18x)/vgpu/gp10b/vgpu_fifo_gp10b.o diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile deleted file mode 100644 index 8b930bca4..000000000 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ /dev/null @@ -1,31 +0,0 @@ -GCOV_PROFILE := y - -ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/include -ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/devfreq -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi - -ccflags-$(CONFIG_GK20A) += -Wno-multichar -ccflags-y += -Werror - -obj-$(CONFIG_GK20A) += \ - gr_gp10b.o \ - gr_ctx_gp10b.o \ - ce2_gp10b.o \ - mc_gp10b.o \ - fifo_gp10b.o \ - ltc_gp10b.o \ - mm_gp10b.o \ - fb_gp10b.o \ - pmu_gp10b.o \ - hal_gp10b.o \ - rpfb_gp10b.o \ - gp10b_gating_reglist.o \ - regops_gp10b.o \ - cde_gp10b.o \ - therm_gp10b.o \ - gp10b_sysfs.o - -obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/Makefile b/drivers/gpu/nvgpu/vgpu/gp10b/Makefile deleted file mode 100644 index fed8a08e7..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -GCOV_PROFILE := y - -ccflags-$(CONFIG_GK20A) += -I$(srctree)/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/include -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/drivers/gpu/nvgpu -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include -ccflags-$(CONFIG_GK20A) += -I$(srctree)/../kernel-t18x/include/uapi - -ccflags-$(CONFIG_GK20A) += -Wno-multichar -ccflags-y += -Werror - -obj-$(CONFIG_GK20A) += \ - vgpu_hal_gp10b.o \ - vgpu_gr_gp10b.o \ - vgpu_mm_gp10b.o \ - vgpu_fifo_gp10b.o -- cgit v1.2.2 From 66f315de7e6e4f51078c7384bcee522ceefbeb38 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Mon, 14 Mar 2016 12:00:05 -0700 Subject: gpu: nvgpu: gp10b: update prod setiings Add/update following prod settings: blcg ce slcg ce2 Change-Id: I10a62d980479ad23efd7033d29e269c4aac08834 Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/1030986 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 20 ++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h | 8 +++++++- drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 +++++- 3 files changed, 32 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c index 6bcd9f358..4719b13e1 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c @@ -163,6 +163,11 @@ static const struct gating_desc gp10b_blcg_bus[] = { {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, }; +/* blcg ce */ +static const struct gating_desc gp10b_blcg_ce[] = { + {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, +}; + /* blcg ctxsw prog */ static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { }; @@ -483,6 +488,21 @@ void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, } } +void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod) +{ + u32 i; + u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); + for (i = 0; i < size; i++) { + if (prod) + gk20a_writel(g, gp10b_blcg_ce[i].addr, + gp10b_blcg_ce[i].prod); + else + gk20a_writel(g, gp10b_blcg_ce[i].addr, + gp10b_blcg_ce[i].disable); + } +} + void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, bool prod) { diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h index 465a0b4de..e4080def8 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h +++ b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,6 +19,9 @@ void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, bool prod); +void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, + bool prod); + void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, bool prod); @@ -58,6 +61,9 @@ void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, bool prod); +void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, + bool prod); + void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, bool prod); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 544be96bb..37fad41ab 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -1,7 +1,7 @@ /* * GP10B Tegra HAL interface * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -47,6 +47,8 @@ static struct gpu_ops gp10b_ops = { .clock_gating = { .slcg_bus_load_gating_prod = gp10b_slcg_bus_load_gating_prod, + .slcg_ce2_load_gating_prod = + gp10b_slcg_ce2_load_gating_prod, .slcg_chiplet_load_gating_prod = gp10b_slcg_chiplet_load_gating_prod, .slcg_ctxsw_firmware_load_gating_prod = @@ -71,6 +73,8 @@ static struct gpu_ops gp10b_ops = { gp10b_slcg_xbar_load_gating_prod, .blcg_bus_load_gating_prod = gp10b_blcg_bus_load_gating_prod, + .blcg_ce_load_gating_prod = + gp10b_blcg_ce_load_gating_prod, .blcg_ctxsw_firmware_load_gating_prod = gp10b_blcg_ctxsw_firmware_load_gating_prod, .blcg_fb_load_gating_prod = -- cgit v1.2.2 From 8edebf8522809bbcac985a83d9eaf9611828d098 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Tue, 8 Mar 2016 18:29:15 +0530 Subject: drm/tegra: add T186 support to NVENC Define nvenc_t186_config and nvenc_t186_ops for NVENC Define .load_regs = nvenc_load_streamid_regs() for NVENC streamid support. Bug 1704301 Change-Id: I71efcfe4208568b5e4cbc463444d7d4a6ccfb96c Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1026451 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/drm/tegra/Makefile | 3 ++- drivers/gpu/drm/tegra/nvenc_t186.c | 47 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/nvenc_t186.h | 27 ++++++++++++++++++++++ 3 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/tegra/nvenc_t186.c create mode 100644 drivers/gpu/drm/tegra/nvenc_t186.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 7b2ba155c..24f66986c 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -2,6 +2,7 @@ ccflags-y += -Idrivers/gpu/drm/tegra ccflags-y += -I../kernel-t18x/drivers/gpu/drm/tegra tegra-drm-t186-y = \ - vic_t186.o + vic_t186.o \ + nvenc_t186.o obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/drm/tegra/nvenc_t186.c b/drivers/gpu/drm/tegra/nvenc_t186.c new file mode 100644 index 000000000..68cc6a7e5 --- /dev/null +++ b/drivers/gpu/drm/tegra/nvenc_t186.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "drm.h" +#include "nvenc_t186.h" + +#include + +static int nvenc_load_streamid_regs(struct tegra_drm_client *client) +{ + struct nvenc *nvenc = to_nvenc(client); + int streamid = -EINVAL; + + streamid = iommu_get_hwid(nvenc->dev->archdata.iommu, nvenc->dev, 0); + + if (streamid >= 0) { + nvenc_writel(nvenc, streamid, NVENC_THI_STREAMID0); + nvenc_writel(nvenc, streamid, NVENC_THI_STREAMID1); + } + + return 0; +} + +static const struct tegra_drm_client_ops nvenc_t186_ops = { + .open_channel = nvenc_open_channel, + .close_channel = nvenc_close_channel, + .submit = tegra_drm_submit, + .load_regs = nvenc_load_streamid_regs, +}; + +const struct nvenc_config nvenc_t186_config = { + .ucode_name = "tegra18x/nvhost_nvenc061.fw", + .drm_client_ops = &nvenc_t186_ops, +}; diff --git a/drivers/gpu/drm/tegra/nvenc_t186.h b/drivers/gpu/drm/tegra/nvenc_t186.h new file mode 100644 index 000000000..1ae36ec16 --- /dev/null +++ b/drivers/gpu/drm/tegra/nvenc_t186.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TEGRA_NVENC_T186_H +#define TEGRA_NVENC_T186_H + +#include "nvenc.h" + +#define NVENC_THI_STREAMID0 0x30 +#define NVENC_THI_STREAMID1 0x34 + +extern const struct nvenc_config nvenc_t186_config; + +#endif -- cgit v1.2.2 From 4159bc6971c8ef20a40bb51846c37002f2e6fcb1 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 9 Mar 2016 21:40:50 +0530 Subject: drm/tegra: add T186 support to NVDEC Define nvdec_t186_config and nvenc_t186_ops for NVDEC Define .load_regs = nvdec_load_streamid_regs() for NVDEC streamid support Define prepare_poweroff() and finalize_poweron() Bug 1704301 Change-Id: Ibfbb9f40ca4646e7d3afa4a150f6303e0399299c Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1029498 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/drm/tegra/Makefile | 3 +- drivers/gpu/drm/tegra/nvdec_t186.c | 63 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/nvdec_t186.h | 27 ++++++++++++++++ 3 files changed, 92 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/tegra/nvdec_t186.c create mode 100644 drivers/gpu/drm/tegra/nvdec_t186.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 24f66986c..90f81004d 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -3,6 +3,7 @@ ccflags-y += -I../kernel-t18x/drivers/gpu/drm/tegra tegra-drm-t186-y = \ vic_t186.o \ - nvenc_t186.o + nvenc_t186.o \ + nvdec_t186.o obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/drm/tegra/nvdec_t186.c b/drivers/gpu/drm/tegra/nvdec_t186.c new file mode 100644 index 000000000..7d9e846c3 --- /dev/null +++ b/drivers/gpu/drm/tegra/nvdec_t186.c @@ -0,0 +1,63 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "drm.h" +#include "nvdec_t186.h" + +#include +#include + +static int nvdec_load_streamid_regs(struct tegra_drm_client *client) +{ + struct nvdec *nvdec = to_nvdec(client); + int streamid = -EINVAL; + + streamid = iommu_get_hwid(nvdec->dev->archdata.iommu, nvdec->dev, 0); + + if (streamid >= 0) { + nvdec_writel(nvdec, streamid, NVDEC_THI_STREAMID0); + nvdec_writel(nvdec, streamid, NVDEC_THI_STREAMID1); + } + + return 0; +} + +static int nvdec_finalize_poweron(struct tegra_drm_client *client) +{ + return tegra_kfuse_enable_sensing(); +} + +static int nvdec_prepare_poweroff(struct tegra_drm_client *client) +{ + tegra_kfuse_disable_sensing(); + return 0; +} + +static const struct tegra_drm_client_ops nvdec_t186_ops = { + .open_channel = nvdec_open_channel, + .close_channel = nvdec_close_channel, + .submit = tegra_drm_submit, + .load_regs = nvdec_load_streamid_regs, + .finalize_poweron = nvdec_finalize_poweron, + .prepare_poweroff = nvdec_prepare_poweroff, +}; + +const struct nvdec_config nvdec_t186_config = { + .ucode_name = "tegra18x/nvhost_nvdec030_ns.fw", + .ucode_name_bl = "tegra18x/nvhost_nvdec_bl030_prod.fw", + .ucode_name_ls = "tegra18x/nvhost_nvdec030_prod.fw", + .drm_client_ops = &nvdec_t186_ops, +}; diff --git a/drivers/gpu/drm/tegra/nvdec_t186.h b/drivers/gpu/drm/tegra/nvdec_t186.h new file mode 100644 index 000000000..8d57e1d59 --- /dev/null +++ b/drivers/gpu/drm/tegra/nvdec_t186.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TEGRA_NVDEC_T186_H +#define TEGRA_NVDEC_T186_H + +#include "nvdec.h" + +#define NVDEC_THI_STREAMID0 0x30 +#define NVDEC_THI_STREAMID1 0x34 + +extern const struct nvdec_config nvdec_t186_config; + +#endif -- cgit v1.2.2 From 4aba7fe8e994769594251757db35e029ab4e295c Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Wed, 9 Mar 2016 21:56:05 +0530 Subject: drm/tegra: add T186 support to NVJPG Define nvjpg_t186_config and nvjpg_t186_ops for NVJPG Define .load_regs = nvjpg_load_streamid_regs() for NVJPG streamid support Bug 1704301 Change-Id: I7181a414ebe4ff5db3ce70592494cda13f03f784 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1029499 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/drm/tegra/Makefile | 3 ++- drivers/gpu/drm/tegra/nvjpg_t186.c | 47 ++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/nvjpg_t186.h | 27 ++++++++++++++++++++++ 3 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/tegra/nvjpg_t186.c create mode 100644 drivers/gpu/drm/tegra/nvjpg_t186.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 90f81004d..ff2e239fc 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -4,6 +4,7 @@ ccflags-y += -I../kernel-t18x/drivers/gpu/drm/tegra tegra-drm-t186-y = \ vic_t186.o \ nvenc_t186.o \ - nvdec_t186.o + nvdec_t186.o \ + nvjpg_t186.o obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/drm/tegra/nvjpg_t186.c b/drivers/gpu/drm/tegra/nvjpg_t186.c new file mode 100644 index 000000000..af262c589 --- /dev/null +++ b/drivers/gpu/drm/tegra/nvjpg_t186.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "drm.h" +#include "nvjpg_t186.h" + +#include + +static int nvjpg_load_streamid_regs(struct tegra_drm_client *client) +{ + struct nvjpg *nvjpg = to_nvjpg(client); + int streamid = -EINVAL; + + streamid = iommu_get_hwid(nvjpg->dev->archdata.iommu, nvjpg->dev, 0); + + if (streamid >= 0) { + nvjpg_writel(nvjpg, streamid, NVJPG_THI_STREAMID0); + nvjpg_writel(nvjpg, streamid, NVJPG_THI_STREAMID1); + } + + return 0; +} + +static const struct tegra_drm_client_ops nvjpg_t186_ops = { + .open_channel = nvjpg_open_channel, + .close_channel = nvjpg_close_channel, + .submit = tegra_drm_submit, + .load_regs = nvjpg_load_streamid_regs, +}; + +const struct nvjpg_config nvjpg_t186_config = { + .ucode_name = "tegra18x/nvhost_nvjpg011.fw", + .drm_client_ops = &nvjpg_t186_ops, +}; diff --git a/drivers/gpu/drm/tegra/nvjpg_t186.h b/drivers/gpu/drm/tegra/nvjpg_t186.h new file mode 100644 index 000000000..a310e34c1 --- /dev/null +++ b/drivers/gpu/drm/tegra/nvjpg_t186.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TEGRA_NVJPG_T186_H +#define TEGRA_NVJPG_T186_H + +#include "nvjpg.h" + +#define NVJPG_THI_STREAMID0 0x30 +#define NVJPG_THI_STREAMID1 0x34 + +extern const struct nvjpg_config nvjpg_t186_config; + +#endif -- cgit v1.2.2 From 379e6ecdd39844fbde4713d1c5f893840acb5ab2 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 10 Mar 2016 14:46:29 +0530 Subject: gpu: host1x: keep device powered on during submit Get pm_runtime reference on device to keep device powered on during submit Bug 1704301 Change-Id: I71d4b4dc6317445bc3d1832ffd3bd4c7afadc654 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1029500 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/host1x/hw/channel_hw_t186.c | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'drivers/gpu') diff --git a/drivers/gpu/host1x/hw/channel_hw_t186.c b/drivers/gpu/host1x/hw/channel_hw_t186.c index 2b90ba638..256368f29 100644 --- a/drivers/gpu/host1x/hw/channel_hw_t186.c +++ b/drivers/gpu/host1x/hw/channel_hw_t186.c @@ -19,6 +19,7 @@ #include #include #include +#include #include @@ -194,6 +195,10 @@ static int channel_submit(struct host1x_job *job) syncpt = host1x_syncpt_get(host, job->syncpts[0].id); prev_max = host1x_syncpt_read_max(syncpt); + /* keep device powered on */ + for (i = 0; i < job->num_syncpts; ++i) + pm_runtime_get_sync(ch->dev); + /* get submit lock */ err = mutex_lock_interruptible(&ch->submitlock); if (err) -- cgit v1.2.2 From c895f5e50e568a0f64fee8020c8cff213739db73 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 10 Mar 2016 15:40:08 +0530 Subject: drm/tegra: add T186 support to TSEC Define tsec_t186_config/tsecb_t186_config and tsec_t186_ops for TSEC Define .load_regs = tsec_load_streamid_regs() for TSEC streamid support Bug 1704301 Change-Id: Ibf3219973627802ee4301c5a23e766d9953dbc3b Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1029501 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/drm/tegra/Makefile | 3 ++- drivers/gpu/drm/tegra/tsec_t186.c | 54 +++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/tegra/tsec_t186.h | 28 ++++++++++++++++++++ 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/tegra/tsec_t186.c create mode 100644 drivers/gpu/drm/tegra/tsec_t186.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index ff2e239fc..048a3f3c2 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -5,6 +5,7 @@ tegra-drm-t186-y = \ vic_t186.o \ nvenc_t186.o \ nvdec_t186.o \ - nvjpg_t186.o + nvjpg_t186.o \ + tsec_t186.o obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/drm/tegra/tsec_t186.c b/drivers/gpu/drm/tegra/tsec_t186.c new file mode 100644 index 000000000..5a47bbc28 --- /dev/null +++ b/drivers/gpu/drm/tegra/tsec_t186.c @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "drm.h" +#include "tsec_t186.h" + +#include + +static int tsec_load_streamid_regs(struct tegra_drm_client *client) +{ + struct tsec *tsec = to_tsec(client); + int streamid = -EINVAL; + + streamid = iommu_get_hwid(tsec->dev->archdata.iommu, tsec->dev, 0); + + if (streamid >= 0) { + tsec_writel(tsec, streamid, TSEC_THI_STREAMID0); + tsec_writel(tsec, streamid, TSEC_THI_STREAMID1); + } + + return 0; +} + +static const struct tegra_drm_client_ops tsec_t186_ops = { + .open_channel = tsec_open_channel, + .close_channel = tsec_close_channel, + .submit = tegra_drm_submit, + .load_regs = tsec_load_streamid_regs, +}; + +const struct tsec_config tsec_t186_config = { + .ucode_name = "tegra18x/nvhost_tsec.fw", + .drm_client_ops = &tsec_t186_ops, + .class_id = HOST1X_CLASS_TSEC, +}; + +const struct tsec_config tsecb_t186_config = { + .ucode_name = "tegra18x/nvhost_tsec.fw", + .drm_client_ops = &tsec_t186_ops, + .class_id = HOST1X_CLASS_TSECB, +}; diff --git a/drivers/gpu/drm/tegra/tsec_t186.h b/drivers/gpu/drm/tegra/tsec_t186.h new file mode 100644 index 000000000..e78ea2cf8 --- /dev/null +++ b/drivers/gpu/drm/tegra/tsec_t186.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2016 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef TEGRA_TSEC_T186_H +#define TEGRA_TSEC_T186_H + +#include "tsec.h" + +#define TSEC_THI_STREAMID0 0x30 +#define TSEC_THI_STREAMID1 0x34 + +extern const struct tsec_config tsec_t186_config; +extern const struct tsec_config tsecb_t186_config; + +#endif -- cgit v1.2.2 From 480b0c2eb327f1c73187dc2ebdd382e696a360b8 Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Thu, 10 Mar 2016 16:31:34 +0530 Subject: gpu: host1x: enable gather filter for T186 Bug 1704301 Change-Id: Id783a06f353ae4627103ac48ab903eefd9b2ec7b Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1029502 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Arto Merilainen GVS: Gerrit_Virtual_Submit Reviewed-by: Shridhar Rasal --- drivers/gpu/host1x/dev_t186.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/host1x/dev_t186.c b/drivers/gpu/host1x/dev_t186.c index e4d148760..d29a48c68 100644 --- a/drivers/gpu/host1x/dev_t186.c +++ b/drivers/gpu/host1x/dev_t186.c @@ -26,7 +26,7 @@ struct host1x_info host1x05_info = { .nb_bases = 16, .init = host1x05_init, .sync_offset = 0x0, - .gather_filter_enabled = false, + .gather_filter_enabled = true, }; void host1x_writel(struct host1x *host1x, u32 v, u32 r) -- cgit v1.2.2 From 139de9fe7c9aafab402fb7179170ce7d56440ce9 Mon Sep 17 00:00:00 2001 From: Terje Bergstrom Date: Fri, 11 Mar 2016 12:45:53 -0800 Subject: gpu: nvgpu: gp10b: Update regops whitelist Update regops whitelist with two new registers. Bug 1734151 Change-Id: Id09bdfb1733620bb75d4558299c5e9c7f66bb00b Signed-off-by: Terje Bergstrom Reviewed-on: http://git-master/r/1029772 GVS: Gerrit_Virtual_Submit Reviewed-by: Richard Zhao --- drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c index 48f6161d2..8934c3248 100644 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c @@ -69,6 +69,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x00142480, 1}, { 0x001424a0, 1}, { 0x00142550, 1}, + { 0x0017e028, 1}, { 0x0017e280, 1}, { 0x0017e294, 1}, { 0x0017e29c, 2}, @@ -138,7 +139,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x001b4094, 3}, { 0x001b40a4, 1}, { 0x001b4100, 6}, - { 0x001b4124, 1}, + { 0x001b4124, 2}, { 0x001b8000, 1}, { 0x001b8008, 1}, { 0x001b8010, 3}, @@ -371,6 +372,7 @@ static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { { 0x00900100, 1}, { 0x009a0100, 1}, }; + static const u32 gp10b_global_whitelist_ranges_count = ARRAY_SIZE(gp10b_global_whitelist_ranges); -- cgit v1.2.2 From 44a97a9a8a433698b252988b6cc4306c22621c5d Mon Sep 17 00:00:00 2001 From: Arul Sekar Date: Fri, 11 Mar 2016 11:25:40 -0800 Subject: gpu: nvgpu: add function to access ptimer time bug 1648908 Change-Id: I32211b13489b21eba25f7473a18b9d1a303d2642 Signed-off-by: Arul Sekar Reviewed-on: http://git-master/r/1029733 Reviewed-by: Arun Gona Tested-by: Arun Gona Reviewed-on: http://git-master/r/1111716 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h index 88d221284..e0fc59df1 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -98,4 +98,12 @@ static inline u32 timer_pri_timeout_fecs_errcode_r(void) { return 0x0000908c; } +static inline u32 timer_time_0_r(void) +{ + return 0x00009400; +} +static inline u32 timer_time_1_r(void) +{ + return 0x00009410; +} #endif -- cgit v1.2.2 From ad1c7b6b494b9dc3716e7126be00700f107429c4 Mon Sep 17 00:00:00 2001 From: Thomas Fleury Date: Mon, 15 Feb 2016 11:15:19 +0100 Subject: gpu: nvpgu: setup fecs_trace hal operations bug 1648908 Change-Id: I630f74f09e0a4143f5028c88634b9793ec86b279 Signed-off-by: Thomas Fleury Reviewed-on: http://git-master/r/1022730 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 1 + drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c | 53 ++++++++ drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h | 23 ++++ drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 17 +++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 + drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 184 +++++++++++++++++++++++++- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4 + drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h | 2 +- 8 files changed, 283 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index c4873257c..c29173f51 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -16,6 +16,7 @@ nvgpu-y += \ $(nvgpu-t18x)/gp10b/regops_gp10b.o \ $(nvgpu-t18x)/gp10b/cde_gp10b.o \ $(nvgpu-t18x)/gp10b/therm_gp10b.o \ + $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \ $(nvgpu-t18x)/gp10b/gp10b_sysfs.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c new file mode 100644 index 000000000..7dd200a98 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c @@ -0,0 +1,53 @@ +/* + * GP10B GPU FECS traces + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gk20a/gk20a.h" +#include "gk20a/fecs_trace_gk20a.h" +#include "gp10b/hw_ctxsw_prog_gp10b.h" +#include "gp10b/hw_gr_gp10b.h" + +#ifdef CONFIG_GK20A_CTXSW_TRACE +static int gp10b_fecs_trace_flush(struct gk20a *g) +{ + struct fecs_method_op_gk20a op = { + .mailbox = { .id = 0, .data = 0, + .clr = ~0, .ok = 0, .fail = 0}, + .method.addr = gr_fecs_method_push_adr_write_timestamp_record_v(), + .method.data = 0, + .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, + .cond.fail = GR_IS_UCODE_OP_SKIP, + }; + int err; + + gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, ""); + + err = gr_gk20a_elpg_protected_call(g, + gr_gk20a_submit_fecs_method_op(g, op, false)); + if (err) + gk20a_err(dev_from_gk20a(g), "write timestamp record failed"); + + return err; +} + +void gp10b_init_fecs_trace_ops(struct gpu_ops *ops) +{ + gk20a_init_fecs_trace_ops(ops); + ops->fecs_trace.flush = gp10b_fecs_trace_flush; +} +#else +void gp10b_init_fecs_trace_ops(struct gpu_ops *ops) +{ +} +#endif /* CONFIG_GK20A_CTXSW_TRACE */ diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h new file mode 100644 index 000000000..2a25f4f67 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h @@ -0,0 +1,23 @@ +/* + * GP10B GPU FECS traces + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _NVGPU_FECS_TRACE_GP10B_H_ +#define _NVGPU_FECS_TRACE_GP10B_H_ + +struct gpu_ops; + +int gp10b_init_fecs_trace_ops(struct gpu_ops *); + +#endif diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9eea7d436..f2308ab5e 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -902,6 +902,23 @@ static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, WARN_ON("Cannot map context"); return; } + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_magic_value_o(), 0), + ctxsw_prog_main_image_magic_value_v_value_v()); + + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(), 0)); + + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), 0)); + + gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", + gk20a_mem_rd32(ctx_ptr + + ctxsw_prog_main_image_context_timestamp_buffer_control_o(), 0)); + gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", gk20a_mem_rd32(ctx_ptr + ctxsw_prog_main_image_num_save_ops_o(), 0)); diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 37fad41ab..4f67cb097 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -21,6 +21,7 @@ #include "gk20a/gk20a.h" #include "gp10b/gr_gp10b.h" +#include "gp10b/fecs_trace_gp10b.h" #include "gp10b/mc_gp10b.h" #include "gp10b/ltc_gp10b.h" #include "gp10b/mm_gp10b.h" @@ -139,6 +140,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_mc(gops); gp10b_init_gr(gops); + gp10b_init_fecs_trace_ops(gops); gp10b_init_ltc(gops); gp10b_init_fb(gops); gp10b_init_fifo(gops); diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h index 49e92df94..eef9a96fd 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h @@ -62,6 +62,10 @@ static inline u32 ctxsw_prog_main_image_patch_count_o(void) { return 0x00000010; } +static inline u32 ctxsw_prog_main_image_context_id_o(void) +{ + return 0x000000f0; +} static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) { return 0x00000014; @@ -286,8 +290,184 @@ static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_ { return 0x2; } -static inline u32 ctxsw_prog_main_image_context_id_o(void) +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) { - return 0x000000f0; + return 0x000000ac; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) +{ + return (v & 0xffff) << 0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) +{ + return 0x000000b0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) +{ + return 0xfffffff << 0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) +{ + return 0x3 << 28; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) +{ + return 0x0; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) +{ + return 0x20000000; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) +{ + return 0x30000000; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) +{ + return 0x000000b4; +} +static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) +{ + return (v & 0xffffffff) << 0; +} +static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) +{ + return 0x00000080; +} +static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) +{ + return 0x00000020; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) +{ + return 0x00000000; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) +{ + return 0x600dbeef; +} +static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) +{ + return 0x00000008; +} +static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) +{ + return 0x00000018; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) +{ + return 0x0000001c; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) +{ + return (v & 0xffffff) << 0; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) +{ + return (r >> 0) & 0xffffff; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) +{ + return (v & 0xff) << 24; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) +{ + return 0xff << 24; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) +{ + return (r >> 24) & 0xff; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) +{ + return 0x00000001; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) +{ + return 0x1000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) +{ + return 0x00000002; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) +{ + return 0x2000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) +{ + return 0x0000000a; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) +{ + return 0xa000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) +{ + return 0x0000000b; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) +{ + return 0xb000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) +{ + return 0x0000000c; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) +{ + return 0xc000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) +{ + return 0x0000000d; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) +{ + return 0xd000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) +{ + return 0x00000003; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) +{ + return 0x3000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) +{ + return 0x00000004; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) +{ + return 0x4000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) +{ + return 0x00000005; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) +{ + return 0x5000000; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) +{ + return 0x000000ff; +} +static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) +{ + return 0xff000000; } #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 62ac13274..26578bb5b 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1094,6 +1094,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) { return 0x21; } +static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) +{ + return 0x0000003d; +} static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) { return 0x0000001a; diff --git a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h index e0fc59df1..df27154ff 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, -- cgit v1.2.2 From 456f931c4e0813c560d678605d01e75bbe1b9f23 Mon Sep 17 00:00:00 2001 From: Seshendra Gadagottu Date: Wed, 9 Dec 2015 13:54:54 -0800 Subject: gpu: nvgpu: gp10b: add emc clock request Use Bandwidth manager API to request required emc clock. Bug 1673672 Change-Id: I909213d2a69a45939247fd079b1c57ce93be6e0e Signed-off-by: Seshendra Gadagottu Reviewed-on: http://git-master/r/843777 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 56 +++++++++++++++++++++++++- 1 file changed, 54 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index e1a96e4c0..27274e955 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c @@ -29,16 +29,23 @@ #include #include "gk20a/platform_gk20a.h" #include "gk20a/gk20a.h" +#include "gk20a/gk20a_scale.h" #include "platform_tegra.h" #include "gr_gp10b.h" #include "ltc_gp10b.h" #include "hw_gr_gp10b.h" #include "hw_ltc_gp10b.h" #include "gp10b_sysfs.h" +#include #define GP10B_MAX_SUPPORTED_FREQS 11 static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; +#define TEGRA_GP10B_BW_PER_FREQ 64 +#define TEGRA_DDR4_BW_PER_FREQ 16 + +#define EMC_BW_RATIO (TEGRA_GP10B_BW_PER_FREQ / TEGRA_DDR4_BW_PER_FREQ) + static struct { char *name; unsigned long default_rate; @@ -84,6 +91,30 @@ static int gp10b_tegra_get_clocks(struct platform_device *pdev) return 0; } +static void gp10b_tegra_scale_init(struct platform_device *pdev) +{ + struct gk20a_platform *platform = gk20a_get_platform(pdev); + struct gk20a_scale_profile *profile = platform->g->scale_profile; + struct tegra_bwmgr_client *bwmgr_handle; + + bwmgr_handle = tegra_bwmgr_register(TEGRA_BWMGR_CLIENT_GPU); + if (!bwmgr_handle) + return; + + profile->private_data = (void *)bwmgr_handle; +} + +static void gp10b_tegra_scale_exit(struct platform_device *pdev) +{ + struct gk20a_platform *platform = gk20a_get_platform(pdev); + struct gk20a_scale_profile *profile = platform->g->scale_profile; + + if (profile) + tegra_bwmgr_unregister( + (struct tegra_bwmgr_client *)profile->private_data); +} + + static int gp10b_tegra_probe(struct platform_device *pdev) { struct gk20a_platform *platform = gk20a_get_platform(pdev); @@ -145,6 +176,9 @@ static int gp10b_tegra_late_probe(struct platform_device *pdev) nvhost_register_client_domain(dev_to_genpd(&pdev->dev)); /*Create GP10B specific sysfs*/ gp10b_create_sysfs(pdev); + + /* Initialise tegra specific scaling quirks */ + gp10b_tegra_scale_init(pdev); return 0; } @@ -155,6 +189,10 @@ static int gp10b_tegra_remove(struct platform_device *pdev) gr_gp10b_remove_sysfs(&pdev->dev); /*Remove GP10B specific sysfs*/ gp10b_remove_sysfs(&pdev->dev); + + /* deinitialise tegra specific scaling quirks */ + gp10b_tegra_scale_exit(pdev); + return 0; } @@ -240,7 +278,6 @@ static void gp10b_tegra_prescale(struct platform_device *pdev) gk20a_dbg_fn(""); gk20a_pmu_load_norm(g, &avg); - /* TBD - Notify EDP about changed constrains */ gk20a_dbg_fn("done"); } @@ -248,8 +285,23 @@ static void gp10b_tegra_prescale(struct platform_device *pdev) static void gp10b_tegra_postscale(struct platform_device *pdev, unsigned long freq) { - /* TBD - notify EMC about frequency change */ + struct gk20a_platform *platform = gk20a_get_platform(pdev); + struct gk20a_scale_profile *profile = platform->g->scale_profile; + struct gk20a *g = get_gk20a(pdev); + unsigned long emc_rate; + gk20a_dbg_fn(""); + if (profile) { + emc_rate = (freq * EMC_BW_RATIO * g->emc3d_ratio) / 1000; + + if (emc_rate > tegra_bwmgr_get_max_emc_rate()) + emc_rate = tegra_bwmgr_get_max_emc_rate(); + + tegra_bwmgr_set_emc( + (struct tegra_bwmgr_client *)profile->private_data, + emc_rate, TEGRA_BWMGR_SET_EMC_FLOOR); + } + gk20a_dbg_fn("done"); } static unsigned long gp10b_get_clk_rate(struct platform_device *dev) -- cgit v1.2.2 From 26fce113cc9db457fd68d579145051c5ce393155 Mon Sep 17 00:00:00 2001 From: Sami Kiminki Date: Mon, 10 Aug 2015 12:06:18 +0300 Subject: gpu: nvgpu: Determine ECC-enabled units for GP10B Determine ECC-enabled units for GP10B by reading fuses/registers. Bug 1637486 Change-Id: I6431709e3c405d6156dd96438df14d4054b48644 Signed-off-by: Sami Kiminki Signed-off-by: Adeel Raza Reviewed-on: http://git-master/r/780992 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/Makefile | 3 +- drivers/gpu/nvgpu/gp10b/gp10b.c | 110 ++++++++++++++++++++++++++++++++ drivers/gpu/nvgpu/gp10b/gp10b.h | 26 ++++++++ drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 + drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 10 ++- drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 32 ++++++++++ 6 files changed, 182 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/nvgpu/gp10b/gp10b.c create mode 100644 drivers/gpu/nvgpu/gp10b/gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index c29173f51..cd46b30df 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile @@ -17,7 +17,8 @@ nvgpu-y += \ $(nvgpu-t18x)/gp10b/cde_gp10b.o \ $(nvgpu-t18x)/gp10b/therm_gp10b.o \ $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \ - $(nvgpu-t18x)/gp10b/gp10b_sysfs.o + $(nvgpu-t18x)/gp10b/gp10b_sysfs.o \ + $(nvgpu-t18x)/gp10b/gp10b.o nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c new file mode 100644 index 000000000..a541dda35 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c @@ -0,0 +1,110 @@ +/* + * GP10B Graphics + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "gk20a/gk20a.h" +#include "hw_fuse_gp10b.h" +#include "hw_gr_gp10b.h" + +static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) +{ + u64 ecc_enabled_units = 0; + u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); + u32 opt_feature_fuses_override_disable = + gk20a_readl(g, + fuse_opt_feature_fuses_override_disable_r()); + u32 fecs_feature_override_ecc = + gk20a_readl(g, + gr_fecs_feature_override_ecc_r()); + + if (opt_feature_fuses_override_disable) { + if (opt_ecc_en) + ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED; + else + ecc_enabled_units = 0; + } else { + /* SM LRF */ + if (gr_fecs_feature_override_ecc_sm_lrf_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_sm_lrf_v( + fecs_feature_override_ecc)) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; + } + } else { + if (opt_ecc_en) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; + } + } + + /* SM SHM */ + if (gr_fecs_feature_override_ecc_sm_shm_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_sm_shm_v( + fecs_feature_override_ecc)) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; + } + } else { + if (opt_ecc_en) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; + } + } + + /* TEX */ + if (gr_fecs_feature_override_ecc_tex_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_tex_v( + fecs_feature_override_ecc)) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; + } + } else { + if (opt_ecc_en) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; + } + } + + /* LTC */ + if (gr_fecs_feature_override_ecc_ltc_override_v( + fecs_feature_override_ecc)) { + if (gr_fecs_feature_override_ecc_ltc_v( + fecs_feature_override_ecc)) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; + } + } else { + if (opt_ecc_en) { + ecc_enabled_units |= + NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; + } + } + } + + return ecc_enabled_units; +} + +int gp10b_init_gpu_characteristics(struct gk20a *g) +{ + gk20a_init_gpu_characteristics(g); + g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g); + + return 0; +} diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.h b/drivers/gpu/nvgpu/gp10b/gp10b.h new file mode 100644 index 000000000..263f3cbea --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/gp10b.h @@ -0,0 +1,26 @@ +/* + * GP10B Graphics + * + * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef GP10B_H +#define GP10B_H + +#include "gk20a/gk20a.h" + +int gp10b_init_gpu_characteristics(struct gk20a *g); + +#endif /* GP10B_H */ diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 4f67cb097..427936c72 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c @@ -41,6 +41,8 @@ #include "gm20b/clk_gm20b.h" #include +#include "gp10b.h" + #define FUSE_OPT_PRIV_SEC_EN_0 0x264 #define PRIV_SECURITY_ENABLED 0x01 @@ -153,6 +155,7 @@ int gp10b_init_hal(struct gk20a *g) gp10b_init_cde_ops(gops); gp10b_init_therm_ops(gops); gops->name = "gp10b"; + gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; c->twod_class = FERMI_TWOD_A; c->threed_class = PASCAL_A; diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index b6b687186..ae524ce54 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -126,4 +126,12 @@ static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) { return (r >> (0 + i*0)) & 0x1; } +static inline u32 fuse_opt_ecc_en_r(void) +{ + return 0x00021228; +} +static inline u32 fuse_opt_feature_fuses_override_disable_r(void) +{ + return 0x000213f0; +} #endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 26578bb5b..b3fd704b8 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h @@ -1486,6 +1486,38 @@ static inline u32 gr_fecs_feature_override_ecc_r(void) { return 0x00409658; } +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) +{ + return (r >> 3) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) +{ + return (r >> 7) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) +{ + return (r >> 11) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) +{ + return (r >> 15) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) +{ + return (r >> 0) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) +{ + return (r >> 4) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) +{ + return (r >> 8) & 0x1; +} +static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) +{ + return (r >> 12) & 0x1; +} static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) { return 0x00502420; -- cgit v1.2.2 From 4840efda393cd5928f1a8463db8b52cc586860bc Mon Sep 17 00:00:00 2001 From: Deepak Nibade Date: Mon, 21 Mar 2016 18:24:49 +0530 Subject: gpu: nvgpu: post CILP_PREEMPTION_STARTED/COMPLETE events Remove posting of events using old channel event API i.e. gk20a_channel_post_event() Also, update gk20a_channel_semaphore_wakeup() to post events when called from ce2_nonblockpipe_isr() Bug 200089620 Change-Id: I677cdab11183a649663ff9272a527c63b9994430 Signed-off-by: Deepak Nibade Reviewed-on: http://git-master/r/1112275 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom --- drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 2 +- drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 20 ++++++++++++++++---- 2 files changed, 17 insertions(+), 5 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c index b2d417b79..4cb13f3b4 100644 --- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c @@ -26,7 +26,7 @@ static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); /* wake theads waiting in this channel */ - gk20a_channel_semaphore_wakeup(g); + gk20a_channel_semaphore_wakeup(g, true); return ce2_intr_status_nonblockpipe_pending_f(); } diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f2308ab5e..1aba35f36 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c @@ -1491,6 +1491,16 @@ static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk2 gr_ctx->t18x.cilp_preempt_pending = true; g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; + if (gk20a_is_channel_marked_as_tsg(fault_ch)) { + struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; + + gk20a_tsg_event_id_post_event(tsg, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); + } else { + gk20a_channel_event_id_post_event(fault_ch, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); + } + return 0; } @@ -1684,8 +1694,6 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g, } if (gk20a_gr_sm_debugger_attached(g)) { - gk20a_err(dev_from_gk20a(g), "CILP: posting usermode event"); - if (gk20a_is_channel_marked_as_tsg(ch)) { struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; struct channel_gk20a *__ch; @@ -1693,12 +1701,16 @@ static int gr_gp10b_handle_fecs_error(struct gk20a *g, mutex_lock(&tsg->ch_list_lock); list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { gk20a_dbg_gpu_post_events(__ch); - gk20a_channel_post_event(__ch); } mutex_unlock(&tsg->ch_list_lock); + + gk20a_tsg_event_id_post_event(tsg, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); } else { gk20a_dbg_gpu_post_events(ch); - gk20a_channel_post_event(ch); + + gk20a_channel_event_id_post_event(ch, + NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); } } -- cgit v1.2.2 From a1e9c97f27bd17767d6eaa117ce0311428aedb07 Mon Sep 17 00:00:00 2001 From: Alex Van Brunt Date: Mon, 4 Apr 2016 09:19:52 -0700 Subject: gpu: nvgpu: move t18x code to kernel-nvgpu-t18x Part of moving the nvgpu driver out of the common kernel is moving the T18x part of the nvgpu driver out of kernel-t18x. So, update the Makefile to replect this change. bug 200187033 Change-Id: I11e0a73c80648ea15e9a81fe2767fe1d05ab8c2f Signed-off-by: Alex Van Brunt Reviewed-on: http://git-master/r/1119777 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom GVS: Gerrit_Virtual_Submit --- drivers/gpu/nvgpu/Makefile | 29 - drivers/gpu/nvgpu/gp10b/cde_gp10b.c | 148 - drivers/gpu/nvgpu/gp10b/cde_gp10b.h | 23 - drivers/gpu/nvgpu/gp10b/ce2_gp10b.c | 83 - drivers/gpu/nvgpu/gp10b/ce2_gp10b.h | 29 - drivers/gpu/nvgpu/gp10b/fb_gp10b.c | 112 - drivers/gpu/nvgpu/gp10b/fb_gp10b.h | 21 - drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c | 53 - drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h | 23 - drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 195 - drivers/gpu/nvgpu/gp10b/fifo_gp10b.h | 20 - drivers/gpu/nvgpu/gp10b/gp10b.c | 110 - drivers/gpu/nvgpu/gp10b/gp10b.h | 26 - drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c | 641 --- drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h | 93 - drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c | 66 - drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h | 25 - drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 73 - drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h | 28 - drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 1781 --------- drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 94 - drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h | 28 - drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 168 - drivers/gpu/nvgpu/gp10b/hal_gp10b.h | 21 - drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h | 125 - drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h | 109 - drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h | 81 - drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h | 85 - drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h | 473 --- drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 457 --- drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 669 ---- drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h | 181 - drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 137 - drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h | 1237 ------ drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 4149 -------------------- drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h | 561 --- drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 245 -- drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h | 577 --- drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h | 205 - drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h | 145 - .../gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h | 69 - drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h | 141 - drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h | 821 ---- drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h | 481 --- drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h | 409 -- drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h | 109 - drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 161 - drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 226 -- drivers/gpu/nvgpu/gp10b/ltc_gp10b.h | 19 - drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 167 - drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 31 - drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 391 -- drivers/gpu/nvgpu/gp10b/mm_gp10b.h | 22 - drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 737 ---- drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 419 -- drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 21 - drivers/gpu/nvgpu/gp10b/regops_gp10b.c | 505 --- drivers/gpu/nvgpu/gp10b/regops_gp10b.h | 24 - drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c | 150 - drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h | 30 - drivers/gpu/nvgpu/gp10b/therm_gp10b.c | 99 - drivers/gpu/nvgpu/gp10b/therm_gp10b.h | 19 - drivers/gpu/nvgpu/gr_t18x.h | 20 - drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h | 36 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c | 20 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h | 21 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c | 206 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h | 21 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 36 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c | 185 - drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h | 21 - 71 files changed, 18943 deletions(-) delete mode 100644 drivers/gpu/nvgpu/Makefile delete mode 100644 drivers/gpu/nvgpu/gp10b/cde_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/cde_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/ce2_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/fb_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/fb_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/fifo_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/fifo_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c delete mode 100644 drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gr_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/gr_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hal_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/hal_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/ltc_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/ltc_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/mc_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/mm_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/mm_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c delete mode 100644 drivers/gpu/nvgpu/gp10b/pmu_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/pmu_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/regops_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/regops_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gp10b/therm_gp10b.c delete mode 100644 drivers/gpu/nvgpu/gp10b/therm_gp10b.h delete mode 100644 drivers/gpu/nvgpu/gr_t18x.h delete mode 100644 drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c delete mode 100644 drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h (limited to 'drivers/gpu') diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile deleted file mode 100644 index cd46b30df..000000000 --- a/drivers/gpu/nvgpu/Makefile +++ /dev/null @@ -1,29 +0,0 @@ -nvgpu-t18x := ../../../../kernel-t18x/drivers/gpu/nvgpu - -nvgpu-y += \ - $(nvgpu-t18x)/gp10b/gr_gp10b.o \ - $(nvgpu-t18x)/gp10b/gr_ctx_gp10b.o \ - $(nvgpu-t18x)/gp10b/ce2_gp10b.o \ - $(nvgpu-t18x)/gp10b/mc_gp10b.o \ - $(nvgpu-t18x)/gp10b/fifo_gp10b.o \ - $(nvgpu-t18x)/gp10b/ltc_gp10b.o \ - $(nvgpu-t18x)/gp10b/mm_gp10b.o \ - $(nvgpu-t18x)/gp10b/fb_gp10b.o \ - $(nvgpu-t18x)/gp10b/pmu_gp10b.o \ - $(nvgpu-t18x)/gp10b/hal_gp10b.o \ - $(nvgpu-t18x)/gp10b/rpfb_gp10b.o \ - $(nvgpu-t18x)/gp10b/gp10b_gating_reglist.o \ - $(nvgpu-t18x)/gp10b/regops_gp10b.o \ - $(nvgpu-t18x)/gp10b/cde_gp10b.o \ - $(nvgpu-t18x)/gp10b/therm_gp10b.o \ - $(nvgpu-t18x)/gp10b/fecs_trace_gp10b.o \ - $(nvgpu-t18x)/gp10b/gp10b_sysfs.o \ - $(nvgpu-t18x)/gp10b/gp10b.o - -nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o - -nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ - $(nvgpu-t18x)/vgpu/gp10b/vgpu_hal_gp10b.o \ - $(nvgpu-t18x)/vgpu/gp10b/vgpu_gr_gp10b.o \ - $(nvgpu-t18x)/vgpu/gp10b/vgpu_mm_gp10b.o \ - $(nvgpu-t18x)/vgpu/gp10b/vgpu_fifo_gp10b.o diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c b/drivers/gpu/nvgpu/gp10b/cde_gp10b.c deleted file mode 100644 index dadec4d26..000000000 --- a/drivers/gpu/nvgpu/gp10b/cde_gp10b.c +++ /dev/null @@ -1,148 +0,0 @@ -/* - * GP10B CDE - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" -#include "cde_gp10b.h" - -enum gp10b_programs { - GP10B_PROG_HPASS = 0, - GP10B_PROG_HPASS_4K = 1, - GP10B_PROG_VPASS = 2, - GP10B_PROG_VPASS_4K = 3, - GP10B_PROG_HPASS_DEBUG = 4, - GP10B_PROG_HPASS_4K_DEBUG = 5, - GP10B_PROG_VPASS_DEBUG = 6, - GP10B_PROG_VPASS_4K_DEBUG = 7, - GP10B_PROG_PASSTHROUGH = 8, -}; - -static void gp10b_cde_get_program_numbers(struct gk20a *g, - u32 block_height_log2, - int *hprog_out, int *vprog_out) -{ - int hprog, vprog; - - if (g->cde_app.shader_parameter == 1) { - hprog = GP10B_PROG_PASSTHROUGH; - vprog = GP10B_PROG_PASSTHROUGH; - } else { - hprog = GP10B_PROG_HPASS; - vprog = GP10B_PROG_VPASS; - if (g->cde_app.shader_parameter == 2) { - hprog = GP10B_PROG_HPASS_DEBUG; - vprog = GP10B_PROG_VPASS_DEBUG; - } - if (g->mm.bypass_smmu) { - if (!g->mm.disable_bigpage) { - gk20a_warn(&g->dev->dev, - "when bypass_smmu is 1, disable_bigpage must be 1 too"); - } - hprog |= 1; - vprog |= 1; - } - } - - *hprog_out = hprog; - *vprog_out = vprog; -} - -static bool gp10b_need_scatter_buffer(struct gk20a *g) -{ - return g->mm.bypass_smmu; -} - -static u8 parity(u32 a) -{ - a ^= a>>16u; - a ^= a>>8u; - a ^= a>>4u; - a &= 0xfu; - return (0x6996u >> a) & 1u; -} - -static int gp10b_populate_scatter_buffer(struct gk20a *g, - struct sg_table *sgt, - size_t surface_size, - void *scatter_buffer_ptr, - size_t scatter_buffer_size) -{ - /* map scatter buffer to CPU VA and fill it */ - const u32 page_size_log2 = 12; - const u32 page_size = 1 << page_size_log2; - const u32 page_size_shift = page_size_log2 - 7u; - - /* 0011 1111 1111 1111 1111 1110 0100 1000 */ - const u32 getSliceMaskGP10B = 0x3ffffe48; - u8 *scatter_buffer = scatter_buffer_ptr; - - size_t i; - struct scatterlist *sg = NULL; - u8 d = 0; - size_t page = 0; - size_t pages_left; - - surface_size = round_up(surface_size, page_size); - - pages_left = surface_size >> page_size_log2; - if ((pages_left >> 3) > scatter_buffer_size) - return -ENOMEM; - - for_each_sg(sgt->sgl, sg, sgt->nents, i) { - unsigned int j; - u64 surf_pa = sg_phys(sg); - unsigned int n = (int)(sg->length >> page_size_log2); - - gk20a_dbg(gpu_dbg_cde, "surfPA=0x%llx + %d pages", surf_pa, n); - - for (j=0; j < n && pages_left > 0; j++, surf_pa += page_size) { - u32 addr = (((u32)(surf_pa>>7)) & getSliceMaskGP10B) >> page_size_shift; - u8 scatter_bit = parity(addr); - u8 bit = page & 7; - - d |= scatter_bit << bit; - if (bit == 7) { - scatter_buffer[page >> 3] = d; - d = 0; - } - - ++page; - --pages_left; - } - - if (pages_left == 0) - break; - } - - /* write the last byte in case the number of pages is not divisible by 8 */ - if ((page & 7) != 0) - scatter_buffer[page >> 3] = d; - -#if defined(GK20A_DEBUG) - if (unlikely(gpu_dbg_cde & gk20a_dbg_mask)) { - gk20a_dbg(gpu_dbg_cde, "scatterBuffer content:"); - for (i=0; i < page>>3; i++) { - gk20a_dbg(gpu_dbg_cde, " %x", scatter_buffer[i]); - } - } -#endif - return 0; -} - -void gp10b_init_cde_ops(struct gpu_ops *gops) -{ - gops->cde.get_program_numbers = gp10b_cde_get_program_numbers; - gops->cde.need_scatter_buffer = gp10b_need_scatter_buffer; - gops->cde.populate_scatter_buffer = gp10b_populate_scatter_buffer; -} diff --git a/drivers/gpu/nvgpu/gp10b/cde_gp10b.h b/drivers/gpu/nvgpu/gp10b/cde_gp10b.h deleted file mode 100644 index 52f785f1c..000000000 --- a/drivers/gpu/nvgpu/gp10b/cde_gp10b.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * GP10B CDE - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVHOST_GP10B_CDE -#define _NVHOST_GP10B_CDE - -struct gpu_ops; - -void gp10b_init_cde_ops(struct gpu_ops *gops); - -#endif diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c deleted file mode 100644 index 4cb13f3b4..000000000 --- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * GK20A Graphics Copy Engine (gr host) - * - * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ -#include "hw_ce2_gp10b.h" -#include "ce2_gp10b.h" - -static u32 ce2_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce2 non-blocking pipe interrupt\n"); - - /* wake theads waiting in this channel */ - gk20a_channel_semaphore_wakeup(g, true); - return ce2_intr_status_nonblockpipe_pending_f(); -} - -static u32 ce2_blockpipe_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce2 blocking pipe interrupt\n"); - - return ce2_intr_status_blockpipe_pending_f(); -} - -static u32 ce2_launcherr_isr(struct gk20a *g, u32 fifo_intr) -{ - gk20a_dbg(gpu_dbg_intr, "ce2 launch error interrupt\n"); - - return ce2_intr_status_launcherr_pending_f(); -} - -static void gp10b_ce2_isr(struct gk20a *g) -{ - u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); - u32 clear_intr = 0; - - gk20a_dbg(gpu_dbg_intr, "ce2 isr %08x\n", ce2_intr); - - /* clear blocking interrupts: they exibit broken behavior */ - if (ce2_intr & ce2_intr_status_blockpipe_pending_f()) - clear_intr |= ce2_blockpipe_isr(g, ce2_intr); - - if (ce2_intr & ce2_intr_status_launcherr_pending_f()) - clear_intr |= ce2_launcherr_isr(g, ce2_intr); - - gk20a_writel(g, ce2_intr_status_r(0), clear_intr); - return; -} - -static void gp10b_ce2_nonstall_isr(struct gk20a *g) -{ - u32 ce2_intr = gk20a_readl(g, ce2_intr_status_r(0)); - u32 clear_intr = 0; - - gk20a_dbg(gpu_dbg_intr, "ce2 nonstall isr %08x\n", ce2_intr); - - if (ce2_intr & ce2_intr_status_nonblockpipe_pending_f()) - clear_intr |= ce2_nonblockpipe_isr(g, ce2_intr); - - gk20a_writel(g, ce2_intr_status_r(0), clear_intr); - - return; -} -void gp10b_init_ce2(struct gpu_ops *gops) -{ - gops->ce2.isr_stall = gp10b_ce2_isr; - gops->ce2.isr_nonstall = gp10b_ce2_nonstall_isr; -} diff --git a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h deleted file mode 100644 index d432d1e0f..000000000 --- a/drivers/gpu/nvgpu/gp10b/ce2_gp10b.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * drivers/video/tegra/host/gk20a/fifo_gk20a.h - * - * GK20A graphics copy engine (gr host) - * - * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ -#ifndef __CE2_GP10B_H__ -#define __CE2_GP10B_H__ - -#include "gk20a/channel_gk20a.h" -#include "gk20a/tsg_gk20a.h" - -void gp10b_init_ce2(struct gpu_ops *gops); - -#endif /*__CE2_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c deleted file mode 100644 index 8b3b21530..000000000 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * GP10B FB - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. -* - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include - -#include "gk20a/gk20a.h" -#include "gm20b/fb_gm20b.h" -#include "gk20a/kind_gk20a.h" - -#include "hw_gmmu_gp10b.h" - -static void gp10b_init_uncompressed_kind_map(void) -{ - gm20b_init_uncompressed_kind_map(); - - gk20a_uc_kind_map[gmmu_pte_kind_z16_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms2_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms4_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms8_2cz_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_z16_ms16_2cz_v()] = - gmmu_pte_kind_z16_v(); - - gk20a_uc_kind_map[gmmu_pte_kind_c32_ms4_4cbra_v()] = - gk20a_uc_kind_map[gmmu_pte_kind_c64_ms4_4cbra_v()] = - gmmu_pte_kind_generic_16bx2_v(); -} - -static bool gp10b_kind_supported(u8 k) -{ - return (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) - || k == gmmu_pte_kind_z16_ms16_2cz_v() - || k == gmmu_pte_kind_c32_ms4_4cbra_v() - || k == gmmu_pte_kind_c64_ms4_4cbra_v(); -} - -static bool gp10b_kind_z(u8 k) -{ - return (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) || - k == gmmu_pte_kind_z16_ms16_2cz_v(); -} - -static bool gp10b_kind_compressible(u8 k) -{ - return (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) || - k == gmmu_pte_kind_z16_ms16_2cz_v() || - (k >= gmmu_pte_kind_z16_4cz_v() && - k <= gmmu_pte_kind_z16_ms16_4cz_v()) || - k == gmmu_pte_kind_c32_ms4_4cbra_v() || - k == gmmu_pte_kind_c64_ms4_4cbra_v(); -} - -static bool gp10b_kind_zbc(u8 k) -{ - return (k >= gmmu_pte_kind_z16_2cz_v() && - k <= gmmu_pte_kind_z16_ms8_2cz_v()) || - k == gmmu_pte_kind_z16_ms16_2cz_v() || - k == gmmu_pte_kind_c32_ms4_4cbra_v() || - k == gmmu_pte_kind_c64_ms4_4cbra_v(); -} - -static void gp10b_init_kind_attr(void) -{ - u16 k; - - gm20b_init_kind_attr(); - - for (k = 0; k < 256; k++) { - if (gp10b_kind_supported((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_SUPPORTED; - if (gp10b_kind_compressible((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_COMPRESSIBLE; - if (gp10b_kind_z((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_Z; - if (gp10b_kind_zbc((u8)k)) - gk20a_kind_attr[k] |= GK20A_KIND_ATTR_ZBC; - } -} - -static int gp10b_fb_compression_page_size(struct gk20a *g) -{ - return SZ_64K; -} - -static int gp10b_fb_compressible_page_size(struct gk20a *g) -{ - return SZ_4K; -} - -void gp10b_init_fb(struct gpu_ops *gops) -{ - gm20b_init_fb(gops); - gops->fb.compression_page_size = gp10b_fb_compression_page_size; - gops->fb.compressible_page_size = gp10b_fb_compressible_page_size; - - gp10b_init_uncompressed_kind_map(); - gp10b_init_kind_attr(); -} diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h deleted file mode 100644 index 76efd3319..000000000 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * GP10B FB - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_GP10B_FB -#define _NVGPU_GP10B_FB -struct gpu_ops; - -void gp10b_init_fb(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c deleted file mode 100644 index 7dd200a98..000000000 --- a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * GP10B GPU FECS traces - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" -#include "gk20a/fecs_trace_gk20a.h" -#include "gp10b/hw_ctxsw_prog_gp10b.h" -#include "gp10b/hw_gr_gp10b.h" - -#ifdef CONFIG_GK20A_CTXSW_TRACE -static int gp10b_fecs_trace_flush(struct gk20a *g) -{ - struct fecs_method_op_gk20a op = { - .mailbox = { .id = 0, .data = 0, - .clr = ~0, .ok = 0, .fail = 0}, - .method.addr = gr_fecs_method_push_adr_write_timestamp_record_v(), - .method.data = 0, - .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, - .cond.fail = GR_IS_UCODE_OP_SKIP, - }; - int err; - - gk20a_dbg(gpu_dbg_fn|gpu_dbg_ctxsw, ""); - - err = gr_gk20a_elpg_protected_call(g, - gr_gk20a_submit_fecs_method_op(g, op, false)); - if (err) - gk20a_err(dev_from_gk20a(g), "write timestamp record failed"); - - return err; -} - -void gp10b_init_fecs_trace_ops(struct gpu_ops *ops) -{ - gk20a_init_fecs_trace_ops(ops); - ops->fecs_trace.flush = gp10b_fecs_trace_flush; -} -#else -void gp10b_init_fecs_trace_ops(struct gpu_ops *ops) -{ -} -#endif /* CONFIG_GK20A_CTXSW_TRACE */ diff --git a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h b/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h deleted file mode 100644 index 2a25f4f67..000000000 --- a/drivers/gpu/nvgpu/gp10b/fecs_trace_gp10b.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * GP10B GPU FECS traces - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_FECS_TRACE_GP10B_H_ -#define _NVGPU_FECS_TRACE_GP10B_H_ - -struct gpu_ops; - -int gp10b_init_fecs_trace_ops(struct gpu_ops *); - -#endif diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c deleted file mode 100644 index ade6ff0a0..000000000 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ /dev/null @@ -1,195 +0,0 @@ -/* - * GP10B fifo - * - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include - -#include "gk20a/gk20a.h" -#include "gm20b/fifo_gm20b.h" -#include "hw_pbdma_gp10b.h" -#include "fifo_gp10b.h" -#include "hw_ccsr_gp10b.h" -#include "hw_fifo_gp10b.h" -#include "hw_ram_gp10b.h" - -static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g, - void *inst_ptr) -{ - u32 val; - - gk20a_dbg_fn(""); - - val = gk20a_mem_rd32(inst_ptr, - ram_in_page_dir_base_fault_replay_tex_w()); - val &= ~ram_in_page_dir_base_fault_replay_tex_m(); - val |= ram_in_page_dir_base_fault_replay_tex_true_f(); - gk20a_mem_wr32(inst_ptr, - ram_in_page_dir_base_fault_replay_tex_w(), val); - - val = gk20a_mem_rd32(inst_ptr, - ram_in_page_dir_base_fault_replay_gcc_w()); - val &= ~ram_in_page_dir_base_fault_replay_gcc_m(); - val |= ram_in_page_dir_base_fault_replay_gcc_true_f(); - gk20a_mem_wr32(inst_ptr, - ram_in_page_dir_base_fault_replay_gcc_w(), val); - - gk20a_dbg_fn("done"); -} - -static int channel_gp10b_commit_userd(struct channel_gk20a *c) -{ - u32 addr_lo; - u32 addr_hi; - void *inst_ptr; - - gk20a_dbg_fn(""); - - inst_ptr = c->inst_block.cpu_va; - if (!inst_ptr) - return -ENOMEM; - - addr_lo = u64_lo32(c->userd_iova >> ram_userd_base_shift_v()); - addr_hi = u64_hi32(c->userd_iova); - - gk20a_dbg_info("channel %d : set ramfc userd 0x%16llx", - c->hw_chid, (u64)c->userd_iova); - - gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_w(), - pbdma_userd_target_vid_mem_f() | - pbdma_userd_addr_f(addr_lo)); - - gk20a_mem_wr32(inst_ptr, ram_in_ramfc_w() + ram_fc_userd_hi_w(), - pbdma_userd_target_vid_mem_f() | - pbdma_userd_hi_addr_f(addr_hi)); - - return 0; -} - -static int channel_gp10b_setup_ramfc(struct channel_gk20a *c, - u64 gpfifo_base, u32 gpfifo_entries, u32 flags) -{ - void *inst_ptr; - - gk20a_dbg_fn(""); - - inst_ptr = c->inst_block.cpu_va; - if (!inst_ptr) - return -ENOMEM; - - memset(inst_ptr, 0, ram_fc_size_val_v()); - - gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_w(), - pbdma_gp_base_offset_f( - u64_lo32(gpfifo_base >> pbdma_gp_base_rsvd_s()))); - - gk20a_mem_wr32(inst_ptr, ram_fc_gp_base_hi_w(), - pbdma_gp_base_hi_offset_f(u64_hi32(gpfifo_base)) | - pbdma_gp_base_hi_limit2_f(ilog2(gpfifo_entries))); - - gk20a_mem_wr32(inst_ptr, ram_fc_signature_w(), - c->g->ops.fifo.get_pbdma_signature(c->g)); - - gk20a_mem_wr32(inst_ptr, ram_fc_formats_w(), - pbdma_formats_gp_fermi0_f() | - pbdma_formats_pb_fermi1_f() | - pbdma_formats_mp_fermi0_f()); - - gk20a_mem_wr32(inst_ptr, ram_fc_pb_header_w(), - pbdma_pb_header_priv_user_f() | - pbdma_pb_header_method_zero_f() | - pbdma_pb_header_subchannel_zero_f() | - pbdma_pb_header_level_main_f() | - pbdma_pb_header_first_true_f() | - pbdma_pb_header_type_inc_f()); - - gk20a_mem_wr32(inst_ptr, ram_fc_subdevice_w(), - pbdma_subdevice_id_f(1) | - pbdma_subdevice_status_active_f() | - pbdma_subdevice_channel_dma_enable_f()); - - gk20a_mem_wr32(inst_ptr, ram_fc_target_w(), pbdma_target_engine_sw_f()); - - gk20a_mem_wr32(inst_ptr, ram_fc_acquire_w(), - channel_gk20a_pbdma_acquire_val(c)); - - gk20a_mem_wr32(inst_ptr, ram_fc_runlist_timeslice_w(), - pbdma_runlist_timeslice_timeout_128_f() | - pbdma_runlist_timeslice_timescale_3_f() | - pbdma_runlist_timeslice_enable_true_f()); - - if ( flags & NVGPU_ALLOC_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE) - gp10b_set_pdb_fault_replay_flags(c->g, inst_ptr); - - - gk20a_mem_wr32(inst_ptr, ram_fc_chid_w(), ram_fc_chid_id_f(c->hw_chid)); - - return channel_gp10b_commit_userd(c); -} - -static u32 gp10b_fifo_get_pbdma_signature(struct gk20a *g) -{ - return g->gpu_characteristics.gpfifo_class - | pbdma_signature_sw_zero_f(); -} - -static int gp10b_fifo_resetup_ramfc(struct channel_gk20a *c) -{ - u32 new_syncpt = 0, old_syncpt; - void *inst_ptr; - u32 v; - - gk20a_dbg_fn(""); - - inst_ptr = c->inst_block.cpu_va; - - v = gk20a_mem_rd32(inst_ptr, ram_fc_allowed_syncpoints_w()); - old_syncpt = pbdma_allowed_syncpoints_0_index_v(v); - if (c->sync) - new_syncpt = c->sync->syncpt_id(c->sync); - - if (new_syncpt && new_syncpt != old_syncpt) { - /* disable channel */ - c->g->ops.fifo.disable_channel(c); - - /* preempt the channel */ - WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->hw_chid)); - - v = pbdma_allowed_syncpoints_0_valid_f(1); - - gk20a_dbg_info("Channel %d, syncpt id %d\n", - c->hw_chid, new_syncpt); - - v |= pbdma_allowed_syncpoints_0_index_f(new_syncpt); - - gk20a_mem_wr32(inst_ptr, ram_fc_allowed_syncpoints_w(), v); - } - - /* enable channel */ - gk20a_writel(c->g, ccsr_channel_r(c->hw_chid), - gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) | - ccsr_channel_enable_set_true_f()); - - gk20a_dbg_fn("done"); - - return 0; -} - -void gp10b_init_fifo(struct gpu_ops *gops) -{ - gm20b_init_fifo(gops); - gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; - gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; - gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; -} diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h deleted file mode 100644 index ad3679aa7..000000000 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * GP10B Fifo - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef FIFO_GP10B_H -#define FIFO_GP10B_H -struct gpu_ops; -void gp10b_init_fifo(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c deleted file mode 100644 index a541dda35..000000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * GP10B Graphics - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "gk20a/gk20a.h" -#include "hw_fuse_gp10b.h" -#include "hw_gr_gp10b.h" - -static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) -{ - u64 ecc_enabled_units = 0; - u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); - u32 opt_feature_fuses_override_disable = - gk20a_readl(g, - fuse_opt_feature_fuses_override_disable_r()); - u32 fecs_feature_override_ecc = - gk20a_readl(g, - gr_fecs_feature_override_ecc_r()); - - if (opt_feature_fuses_override_disable) { - if (opt_ecc_en) - ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED; - else - ecc_enabled_units = 0; - } else { - /* SM LRF */ - if (gr_fecs_feature_override_ecc_sm_lrf_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_sm_lrf_v( - fecs_feature_override_ecc)) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; - } - } else { - if (opt_ecc_en) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; - } - } - - /* SM SHM */ - if (gr_fecs_feature_override_ecc_sm_shm_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_sm_shm_v( - fecs_feature_override_ecc)) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; - } - } else { - if (opt_ecc_en) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; - } - } - - /* TEX */ - if (gr_fecs_feature_override_ecc_tex_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_tex_v( - fecs_feature_override_ecc)) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; - } - } else { - if (opt_ecc_en) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; - } - } - - /* LTC */ - if (gr_fecs_feature_override_ecc_ltc_override_v( - fecs_feature_override_ecc)) { - if (gr_fecs_feature_override_ecc_ltc_v( - fecs_feature_override_ecc)) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; - } - } else { - if (opt_ecc_en) { - ecc_enabled_units |= - NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; - } - } - } - - return ecc_enabled_units; -} - -int gp10b_init_gpu_characteristics(struct gk20a *g) -{ - gk20a_init_gpu_characteristics(g); - g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g); - - return 0; -} diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.h b/drivers/gpu/nvgpu/gp10b/gp10b.h deleted file mode 100644 index 263f3cbea..000000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * GP10B Graphics - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef GP10B_H -#define GP10B_H - -#include "gk20a/gk20a.h" - -int gp10b_init_gpu_characteristics(struct gk20a *g); - -#endif /* GP10B_H */ diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c deleted file mode 100644 index 4719b13e1..000000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.c +++ /dev/null @@ -1,641 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. - * - * This file is autogenerated. Do not edit. - */ - -#ifndef __gp10b_gating_reglist_h__ -#define __gp10b_gating_reglist_h__ - -#include -#include "gp10b_gating_reglist.h" - -struct gating_desc { - u32 addr; - u32 prod; - u32 disable; -}; -/* slcg bus */ -static const struct gating_desc gp10b_slcg_bus[] = { - {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, -}; - -/* slcg ce2 */ -static const struct gating_desc gp10b_slcg_ce2[] = { - {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, -}; - -/* slcg chiplet */ -static const struct gating_desc gp10b_slcg_chiplet[] = { - {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, - {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, -}; - -/* slcg fb */ -static const struct gating_desc gp10b_slcg_fb[] = { - {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, -}; - -/* slcg fifo */ -static const struct gating_desc gp10b_slcg_fifo[] = { - {.addr = 0x000026ac, .prod = 0x00000f00, .disable = 0x0001fffe}, -}; - -/* slcg gr */ -static const struct gating_desc gp10b_slcg_gr[] = { - {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, - {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, - {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00406004, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, - {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, - {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, - {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, - {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, - {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, - {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, - {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, - {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, - {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, - {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, - {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, - {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, - {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, - {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, - {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, - {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, - {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, - {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, - {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, - {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, - {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, - {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, - {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, - {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, - {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, -}; - -/* slcg ltc */ -static const struct gating_desc gp10b_slcg_ltc[] = { - {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, - {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, -}; - -/* slcg perf */ -static const struct gating_desc gp10b_slcg_perf[] = { - {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, - {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, -}; - -/* slcg PriRing */ -static const struct gating_desc gp10b_slcg_priring[] = { - {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, -}; - -/* slcg pwr_csb */ -static const struct gating_desc gp10b_slcg_pwr_csb[] = { - {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, - {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, - {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg pmu */ -static const struct gating_desc gp10b_slcg_pmu[] = { - {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, - {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, - {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* therm gr */ -static const struct gating_desc gp10b_slcg_therm[] = { - {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, -}; - -/* slcg Xbar */ -static const struct gating_desc gp10b_slcg_xbar[] = { - {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, - {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, -}; - -/* blcg bus */ -static const struct gating_desc gp10b_blcg_bus[] = { - {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* blcg ce */ -static const struct gating_desc gp10b_blcg_ce[] = { - {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, -}; - -/* blcg ctxsw prog */ -static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { -}; - -/* blcg fb */ -static const struct gating_desc gp10b_blcg_fb[] = { - {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, - {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00100d1c, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, -}; - -/* blcg fifo */ -static const struct gating_desc gp10b_blcg_fifo[] = { - {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg gr */ -static const struct gating_desc gp10b_blcg_gr[] = { - {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, - {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, - {.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, - {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, - {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, - {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, - {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, - {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, - {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, - {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, - {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, - {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, - {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, - {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, - {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, - {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, - {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, -}; - -/* blcg ltc */ -static const struct gating_desc gp10b_blcg_ltc[] = { - {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, - {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, -}; - -/* blcg pwr_csb */ -static const struct gating_desc gp10b_blcg_pwr_csb[] = { - {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg pmu */ -static const struct gating_desc gp10b_blcg_pmu[] = { - {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, -}; - -/* blcg Xbar */ -static const struct gating_desc gp10b_blcg_xbar[] = { - {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, - {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, -}; - -/* pg gr */ -static const struct gating_desc gp10b_pg_gr[] = { -}; - -/* inline functions */ -void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_bus[i].addr, - gp10b_slcg_bus[i].prod); - else - gk20a_writel(g, gp10b_slcg_bus[i].addr, - gp10b_slcg_bus[i].disable); - } -} - -void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_ce2[i].addr, - gp10b_slcg_ce2[i].prod); - else - gk20a_writel(g, gp10b_slcg_ce2[i].addr, - gp10b_slcg_ce2[i].disable); - } -} - -void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_chiplet[i].addr, - gp10b_slcg_chiplet[i].prod); - else - gk20a_writel(g, gp10b_slcg_chiplet[i].addr, - gp10b_slcg_chiplet[i].disable); - } -} - -void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ -} - -void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_fb[i].addr, - gp10b_slcg_fb[i].prod); - else - gk20a_writel(g, gp10b_slcg_fb[i].addr, - gp10b_slcg_fb[i].disable); - } -} - -void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_fifo[i].addr, - gp10b_slcg_fifo[i].prod); - else - gk20a_writel(g, gp10b_slcg_fifo[i].addr, - gp10b_slcg_fifo[i].disable); - } -} - -void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_gr[i].addr, - gp10b_slcg_gr[i].prod); - else - gk20a_writel(g, gp10b_slcg_gr[i].addr, - gp10b_slcg_gr[i].disable); - } -} - -void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_ltc[i].addr, - gp10b_slcg_ltc[i].prod); - else - gk20a_writel(g, gp10b_slcg_ltc[i].addr, - gp10b_slcg_ltc[i].disable); - } -} - -void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_perf[i].addr, - gp10b_slcg_perf[i].prod); - else - gk20a_writel(g, gp10b_slcg_perf[i].addr, - gp10b_slcg_perf[i].disable); - } -} - -void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_priring[i].addr, - gp10b_slcg_priring[i].prod); - else - gk20a_writel(g, gp10b_slcg_priring[i].addr, - gp10b_slcg_priring[i].disable); - } -} - -void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, - gp10b_slcg_pwr_csb[i].prod); - else - gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, - gp10b_slcg_pwr_csb[i].disable); - } -} - -void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_pmu[i].addr, - gp10b_slcg_pmu[i].prod); - else - gk20a_writel(g, gp10b_slcg_pmu[i].addr, - gp10b_slcg_pmu[i].disable); - } -} - -void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_therm[i].addr, - gp10b_slcg_therm[i].prod); - else - gk20a_writel(g, gp10b_slcg_therm[i].addr, - gp10b_slcg_therm[i].disable); - } -} - -void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_slcg_xbar[i].addr, - gp10b_slcg_xbar[i].prod); - else - gk20a_writel(g, gp10b_slcg_xbar[i].addr, - gp10b_slcg_xbar[i].disable); - } -} - -void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_bus[i].addr, - gp10b_blcg_bus[i].prod); - else - gk20a_writel(g, gp10b_blcg_bus[i].addr, - gp10b_blcg_bus[i].disable); - } -} - -void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_ce[i].addr, - gp10b_blcg_ce[i].prod); - else - gk20a_writel(g, gp10b_blcg_ce[i].addr, - gp10b_blcg_ce[i].disable); - } -} - -void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, - gp10b_blcg_ctxsw_prog[i].prod); - else - gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, - gp10b_blcg_ctxsw_prog[i].disable); - } -} - -void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_fb[i].addr, - gp10b_blcg_fb[i].prod); - else - gk20a_writel(g, gp10b_blcg_fb[i].addr, - gp10b_blcg_fb[i].disable); - } -} - -void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_fifo[i].addr, - gp10b_blcg_fifo[i].prod); - else - gk20a_writel(g, gp10b_blcg_fifo[i].addr, - gp10b_blcg_fifo[i].disable); - } -} - -void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_gr[i].addr, - gp10b_blcg_gr[i].prod); - else - gk20a_writel(g, gp10b_blcg_gr[i].addr, - gp10b_blcg_gr[i].disable); - } -} - -void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_ltc[i].addr, - gp10b_blcg_ltc[i].prod); - else - gk20a_writel(g, gp10b_blcg_ltc[i].addr, - gp10b_blcg_ltc[i].disable); - } -} - -void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, - gp10b_blcg_pwr_csb[i].prod); - else - gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, - gp10b_blcg_pwr_csb[i].disable); - } -} - -void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_pmu[i].addr, - gp10b_blcg_pmu[i].prod); - else - gk20a_writel(g, gp10b_blcg_pmu[i].addr, - gp10b_blcg_pmu[i].disable); - } -} - -void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_blcg_xbar[i].addr, - gp10b_blcg_xbar[i].prod); - else - gk20a_writel(g, gp10b_blcg_xbar[i].addr, - gp10b_blcg_xbar[i].disable); - } -} - -void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod) -{ - u32 i; - u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); - for (i = 0; i < size; i++) { - if (prod) - gk20a_writel(g, gp10b_pg_gr[i].addr, - gp10b_pg_gr[i].prod); - else - gk20a_writel(g, gp10b_pg_gr[i].addr, - gp10b_pg_gr[i].disable); - } -} - -#endif /* __gp10b_gating_reglist_h__ */ diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h b/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h deleted file mode 100644 index e4080def8..000000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b_gating_reglist.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2015-2016, NVIDIA Corporation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include "gk20a/gk20a.h" - -void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, - bool prod); - -void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, - bool prod); - -void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, - bool prod); - diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c deleted file mode 100644 index 800f39c3e..000000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.c +++ /dev/null @@ -1,66 +0,0 @@ -/* - * GP10B specific sysfs files - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include - -#include "gk20a/gk20a.h" -#include "gp10b_sysfs.h" - -#define ROOTRW (S_IRWXU|S_IRGRP|S_IROTH) - -static ssize_t ecc_enable_store(struct device *device, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct platform_device *ndev = to_platform_device(device); - struct gk20a *g = get_gk20a(ndev); - u32 ecc_mask; - u32 err = 0; - - err = sscanf(buf, "%d", &ecc_mask); - if (err == 1) { - err = g->ops.pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd - (g, ecc_mask); - if (err) - dev_err(device, "ECC override did not happen\n"); - } else - return -EINVAL; - return count; -} - -static ssize_t ecc_enable_read(struct device *device, - struct device_attribute *attr, char *buf) -{ - struct platform_device *ndev = to_platform_device(device); - struct gk20a *g = get_gk20a(ndev); - - return sprintf(buf, "ecc override =0x%x\n", - g->ops.gr.get_lrf_tex_ltc_dram_override(g)); -} - -static DEVICE_ATTR(ecc_enable, ROOTRW, ecc_enable_read, ecc_enable_store); - -void gp10b_create_sysfs(struct platform_device *dev) -{ - int error = 0; - - error |= device_create_file(&dev->dev, &dev_attr_ecc_enable); - if (error) - dev_err(&dev->dev, "Failed to create sysfs attributes!\n"); -} - -void gp10b_remove_sysfs(struct device *dev) -{ - device_remove_file(dev, &dev_attr_ecc_enable); -} diff --git a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h b/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h deleted file mode 100644 index c1d101daf..000000000 --- a/drivers/gpu/nvgpu/gp10b/gp10b_sysfs.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * GP10B specific sysfs files - * - * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _GP10B_SYSFS_H_ -#define _GP10B_SYSFS_H_ - -/*ECC Fuse*/ -#define FUSE_OPT_ECC_EN 0x358 - -void gp10b_create_sysfs(struct platform_device *dev); -void gp10b_remove_sysfs(struct device *dev); - -#endif /*_GP10B_SYSFS_H_*/ diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c deleted file mode 100644 index b29562574..000000000 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * drivers/video/tegra/host/gp10b/gr_ctx_gp10b.c - * - * GM20B Graphics Context - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include "gk20a/gk20a.h" -#include "gr_ctx_gp10b.h" - -static int gr_gp10b_get_netlist_name(int index, char *name) -{ - switch (index) { -#ifdef GP10B_NETLIST_IMAGE_FW_NAME - case NETLIST_FINAL: - sprintf(name, GP10B_NETLIST_IMAGE_FW_NAME); - return 0; -#endif -#ifdef GK20A_NETLIST_IMAGE_A - case NETLIST_SLOT_A: - sprintf(name, GK20A_NETLIST_IMAGE_A); - return 0; -#endif -#ifdef GK20A_NETLIST_IMAGE_B - case NETLIST_SLOT_B: - sprintf(name, GK20A_NETLIST_IMAGE_B); - return 0; -#endif -#ifdef GK20A_NETLIST_IMAGE_C - case NETLIST_SLOT_C: - sprintf(name, GK20A_NETLIST_IMAGE_C); - return 0; -#endif -#ifdef GK20A_NETLIST_IMAGE_D - case NETLIST_SLOT_D: - sprintf(name, GK20A_NETLIST_IMAGE_D); - return 0; -#endif - default: - return -1; - } - - return -1; -} - -static bool gr_gp10b_is_firmware_defined(void) -{ -#ifdef GP10B_NETLIST_IMAGE_FW_NAME - return true; -#else - return false; -#endif -} - -void gp10b_init_gr_ctx(struct gpu_ops *gops) { - gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; - gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; - gops->gr_ctx.use_dma_for_fw_bootstrap = true; -} diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h deleted file mode 100644 index b5c76d24d..000000000 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * GP10B Graphics Context - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef __GR_CTX_GM10B_H__ -#define __GR_CTX_GM10B_H__ - -#include "gk20a/gr_ctx_gk20a.h" - -/* production netlist, one and only one from below */ -#define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A - -void gp10b_init_gr_ctx(struct gpu_ops *gops); - -#endif /*__GR_CTX_GP10B_H__*/ diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c deleted file mode 100644 index 1aba35f36..000000000 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ /dev/null @@ -1,1781 +0,0 @@ -/* - * GP10B GPU GR - * - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ -#include -#include - -#include "gk20a/gr_gk20a.h" -#include "gk20a/semaphore_gk20a.h" -#include "gk20a/dbg_gpu_gk20a.h" - -#include "gm20b/gr_gm20b.h" /* for MAXWELL classes */ -#include "gp10b/gr_gp10b.h" -#include "hw_gr_gp10b.h" -#include "hw_fifo_gp10b.h" -#include "hw_proj_gp10b.h" -#include "hw_ctxsw_prog_gp10b.h" -#include "hw_mc_gp10b.h" -#include "gp10b_sysfs.h" -#include - -static bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num) -{ - bool valid = false; - - switch (class_num) { - case PASCAL_COMPUTE_A: - case PASCAL_A: - case PASCAL_DMA_COPY_A: - valid = true; - break; - - case MAXWELL_COMPUTE_B: - case MAXWELL_B: - case FERMI_TWOD_A: - case KEPLER_DMA_COPY_A: - case MAXWELL_DMA_COPY_A: - valid = true; - break; - - default: - break; - } - gk20a_dbg_info("class=0x%x valid=%d", class_num, valid); - return valid; -} - -static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event, struct channel_gk20a *fault_ch) -{ - int ret = 0; - u32 offset = proj_gpc_stride_v() * gpc + - proj_tpc_in_gpc_stride_v() * tpc; - u32 lrf_ecc_status, shm_ecc_status; - - gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch); - - /* Check for LRF ECC errors. */ - lrf_ecc_status = gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); - if ( (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) { - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Single bit error detected in SM LRF!"); - - g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, - 0); - } - if ( (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || - (lrf_ecc_status & - gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) { - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Double bit error detected in SM LRF!"); - - g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, - 0); - } - gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, - lrf_ecc_status); - - /* Check for SHM ECC errors. */ - shm_ecc_status = gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); - if ((shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) { - u32 ecc_stats_reg_val; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Single bit error detected in SM SHM!"); - - ecc_stats_reg_val = - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); - g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); - g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, - ecc_stats_reg_val); - } - if ( (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || - (shm_ecc_status & - gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) { - u32 ecc_stats_reg_val; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Double bit error detected in SM SHM!"); - - ecc_stats_reg_val = - gk20a_readl(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); - g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); - gk20a_writel(g, - gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, - ecc_stats_reg_val); - } - gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset, - shm_ecc_status); - - - return ret; -} - -static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, - bool *post_event) -{ - int ret = 0; - u32 offset = proj_gpc_stride_v() * gpc + - proj_tpc_in_gpc_stride_v() * tpc; - u32 esr; - u32 ecc_stats_reg_val; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); - - esr = gk20a_readl(g, - gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); - gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); - - if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Single bit error detected in TEX!"); - - /* Pipe 0 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - /* Pipe 1 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); - } - if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, - "Double bit error detected in TEX!"); - - /* Pipe 0 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - /* Pipe 1 counters */ - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); - g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, - ecc_stats_reg_val); - - ecc_stats_reg_val = gk20a_readl(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); - g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); - ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, - ecc_stats_reg_val); - - - gk20a_writel(g, - gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, - gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); - } - - gk20a_writel(g, - gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, - esr); - - return ret; -} - -static int gr_gp10b_commit_global_cb_manager(struct gk20a *g, - struct channel_gk20a *c, bool patch) -{ - struct gr_gk20a *gr = &g->gr; - struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; - struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; - u32 attrib_offset_in_chunk = 0; - u32 alpha_offset_in_chunk = 0; - u32 pd_ab_max_output; - u32 gpc_index, ppc_index; - u32 temp, temp2; - u32 cbm_cfg_size_beta, cbm_cfg_size_alpha, cbm_cfg_size_steadystate; - u32 attrib_size_in_chunk, cb_attrib_cache_size_init; - - gk20a_dbg_fn(""); - - if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { - attrib_size_in_chunk = gr->attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - cb_attrib_cache_size_init = gr->attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - } else { - attrib_size_in_chunk = gr->attrib_cb_size; - cb_attrib_cache_size_init = gr->attrib_cb_default_size; - } - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_beta_r(), - gr->attrib_cb_default_size, patch); - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_tga_constraintlogic_alpha_r(), - gr->alpha_cb_default_size, patch); - - pd_ab_max_output = (gr->alpha_cb_default_size * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v()) / - gr_pd_ab_dist_cfg1_max_output_granularity_v(); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg1_r(), - gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | - gr_pd_ab_dist_cfg1_max_batches_init_f(), patch); - - attrib_offset_in_chunk = alpha_offset_in_chunk + - gr->tpc_count * gr->alpha_cb_size; - - for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { - temp = proj_gpc_stride_v() * gpc_index; - temp2 = proj_scal_litter_num_pes_per_gpc_v() * gpc_index; - for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; - ppc_index++) { - cbm_cfg_size_beta = cb_attrib_cache_size_init * - gr->pes_tpc_count[ppc_index][gpc_index]; - cbm_cfg_size_alpha = gr->alpha_cb_default_size * - gr->pes_tpc_count[ppc_index][gpc_index]; - cbm_cfg_size_steadystate = gr->attrib_cb_default_size * - gr->pes_tpc_count[ppc_index][gpc_index]; - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size_beta, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_cb_offset_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - attrib_offset_in_chunk, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size_steadystate, - patch); - - attrib_offset_in_chunk += attrib_size_in_chunk * - gr->pes_tpc_count[ppc_index][gpc_index]; - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_alpha_cb_size_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - cbm_cfg_size_alpha, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_ppc0_cbm_alpha_cb_offset_r() + temp + - proj_ppc_in_gpc_stride_v() * ppc_index, - alpha_offset_in_chunk, patch); - - alpha_offset_in_chunk += gr->alpha_cb_size * - gr->pes_tpc_count[ppc_index][gpc_index]; - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_swdx_tc_beta_cb_size_r(ppc_index + temp2), - gr_gpcs_swdx_tc_beta_cb_size_v_f(cbm_cfg_size_steadystate), - patch); - } - } - - return 0; -} - -static void gr_gp10b_commit_global_pagepool(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - u64 addr, u32 size, bool patch) -{ - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_base_r(), - gr_scc_pagepool_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_pagepool_r(), - gr_scc_pagepool_total_pages_f(size) | - gr_scc_pagepool_valid_true_f(), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_base_r(), - gr_gpcs_gcc_pagepool_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_gcc_pagepool_r(), - gr_gpcs_gcc_pagepool_total_pages_f(size), patch); -} - -static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *color_val, u32 index) -{ - u32 i; - u32 zbc_c; - - /* update l2 table */ - g->ops.ltc.set_zbc_color_entry(g, color_val, index); - - /* update ds table */ - gk20a_writel(g, gr_ds_zbc_color_r_r(), - gr_ds_zbc_color_r_val_f(color_val->color_ds[0])); - gk20a_writel(g, gr_ds_zbc_color_g_r(), - gr_ds_zbc_color_g_val_f(color_val->color_ds[1])); - gk20a_writel(g, gr_ds_zbc_color_b_r(), - gr_ds_zbc_color_b_val_f(color_val->color_ds[2])); - gk20a_writel(g, gr_ds_zbc_color_a_r(), - gr_ds_zbc_color_a_val_f(color_val->color_ds[3])); - - gk20a_writel(g, gr_ds_zbc_color_fmt_r(), - gr_ds_zbc_color_fmt_val_f(color_val->format)); - - gk20a_writel(g, gr_ds_zbc_tbl_index_r(), - gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); - - /* trigger the write */ - gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), - gr_ds_zbc_tbl_ld_select_c_f() | - gr_ds_zbc_tbl_ld_action_write_f() | - gr_ds_zbc_tbl_ld_trigger_active_f()); - - /* update local copy */ - for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { - gr->zbc_col_tbl[index].color_l2[i] = color_val->color_l2[i]; - gr->zbc_col_tbl[index].color_ds[i] = color_val->color_ds[i]; - } - gr->zbc_col_tbl[index].format = color_val->format; - gr->zbc_col_tbl[index].ref_cnt++; - - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_r_r(index), - color_val->color_ds[0]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_g_r(index), - color_val->color_ds[1]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_b_r(index), - color_val->color_ds[2]); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), - color_val->color_ds[3]); - zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); - zbc_c &= ~(0x7f << ((index % 4) * 7)); - zbc_c |= color_val->format << ((index % 4) * 7); - gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); - - return 0; -} - -static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, - struct zbc_entry *depth_val, u32 index) -{ - u32 zbc_z; - - /* update l2 table */ - g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); - - /* update ds table */ - gk20a_writel(g, gr_ds_zbc_z_r(), - gr_ds_zbc_z_val_f(depth_val->depth)); - - gk20a_writel(g, gr_ds_zbc_z_fmt_r(), - gr_ds_zbc_z_fmt_val_f(depth_val->format)); - - gk20a_writel(g, gr_ds_zbc_tbl_index_r(), - gr_ds_zbc_tbl_index_val_f(index + GK20A_STARTOF_ZBC_TABLE)); - - /* trigger the write */ - gk20a_writel(g, gr_ds_zbc_tbl_ld_r(), - gr_ds_zbc_tbl_ld_select_z_f() | - gr_ds_zbc_tbl_ld_action_write_f() | - gr_ds_zbc_tbl_ld_trigger_active_f()); - - /* update local copy */ - gr->zbc_dep_tbl[index].depth = depth_val->depth; - gr->zbc_dep_tbl[index].format = depth_val->format; - gr->zbc_dep_tbl[index].ref_cnt++; - - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); - zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); - zbc_z &= ~(0x7f << (index % 4) * 7); - zbc_z |= depth_val->format << (index % 4) * 7; - gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); - - return 0; -} - -static u32 gr_gp10b_pagepool_default_size(struct gk20a *g) -{ - return gr_scc_pagepool_total_pages_hwmax_value_v(); -} - -static int gr_gp10b_calc_global_ctx_buffer_size(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - int size; - - gr->attrib_cb_size = gr->attrib_cb_default_size; - gr->alpha_cb_size = gr->alpha_cb_default_size; - - gr->attrib_cb_size = min(gr->attrib_cb_size, - gr_gpc0_ppc0_cbm_beta_cb_size_v_f(~0) / g->gr.tpc_count); - gr->alpha_cb_size = min(gr->alpha_cb_size, - gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(~0) / g->gr.tpc_count); - - size = gr->attrib_cb_size * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - gr->max_tpc_count; - - size += gr->alpha_cb_size * - gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() * - gr->max_tpc_count; - - size = ALIGN(size, 128); - - return size; -} - -static void gr_gp10b_set_go_idle_timeout(struct gk20a *g, u32 data) -{ - gk20a_writel(g, gr_fe_go_idle_timeout_r(), data); -} - -static void gr_gp10b_set_coalesce_buffer_size(struct gk20a *g, u32 data) -{ - u32 val; - - gk20a_dbg_fn(""); - - val = gk20a_readl(g, gr_gpcs_tc_debug0_r()); - val = set_field(val, gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(), - gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(data)); - gk20a_writel(g, gr_gpcs_tc_debug0_r(), val); - - gk20a_dbg_fn("done"); -} - -static int gr_gp10b_handle_sw_method(struct gk20a *g, u32 addr, - u32 class_num, u32 offset, u32 data) -{ - gk20a_dbg_fn(""); - - if (class_num == PASCAL_COMPUTE_A) { - switch (offset << 2) { - case NVC0C0_SET_SHADER_EXCEPTIONS: - gk20a_gr_set_shader_exceptions(g, data); - break; - default: - goto fail; - } - } - - if (class_num == PASCAL_A) { - switch (offset << 2) { - case NVC097_SET_SHADER_EXCEPTIONS: - gk20a_gr_set_shader_exceptions(g, data); - break; - case NVC097_SET_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_circular_buffer_size(g, data); - break; - case NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE: - g->ops.gr.set_alpha_circular_buffer_size(g, data); - break; - case NVC097_SET_GO_IDLE_TIMEOUT: - gr_gp10b_set_go_idle_timeout(g, data); - break; - case NVC097_SET_COALESCE_BUFFER_SIZE: - gr_gp10b_set_coalesce_buffer_size(g, data); - break; - default: - goto fail; - } - } - return 0; - -fail: - return -EINVAL; -} - -static void gr_gp10b_cb_size_default(struct gk20a *g) -{ - struct gr_gk20a *gr = &g->gr; - - if (!gr->attrib_cb_default_size) - gr->attrib_cb_default_size = 0x800; - gr->alpha_cb_default_size = - gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); -} - -static void gr_gp10b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) -{ - struct gr_gk20a *gr = &g->gr; - u32 gpc_index, ppc_index, stride, val; - u32 pd_ab_max_output; - u32 alpha_cb_size = data * 4; - - gk20a_dbg_fn(""); - - if (alpha_cb_size > gr->alpha_cb_size) - alpha_cb_size = gr->alpha_cb_size; - - gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), - (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & - ~gr_ds_tga_constraintlogic_alpha_cbsize_f(~0)) | - gr_ds_tga_constraintlogic_alpha_cbsize_f(alpha_cb_size)); - - pd_ab_max_output = alpha_cb_size * - gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v() / - gr_pd_ab_dist_cfg1_max_output_granularity_v(); - - gk20a_writel(g, gr_pd_ab_dist_cfg1_r(), - gr_pd_ab_dist_cfg1_max_output_f(pd_ab_max_output) | - gr_pd_ab_dist_cfg1_max_batches_init_f()); - - for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { - stride = proj_gpc_stride_v() * gpc_index; - - for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; - ppc_index++) { - - val = gk20a_readl(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + - stride + - proj_ppc_in_gpc_stride_v() * ppc_index); - - val = set_field(val, gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(), - gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(alpha_cb_size * - gr->pes_tpc_count[ppc_index][gpc_index])); - - gk20a_writel(g, gr_gpc0_ppc0_cbm_alpha_cb_size_r() + - stride + - proj_ppc_in_gpc_stride_v() * ppc_index, val); - } - } -} - -static void gr_gp10b_set_circular_buffer_size(struct gk20a *g, u32 data) -{ - struct gr_gk20a *gr = &g->gr; - u32 gpc_index, ppc_index, stride, val; - u32 cb_size_steady = data * 4, cb_size; - - gk20a_dbg_fn(""); - - if (cb_size_steady > gr->attrib_cb_size) - cb_size_steady = gr->attrib_cb_size; - if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != - gk20a_readl(g, - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { - cb_size = cb_size_steady + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - } else { - cb_size = cb_size_steady; - } - - gk20a_writel(g, gr_ds_tga_constraintlogic_beta_r(), - (gk20a_readl(g, gr_ds_tga_constraintlogic_beta_r()) & - ~gr_ds_tga_constraintlogic_beta_cbsize_f(~0)) | - gr_ds_tga_constraintlogic_beta_cbsize_f(cb_size_steady)); - - for (gpc_index = 0; gpc_index < gr->gpc_count; gpc_index++) { - stride = proj_gpc_stride_v() * gpc_index; - - for (ppc_index = 0; ppc_index < gr->gpc_ppc_count[gpc_index]; - ppc_index++) { - - val = gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + - stride + - proj_ppc_in_gpc_stride_v() * ppc_index); - - val = set_field(val, - gr_gpc0_ppc0_cbm_beta_cb_size_v_m(), - gr_gpc0_ppc0_cbm_beta_cb_size_v_f(cb_size * - gr->pes_tpc_count[ppc_index][gpc_index])); - - gk20a_writel(g, gr_gpc0_ppc0_cbm_beta_cb_size_r() + - stride + - proj_ppc_in_gpc_stride_v() * ppc_index, val); - - gk20a_writel(g, proj_ppc_in_gpc_stride_v() * ppc_index + - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + - stride, - gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f( - cb_size_steady)); - - val = gk20a_readl(g, gr_gpcs_swdx_tc_beta_cb_size_r( - ppc_index + gpc_index)); - - val = set_field(val, - gr_gpcs_swdx_tc_beta_cb_size_v_m(), - gr_gpcs_swdx_tc_beta_cb_size_v_f( - cb_size_steady * - gr->gpc_ppc_count[gpc_index])); - - gk20a_writel(g, gr_gpcs_swdx_tc_beta_cb_size_r( - ppc_index + gpc_index), val); - } - } -} - -static int gr_gp10b_init_ctx_state(struct gk20a *g) -{ - struct fecs_method_op_gk20a op = { - .mailbox = { .id = 0, .data = 0, - .clr = ~0, .ok = 0, .fail = 0}, - .method.data = 0, - .cond.ok = GR_IS_UCODE_OP_NOT_EQUAL, - .cond.fail = GR_IS_UCODE_OP_SKIP, - }; - int err; - - gk20a_dbg_fn(""); - - err = gr_gk20a_init_ctx_state(g); - if (err) - return err; - - if (!g->gr.t18x.ctx_vars.preempt_image_size) { - op.method.addr = - gr_fecs_method_push_adr_discover_preemption_image_size_v(); - op.mailbox.ret = &g->gr.t18x.ctx_vars.preempt_image_size; - err = gr_gk20a_submit_fecs_method_op(g, op, false); - if (err) { - gk20a_err(dev_from_gk20a(g), - "query preempt image size failed"); - return err; - } - } - - gk20a_dbg_info("preempt image size: %u", - g->gr.t18x.ctx_vars.preempt_image_size); - - gk20a_dbg_fn("done"); - - return 0; -} - -int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem) -{ - int err; - - gk20a_dbg_fn(""); - - err = gk20a_gmmu_alloc_attr(vm->mm->g, 0, size, mem); - if (err) - return err; - - mem->gpu_va = gk20a_gmmu_map(vm, - &mem->sgt, - size, - NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE, - gk20a_mem_flag_none, - false); - - if (!mem->gpu_va) { - err = -ENOMEM; - goto fail_free; - } - - return 0; - -fail_free: - gk20a_gmmu_free(vm->mm->g, mem); - return err; -} - -static int gr_gp10b_alloc_gr_ctx(struct gk20a *g, - struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, - u32 class, - u32 flags) -{ - int err; - - gk20a_dbg_fn(""); - - err = gr_gk20a_alloc_gr_ctx(g, gr_ctx, vm, class, flags); - if (err) - return err; - - (*gr_ctx)->t18x.ctx_id_valid = false; - - if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; - - if (class == PASCAL_COMPUTE_A && - g->gr.t18x.ctx_vars.force_preemption_cilp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; - - if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { - u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); - u32 betacb_size = g->gr.attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - g->gr.max_tpc_count; - attrib_cb_size = ALIGN(attrib_cb_size, 128); - - gk20a_dbg_info("gfxp context spill_size=%d", spill_size); - gk20a_dbg_info("gfxp context pagepool_size=%d", pagepool_size); - gk20a_dbg_info("gfxp context attrib_cb_size=%d", - attrib_cb_size); - err = gr_gp10b_alloc_buffer(vm, - g->gr.t18x.ctx_vars.preempt_image_size, - &(*gr_ctx)->t18x.preempt_ctxsw_buffer); - if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate preempt buffer"); - goto fail_free_gk20a_ctx; - } - - err = gr_gp10b_alloc_buffer(vm, - spill_size, - &(*gr_ctx)->t18x.spill_ctxsw_buffer); - if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate spill buffer"); - goto fail_free_preempt; - } - - err = gr_gp10b_alloc_buffer(vm, - attrib_cb_size, - &(*gr_ctx)->t18x.betacb_ctxsw_buffer); - if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate beta buffer"); - goto fail_free_spill; - } - - err = gr_gp10b_alloc_buffer(vm, - pagepool_size, - &(*gr_ctx)->t18x.pagepool_ctxsw_buffer); - if (err) { - gk20a_err(dev_from_gk20a(vm->mm->g), - "cannot allocate page pool"); - goto fail_free_betacb; - } - - (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; - } - - if (class == PASCAL_COMPUTE_A) { - if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) - (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; - else - (*gr_ctx)->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; - } - - gk20a_dbg_fn("done"); - - return err; - -fail_free_betacb: - gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.betacb_ctxsw_buffer); -fail_free_spill: - gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.spill_ctxsw_buffer); -fail_free_preempt: - gk20a_gmmu_unmap_free(vm, &(*gr_ctx)->t18x.preempt_ctxsw_buffer); -fail_free_gk20a_ctx: - gr_gk20a_free_gr_ctx(g, vm, *gr_ctx); - *gr_ctx = NULL; - - return err; -} - -static void dump_ctx_switch_stats(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) { - void *ctx_ptr = vmap(gr_ctx->mem.pages, - PAGE_ALIGN(gr_ctx->mem.size) >> PAGE_SHIFT, - 0, pgprot_writecombine(PAGE_KERNEL)); - if (!ctx_ptr) { - WARN_ON("Cannot map context"); - return; - } - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_magic_value_o : %x (expect %x)\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_magic_value_o(), 0), - ctxsw_prog_main_image_magic_value_v_value_v()); - - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi : %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(), 0)); - - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_ptr : %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), 0)); - - gk20a_err(dev_from_gk20a(g), "ctxsw_prog_main_image_context_timestamp_buffer_control : %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_context_timestamp_buffer_control_o(), 0)); - - gk20a_err(dev_from_gk20a(g), "NUM_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_save_ops_o(), 0)); - gk20a_err(dev_from_gk20a(g), "WFI_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_wfi_save_ops_o(), 0)); - gk20a_err(dev_from_gk20a(g), "CTA_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_cta_save_ops_o(), 0)); - gk20a_err(dev_from_gk20a(g), "GFXP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_gfxp_save_ops_o(), 0)); - gk20a_err(dev_from_gk20a(g), "CILP_SAVE_OPERATIONS : %d\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_num_cilp_save_ops_o(), 0)); - gk20a_err(dev_from_gk20a(g), - "image gfx preemption option (GFXP is 1) %x\n", - gk20a_mem_rd32(ctx_ptr + - ctxsw_prog_main_image_graphics_preemption_options_o(), - 0)); - vunmap(ctx_ptr); -} - -static void gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) -{ - gk20a_dbg_fn(""); - - if (!gr_ctx) - return; - - if (g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close) - dump_ctx_switch_stats(g, vm, gr_ctx); - - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); - gr_gk20a_free_gr_ctx(g, vm, gr_ctx); - gk20a_dbg_fn("done"); -} - - -static void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - void *ctx_ptr) -{ - struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; - u32 gfxp_preempt_option = - ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); - u32 cilp_preempt_option = - ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(); - int err; - - gk20a_dbg_fn(""); - - if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_GFXP) { - gk20a_dbg_info("GfxP: %x", gfxp_preempt_option); - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_graphics_preemption_options_o(), 0, - gfxp_preempt_option); - } - - if (gr_ctx->preempt_mode == NVGPU_GR_PREEMPTION_MODE_CILP) { - gk20a_dbg_info("CILP: %x", cilp_preempt_option); - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_compute_preemption_options_o(), 0, - cilp_preempt_option); - } - - if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) { - u32 addr; - u32 size; - u32 cbes_reserve; - - gk20a_mem_wr32(ctx_ptr + ctxsw_prog_main_image_full_preemption_ptr_o(), 0, - gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va >> 8); - - err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); - - addr = (u64_lo32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) >> - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.betacb_ctxsw_buffer.gpu_va) << - (32 - gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v())); - - gk20a_dbg_info("attrib cb addr : 0x%016x", addr); - g->ops.gr.commit_global_attrib_cb(g, ch_ctx, addr, true); - - addr = (u64_lo32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) >> - gr_scc_pagepool_base_addr_39_8_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.pagepool_ctxsw_buffer.gpu_va) << - (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); - size = gr_ctx->t18x.pagepool_ctxsw_buffer.size; - - if (size == g->ops.gr.pagepool_default_size(g)) - size = gr_scc_pagepool_total_pages_hwmax_v(); - - g->ops.gr.commit_global_pagepool(g, ch_ctx, addr, size, true); - - addr = (u64_lo32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) >> - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v()) | - (u64_hi32(gr_ctx->t18x.spill_ctxsw_buffer.gpu_va) << - (32 - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v())); - size = gr_ctx->t18x.spill_ctxsw_buffer.size / - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_swdx_rm_spill_buffer_addr_r(), - gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(addr), - true); - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpc0_swdx_rm_spill_buffer_size_r(), - gr_gpc0_swdx_rm_spill_buffer_size_256b_f(size), - true); - - cbes_reserve = gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(); - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_swdx_beta_cb_ctrl_r(), - gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f( - cbes_reserve), - true); - gr_gk20a_ctx_patch_write(g, ch_ctx, - gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(), - gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f( - cbes_reserve), - true); - - gr_gk20a_ctx_patch_write_end(g, ch_ctx); - } - - gk20a_dbg_fn("done"); -} - -static int gr_gp10b_dump_gr_status_regs(struct gk20a *g, - struct gk20a_debug_output *o) -{ - struct gr_gk20a *gr = &g->gr; - - gk20a_debug_output(o, "NV_PGRAPH_STATUS: 0x%x\n", - gk20a_readl(g, gr_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_STATUS1: 0x%x\n", - gk20a_readl(g, gr_status_1_r())); - gk20a_debug_output(o, "NV_PGRAPH_STATUS2: 0x%x\n", - gk20a_readl(g, gr_status_2_r())); - gk20a_debug_output(o, "NV_PGRAPH_ENGINE_STATUS: 0x%x\n", - gk20a_readl(g, gr_engine_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_STATUS : 0x%x\n", - gk20a_readl(g, gr_gpfifo_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_GRFIFO_CONTROL : 0x%x\n", - gk20a_readl(g, gr_gpfifo_ctl_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n", - gk20a_readl(g, gr_fecs_host_int_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_EXCEPTION : 0x%x\n", - gk20a_readl(g, gr_exception_r())); - gk20a_debug_output(o, "NV_PGRAPH_FECS_INTR : 0x%x\n", - gk20a_readl(g, gr_fecs_intr_r())); - gk20a_debug_output(o, "NV_PFIFO_ENGINE_STATUS(GR) : 0x%x\n", - gk20a_readl(g, fifo_engine_status_r(ENGINE_GR_GK20A))); - gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_activity_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY1: 0x%x\n", - gk20a_readl(g, gr_activity_1_r())); - gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY2: 0x%x\n", - gk20a_readl(g, gr_activity_2_r())); - gk20a_debug_output(o, "NV_PGRAPH_ACTIVITY4: 0x%x\n", - gk20a_readl(g, gr_activity_4_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_SKED_ACTIVITY: 0x%x\n", - gk20a_readl(g, gr_pri_sked_activity_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY1: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity1_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY2: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity2_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_ACTIVITY3: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); - if (gr->gpc_tpc_count[0] == 2) - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY1: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_1_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY2: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_2_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY3: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); - if (gr->gpc_tpc_count[0] == 2) - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_be0_becs_be_activity0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE1_BECS_BE_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_be1_becs_be_activity0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_BECS_BE_ACTIVITY0: 0x%x\n", - gk20a_readl(g, gr_pri_bes_becs_be_activity0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_DS_MPIPE_STATUS: 0x%x\n", - gk20a_readl(g, gr_pri_ds_mpipe_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT : 0x%x\n", - gk20a_readl(g, gr_fe_go_idle_timeout_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_GO_IDLE_INFO : 0x%x\n", - gk20a_readl(g, gr_pri_fe_go_idle_info_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TEX_M_TEX_SUBUNITS_STATUS: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", - gk20a_readl(g, gr_cwd_fs_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", - gk20a_readl(g, gr_fe_tpc_fs_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID(0): 0x%x\n", - gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); - gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", - gk20a_readl(g, gr_cwd_sm_id_r(0))); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_FE_0: 0x%x\n", - gk20a_readl(g, gr_fecs_ctxsw_status_fe_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_STATUS_1: 0x%x\n", - gk20a_readl(g, gr_fecs_ctxsw_status_1_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_GPC_0: 0x%x\n", - gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_gpc_0_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_STATUS_1: 0x%x\n", - gk20a_readl(g, gr_gpc0_gpccs_ctxsw_status_1_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CTXSW_IDLESTATE : 0x%x\n", - gk20a_readl(g, gr_fecs_ctxsw_idlestate_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_CTXSW_IDLESTATE : 0x%x\n", - gk20a_readl(g, gr_gpc0_gpccs_ctxsw_idlestate_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_CURRENT_CTX : 0x%x\n", - gk20a_readl(g, gr_fecs_current_ctx_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n", - gk20a_readl(g, gr_fecs_new_ctx_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n", - gk20a_readl(g, gr_pri_be0_crop_status1_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n", - gk20a_readl(g, gr_pri_bes_crop_status1_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS : 0x%x\n", - gk20a_readl(g, gr_pri_be0_zrop_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_ZROP_STATUS2 : 0x%x\n", - gk20a_readl(g, gr_pri_be0_zrop_status2_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS : 0x%x\n", - gk20a_readl(g, gr_pri_bes_zrop_status_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_ZROP_STATUS2 : 0x%x\n", - gk20a_readl(g, gr_pri_bes_zrop_status2_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION: 0x%x\n", - gk20a_readl(g, gr_pri_be0_becs_be_exception_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_EXCEPTION_EN: 0x%x\n", - gk20a_readl(g, gr_pri_be0_becs_be_exception_en_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_GPCCS_GPC_EXCEPTION_EN: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_exception_en_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r())); - gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n", - gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r())); - return 0; -} - -static bool gr_activity_empty_or_preempted(u32 val) -{ - while(val) { - u32 v = val & 7; - if (v != gr_activity_4_gpc0_empty_v() && - v != gr_activity_4_gpc0_preempted_v()) - return false; - val >>= 3; - } - - return true; -} - -static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long end_jiffies, - u32 expect_delay) -{ - u32 delay = expect_delay; - bool gr_enabled; - bool ctxsw_active; - bool gr_busy; - u32 gr_status; - u32 activity0, activity1, activity2, activity4; - - gk20a_dbg_fn(""); - - do { - /* fmodel: host gets fifo_engine_status(gr) from gr - only when gr_status is read */ - gr_status = gk20a_readl(g, gr_status_r()); - - gr_enabled = gk20a_readl(g, mc_enable_r()) & - mc_enable_pgraph_enabled_f(); - - ctxsw_active = gr_status & 1<<7; - - activity0 = gk20a_readl(g, gr_activity_0_r()); - activity1 = gk20a_readl(g, gr_activity_1_r()); - activity2 = gk20a_readl(g, gr_activity_2_r()); - activity4 = gk20a_readl(g, gr_activity_4_r()); - - gr_busy = !(gr_activity_empty_or_preempted(activity0) && - gr_activity_empty_or_preempted(activity1) && - activity2 == 0 && - gr_activity_empty_or_preempted(activity4)); - - if (!gr_enabled || (!gr_busy && !ctxsw_active)) { - gk20a_dbg_fn("done"); - return 0; - } - - usleep_range(delay, delay * 2); - delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); - - } while (time_before(jiffies, end_jiffies) - || !tegra_platform_is_silicon()); - - gk20a_err(dev_from_gk20a(g), - "timeout, ctxsw busy : %d, gr busy : %d, %08x, %08x, %08x, %08x", - ctxsw_active, gr_busy, activity0, activity1, activity2, activity4); - - return -EAGAIN; -} - -static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - u64 addr, bool patch) -{ - struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx; - int attrBufferSize; - - if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va) - attrBufferSize = gr_ctx->t18x.betacb_ctxsw_buffer.size; - else - attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); - - attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); - - gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(), - gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) | - gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(), - gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(), - gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) | - gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch); -} - -static void gr_gp10b_commit_global_bundle_cb(struct gk20a *g, - struct channel_ctx_gk20a *ch_ctx, - u64 addr, u64 size, bool patch) -{ - u32 data; - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_base_r(), - gr_scc_bundle_cb_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_scc_bundle_cb_size_r(), - gr_scc_bundle_cb_size_div_256b_f(size) | - gr_scc_bundle_cb_size_valid_true_f(), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_base_r(), - gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(addr), patch); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_swdx_bundle_cb_size_r(), - gr_gpcs_swdx_bundle_cb_size_div_256b_f(size) | - gr_gpcs_swdx_bundle_cb_size_valid_true_f(), patch); - - /* data for state_limit */ - data = (g->gr.bundle_cb_default_size * - gr_scc_bundle_cb_size_div_256b_byte_granularity_v()) / - gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(); - - data = min_t(u32, data, g->gr.min_gpm_fifo_depth); - - gk20a_dbg_info("bundle cb token limit : %d, state limit : %d", - g->gr.bundle_cb_token_limit, data); - - gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg2_r(), - gr_pd_ab_dist_cfg2_token_limit_f(g->gr.bundle_cb_token_limit) | - gr_pd_ab_dist_cfg2_state_limit_f(data), patch); -} - -static int gr_gp10b_init_fs_state(struct gk20a *g) -{ - u32 data; - - data = gk20a_readl(g, gr_gpcs_tpcs_sm_texio_control_r()); - data = set_field(data, gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(), - gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); - gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); - - data = gk20a_readl(g, gr_gpcs_tpcs_sm_disp_ctrl_r()); - data = set_field(data, gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(), - gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f()); - gk20a_writel(g, gr_gpcs_tpcs_sm_disp_ctrl_r(), data); - - return gr_gm20b_ctx_state_floorsweep(g); -} - -static void gr_gp10b_init_cyclestats(struct gk20a *g) -{ -#if defined(CONFIG_GK20A_CYCLE_STATS) - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; - g->gpu_characteristics.flags |= - NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; -#else - (void)g; -#endif -} - -static void gr_gp10b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) -{ - tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); - tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); - - if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) - tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); - else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) - tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); - else - tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); -} - -static void gr_gp10b_get_access_map(struct gk20a *g, - u32 **whitelist, int *num_entries) -{ - static u32 wl_addr_gp10b[] = { - /* this list must be sorted (low to high) */ - 0x404468, /* gr_pri_mme_max_instructions */ - 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ - 0x418800, /* gr_pri_gpcs_setup_debug */ - 0x418e00, /* gr_pri_gpcs_swdx_config */ - 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ - 0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ - 0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ - 0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ - 0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ - 0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr */ - 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ - 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ - 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ - 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ - 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ - }; - - *whitelist = wl_addr_gp10b; - *num_entries = ARRAY_SIZE(wl_addr_gp10b); -} - -static int gr_gp10b_disable_channel_or_tsg(struct gk20a *g, struct channel_gk20a *fault_ch) -{ - int ret = 0; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - ret = gk20a_disable_channel_tsg(g, fault_ch); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to disable channel/TSG!\n"); - return ret; - } - - ret = g->ops.fifo.update_runlist(g, 0, ~0, true, false); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to restart runlist 0!"); - return ret; - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: restarted runlist"); - - if (gk20a_is_channel_marked_as_tsg(fault_ch)) - gk20a_fifo_issue_preempt(g, fault_ch->tsgid, true); - else - gk20a_fifo_issue_preempt(g, fault_ch->hw_chid, false); - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, "CILP: preempted the channel/tsg"); - - return ret; -} - -static int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g, struct channel_gk20a *fault_ch) -{ - int ret; - struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - if (!gr_ctx) - return -EINVAL; - - if (gr_ctx->t18x.cilp_preempt_pending) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP is already pending for chid %d", - fault_ch->hw_chid); - return 0; - } - - /* get ctx_id from the ucode image */ - if (!gr_ctx->t18x.ctx_id_valid) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: looking up ctx id"); - ret = gr_gk20a_get_ctx_id(g, fault_ch, &gr_ctx->t18x.ctx_id); - if (ret) { - gk20a_err(dev_from_gk20a(g), "CILP: error looking up ctx id!\n"); - return ret; - } - gr_ctx->t18x.ctx_id_valid = true; - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: ctx id is 0x%x", gr_ctx->t18x.ctx_id); - - /* send ucode method to set ctxsw interrupt */ - ret = gr_gk20a_submit_fecs_sideband_method_op(g, - (struct fecs_method_op_gk20a) { - .method.data = gr_ctx->t18x.ctx_id, - .method.addr = - gr_fecs_method_push_adr_configure_interrupt_completion_option_v(), - .mailbox = { - .id = 1 /* sideband */, .data = 0, - .clr = ~0, .ret = NULL, - .ok = gr_fecs_ctxsw_mailbox_value_pass_v(), - .fail = 0}, - .cond.ok = GR_IS_UCODE_OP_EQUAL, - .cond.fail = GR_IS_UCODE_OP_SKIP}); - - if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to enable ctxsw interrupt!"); - return ret; - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: enabled ctxsw completion interrupt"); - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: disabling channel %d", - fault_ch->hw_chid); - - ret = gr_gp10b_disable_channel_or_tsg(g, fault_ch); - if (ret) { - gk20a_err(dev_from_gk20a(g), - "CILP: failed to disable channel!!"); - return ret; - } - - /* set cilp_preempt_pending = true and record the channel */ - gr_ctx->t18x.cilp_preempt_pending = true; - g->gr.t18x.cilp_preempt_pending_chid = fault_ch->hw_chid; - - if (gk20a_is_channel_marked_as_tsg(fault_ch)) { - struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid]; - - gk20a_tsg_event_id_post_event(tsg, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); - } else { - gk20a_channel_event_id_post_event(fault_ch, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_STARTED); - } - - return 0; -} - -static int gr_gp10b_clear_cilp_preempt_pending(struct gk20a *g, - struct channel_gk20a *fault_ch) -{ - struct gr_ctx_desc *gr_ctx = fault_ch->ch_ctx.gr_ctx; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - if (!gr_ctx) - return -EINVAL; - - /* The ucode is self-clearing, so all we need to do here is - to clear cilp_preempt_pending. */ - if (!gr_ctx->t18x.cilp_preempt_pending) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP is already cleared for chid %d\n", - fault_ch->hw_chid); - return 0; - } - - gr_ctx->t18x.cilp_preempt_pending = false; - g->gr.t18x.cilp_preempt_pending_chid = -1; - - return 0; -} - -/* @brief pre-process work on the SM exceptions to determine if we clear them or not. - * - * On Pascal, if we are in CILP preemtion mode, preempt the channel and handle errors with special processing - */ -static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, - u32 gpc, u32 tpc, u32 global_esr, u32 warp_esr, - bool sm_debugger_attached, struct channel_gk20a *fault_ch, - bool *early_exit, bool *ignore_debugger) -{ - int ret; - bool cilp_enabled = (fault_ch->ch_ctx.gr_ctx->preempt_mode == - NVGPU_GR_PREEMPTION_MODE_CILP) ; - u32 global_mask = 0, dbgr_control0, global_esr_copy; - u32 offset = proj_gpc_stride_v() * gpc + - proj_tpc_in_gpc_stride_v() * tpc; - - *early_exit = false; - *ignore_debugger = false; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "SM Exception received on gpc %d tpc %d = %u\n", - gpc, tpc, global_esr); - - if (cilp_enabled && sm_debugger_attached) { - if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) - gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, - gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); - - if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) - gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, - gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); - - global_mask = gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f() | - gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f() | - gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() | - gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f() | - gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f() | - gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(); - - if (warp_esr != 0 || (global_esr & global_mask) != 0) { - *ignore_debugger = true; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: starting wait for LOCKED_DOWN on gpc %d tpc %d\n", - gpc, tpc); - - if (gk20a_dbg_gpu_broadcast_stop_trigger(fault_ch)) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: Broadcasting STOP_TRIGGER from gpc %d tpc %d\n", - gpc, tpc); - gk20a_suspend_all_sms(g, global_mask, false); - - gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch); - } else { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: STOP_TRIGGER from gpc %d tpc %d\n", - gpc, tpc); - gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); - } - - /* reset the HWW errors after locking down */ - global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); - gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: HWWs cleared for gpc %d tpc %d\n", - gpc, tpc); - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: Setting CILP preempt pending\n"); - ret = gr_gp10b_set_cilp_preempt_pending(g, fault_ch); - if (ret) { - gk20a_err(dev_from_gk20a(g), "CILP: error while setting CILP preempt pending!\n"); - return ret; - } - - dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); - if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", - gpc, tpc); - dbgr_control0 = set_field(dbgr_control0, - gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), - gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); - gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); - } - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, - "CILP: resume for gpc %d tpc %d\n", - gpc, tpc); - gk20a_resume_single_sm(g, gpc, tpc); - - *ignore_debugger = true; - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); - } - - *early_exit = true; - } - return 0; -} - -static int gr_gp10b_get_cilp_preempt_pending_chid(struct gk20a *g, int *__chid) -{ - struct gr_ctx_desc *gr_ctx; - struct channel_gk20a *ch; - int chid; - int ret = -EINVAL; - - chid = g->gr.t18x.cilp_preempt_pending_chid; - - ch = gk20a_channel_get(gk20a_fifo_channel_from_hw_chid(g, chid)); - if (!ch) - return ret; - - gr_ctx = ch->ch_ctx.gr_ctx; - - if (gr_ctx->t18x.cilp_preempt_pending) { - *__chid = chid; - ret = 0; - } - - gk20a_channel_put(ch); - - return ret; -} - -static int gr_gp10b_handle_fecs_error(struct gk20a *g, - struct channel_gk20a *__ch, - struct gr_gk20a_isr_data *isr_data) -{ - u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); - struct channel_gk20a *ch; - int chid = -1; - int ret = 0; - - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); - - /* - * INTR1 (bit 1 of the HOST_INT_STATUS_CTXSW_INTR) - * indicates that a CILP ctxsw save has finished - */ - if (gr_fecs_intr & gr_fecs_host_int_status_ctxsw_intr_f(2)) { - gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, - "CILP: ctxsw save completed!\n"); - - /* now clear the interrupt */ - gk20a_writel(g, gr_fecs_host_int_clear_r(), - gr_fecs_host_int_clear_ctxsw_intr1_clear_f()); - - ret = gr_gp10b_get_cilp_preempt_pending_chid(g, &chid); - if (ret) - goto clean_up; - - ch = gk20a_channel_get( - gk20a_fifo_channel_from_hw_chid(g, chid)); - if (!ch) - goto clean_up; - - - /* set preempt_pending to false */ - ret = gr_gp10b_clear_cilp_preempt_pending(g, ch); - if (ret) { - gk20a_err(dev_from_gk20a(g), "CILP: error while unsetting CILP preempt pending!\n"); - gk20a_channel_put(ch); - goto clean_up; - } - - if (gk20a_gr_sm_debugger_attached(g)) { - if (gk20a_is_channel_marked_as_tsg(ch)) { - struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid]; - struct channel_gk20a *__ch; - - mutex_lock(&tsg->ch_list_lock); - list_for_each_entry(__ch, &tsg->ch_list, ch_entry) { - gk20a_dbg_gpu_post_events(__ch); - } - mutex_unlock(&tsg->ch_list_lock); - - gk20a_tsg_event_id_post_event(tsg, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); - } else { - gk20a_dbg_gpu_post_events(ch); - - gk20a_channel_event_id_post_event(ch, - NVGPU_IOCTL_CHANNEL_EVENT_ID_CILP_PREEMPTION_COMPLETE); - } - } - - gk20a_channel_put(ch); - } - -clean_up: - /* handle any remaining interrupts */ - return gk20a_gr_handle_fecs_error(g, __ch, isr_data); -} - -static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) -{ - if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) - hww_warp_esr = set_field(hww_warp_esr, - gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), - gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); - - return hww_warp_esr; -} - -static u32 get_ecc_override_val(struct gk20a *g) -{ - if (tegra_fuse_readl(FUSE_OPT_ECC_EN)) - return gk20a_readl(g, gr_fecs_feature_override_ecc_r()); - else - return 0; -} - -void gp10b_init_gr(struct gpu_ops *gops) -{ - gm20b_init_gr(gops); - gops->gr.init_fs_state = gr_gp10b_init_fs_state; - gops->gr.is_valid_class = gr_gp10b_is_valid_class; - gops->gr.commit_global_cb_manager = gr_gp10b_commit_global_cb_manager; - gops->gr.commit_global_pagepool = gr_gp10b_commit_global_pagepool; - gops->gr.add_zbc_color = gr_gp10b_add_zbc_color; - gops->gr.add_zbc_depth = gr_gp10b_add_zbc_depth; - gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size; - gops->gr.calc_global_ctx_buffer_size = - gr_gp10b_calc_global_ctx_buffer_size; - gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb; - gops->gr.commit_global_bundle_cb = gr_gp10b_commit_global_bundle_cb; - gops->gr.handle_sw_method = gr_gp10b_handle_sw_method; - gops->gr.cb_size_default = gr_gp10b_cb_size_default; - gops->gr.set_alpha_circular_buffer_size = - gr_gp10b_set_alpha_circular_buffer_size; - gops->gr.set_circular_buffer_size = - gr_gp10b_set_circular_buffer_size; - gops->gr.init_ctx_state = gr_gp10b_init_ctx_state; - gops->gr.alloc_gr_ctx = gr_gp10b_alloc_gr_ctx; - gops->gr.free_gr_ctx = gr_gp10b_free_gr_ctx; - gops->gr.update_ctxsw_preemption_mode = - gr_gp10b_update_ctxsw_preemption_mode; - gops->gr.dump_gr_regs = gr_gp10b_dump_gr_status_regs; - gops->gr.wait_empty = gr_gp10b_wait_empty; - gops->gr.init_cyclestats = gr_gp10b_init_cyclestats; - gops->gr.set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask; - gops->gr.get_access_map = gr_gp10b_get_access_map; - gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; - gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; - gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr; - gops->gr.pre_process_sm_exception = - gr_gp10b_pre_process_sm_exception; - gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; - gops->gr.create_gr_sysfs = gr_gp10b_create_sysfs; - gops->gr.get_lrf_tex_ltc_dram_override = get_ecc_override_val; -} diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h deleted file mode 100644 index bd4b5879a..000000000 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * GM20B GPU GR - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_GR_GP10B_H_ -#define _NVGPU_GR_GP10B_H_ - -struct gpu_ops; - -enum { - PASCAL_CHANNEL_GPFIFO_A = 0xC06F, - PASCAL_A = 0xC097, - PASCAL_COMPUTE_A = 0xC0C0, - PASCAL_DMA_COPY_A = 0xC0B5, -}; - -#define NVC097_SET_GO_IDLE_TIMEOUT 0x022c -#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE 0x02dc -#define NVC097_SET_COALESCE_BUFFER_SIZE 0x1028 -#define NVC097_SET_CIRCULAR_BUFFER_SIZE 0x1280 -#define NVC097_SET_SHADER_EXCEPTIONS 0x1528 -#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 - -void gp10b_init_gr(struct gpu_ops *ops); -int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size, - struct mem_desc *mem); -void gr_gp10b_create_sysfs(struct platform_device *dev); - -struct ecc_stat { - char **names; - u32 *counters; - struct hlist_node hash_node; -}; - -struct gr_t18x { - struct { - u32 preempt_image_size; - u32 force_preemption_gfxp; - u32 force_preemption_cilp; - u32 dump_ctxsw_stats_on_channel_close; - struct dentry *debugfs_force_preemption_cilp; - struct dentry *debugfs_force_preemption_gfxp; - struct dentry *debugfs_dump_ctxsw_stats; - } ctx_vars; - - struct { - struct ecc_stat sm_lrf_single_err_count; - struct ecc_stat sm_lrf_double_err_count; - - struct ecc_stat sm_shm_sec_count; - struct ecc_stat sm_shm_sed_count; - struct ecc_stat sm_shm_ded_count; - - struct ecc_stat tex_total_sec_pipe0_count; - struct ecc_stat tex_total_ded_pipe0_count; - struct ecc_stat tex_unique_sec_pipe0_count; - struct ecc_stat tex_unique_ded_pipe0_count; - struct ecc_stat tex_total_sec_pipe1_count; - struct ecc_stat tex_total_ded_pipe1_count; - struct ecc_stat tex_unique_sec_pipe1_count; - struct ecc_stat tex_unique_ded_pipe1_count; - - struct ecc_stat l2_sec_count; - struct ecc_stat l2_ded_count; - } ecc_stats; - - int cilp_preempt_pending_chid; -}; - -struct gr_ctx_desc_t18x { - struct mem_desc preempt_ctxsw_buffer; - struct mem_desc spill_ctxsw_buffer; - struct mem_desc betacb_ctxsw_buffer; - struct mem_desc pagepool_ctxsw_buffer; - u32 ctx_id; - bool ctx_id_valid; - bool cilp_preempt_pending; -}; - -#define NVGPU_GR_PREEMPTION_MODE_GFXP 1 -#define NVGPU_GR_PREEMPTION_MODE_CILP 3 - -#endif diff --git a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h deleted file mode 100644 index c32770178..000000000 --- a/drivers/gpu/nvgpu/gp10b/gr_ops_gp10b.h +++ /dev/null @@ -1,28 +0,0 @@ -/* - * GP10B GPU graphics ops - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _GR_OPS_GP10B_H_ -#define _GR_OPS_GP10B_H_ - -#include "gr_ops.h" - -#define __gr_gp10b_op(X) gr_gp10b_ ## X -#define __set_gr_gp10b_op(X) . X = gr_gp10b_ ## X - -bool __gr_gp10b_op(is_valid_class)(struct gk20a *, u32); -int __gr_gp10b_op(alloc_obj_ctx)(struct channel_gk20a *, struct nvgpu_alloc_obj_ctx_args *); - - -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c deleted file mode 100644 index 427936c72..000000000 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * GP10B Tegra HAL interface - * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include - -#include - -#include "gk20a/gk20a.h" - -#include "gp10b/gr_gp10b.h" -#include "gp10b/fecs_trace_gp10b.h" -#include "gp10b/mc_gp10b.h" -#include "gp10b/ltc_gp10b.h" -#include "gp10b/mm_gp10b.h" -#include "gp10b/ce2_gp10b.h" -#include "gp10b/fb_gp10b.h" -#include "gp10b/pmu_gp10b.h" -#include "gp10b/gr_ctx_gp10b.h" -#include "gp10b/fifo_gp10b.h" -#include "gp10b/gp10b_gating_reglist.h" -#include "gp10b/regops_gp10b.h" -#include "gp10b/cde_gp10b.h" -#include "gp10b/therm_gp10b.h" - -#include "gm20b/gr_gm20b.h" -#include "gm20b/fifo_gm20b.h" -#include "gm20b/pmu_gm20b.h" -#include "gm20b/clk_gm20b.h" -#include - -#include "gp10b.h" - -#define FUSE_OPT_PRIV_SEC_EN_0 0x264 -#define PRIV_SECURITY_ENABLED 0x01 - -static struct gpu_ops gp10b_ops = { - .clock_gating = { - .slcg_bus_load_gating_prod = - gp10b_slcg_bus_load_gating_prod, - .slcg_ce2_load_gating_prod = - gp10b_slcg_ce2_load_gating_prod, - .slcg_chiplet_load_gating_prod = - gp10b_slcg_chiplet_load_gating_prod, - .slcg_ctxsw_firmware_load_gating_prod = - gp10b_slcg_ctxsw_firmware_load_gating_prod, - .slcg_fb_load_gating_prod = - gp10b_slcg_fb_load_gating_prod, - .slcg_fifo_load_gating_prod = - gp10b_slcg_fifo_load_gating_prod, - .slcg_gr_load_gating_prod = - gr_gp10b_slcg_gr_load_gating_prod, - .slcg_ltc_load_gating_prod = - ltc_gp10b_slcg_ltc_load_gating_prod, - .slcg_perf_load_gating_prod = - gp10b_slcg_perf_load_gating_prod, - .slcg_priring_load_gating_prod = - gp10b_slcg_priring_load_gating_prod, - .slcg_pmu_load_gating_prod = - gp10b_slcg_pmu_load_gating_prod, - .slcg_therm_load_gating_prod = - gp10b_slcg_therm_load_gating_prod, - .slcg_xbar_load_gating_prod = - gp10b_slcg_xbar_load_gating_prod, - .blcg_bus_load_gating_prod = - gp10b_blcg_bus_load_gating_prod, - .blcg_ce_load_gating_prod = - gp10b_blcg_ce_load_gating_prod, - .blcg_ctxsw_firmware_load_gating_prod = - gp10b_blcg_ctxsw_firmware_load_gating_prod, - .blcg_fb_load_gating_prod = - gp10b_blcg_fb_load_gating_prod, - .blcg_fifo_load_gating_prod = - gp10b_blcg_fifo_load_gating_prod, - .blcg_gr_load_gating_prod = - gp10b_blcg_gr_load_gating_prod, - .blcg_ltc_load_gating_prod = - gp10b_blcg_ltc_load_gating_prod, - .blcg_pwr_csb_load_gating_prod = - gp10b_blcg_pwr_csb_load_gating_prod, - .blcg_pmu_load_gating_prod = - gp10b_blcg_pmu_load_gating_prod, - .blcg_xbar_load_gating_prod = - gp10b_blcg_xbar_load_gating_prod, - .pg_gr_load_gating_prod = - gr_gp10b_pg_gr_load_gating_prod, - } -}; - -int gp10b_init_hal(struct gk20a *g) -{ - struct gpu_ops *gops = &g->ops; - struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; - - *gops = gp10b_ops; - -#ifdef CONFIG_TEGRA_ACR - if (tegra_platform_is_linsim()) { - gops->privsecurity = 0; - gops->securegpccs = 0; - } else { - if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & - PRIV_SECURITY_ENABLED) { - gops->privsecurity = 1; - gops->securegpccs =1; - } else { - gk20a_dbg_info("priv security is disabled in HW"); - gops->privsecurity = 0; - gops->securegpccs = 0; - } - } -#else - if (tegra_platform_is_linsim()) { - gk20a_dbg_info("running ASIM with PRIV security disabled"); - gops->privsecurity = 0; - gops->securegpccs = 0; - } else { - if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_EN_0) & - PRIV_SECURITY_ENABLED) { - gk20a_dbg_info("priv security is not supported but enabled"); - gops->privsecurity = 1; - gops->securegpccs =1; - return -EPERM; - } else { - gops->privsecurity = 0; - gops->securegpccs = 0; - } - } -#endif - - gp10b_init_mc(gops); - gp10b_init_gr(gops); - gp10b_init_fecs_trace_ops(gops); - gp10b_init_ltc(gops); - gp10b_init_fb(gops); - gp10b_init_fifo(gops); - gp10b_init_ce2(gops); - gp10b_init_gr_ctx(gops); - gp10b_init_mm(gops); - gp10b_init_pmu_ops(gops); - gk20a_init_debug_ops(gops); - gp10b_init_regops(gops); - gp10b_init_cde_ops(gops); - gp10b_init_therm_ops(gops); - gops->name = "gp10b"; - gops->chip_init_gpu_characteristics = gp10b_init_gpu_characteristics; - - c->twod_class = FERMI_TWOD_A; - c->threed_class = PASCAL_A; - c->compute_class = PASCAL_COMPUTE_A; - c->gpfifo_class = PASCAL_CHANNEL_GPFIFO_A; - c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B; - c->dma_copy_class = PASCAL_DMA_COPY_A; - - return 0; -} diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h b/drivers/gpu/nvgpu/gp10b/hal_gp10b.h deleted file mode 100644 index 0b464d07c..000000000 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * GP10B Tegra HAL interface - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef _NVGPU_HAL_GP10B_H -#define _NVGPU_HAL_GP10B_H -struct gk20a; - -int gp10b_init_hal(struct gk20a *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h deleted file mode 100644 index c04b01c1f..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_bus_gp10b.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_bus_gp10b_h_ -#define _hw_bus_gp10b_h_ - -static inline u32 bus_bar1_block_r(void) -{ - return 0x00001704; -} -static inline u32 bus_bar1_block_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 bus_bar1_block_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 bus_bar1_block_mode_virtual_f(void) -{ - return 0x80000000; -} -static inline u32 bus_bar2_block_r(void) -{ - return 0x00001714; -} -static inline u32 bus_bar2_block_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 bus_bar2_block_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 bus_bar2_block_mode_virtual_f(void) -{ - return 0x80000000; -} -static inline u32 bus_bar1_block_ptr_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 bus_bar2_block_ptr_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 bus_intr_0_r(void) -{ - return 0x00001100; -} -static inline u32 bus_intr_0_pri_squash_m(void) -{ - return 0x1 << 1; -} -static inline u32 bus_intr_0_pri_fecserr_m(void) -{ - return 0x1 << 2; -} -static inline u32 bus_intr_0_pri_timeout_m(void) -{ - return 0x1 << 3; -} -static inline u32 bus_intr_en_0_r(void) -{ - return 0x00001140; -} -static inline u32 bus_intr_en_0_pri_squash_m(void) -{ - return 0x1 << 1; -} -static inline u32 bus_intr_en_0_pri_fecserr_m(void) -{ - return 0x1 << 2; -} -static inline u32 bus_intr_en_0_pri_timeout_m(void) -{ - return 0x1 << 3; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h deleted file mode 100644 index cd5265b33..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_ccsr_gp10b.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ccsr_gp10b_h_ -#define _hw_ccsr_gp10b_h_ - -static inline u32 ccsr_channel_inst_r(u32 i) -{ - return 0x00800000 + i*8; -} -static inline u32 ccsr_channel_inst__size_1_v(void) -{ - return 0x00000200; -} -static inline u32 ccsr_channel_inst_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 ccsr_channel_inst_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 ccsr_channel_inst_bind_false_f(void) -{ - return 0x0; -} -static inline u32 ccsr_channel_inst_bind_true_f(void) -{ - return 0x80000000; -} -static inline u32 ccsr_channel_r(u32 i) -{ - return 0x00800004 + i*8; -} -static inline u32 ccsr_channel__size_1_v(void) -{ - return 0x00000200; -} -static inline u32 ccsr_channel_enable_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ccsr_channel_enable_set_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 ccsr_channel_enable_set_true_f(void) -{ - return 0x400; -} -static inline u32 ccsr_channel_enable_clr_true_f(void) -{ - return 0x800; -} -static inline u32 ccsr_channel_status_v(u32 r) -{ - return (r >> 24) & 0xf; -} -static inline u32 ccsr_channel_busy_v(u32 r) -{ - return (r >> 28) & 0x1; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h deleted file mode 100644 index b0c35a302..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_ce2_gp10b.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ce2_gp10b_h_ -#define _hw_ce2_gp10b_h_ - -static inline u32 ce2_intr_status_r(u32 i) -{ - return 0x00104410 + i*128; -} -static inline u32 ce2_intr_status_blockpipe_pending_f(void) -{ - return 0x1; -} -static inline u32 ce2_intr_status_blockpipe_reset_f(void) -{ - return 0x1; -} -static inline u32 ce2_intr_status_nonblockpipe_pending_f(void) -{ - return 0x2; -} -static inline u32 ce2_intr_status_nonblockpipe_reset_f(void) -{ - return 0x2; -} -static inline u32 ce2_intr_status_launcherr_pending_f(void) -{ - return 0x4; -} -static inline u32 ce2_intr_status_launcherr_reset_f(void) -{ - return 0x4; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h deleted file mode 100644 index 640453ceb..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_chiplet_pwr_gp10b.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_chiplet_pwr_gp10b_h_ -#define _hw_chiplet_pwr_gp10b_h_ - -static inline u32 chiplet_pwr_gpcs_weight_6_r(void) -{ - return 0x0010e018; -} -static inline u32 chiplet_pwr_gpcs_weight_7_r(void) -{ - return 0x0010e01c; -} -static inline u32 chiplet_pwr_gpcs_config_1_r(void) -{ - return 0x0010e03c; -} -static inline u32 chiplet_pwr_gpcs_config_1_ba_enable_yes_f(void) -{ - return 0x1; -} -static inline u32 chiplet_pwr_fbps_weight_0_r(void) -{ - return 0x0010e100; -} -static inline u32 chiplet_pwr_fbps_weight_1_r(void) -{ - return 0x0010e104; -} -static inline u32 chiplet_pwr_fbps_config_1_r(void) -{ - return 0x0010e13c; -} -static inline u32 chiplet_pwr_fbps_config_1_ba_enable_yes_f(void) -{ - return 0x1; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h deleted file mode 100644 index eef9a96fd..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_ctxsw_prog_gp10b.h +++ /dev/null @@ -1,473 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ctxsw_prog_gp10b_h_ -#define _hw_ctxsw_prog_gp10b_h_ - -static inline u32 ctxsw_prog_fecs_header_v(void) -{ - return 0x00000100; -} -static inline u32 ctxsw_prog_main_image_num_gpcs_o(void) -{ - return 0x00000008; -} -static inline u32 ctxsw_prog_main_image_patch_count_o(void) -{ - return 0x00000010; -} -static inline u32 ctxsw_prog_main_image_context_id_o(void) -{ - return 0x000000f0; -} -static inline u32 ctxsw_prog_main_image_patch_adr_lo_o(void) -{ - return 0x00000014; -} -static inline u32 ctxsw_prog_main_image_patch_adr_hi_o(void) -{ - return 0x00000018; -} -static inline u32 ctxsw_prog_main_image_zcull_o(void) -{ - return 0x0000001c; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_no_ctxsw_v(void) -{ - return 0x00000001; -} -static inline u32 ctxsw_prog_main_image_zcull_mode_separate_buffer_v(void) -{ - return 0x00000002; -} -static inline u32 ctxsw_prog_main_image_zcull_ptr_o(void) -{ - return 0x00000020; -} -static inline u32 ctxsw_prog_main_image_pm_o(void) -{ - return 0x00000028; -} -static inline u32 ctxsw_prog_main_image_pm_mode_m(void) -{ - return 0x7 << 0; -} -static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void) -{ - return 0x7 << 3; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_ctxsw_f(void) -{ - return 0x8; -} -static inline u32 ctxsw_prog_main_image_pm_smpc_mode_no_ctxsw_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_pm_ptr_o(void) -{ - return 0x0000002c; -} -static inline u32 ctxsw_prog_main_image_num_save_ops_o(void) -{ - return 0x000000f4; -} -static inline u32 ctxsw_prog_main_image_num_wfi_save_ops_o(void) -{ - return 0x000000d0; -} -static inline u32 ctxsw_prog_main_image_num_cta_save_ops_o(void) -{ - return 0x000000d4; -} -static inline u32 ctxsw_prog_main_image_num_gfxp_save_ops_o(void) -{ - return 0x000000d8; -} -static inline u32 ctxsw_prog_main_image_num_cilp_save_ops_o(void) -{ - return 0x000000dc; -} -static inline u32 ctxsw_prog_main_image_num_restore_ops_o(void) -{ - return 0x000000f8; -} -static inline u32 ctxsw_prog_main_image_magic_value_o(void) -{ - return 0x000000fc; -} -static inline u32 ctxsw_prog_main_image_magic_value_v_value_v(void) -{ - return 0x600dc0de; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_o(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_local_priv_register_ctl_offset_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ctxsw_prog_local_image_ppc_info_o(void) -{ - return 0x000000f4; -} -static inline u32 ctxsw_prog_local_image_ppc_info_num_ppcs_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ctxsw_prog_local_image_ppc_info_ppc_mask_v(u32 r) -{ - return (r >> 16) & 0xffff; -} -static inline u32 ctxsw_prog_local_image_num_tpcs_o(void) -{ - return 0x000000f8; -} -static inline u32 ctxsw_prog_local_magic_value_o(void) -{ - return 0x000000fc; -} -static inline u32 ctxsw_prog_local_magic_value_v_value_v(void) -{ - return 0xad0becab; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_o(void) -{ - return 0x000000ec; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_offset_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ctxsw_prog_main_extended_buffer_ctl_size_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 ctxsw_prog_extended_buffer_segments_size_in_bytes_v(void) -{ - return 0x00000100; -} -static inline u32 ctxsw_prog_extended_marker_size_in_bytes_v(void) -{ - return 0x00000004; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(void) -{ - return 0x00000002; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_o(void) -{ - return 0x000000a0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_s(void) -{ - return 2; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_m(void) -{ - return 0x3 << 0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_allow_all_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_config_mode_use_map_f(void) -{ - return 0x2; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_lo_o(void) -{ - return 0x000000a4; -} -static inline u32 ctxsw_prog_main_image_priv_access_map_addr_hi_o(void) -{ - return 0x000000a8; -} -static inline u32 ctxsw_prog_main_image_misc_options_o(void) -{ - return 0x0000003c; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_m(void) -{ - return 0x1 << 3; -} -static inline u32 ctxsw_prog_main_image_misc_options_verif_features_disabled_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_o(void) -{ - return 0x00000080; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(void) -{ - return 0x1; -} -static inline u32 ctxsw_prog_main_image_full_preemption_ptr_o(void) -{ - return 0x00000068; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_o(void) -{ - return 0x00000084; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cta_f(void) -{ - return 0x1; -} -static inline u32 ctxsw_prog_main_image_compute_preemption_options_control_cilp_f(void) -{ - return 0x2; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_o(void) -{ - return 0x000000ac; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_control_num_records_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_o(void) -{ - return 0x000000b0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_v_m(void) -{ - return 0xfffffff << 0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_coherent_f(void) -{ - return 0x20000000; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_hi_target_sys_mem_noncoherent_f(void) -{ - return 0x30000000; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(void) -{ - return 0x000000b4; -} -static inline u32 ctxsw_prog_main_image_context_timestamp_buffer_ptr_v_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_bytes_v(void) -{ - return 0x00000080; -} -static inline u32 ctxsw_prog_record_timestamp_record_size_in_words_v(void) -{ - return 0x00000020; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_o(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_lo_v_value_v(void) -{ - return 0x00000000; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_o(void) -{ - return 0x00000004; -} -static inline u32 ctxsw_prog_record_timestamp_magic_value_hi_v_value_v(void) -{ - return 0x600dbeef; -} -static inline u32 ctxsw_prog_record_timestamp_context_id_o(void) -{ - return 0x00000008; -} -static inline u32 ctxsw_prog_record_timestamp_context_ptr_o(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_lo_o(void) -{ - return 0x00000018; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_o(void) -{ - return 0x0000001c; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_v_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_m(void) -{ - return 0xff << 24; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_v(u32 r) -{ - return (r >> 24) & 0xff; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_v(void) -{ - return 0x00000001; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_ctxsw_req_by_host_f(void) -{ - return 0x1000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_v(void) -{ - return 0x00000002; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_f(void) -{ - return 0x2000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_v(void) -{ - return 0x0000000a; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_wfi_f(void) -{ - return 0xa000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_v(void) -{ - return 0x0000000b; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_gfxp_f(void) -{ - return 0xb000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_v(void) -{ - return 0x0000000c; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_ctap_f(void) -{ - return 0xc000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_v(void) -{ - return 0x0000000d; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_fe_ack_cilp_f(void) -{ - return 0xd000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_v(void) -{ - return 0x00000003; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_save_end_f(void) -{ - return 0x3000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_v(void) -{ - return 0x00000004; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_restore_start_f(void) -{ - return 0x4000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_v(void) -{ - return 0x00000005; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_context_start_f(void) -{ - return 0x5000000; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_v(void) -{ - return 0x000000ff; -} -static inline u32 ctxsw_prog_record_timestamp_timestamp_hi_tag_invalid_timestamp_f(void) -{ - return 0xff000000; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h deleted file mode 100644 index 1fee19b14..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ /dev/null @@ -1,457 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fb_gp10b_h_ -#define _hw_fb_gp10b_h_ - -static inline u32 fb_fbhub_num_active_ltcs_r(void) -{ - return 0x00100800; -} -static inline u32 fb_mmu_ctrl_r(void) -{ - return 0x00100c80; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_128kb_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_ctrl_vm_pg_size_64kb_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fb_mmu_ctrl_pri_fifo_empty_false_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_ctrl_pri_fifo_space_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_true_f(void) -{ - return 0x800; -} -static inline u32 fb_mmu_ctrl_use_pdb_big_page_size_false_f(void) -{ - return 0x0; -} -static inline u32 fb_priv_mmu_phy_secure_r(void) -{ - return 0x00100ce4; -} -static inline u32 fb_mmu_invalidate_pdb_r(void) -{ - return 0x00100cb8; -} -static inline u32 fb_mmu_invalidate_pdb_aperture_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_pdb_addr_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 fb_mmu_invalidate_r(void) -{ - return 0x00100cbc; -} -static inline u32 fb_mmu_invalidate_all_va_true_f(void) -{ - return 0x1; -} -static inline u32 fb_mmu_invalidate_all_pdb_true_f(void) -{ - return 0x2; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_m(void) -{ - return 0x1 << 2; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 fb_mmu_invalidate_hubtlb_only_true_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_invalidate_replay_s(void) -{ - return 3; -} -static inline u32 fb_mmu_invalidate_replay_f(u32 v) -{ - return (v & 0x7) << 3; -} -static inline u32 fb_mmu_invalidate_replay_m(void) -{ - return 0x7 << 3; -} -static inline u32 fb_mmu_invalidate_replay_v(u32 r) -{ - return (r >> 3) & 0x7; -} -static inline u32 fb_mmu_invalidate_replay_none_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_replay_start_f(void) -{ - return 0x8; -} -static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) -{ - return 0x10; -} -static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) -{ - return 0x18; -} -static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) -{ - return 0x20; -} -static inline u32 fb_mmu_invalidate_replay_cancel_f(void) -{ - return 0x20; -} -static inline u32 fb_mmu_invalidate_sys_membar_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_sys_membar_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 fb_mmu_invalidate_sys_membar_m(void) -{ - return 0x1 << 6; -} -static inline u32 fb_mmu_invalidate_sys_membar_v(u32 r) -{ - return (r >> 6) & 0x1; -} -static inline u32 fb_mmu_invalidate_sys_membar_true_f(void) -{ - return 0x40; -} -static inline u32 fb_mmu_invalidate_ack_s(void) -{ - return 2; -} -static inline u32 fb_mmu_invalidate_ack_f(u32 v) -{ - return (v & 0x3) << 7; -} -static inline u32 fb_mmu_invalidate_ack_m(void) -{ - return 0x3 << 7; -} -static inline u32 fb_mmu_invalidate_ack_v(u32 r) -{ - return (r >> 7) & 0x3; -} -static inline u32 fb_mmu_invalidate_ack_ack_none_required_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_ack_ack_intranode_f(void) -{ - return 0x100; -} -static inline u32 fb_mmu_invalidate_ack_ack_globally_f(void) -{ - return 0x80; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_s(void) -{ - return 6; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_f(u32 v) -{ - return (v & 0x3f) << 9; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_m(void) -{ - return 0x3f << 9; -} -static inline u32 fb_mmu_invalidate_cancel_client_id_v(u32 r) -{ - return (r >> 9) & 0x3f; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_s(void) -{ - return 5; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_f(u32 v) -{ - return (v & 0x1f) << 15; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_m(void) -{ - return 0x1f << 15; -} -static inline u32 fb_mmu_invalidate_cancel_gpc_id_v(u32 r) -{ - return (r >> 15) & 0x1f; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_f(u32 v) -{ - return (v & 0x1) << 20; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_m(void) -{ - return 0x1 << 20; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_gpc_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_cancel_client_type_hub_f(void) -{ - return 0x100000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_s(void) -{ - return 3; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_m(void) -{ - return 0x7 << 24; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_v(u32 r) -{ - return (r >> 24) & 0x7; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_all_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_pte_only_f(void) -{ - return 0x1000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde0_f(void) -{ - return 0x2000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde1_f(void) -{ - return 0x3000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde2_f(void) -{ - return 0x4000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde3_f(void) -{ - return 0x5000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde4_f(void) -{ - return 0x6000000; -} -static inline u32 fb_mmu_invalidate_cancel_cache_level_up_to_pde5_f(void) -{ - return 0x7000000; -} -static inline u32 fb_mmu_invalidate_trigger_s(void) -{ - return 1; -} -static inline u32 fb_mmu_invalidate_trigger_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 fb_mmu_invalidate_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 fb_mmu_invalidate_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fb_mmu_invalidate_trigger_true_f(void) -{ - return 0x80000000; -} -static inline u32 fb_mmu_debug_wr_r(void) -{ - return 0x00100cc8; -} -static inline u32 fb_mmu_debug_wr_aperture_s(void) -{ - return 2; -} -static inline u32 fb_mmu_debug_wr_aperture_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 fb_mmu_debug_wr_aperture_m(void) -{ - return 0x3 << 0; -} -static inline u32 fb_mmu_debug_wr_aperture_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 fb_mmu_debug_wr_aperture_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_wr_vol_false_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_wr_vol_true_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_debug_wr_vol_true_f(void) -{ - return 0x4; -} -static inline u32 fb_mmu_debug_wr_addr_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 fb_mmu_debug_wr_addr_alignment_v(void) -{ - return 0x0000000c; -} -static inline u32 fb_mmu_debug_rd_r(void) -{ - return 0x00100ccc; -} -static inline u32 fb_mmu_debug_rd_aperture_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_rd_vol_false_f(void) -{ - return 0x0; -} -static inline u32 fb_mmu_debug_rd_addr_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 fb_mmu_debug_rd_addr_alignment_v(void) -{ - return 0x0000000c; -} -static inline u32 fb_mmu_debug_ctrl_r(void) -{ - return 0x00100cc4; -} -static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16) & 0x1; -} -static inline u32 fb_mmu_debug_ctrl_debug_m(void) -{ - return 0x1 << 16; -} -static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 fb_mmu_vpr_info_r(void) -{ - return 0x00100cd0; -} -static inline u32 fb_mmu_vpr_info_fetch_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 fb_mmu_vpr_info_fetch_false_v(void) -{ - return 0x00000000; -} -static inline u32 fb_mmu_vpr_info_fetch_true_v(void) -{ - return 0x00000001; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h deleted file mode 100644 index 6f7e09ff9..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ /dev/null @@ -1,669 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fifo_gp10b_h_ -#define _hw_fifo_gp10b_h_ - -static inline u32 fifo_bar1_base_r(void) -{ - return 0x00002254; -} -static inline u32 fifo_bar1_base_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 fifo_bar1_base_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 fifo_bar1_base_valid_false_f(void) -{ - return 0x0; -} -static inline u32 fifo_bar1_base_valid_true_f(void) -{ - return 0x10000000; -} -static inline u32 fifo_runlist_base_r(void) -{ - return 0x00002270; -} -static inline u32 fifo_runlist_base_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 fifo_runlist_base_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 fifo_runlist_r(void) -{ - return 0x00002274; -} -static inline u32 fifo_runlist_engine_f(u32 v) -{ - return (v & 0xf) << 20; -} -static inline u32 fifo_eng_runlist_base_r(u32 i) -{ - return 0x00002280 + i*8; -} -static inline u32 fifo_eng_runlist_base__size_1_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_eng_runlist_r(u32 i) -{ - return 0x00002284 + i*8; -} -static inline u32 fifo_eng_runlist__size_1_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_eng_runlist_length_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 fifo_eng_runlist_pending_true_f(void) -{ - return 0x100000; -} -static inline u32 fifo_pb_timeslice_r(u32 i) -{ - return 0x00002350 + i*4; -} -static inline u32 fifo_pb_timeslice_timeout_16_f(void) -{ - return 0x10; -} -static inline u32 fifo_pb_timeslice_timescale_0_f(void) -{ - return 0x0; -} -static inline u32 fifo_pb_timeslice_enable_true_f(void) -{ - return 0x10000000; -} -static inline u32 fifo_pbdma_map_r(u32 i) -{ - return 0x00002390 + i*4; -} -static inline u32 fifo_intr_0_r(void) -{ - return 0x00002100; -} -static inline u32 fifo_intr_0_bind_error_pending_f(void) -{ - return 0x1; -} -static inline u32 fifo_intr_0_bind_error_reset_f(void) -{ - return 0x1; -} -static inline u32 fifo_intr_0_sched_error_pending_f(void) -{ - return 0x100; -} -static inline u32 fifo_intr_0_sched_error_reset_f(void) -{ - return 0x100; -} -static inline u32 fifo_intr_0_chsw_error_pending_f(void) -{ - return 0x10000; -} -static inline u32 fifo_intr_0_chsw_error_reset_f(void) -{ - return 0x10000; -} -static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) -{ - return 0x800000; -} -static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) -{ - return 0x800000; -} -static inline u32 fifo_intr_0_lb_error_pending_f(void) -{ - return 0x1000000; -} -static inline u32 fifo_intr_0_lb_error_reset_f(void) -{ - return 0x1000000; -} -static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) -{ - return 0x2000000; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) -{ - return 0x8000000; -} -static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) -{ - return 0x8000000; -} -static inline u32 fifo_intr_0_mmu_fault_pending_f(void) -{ - return 0x10000000; -} -static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) -{ - return 0x20000000; -} -static inline u32 fifo_intr_0_runlist_event_pending_f(void) -{ - return 0x40000000; -} -static inline u32 fifo_intr_0_channel_intr_pending_f(void) -{ - return 0x80000000; -} -static inline u32 fifo_intr_en_0_r(void) -{ - return 0x00002140; -} -static inline u32 fifo_intr_en_0_sched_error_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 fifo_intr_en_0_sched_error_m(void) -{ - return 0x1 << 8; -} -static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fifo_intr_en_0_mmu_fault_m(void) -{ - return 0x1 << 28; -} -static inline u32 fifo_intr_en_1_r(void) -{ - return 0x00002528; -} -static inline u32 fifo_intr_bind_error_r(void) -{ - return 0x0000252c; -} -static inline u32 fifo_intr_sched_error_r(void) -{ - return 0x0000254c; -} -static inline u32 fifo_intr_sched_error_code_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) -{ - return 0x0000000a; -} -static inline u32 fifo_intr_chsw_error_r(void) -{ - return 0x0000256c; -} -static inline u32 fifo_intr_mmu_fault_id_r(void) -{ - return 0x0000259c; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) -{ - return 0x0; -} -static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) -{ - return 0x00002800 + i*16; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) -{ - return 0x00002804 + i*16; -} -static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) -{ - return 0x00002808 + i*16; -} -static inline u32 fifo_intr_mmu_fault_info_r(u32 i) -{ - return 0x0000280c + i*16; -} -static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) -{ - return (r >> 8) & 0x7f; -} -static inline u32 fifo_intr_pbdma_id_r(void) -{ - return 0x000025a0; -} -static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) -{ - return (v & 0x1) << (0 + i*1); -} -static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_intr_runlist_r(void) -{ - return 0x00002a00; -} -static inline u32 fifo_fb_timeout_r(void) -{ - return 0x00002a04; -} -static inline u32 fifo_fb_timeout_period_m(void) -{ - return 0x3fffffff << 0; -} -static inline u32 fifo_fb_timeout_period_max_f(void) -{ - return 0x3fffffff; -} -static inline u32 fifo_error_sched_disable_r(void) -{ - return 0x0000262c; -} -static inline u32 fifo_sched_disable_r(void) -{ - return 0x00002630; -} -static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) -{ - return (v & 0x1) << (0 + i*1); -} -static inline u32 fifo_sched_disable_runlist_m(u32 i) -{ - return 0x1 << (0 + i*1); -} -static inline u32 fifo_sched_disable_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_preempt_r(void) -{ - return 0x00002634; -} -static inline u32 fifo_preempt_pending_true_f(void) -{ - return 0x100000; -} -static inline u32 fifo_preempt_type_channel_f(void) -{ - return 0x0; -} -static inline u32 fifo_preempt_type_tsg_f(void) -{ - return 0x1000000; -} -static inline u32 fifo_preempt_chid_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 fifo_preempt_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 fifo_trigger_mmu_fault_r(u32 i) -{ - return 0x00002a30 + i*4; -} -static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 fifo_engine_status_r(u32 i) -{ - return 0x00002640 + i*8; -} -static inline u32 fifo_engine_status__size_1_v(void) -{ - return 0x00000002; -} -static inline u32 fifo_engine_status_id_v(u32 r) -{ - return (r >> 0) & 0xfff; -} -static inline u32 fifo_engine_status_id_type_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 fifo_engine_status_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_engine_status_id_type_tsgid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctx_status_v(u32 r) -{ - return (r >> 13) & 0x7; -} -static inline u32 fifo_engine_status_ctx_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) -{ - return 0x00000005; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) -{ - return 0x00000006; -} -static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) -{ - return 0x00000007; -} -static inline u32 fifo_engine_status_next_id_v(u32 r) -{ - return (r >> 16) & 0xfff; -} -static inline u32 fifo_engine_status_next_id_type_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 fifo_engine_status_next_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_engine_status_faulted_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 fifo_engine_status_faulted_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_engine_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 fifo_engine_status_engine_idle_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_engine_status_engine_busy_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctxsw_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) -{ - return 0x8000; -} -static inline u32 fifo_pbdma_status_r(u32 i) -{ - return 0x00003080 + i*4; -} -static inline u32 fifo_pbdma_status__size_1_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_pbdma_status_id_v(u32 r) -{ - return (r >> 0) & 0xfff; -} -static inline u32 fifo_pbdma_status_id_type_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 fifo_pbdma_status_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_pbdma_status_chan_status_v(u32 r) -{ - return (r >> 13) & 0x7; -} -static inline u32 fifo_pbdma_status_chan_status_valid_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) -{ - return 0x00000005; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) -{ - return 0x00000006; -} -static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) -{ - return 0x00000007; -} -static inline u32 fifo_pbdma_status_next_id_v(u32 r) -{ - return (r >> 16) & 0xfff; -} -static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_pbdma_status_chsw_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_lo_r(void) -{ - return 0x00002a70; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_lo_enable_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_lo_base_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 fifo_replay_fault_buffer_lo_base_reset_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_hi_r(void) -{ - return 0x00002a74; -} -static inline u32 fifo_replay_fault_buffer_hi_base_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fifo_replay_fault_buffer_hi_base_reset_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_size_r(void) -{ - return 0x00002a78; -} -static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) -{ - return 0x000000c0; -} -static inline u32 fifo_replay_fault_buffer_get_r(void) -{ - return 0x00002a7c; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_put_r(void) -{ - return 0x00002a80; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_r(void) -{ - return 0x00002a84; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_overflow_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_write_nack_clear_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_false_v(void) -{ - return 0x00000000; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_true_v(void) -{ - return 0x00000001; -} -static inline u32 fifo_replay_fault_buffer_info_fault_while_buffer_disabled_clear_v(void) -{ - return 0x00000001; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h deleted file mode 100644 index e2dff4909..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_flush_gp10b.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_flush_gp10b_h_ -#define _hw_flush_gp10b_h_ - -static inline u32 flush_l2_system_invalidate_r(void) -{ - return 0x00070004; -} -static inline u32 flush_l2_system_invalidate_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_l2_system_invalidate_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_system_invalidate_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_l2_system_invalidate_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_l2_system_invalidate_outstanding_true_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_flush_dirty_r(void) -{ - return 0x00070010; -} -static inline u32 flush_l2_flush_dirty_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_l2_flush_dirty_pending_empty_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_flush_dirty_pending_empty_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_flush_dirty_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_flush_dirty_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_l2_flush_dirty_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_flush_dirty_outstanding_false_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_flush_dirty_outstanding_true_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_clean_comptags_r(void) -{ - return 0x0007000c; -} -static inline u32 flush_l2_clean_comptags_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_l2_clean_comptags_pending_empty_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_clean_comptags_pending_empty_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_clean_comptags_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_l2_clean_comptags_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_l2_clean_comptags_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_v(void) -{ - return 0x00000000; -} -static inline u32 flush_l2_clean_comptags_outstanding_false_f(void) -{ - return 0x0; -} -static inline u32 flush_l2_clean_comptags_outstanding_true_v(void) -{ - return 0x00000001; -} -static inline u32 flush_fb_flush_r(void) -{ - return 0x00070000; -} -static inline u32 flush_fb_flush_pending_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 flush_fb_flush_pending_busy_v(void) -{ - return 0x00000001; -} -static inline u32 flush_fb_flush_pending_busy_f(void) -{ - return 0x1; -} -static inline u32 flush_fb_flush_outstanding_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 flush_fb_flush_outstanding_true_v(void) -{ - return 0x00000001; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h deleted file mode 100644 index ae524ce54..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ /dev/null @@ -1,137 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_fuse_gp10b_h_ -#define _hw_fuse_gp10b_h_ - -static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) -{ - return 0x00021c38 + i*4; -} -static inline u32 fuse_ctrl_opt_tpc_gpc_r(u32 i) -{ - return 0x00021838 + i*4; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_r(void) -{ - return 0x00021944; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_m(void) -{ - return 0xff << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_data_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_r(void) -{ - return 0x00021948; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_m(void) -{ - return 0x1 << 0; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_yes_f(void) -{ - return 0x1; -} -static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) -{ - return 0x0; -} -static inline u32 fuse_status_opt_fbio_r(void) -{ - return 0x00021c14; -} -static inline u32 fuse_status_opt_fbio_data_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 fuse_status_opt_fbio_data_m(void) -{ - return 0xffff << 0; -} -static inline u32 fuse_status_opt_fbio_data_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) -{ - return 0x00021d70 + i*4; -} -static inline u32 fuse_status_opt_fbp_r(void) -{ - return 0x00021d38; -} -static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) -{ - return (r >> (0 + i*0)) & 0x1; -} -static inline u32 fuse_opt_ecc_en_r(void) -{ - return 0x00021228; -} -static inline u32 fuse_opt_feature_fuses_override_disable_r(void) -{ - return 0x000213f0; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h deleted file mode 100644 index 9ce9448e1..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_gmmu_gp10b.h +++ /dev/null @@ -1,1237 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gmmu_gp10b_h_ -#define _hw_gmmu_gp10b_h_ - -static inline u32 gmmu_new_pde_is_pte_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_is_pte_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pde_aperture_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_aperture_invalid_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pde_aperture_video_memory_f(void) -{ - return 0x2; -} -static inline u32 gmmu_new_pde_address_sys_f(u32 v) -{ - return (v & 0xfffffff) << 8; -} -static inline u32 gmmu_new_pde_address_sys_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_vol_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pde_vol_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_pde_vol_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pde_address_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_new_pde__size_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_new_dual_pde_is_pte_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_is_pte_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_aperture_big_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_aperture_big_invalid_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_aperture_big_video_memory_f(void) -{ - return 0x2; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 gmmu_new_dual_pde_address_big_sys_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_aperture_small_w(void) -{ - return 2; -} -static inline u32 gmmu_new_dual_pde_aperture_small_invalid_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_aperture_small_video_memory_f(void) -{ - return 0x2; -} -static inline u32 gmmu_new_dual_pde_vol_small_w(void) -{ - return 2; -} -static inline u32 gmmu_new_dual_pde_vol_small_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_dual_pde_vol_small_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_vol_big_w(void) -{ - return 0; -} -static inline u32 gmmu_new_dual_pde_vol_big_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_dual_pde_vol_big_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_f(u32 v) -{ - return (v & 0xfffffff) << 8; -} -static inline u32 gmmu_new_dual_pde_address_small_sys_w(void) -{ - return 2; -} -static inline u32 gmmu_new_dual_pde_address_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_new_dual_pde_address_big_shift_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_new_dual_pde__size_v(void) -{ - return 0x00000010; -} -static inline u32 gmmu_new_pte__size_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_new_pte_valid_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_valid_true_f(void) -{ - return 0x1; -} -static inline u32 gmmu_new_pte_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_privilege_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_privilege_true_f(void) -{ - return 0x20; -} -static inline u32 gmmu_new_pte_privilege_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_address_sys_f(u32 v) -{ - return (v & 0xfffffff) << 8; -} -static inline u32 gmmu_new_pte_address_sys_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_vol_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_vol_true_f(void) -{ - return 0x8; -} -static inline u32 gmmu_new_pte_vol_false_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_aperture_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_aperture_video_memory_f(void) -{ - return 0x0; -} -static inline u32 gmmu_new_pte_read_only_w(void) -{ - return 0; -} -static inline u32 gmmu_new_pte_read_only_true_f(void) -{ - return 0x40; -} -static inline u32 gmmu_new_pte_comptagline_f(u32 v) -{ - return (v & 0x3ffff) << 4; -} -static inline u32 gmmu_new_pte_comptagline_w(void) -{ - return 1; -} -static inline u32 gmmu_new_pte_kind_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 gmmu_new_pte_kind_w(void) -{ - return 1; -} -static inline u32 gmmu_new_pte_address_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_pte_kind_f(u32 v) -{ - return (v & 0xff) << 4; -} -static inline u32 gmmu_pte_kind_w(void) -{ - return 1; -} -static inline u32 gmmu_pte_kind_invalid_v(void) -{ - return 0x000000ff; -} -static inline u32 gmmu_pte_kind_pitch_v(void) -{ - return 0x00000000; -} -static inline u32 gmmu_pte_kind_z16_v(void) -{ - return 0x00000001; -} -static inline u32 gmmu_pte_kind_z16_2c_v(void) -{ - return 0x00000002; -} -static inline u32 gmmu_pte_kind_z16_ms2_2c_v(void) -{ - return 0x00000003; -} -static inline u32 gmmu_pte_kind_z16_ms4_2c_v(void) -{ - return 0x00000004; -} -static inline u32 gmmu_pte_kind_z16_ms8_2c_v(void) -{ - return 0x00000005; -} -static inline u32 gmmu_pte_kind_z16_ms16_2c_v(void) -{ - return 0x00000006; -} -static inline u32 gmmu_pte_kind_z16_2z_v(void) -{ - return 0x00000007; -} -static inline u32 gmmu_pte_kind_z16_ms2_2z_v(void) -{ - return 0x00000008; -} -static inline u32 gmmu_pte_kind_z16_ms4_2z_v(void) -{ - return 0x00000009; -} -static inline u32 gmmu_pte_kind_z16_ms8_2z_v(void) -{ - return 0x0000000a; -} -static inline u32 gmmu_pte_kind_z16_ms16_2z_v(void) -{ - return 0x0000000b; -} -static inline u32 gmmu_pte_kind_z16_2cz_v(void) -{ - return 0x00000036; -} -static inline u32 gmmu_pte_kind_z16_ms2_2cz_v(void) -{ - return 0x00000037; -} -static inline u32 gmmu_pte_kind_z16_ms4_2cz_v(void) -{ - return 0x00000038; -} -static inline u32 gmmu_pte_kind_z16_ms8_2cz_v(void) -{ - return 0x00000039; -} -static inline u32 gmmu_pte_kind_z16_ms16_2cz_v(void) -{ - return 0x0000005f; -} -static inline u32 gmmu_pte_kind_z16_4cz_v(void) -{ - return 0x0000000c; -} -static inline u32 gmmu_pte_kind_z16_ms2_4cz_v(void) -{ - return 0x0000000d; -} -static inline u32 gmmu_pte_kind_z16_ms4_4cz_v(void) -{ - return 0x0000000e; -} -static inline u32 gmmu_pte_kind_z16_ms8_4cz_v(void) -{ - return 0x0000000f; -} -static inline u32 gmmu_pte_kind_z16_ms16_4cz_v(void) -{ - return 0x00000010; -} -static inline u32 gmmu_pte_kind_s8z24_v(void) -{ - return 0x00000011; -} -static inline u32 gmmu_pte_kind_s8z24_1z_v(void) -{ - return 0x00000012; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_1z_v(void) -{ - return 0x00000013; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_1z_v(void) -{ - return 0x00000014; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_1z_v(void) -{ - return 0x00000015; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_1z_v(void) -{ - return 0x00000016; -} -static inline u32 gmmu_pte_kind_s8z24_2cz_v(void) -{ - return 0x00000017; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_2cz_v(void) -{ - return 0x00000018; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_2cz_v(void) -{ - return 0x00000019; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_2cz_v(void) -{ - return 0x0000001a; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_2cz_v(void) -{ - return 0x0000001b; -} -static inline u32 gmmu_pte_kind_s8z24_2cs_v(void) -{ - return 0x0000001c; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_2cs_v(void) -{ - return 0x0000001d; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_2cs_v(void) -{ - return 0x0000001e; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_2cs_v(void) -{ - return 0x0000001f; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_2cs_v(void) -{ - return 0x00000020; -} -static inline u32 gmmu_pte_kind_s8z24_4cszv_v(void) -{ - return 0x00000021; -} -static inline u32 gmmu_pte_kind_s8z24_ms2_4cszv_v(void) -{ - return 0x00000022; -} -static inline u32 gmmu_pte_kind_s8z24_ms4_4cszv_v(void) -{ - return 0x00000023; -} -static inline u32 gmmu_pte_kind_s8z24_ms8_4cszv_v(void) -{ - return 0x00000024; -} -static inline u32 gmmu_pte_kind_s8z24_ms16_4cszv_v(void) -{ - return 0x00000025; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_v(void) -{ - return 0x00000026; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_v(void) -{ - return 0x00000027; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_v(void) -{ - return 0x00000028; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_v(void) -{ - return 0x00000029; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_1zv_v(void) -{ - return 0x0000002e; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_1zv_v(void) -{ - return 0x0000002f; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_1zv_v(void) -{ - return 0x00000030; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_1zv_v(void) -{ - return 0x00000031; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2cs_v(void) -{ - return 0x00000032; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2cs_v(void) -{ - return 0x00000033; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2cs_v(void) -{ - return 0x00000034; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2cs_v(void) -{ - return 0x00000035; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2czv_v(void) -{ - return 0x0000003a; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2czv_v(void) -{ - return 0x0000003b; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2czv_v(void) -{ - return 0x0000003c; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2czv_v(void) -{ - return 0x0000003d; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_2zv_v(void) -{ - return 0x0000003e; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_2zv_v(void) -{ - return 0x0000003f; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_2zv_v(void) -{ - return 0x00000040; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_2zv_v(void) -{ - return 0x00000041; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc12_4cszv_v(void) -{ - return 0x00000042; -} -static inline u32 gmmu_pte_kind_v8z24_ms4_vc4_4cszv_v(void) -{ - return 0x00000043; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc8_4cszv_v(void) -{ - return 0x00000044; -} -static inline u32 gmmu_pte_kind_v8z24_ms8_vc24_4cszv_v(void) -{ - return 0x00000045; -} -static inline u32 gmmu_pte_kind_z24s8_v(void) -{ - return 0x00000046; -} -static inline u32 gmmu_pte_kind_z24s8_1z_v(void) -{ - return 0x00000047; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_1z_v(void) -{ - return 0x00000048; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_1z_v(void) -{ - return 0x00000049; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_1z_v(void) -{ - return 0x0000004a; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_1z_v(void) -{ - return 0x0000004b; -} -static inline u32 gmmu_pte_kind_z24s8_2cs_v(void) -{ - return 0x0000004c; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_2cs_v(void) -{ - return 0x0000004d; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_2cs_v(void) -{ - return 0x0000004e; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_2cs_v(void) -{ - return 0x0000004f; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_2cs_v(void) -{ - return 0x00000050; -} -static inline u32 gmmu_pte_kind_z24s8_2cz_v(void) -{ - return 0x00000051; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_2cz_v(void) -{ - return 0x00000052; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_2cz_v(void) -{ - return 0x00000053; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_2cz_v(void) -{ - return 0x00000054; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_2cz_v(void) -{ - return 0x00000055; -} -static inline u32 gmmu_pte_kind_z24s8_4cszv_v(void) -{ - return 0x00000056; -} -static inline u32 gmmu_pte_kind_z24s8_ms2_4cszv_v(void) -{ - return 0x00000057; -} -static inline u32 gmmu_pte_kind_z24s8_ms4_4cszv_v(void) -{ - return 0x00000058; -} -static inline u32 gmmu_pte_kind_z24s8_ms8_4cszv_v(void) -{ - return 0x00000059; -} -static inline u32 gmmu_pte_kind_z24s8_ms16_4cszv_v(void) -{ - return 0x0000005a; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_v(void) -{ - return 0x0000005b; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_v(void) -{ - return 0x0000005c; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_v(void) -{ - return 0x0000005d; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_v(void) -{ - return 0x0000005e; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_1zv_v(void) -{ - return 0x00000063; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_1zv_v(void) -{ - return 0x00000064; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_1zv_v(void) -{ - return 0x00000065; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_1zv_v(void) -{ - return 0x00000066; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2cs_v(void) -{ - return 0x00000067; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2cs_v(void) -{ - return 0x00000068; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2cs_v(void) -{ - return 0x00000069; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2cs_v(void) -{ - return 0x0000006a; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2czv_v(void) -{ - return 0x0000006f; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2czv_v(void) -{ - return 0x00000070; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2czv_v(void) -{ - return 0x00000071; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2czv_v(void) -{ - return 0x00000072; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_2zv_v(void) -{ - return 0x00000073; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_2zv_v(void) -{ - return 0x00000074; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_2zv_v(void) -{ - return 0x00000075; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_2zv_v(void) -{ - return 0x00000076; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc12_4cszv_v(void) -{ - return 0x00000077; -} -static inline u32 gmmu_pte_kind_z24v8_ms4_vc4_4cszv_v(void) -{ - return 0x00000078; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc8_4cszv_v(void) -{ - return 0x00000079; -} -static inline u32 gmmu_pte_kind_z24v8_ms8_vc24_4cszv_v(void) -{ - return 0x0000007a; -} -static inline u32 gmmu_pte_kind_zf32_v(void) -{ - return 0x0000007b; -} -static inline u32 gmmu_pte_kind_zf32_1z_v(void) -{ - return 0x0000007c; -} -static inline u32 gmmu_pte_kind_zf32_ms2_1z_v(void) -{ - return 0x0000007d; -} -static inline u32 gmmu_pte_kind_zf32_ms4_1z_v(void) -{ - return 0x0000007e; -} -static inline u32 gmmu_pte_kind_zf32_ms8_1z_v(void) -{ - return 0x0000007f; -} -static inline u32 gmmu_pte_kind_zf32_ms16_1z_v(void) -{ - return 0x00000080; -} -static inline u32 gmmu_pte_kind_zf32_2cs_v(void) -{ - return 0x00000081; -} -static inline u32 gmmu_pte_kind_zf32_ms2_2cs_v(void) -{ - return 0x00000082; -} -static inline u32 gmmu_pte_kind_zf32_ms4_2cs_v(void) -{ - return 0x00000083; -} -static inline u32 gmmu_pte_kind_zf32_ms8_2cs_v(void) -{ - return 0x00000084; -} -static inline u32 gmmu_pte_kind_zf32_ms16_2cs_v(void) -{ - return 0x00000085; -} -static inline u32 gmmu_pte_kind_zf32_2cz_v(void) -{ - return 0x00000086; -} -static inline u32 gmmu_pte_kind_zf32_ms2_2cz_v(void) -{ - return 0x00000087; -} -static inline u32 gmmu_pte_kind_zf32_ms4_2cz_v(void) -{ - return 0x00000088; -} -static inline u32 gmmu_pte_kind_zf32_ms8_2cz_v(void) -{ - return 0x00000089; -} -static inline u32 gmmu_pte_kind_zf32_ms16_2cz_v(void) -{ - return 0x0000008a; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_v(void) -{ - return 0x0000008b; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_v(void) -{ - return 0x0000008c; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_v(void) -{ - return 0x0000008d; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_v(void) -{ - return 0x0000008e; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1cs_v(void) -{ - return 0x0000008f; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1cs_v(void) -{ - return 0x00000090; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1cs_v(void) -{ - return 0x00000091; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1cs_v(void) -{ - return 0x00000092; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1zv_v(void) -{ - return 0x00000097; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1zv_v(void) -{ - return 0x00000098; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1zv_v(void) -{ - return 0x00000099; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1zv_v(void) -{ - return 0x0000009a; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_1czv_v(void) -{ - return 0x0000009b; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_1czv_v(void) -{ - return 0x0000009c; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_1czv_v(void) -{ - return 0x0000009d; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_1czv_v(void) -{ - return 0x0000009e; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cs_v(void) -{ - return 0x0000009f; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cs_v(void) -{ - return 0x000000a0; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cs_v(void) -{ - return 0x000000a1; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cs_v(void) -{ - return 0x000000a2; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc12_2cszv_v(void) -{ - return 0x000000a3; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms4_vc4_2cszv_v(void) -{ - return 0x000000a4; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc8_2cszv_v(void) -{ - return 0x000000a5; -} -static inline u32 gmmu_pte_kind_x8z24_x16v8s8_ms8_vc24_2cszv_v(void) -{ - return 0x000000a6; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_v(void) -{ - return 0x000000a7; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_v(void) -{ - return 0x000000a8; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_v(void) -{ - return 0x000000a9; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_v(void) -{ - return 0x000000aa; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1cs_v(void) -{ - return 0x000000ab; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1cs_v(void) -{ - return 0x000000ac; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1cs_v(void) -{ - return 0x000000ad; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1cs_v(void) -{ - return 0x000000ae; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1zv_v(void) -{ - return 0x000000b3; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1zv_v(void) -{ - return 0x000000b4; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1zv_v(void) -{ - return 0x000000b5; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1zv_v(void) -{ - return 0x000000b6; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_1czv_v(void) -{ - return 0x000000b7; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_1czv_v(void) -{ - return 0x000000b8; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_1czv_v(void) -{ - return 0x000000b9; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_1czv_v(void) -{ - return 0x000000ba; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cs_v(void) -{ - return 0x000000bb; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cs_v(void) -{ - return 0x000000bc; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cs_v(void) -{ - return 0x000000bd; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cs_v(void) -{ - return 0x000000be; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc12_2cszv_v(void) -{ - return 0x000000bf; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms4_vc4_2cszv_v(void) -{ - return 0x000000c0; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc8_2cszv_v(void) -{ - return 0x000000c1; -} -static inline u32 gmmu_pte_kind_zf32_x16v8s8_ms8_vc24_2cszv_v(void) -{ - return 0x000000c2; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_v(void) -{ - return 0x000000c3; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_1cs_v(void) -{ - return 0x000000c4; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_1cs_v(void) -{ - return 0x000000c5; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_1cs_v(void) -{ - return 0x000000c6; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_1cs_v(void) -{ - return 0x000000c7; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_1cs_v(void) -{ - return 0x000000c8; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_2cszv_v(void) -{ - return 0x000000ce; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cszv_v(void) -{ - return 0x000000cf; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cszv_v(void) -{ - return 0x000000d0; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cszv_v(void) -{ - return 0x000000d1; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cszv_v(void) -{ - return 0x000000d2; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_2cs_v(void) -{ - return 0x000000d3; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms2_2cs_v(void) -{ - return 0x000000d4; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms4_2cs_v(void) -{ - return 0x000000d5; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms8_2cs_v(void) -{ - return 0x000000d6; -} -static inline u32 gmmu_pte_kind_zf32_x24s8_ms16_2cs_v(void) -{ - return 0x000000d7; -} -static inline u32 gmmu_pte_kind_generic_16bx2_v(void) -{ - return 0x000000fe; -} -static inline u32 gmmu_pte_kind_c32_2c_v(void) -{ - return 0x000000d8; -} -static inline u32 gmmu_pte_kind_c32_2cbr_v(void) -{ - return 0x000000d9; -} -static inline u32 gmmu_pte_kind_c32_2cba_v(void) -{ - return 0x000000da; -} -static inline u32 gmmu_pte_kind_c32_2cra_v(void) -{ - return 0x000000db; -} -static inline u32 gmmu_pte_kind_c32_2bra_v(void) -{ - return 0x000000dc; -} -static inline u32 gmmu_pte_kind_c32_ms2_2c_v(void) -{ - return 0x000000dd; -} -static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) -{ - return 0x000000de; -} -static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) -{ - return 0x000000cc; -} -static inline u32 gmmu_pte_kind_c32_ms4_2c_v(void) -{ - return 0x000000df; -} -static inline u32 gmmu_pte_kind_c32_ms4_2cbr_v(void) -{ - return 0x000000e0; -} -static inline u32 gmmu_pte_kind_c32_ms4_2cba_v(void) -{ - return 0x000000e1; -} -static inline u32 gmmu_pte_kind_c32_ms4_2cra_v(void) -{ - return 0x000000e2; -} -static inline u32 gmmu_pte_kind_c32_ms4_2bra_v(void) -{ - return 0x000000e3; -} -static inline u32 gmmu_pte_kind_c32_ms4_4cbra_v(void) -{ - return 0x0000002c; -} -static inline u32 gmmu_pte_kind_c32_ms8_ms16_2c_v(void) -{ - return 0x000000e4; -} -static inline u32 gmmu_pte_kind_c32_ms8_ms16_2cra_v(void) -{ - return 0x000000e5; -} -static inline u32 gmmu_pte_kind_c64_2c_v(void) -{ - return 0x000000e6; -} -static inline u32 gmmu_pte_kind_c64_2cbr_v(void) -{ - return 0x000000e7; -} -static inline u32 gmmu_pte_kind_c64_2cba_v(void) -{ - return 0x000000e8; -} -static inline u32 gmmu_pte_kind_c64_2cra_v(void) -{ - return 0x000000e9; -} -static inline u32 gmmu_pte_kind_c64_2bra_v(void) -{ - return 0x000000ea; -} -static inline u32 gmmu_pte_kind_c64_ms2_2c_v(void) -{ - return 0x000000eb; -} -static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) -{ - return 0x000000ec; -} -static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) -{ - return 0x000000cd; -} -static inline u32 gmmu_pte_kind_c64_ms4_2c_v(void) -{ - return 0x000000ed; -} -static inline u32 gmmu_pte_kind_c64_ms4_2cbr_v(void) -{ - return 0x000000ee; -} -static inline u32 gmmu_pte_kind_c64_ms4_2cba_v(void) -{ - return 0x000000ef; -} -static inline u32 gmmu_pte_kind_c64_ms4_2cra_v(void) -{ - return 0x000000f0; -} -static inline u32 gmmu_pte_kind_c64_ms4_2bra_v(void) -{ - return 0x000000f1; -} -static inline u32 gmmu_pte_kind_c64_ms4_4cbra_v(void) -{ - return 0x0000002d; -} -static inline u32 gmmu_pte_kind_c64_ms8_ms16_2c_v(void) -{ - return 0x000000f2; -} -static inline u32 gmmu_pte_kind_c64_ms8_ms16_2cra_v(void) -{ - return 0x000000f3; -} -static inline u32 gmmu_pte_kind_c128_2c_v(void) -{ - return 0x000000f4; -} -static inline u32 gmmu_pte_kind_c128_2cr_v(void) -{ - return 0x000000f5; -} -static inline u32 gmmu_pte_kind_c128_ms2_2c_v(void) -{ - return 0x000000f6; -} -static inline u32 gmmu_pte_kind_c128_ms2_2cr_v(void) -{ - return 0x000000f7; -} -static inline u32 gmmu_pte_kind_c128_ms4_2c_v(void) -{ - return 0x000000f8; -} -static inline u32 gmmu_pte_kind_c128_ms4_2cr_v(void) -{ - return 0x000000f9; -} -static inline u32 gmmu_pte_kind_c128_ms8_ms16_2c_v(void) -{ - return 0x000000fa; -} -static inline u32 gmmu_pte_kind_c128_ms8_ms16_2cr_v(void) -{ - return 0x000000fb; -} -static inline u32 gmmu_pte_kind_x8c24_v(void) -{ - return 0x000000fc; -} -static inline u32 gmmu_pte_kind_pitch_no_swizzle_v(void) -{ - return 0x000000fd; -} -static inline u32 gmmu_pte_kind_smsked_message_v(void) -{ - return 0x000000ca; -} -static inline u32 gmmu_pte_kind_smhost_message_v(void) -{ - return 0x000000cb; -} -static inline u32 gmmu_pte_kind_s8_v(void) -{ - return 0x0000002a; -} -static inline u32 gmmu_pte_kind_s8_2s_v(void) -{ - return 0x0000002b; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h deleted file mode 100644 index b3fd704b8..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ /dev/null @@ -1,4149 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_gr_gp10b_h_ -#define _hw_gr_gp10b_h_ - -static inline u32 gr_intr_r(void) -{ - return 0x00400100; -} -static inline u32 gr_intr_notify_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_intr_notify_reset_f(void) -{ - return 0x1; -} -static inline u32 gr_intr_semaphore_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_intr_semaphore_reset_f(void) -{ - return 0x2; -} -static inline u32 gr_intr_illegal_method_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_intr_illegal_method_reset_f(void) -{ - return 0x10; -} -static inline u32 gr_intr_illegal_notify_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_intr_illegal_notify_reset_f(void) -{ - return 0x40; -} -static inline u32 gr_intr_firmware_method_f(u32 v) -{ - return (v & 0x1) << 8; -} -static inline u32 gr_intr_firmware_method_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_intr_firmware_method_reset_f(void) -{ - return 0x100; -} -static inline u32 gr_intr_illegal_class_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_intr_illegal_class_reset_f(void) -{ - return 0x20; -} -static inline u32 gr_intr_fecs_error_pending_f(void) -{ - return 0x80000; -} -static inline u32 gr_intr_fecs_error_reset_f(void) -{ - return 0x80000; -} -static inline u32 gr_intr_class_error_pending_f(void) -{ - return 0x100000; -} -static inline u32 gr_intr_class_error_reset_f(void) -{ - return 0x100000; -} -static inline u32 gr_intr_exception_pending_f(void) -{ - return 0x200000; -} -static inline u32 gr_intr_exception_reset_f(void) -{ - return 0x200000; -} -static inline u32 gr_fecs_intr_r(void) -{ - return 0x00400144; -} -static inline u32 gr_class_error_r(void) -{ - return 0x00400110; -} -static inline u32 gr_class_error_code_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_intr_nonstall_r(void) -{ - return 0x00400120; -} -static inline u32 gr_intr_nonstall_trap_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_intr_en_r(void) -{ - return 0x0040013c; -} -static inline u32 gr_exception_r(void) -{ - return 0x00400108; -} -static inline u32 gr_exception_fe_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_exception_gpc_m(void) -{ - return 0x1 << 24; -} -static inline u32 gr_exception_memfmt_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_exception_ds_m(void) -{ - return 0x1 << 4; -} -static inline u32 gr_exception1_r(void) -{ - return 0x00400118; -} -static inline u32 gr_exception1_gpc_0_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_exception2_r(void) -{ - return 0x0040011c; -} -static inline u32 gr_exception_en_r(void) -{ - return 0x00400138; -} -static inline u32 gr_exception_en_fe_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_exception1_en_r(void) -{ - return 0x00400130; -} -static inline u32 gr_exception2_en_r(void) -{ - return 0x00400134; -} -static inline u32 gr_gpfifo_ctl_r(void) -{ - return 0x00400500; -} -static inline u32 gr_gpfifo_ctl_access_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpfifo_ctl_access_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_gpfifo_ctl_access_enabled_f(void) -{ - return 0x1; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpfifo_ctl_semaphore_access_enabled_f(void) -{ - return 0x10000; -} -static inline u32 gr_gpfifo_status_r(void) -{ - return 0x00400504; -} -static inline u32 gr_trapped_addr_r(void) -{ - return 0x00400704; -} -static inline u32 gr_trapped_addr_mthd_v(u32 r) -{ - return (r >> 2) & 0xfff; -} -static inline u32 gr_trapped_addr_subch_v(u32 r) -{ - return (r >> 16) & 0x7; -} -static inline u32 gr_trapped_data_lo_r(void) -{ - return 0x00400708; -} -static inline u32 gr_trapped_data_hi_r(void) -{ - return 0x0040070c; -} -static inline u32 gr_status_r(void) -{ - return 0x00400700; -} -static inline u32 gr_status_fe_method_upper_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_status_fe_method_lower_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 gr_status_fe_method_lower_idle_v(void) -{ - return 0x00000000; -} -static inline u32 gr_status_fe_gi_v(u32 r) -{ - return (r >> 21) & 0x1; -} -static inline u32 gr_status_mask_r(void) -{ - return 0x00400610; -} -static inline u32 gr_status_1_r(void) -{ - return 0x00400604; -} -static inline u32 gr_status_2_r(void) -{ - return 0x00400608; -} -static inline u32 gr_engine_status_r(void) -{ - return 0x0040060c; -} -static inline u32 gr_engine_status_value_busy_f(void) -{ - return 0x1; -} -static inline u32 gr_pri_be0_becs_be_exception_r(void) -{ - return 0x00410204; -} -static inline u32 gr_pri_be0_becs_be_exception_en_r(void) -{ - return 0x00410208; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_exception_en_r(void) -{ - return 0x00502c94; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450c; -} -static inline u32 gr_activity_0_r(void) -{ - return 0x00400380; -} -static inline u32 gr_activity_1_r(void) -{ - return 0x00400384; -} -static inline u32 gr_activity_2_r(void) -{ - return 0x00400388; -} -static inline u32 gr_activity_4_r(void) -{ - return 0x00400390; -} -static inline u32 gr_activity_4_gpc0_s(void) -{ - return 3; -} -static inline u32 gr_activity_4_gpc0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_activity_4_gpc0_m(void) -{ - return 0x7 << 0; -} -static inline u32 gr_activity_4_gpc0_v(u32 r) -{ - return (r >> 0) & 0x7; -} -static inline u32 gr_activity_4_gpc0_empty_v(void) -{ - return 0x00000000; -} -static inline u32 gr_activity_4_gpc0_preempted_v(void) -{ - return 0x00000004; -} -static inline u32 gr_pri_gpc0_gcc_dbg_r(void) -{ - return 0x00501000; -} -static inline u32 gr_pri_gpcs_gcc_dbg_r(void) -{ - return 0x00419000; -} -static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) -{ - return 0x005046a4; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) -{ - return 0x00419ea4; -} -static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_pri_sked_activity_r(void) -{ - return 0x00407054; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity0_r(void) -{ - return 0x00502c80; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity1_r(void) -{ - return 0x00502c84; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity2_r(void) -{ - return 0x00502c88; -} -static inline u32 gr_pri_gpc0_gpccs_gpc_activity3_r(void) -{ - return 0x00502c8c; -} -static inline u32 gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x00504500; -} -static inline u32 gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x00504d00; -} -static inline u32 gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00501d00; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_0_r(void) -{ - return 0x0041ac80; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_1_r(void) -{ - return 0x0041ac84; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_2_r(void) -{ - return 0x0041ac88; -} -static inline u32 gr_pri_gpcs_gpccs_gpc_activity_3_r(void) -{ - return 0x0041ac8c; -} -static inline u32 gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r(void) -{ - return 0x0041c500; -} -static inline u32 gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r(void) -{ - return 0x0041cd00; -} -static inline u32 gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r(void) -{ - return 0x00419d00; -} -static inline u32 gr_pri_be0_becs_be_activity0_r(void) -{ - return 0x00410200; -} -static inline u32 gr_pri_be1_becs_be_activity0_r(void) -{ - return 0x00410600; -} -static inline u32 gr_pri_bes_becs_be_activity0_r(void) -{ - return 0x00408a00; -} -static inline u32 gr_pri_ds_mpipe_status_r(void) -{ - return 0x00405858; -} -static inline u32 gr_pri_fe_go_idle_info_r(void) -{ - return 0x00404194; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) -{ - return 0x00504238; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) -{ - return 0x005046b8; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) -{ - return 0x80; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) -{ - return 0x200; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) -{ - return 0x400; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) -{ - return 0x800; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) -{ - return 0x005044a0; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) -{ - return 0x200; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) -{ - return 0x005046bc; -} -static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) -{ - return 0x005046c0; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) -{ - return 0x005044a4; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) -{ - return 0xff << 0; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) -{ - return 0xff << 8; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) -{ - return (r >> 8) & 0xff; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) -{ - return 0xff << 16; -} -static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) -{ - return 0x005042c4; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f(void) -{ - return 0x0; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f(void) -{ - return 0x1; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) -{ - return 0x2; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) -{ - return 0x00504218; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) -{ - return 0xffff << 0; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) -{ - return 0xffff << 16; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) -{ - return (r >> 16) & 0xffff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) -{ - return 0x005042ec; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) -{ - return 0xffff << 0; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) -{ - return 0xffff << 16; -} -static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) -{ - return (r >> 16) & 0xffff; -} -static inline u32 gr_pri_be0_crop_status1_r(void) -{ - return 0x00410134; -} -static inline u32 gr_pri_bes_crop_status1_r(void) -{ - return 0x00408934; -} -static inline u32 gr_pri_be0_zrop_status_r(void) -{ - return 0x00410048; -} -static inline u32 gr_pri_be0_zrop_status2_r(void) -{ - return 0x0041004c; -} -static inline u32 gr_pri_bes_zrop_status_r(void) -{ - return 0x00408848; -} -static inline u32 gr_pri_bes_zrop_status2_r(void) -{ - return 0x0040884c; -} -static inline u32 gr_pipe_bundle_address_r(void) -{ - return 0x00400200; -} -static inline u32 gr_pipe_bundle_address_value_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_pipe_bundle_data_r(void) -{ - return 0x00400204; -} -static inline u32 gr_pipe_bundle_config_r(void) -{ - return 0x00400208; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_pipe_bundle_config_override_pipe_mode_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 gr_fe_hww_esr_r(void) -{ - return 0x00404000; -} -static inline u32 gr_fe_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_fe_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_fe_go_idle_timeout_r(void) -{ - return 0x00404154; -} -static inline u32 gr_fe_go_idle_timeout_count_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) -{ - return 0x7fffffff; -} -static inline u32 gr_fe_object_table_r(u32 i) -{ - return 0x00404200 + i*4; -} -static inline u32 gr_fe_object_table_nvclass_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_fe_tpc_fs_r(void) -{ - return 0x004041c4; -} -static inline u32 gr_pri_mme_shadow_raw_index_r(void) -{ - return 0x00404488; -} -static inline u32 gr_pri_mme_shadow_raw_index_write_trigger_f(void) -{ - return 0x80000000; -} -static inline u32 gr_pri_mme_shadow_raw_data_r(void) -{ - return 0x0040448c; -} -static inline u32 gr_mme_hww_esr_r(void) -{ - return 0x00404490; -} -static inline u32 gr_mme_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_mme_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_memfmt_hww_esr_r(void) -{ - return 0x00404600; -} -static inline u32 gr_memfmt_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_memfmt_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_fecs_cpuctl_r(void) -{ - return 0x00409100; -} -static inline u32 gr_fecs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_fecs_cpuctl_alias_r(void) -{ - return 0x00409130; -} -static inline u32 gr_fecs_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_fecs_dmactl_r(void) -{ - return 0x0040910c; -} -static inline u32 gr_fecs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_fecs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_fecs_dmactl_imem_scrubbing_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_fecs_os_r(void) -{ - return 0x00409080; -} -static inline u32 gr_fecs_idlestate_r(void) -{ - return 0x0040904c; -} -static inline u32 gr_fecs_mailbox0_r(void) -{ - return 0x00409040; -} -static inline u32 gr_fecs_mailbox1_r(void) -{ - return 0x00409044; -} -static inline u32 gr_fecs_irqstat_r(void) -{ - return 0x00409008; -} -static inline u32 gr_fecs_irqmode_r(void) -{ - return 0x0040900c; -} -static inline u32 gr_fecs_irqmask_r(void) -{ - return 0x00409018; -} -static inline u32 gr_fecs_irqdest_r(void) -{ - return 0x0040901c; -} -static inline u32 gr_fecs_curctx_r(void) -{ - return 0x00409050; -} -static inline u32 gr_fecs_nxtctx_r(void) -{ - return 0x00409054; -} -static inline u32 gr_fecs_engctl_r(void) -{ - return 0x004090a4; -} -static inline u32 gr_fecs_debug1_r(void) -{ - return 0x00409090; -} -static inline u32 gr_fecs_debuginfo_r(void) -{ - return 0x00409094; -} -static inline u32 gr_fecs_icd_cmd_r(void) -{ - return 0x00409200; -} -static inline u32 gr_fecs_icd_cmd_opc_s(void) -{ - return 4; -} -static inline u32 gr_fecs_icd_cmd_opc_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_fecs_icd_cmd_opc_m(void) -{ - return 0xf << 0; -} -static inline u32 gr_fecs_icd_cmd_opc_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 gr_fecs_icd_cmd_opc_rreg_f(void) -{ - return 0x8; -} -static inline u32 gr_fecs_icd_cmd_opc_rstat_f(void) -{ - return 0xe; -} -static inline u32 gr_fecs_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 gr_fecs_icd_rdata_r(void) -{ - return 0x0040920c; -} -static inline u32 gr_fecs_imemc_r(u32 i) -{ - return 0x00409180 + i*16; -} -static inline u32 gr_fecs_imemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_fecs_imemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_fecs_imemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_fecs_imemd_r(u32 i) -{ - return 0x00409184 + i*16; -} -static inline u32 gr_fecs_imemt_r(u32 i) -{ - return 0x00409188 + i*16; -} -static inline u32 gr_fecs_imemt_tag_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_fecs_dmemc_r(u32 i) -{ - return 0x004091c0 + i*8; -} -static inline u32 gr_fecs_dmemc_offs_s(void) -{ - return 6; -} -static inline u32 gr_fecs_dmemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_fecs_dmemc_offs_m(void) -{ - return 0x3f << 2; -} -static inline u32 gr_fecs_dmemc_offs_v(u32 r) -{ - return (r >> 2) & 0x3f; -} -static inline u32 gr_fecs_dmemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_fecs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_fecs_dmemd_r(u32 i) -{ - return 0x004091c4 + i*8; -} -static inline u32 gr_fecs_dmatrfbase_r(void) -{ - return 0x00409110; -} -static inline u32 gr_fecs_dmatrfmoffs_r(void) -{ - return 0x00409114; -} -static inline u32 gr_fecs_dmatrffboffs_r(void) -{ - return 0x0040911c; -} -static inline u32 gr_fecs_dmatrfcmd_r(void) -{ - return 0x00409118; -} -static inline u32 gr_fecs_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 gr_fecs_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 gr_fecs_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_fecs_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_fecs_bootvec_r(void) -{ - return 0x00409104; -} -static inline u32 gr_fecs_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_falcon_hwcfg_r(void) -{ - return 0x00409108; -} -static inline u32 gr_gpcs_gpccs_falcon_hwcfg_r(void) -{ - return 0x0041a108; -} -static inline u32 gr_fecs_falcon_rm_r(void) -{ - return 0x00409084; -} -static inline u32 gr_fecs_current_ctx_r(void) -{ - return 0x00409b00; -} -static inline u32 gr_fecs_current_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_fecs_current_ctx_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 gr_fecs_current_ctx_target_s(void) -{ - return 2; -} -static inline u32 gr_fecs_current_ctx_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 gr_fecs_current_ctx_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_fecs_current_ctx_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 gr_fecs_current_ctx_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_current_ctx_valid_s(void) -{ - return 1; -} -static inline u32 gr_fecs_current_ctx_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_fecs_current_ctx_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_fecs_current_ctx_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_fecs_current_ctx_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_method_data_r(void) -{ - return 0x00409500; -} -static inline u32 gr_fecs_method_push_r(void) -{ - return 0x00409504; -} -static inline u32 gr_fecs_method_push_adr_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_v(void) -{ - return 0x00000003; -} -static inline u32 gr_fecs_method_push_adr_bind_pointer_f(void) -{ - return 0x3; -} -static inline u32 gr_fecs_method_push_adr_discover_image_size_v(void) -{ - return 0x00000010; -} -static inline u32 gr_fecs_method_push_adr_wfi_golden_save_v(void) -{ - return 0x00000009; -} -static inline u32 gr_fecs_method_push_adr_restore_golden_v(void) -{ - return 0x00000015; -} -static inline u32 gr_fecs_method_push_adr_discover_zcull_image_size_v(void) -{ - return 0x00000016; -} -static inline u32 gr_fecs_method_push_adr_discover_pm_image_size_v(void) -{ - return 0x00000025; -} -static inline u32 gr_fecs_method_push_adr_discover_reglist_image_size_v(void) -{ - return 0x00000030; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_bind_instance_v(void) -{ - return 0x00000031; -} -static inline u32 gr_fecs_method_push_adr_set_reglist_virtual_address_v(void) -{ - return 0x00000032; -} -static inline u32 gr_fecs_method_push_adr_stop_ctxsw_v(void) -{ - return 0x00000038; -} -static inline u32 gr_fecs_method_push_adr_start_ctxsw_v(void) -{ - return 0x00000039; -} -static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) -{ - return 0x21; -} -static inline u32 gr_fecs_method_push_adr_write_timestamp_record_v(void) -{ - return 0x0000003d; -} -static inline u32 gr_fecs_method_push_adr_discover_preemption_image_size_v(void) -{ - return 0x0000001a; -} -static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void) -{ - return 0x00000004; -} -static inline u32 gr_fecs_method_push_adr_configure_interrupt_completion_option_v(void) -{ - return 0x0000003a; -} -static inline u32 gr_fecs_host_int_status_r(void) -{ - return 0x00409c18; -} -static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) -{ - return (v & 0x1) << 17; -} -static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) -{ - return (v & 0x1) << 18; -} -static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_fecs_host_int_clear_r(void) -{ - return 0x00409c20; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) -{ - return 0x2; -} -static inline u32 gr_fecs_host_int_enable_r(void) -{ - return 0x00409c24; -} -static inline u32 gr_fecs_host_int_enable_ctxsw_intr1_enable_f(void) -{ - return 0x2; -} -static inline u32 gr_fecs_host_int_enable_fault_during_ctxsw_enable_f(void) -{ - return 0x10000; -} -static inline u32 gr_fecs_host_int_enable_umimp_firmware_method_enable_f(void) -{ - return 0x20000; -} -static inline u32 gr_fecs_host_int_enable_umimp_illegal_method_enable_f(void) -{ - return 0x40000; -} -static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) -{ - return 0x80000; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) -{ - return 0x00409614; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_halt_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_halt_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_halt_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_engine_reset_disabled_f(void) -{ - return 0x10; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_engine_reset_disabled_f(void) -{ - return 0x20; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_engine_reset_disabled_f(void) -{ - return 0x40; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_enabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_sys_context_reset_disabled_f(void) -{ - return 0x100; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_enabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_gpc_context_reset_disabled_f(void) -{ - return 0x200; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_s(void) -{ - return 1; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_f(u32 v) -{ - return (v & 0x1) << 10; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_m(void) -{ - return 0x1 << 10; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_v(u32 r) -{ - return (r >> 10) & 0x1; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_enabled_f(void) -{ - return 0x0; -} -static inline u32 gr_fecs_ctxsw_reset_ctl_be_context_reset_disabled_f(void) -{ - return 0x400; -} -static inline u32 gr_fecs_ctx_state_store_major_rev_id_r(void) -{ - return 0x0040960c; -} -static inline u32 gr_fecs_ctxsw_mailbox_r(u32 i) -{ - return 0x00409800 + i*4; -} -static inline u32 gr_fecs_ctxsw_mailbox__size_1_v(void) -{ - return 0x00000010; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_pass_v(void) -{ - return 0x00000001; -} -static inline u32 gr_fecs_ctxsw_mailbox_value_fail_v(void) -{ - return 0x00000002; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_r(u32 i) -{ - return 0x004098c0 + i*4; -} -static inline u32 gr_fecs_ctxsw_mailbox_set_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_r(u32 i) -{ - return 0x00409840 + i*4; -} -static inline u32 gr_fecs_ctxsw_mailbox_clear_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fecs_fs_r(void) -{ - return 0x00409604; -} -static inline u32 gr_fecs_fs_num_available_gpcs_s(void) -{ - return 5; -} -static inline u32 gr_fecs_fs_num_available_gpcs_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 gr_fecs_fs_num_available_gpcs_m(void) -{ - return 0x1f << 0; -} -static inline u32 gr_fecs_fs_num_available_gpcs_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gr_fecs_fs_num_available_fbps_s(void) -{ - return 5; -} -static inline u32 gr_fecs_fs_num_available_fbps_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 gr_fecs_fs_num_available_fbps_m(void) -{ - return 0x1f << 16; -} -static inline u32 gr_fecs_fs_num_available_fbps_v(u32 r) -{ - return (r >> 16) & 0x1f; -} -static inline u32 gr_fecs_cfg_r(void) -{ - return 0x00409620; -} -static inline u32 gr_fecs_cfg_imem_sz_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_fecs_rc_lanes_r(void) -{ - return 0x00409880; -} -static inline u32 gr_fecs_rc_lanes_num_chains_s(void) -{ - return 6; -} -static inline u32 gr_fecs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 gr_fecs_rc_lanes_num_chains_m(void) -{ - return 0x3f << 0; -} -static inline u32 gr_fecs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 gr_fecs_ctxsw_status_1_r(void) -{ - return 0x00409400; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_s(void) -{ - return 1; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_f(u32 v) -{ - return (v & 0x1) << 12; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_m(void) -{ - return 0x1 << 12; -} -static inline u32 gr_fecs_ctxsw_status_1_arb_busy_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 gr_fecs_arb_ctx_adr_r(void) -{ - return 0x00409a24; -} -static inline u32 gr_fecs_new_ctx_r(void) -{ - return 0x00409b04; -} -static inline u32 gr_fecs_new_ctx_ptr_s(void) -{ - return 28; -} -static inline u32 gr_fecs_new_ctx_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_fecs_new_ctx_ptr_m(void) -{ - return 0xfffffff << 0; -} -static inline u32 gr_fecs_new_ctx_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 gr_fecs_new_ctx_target_s(void) -{ - return 2; -} -static inline u32 gr_fecs_new_ctx_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 gr_fecs_new_ctx_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_fecs_new_ctx_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 gr_fecs_new_ctx_valid_s(void) -{ - return 1; -} -static inline u32 gr_fecs_new_ctx_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_fecs_new_ctx_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_fecs_new_ctx_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_fecs_arb_ctx_ptr_r(void) -{ - return 0x00409a0c; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_s(void) -{ - return 28; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_m(void) -{ - return 0xfffffff << 0; -} -static inline u32 gr_fecs_arb_ctx_ptr_ptr_v(u32 r) -{ - return (r >> 0) & 0xfffffff; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_s(void) -{ - return 2; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_fecs_arb_ctx_ptr_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 gr_fecs_arb_ctx_cmd_r(void) -{ - return 0x00409a10; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_s(void) -{ - return 5; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_m(void) -{ - return 0x1f << 0; -} -static inline u32 gr_fecs_arb_ctx_cmd_cmd_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gr_fecs_ctxsw_status_fe_0_r(void) -{ - return 0x00409c00; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_gpc_0_r(void) -{ - return 0x00502c04; -} -static inline u32 gr_gpc0_gpccs_ctxsw_status_1_r(void) -{ - return 0x00502400; -} -static inline u32 gr_fecs_ctxsw_idlestate_r(void) -{ - return 0x00409420; -} -static inline u32 gr_fecs_feature_override_ecc_r(void) -{ - return 0x00409658; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) -{ - return (r >> 3) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) -{ - return (r >> 7) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) -{ - return (r >> 11) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) -{ - return (r >> 15) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) -{ - return (r >> 8) & 0x1; -} -static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) -{ - return (r >> 12) & 0x1; -} -static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) -{ - return 0x00502420; -} -static inline u32 gr_rstr2d_gpc_map0_r(void) -{ - return 0x0040780c; -} -static inline u32 gr_rstr2d_gpc_map1_r(void) -{ - return 0x00407810; -} -static inline u32 gr_rstr2d_gpc_map2_r(void) -{ - return 0x00407814; -} -static inline u32 gr_rstr2d_gpc_map3_r(void) -{ - return 0x00407818; -} -static inline u32 gr_rstr2d_gpc_map4_r(void) -{ - return 0x0040781c; -} -static inline u32 gr_rstr2d_gpc_map5_r(void) -{ - return 0x00407820; -} -static inline u32 gr_rstr2d_map_table_cfg_r(void) -{ - return 0x004078bc; -} -static inline u32 gr_rstr2d_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_rstr2d_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_pd_hww_esr_r(void) -{ - return 0x00406018; -} -static inline u32 gr_pd_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_pd_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_pd_num_tpc_per_gpc_r(u32 i) -{ - return 0x00406028 + i*4; -} -static inline u32 gr_pd_num_tpc_per_gpc__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 gr_pd_num_tpc_per_gpc_count0_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_pd_num_tpc_per_gpc_count1_f(u32 v) -{ - return (v & 0xf) << 4; -} -static inline u32 gr_pd_num_tpc_per_gpc_count2_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 gr_pd_num_tpc_per_gpc_count3_f(u32 v) -{ - return (v & 0xf) << 12; -} -static inline u32 gr_pd_num_tpc_per_gpc_count4_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 gr_pd_num_tpc_per_gpc_count5_f(u32 v) -{ - return (v & 0xf) << 20; -} -static inline u32 gr_pd_num_tpc_per_gpc_count6_f(u32 v) -{ - return (v & 0xf) << 24; -} -static inline u32 gr_pd_num_tpc_per_gpc_count7_f(u32 v) -{ - return (v & 0xf) << 28; -} -static inline u32 gr_pd_ab_dist_cfg0_r(void) -{ - return 0x004064c0; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_en_f(void) -{ - return 0x80000000; -} -static inline u32 gr_pd_ab_dist_cfg0_timeslice_enable_dis_f(void) -{ - return 0x0; -} -static inline u32 gr_pd_ab_dist_cfg1_r(void) -{ - return 0x004064c4; -} -static inline u32 gr_pd_ab_dist_cfg1_max_batches_init_f(void) -{ - return 0xffff; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_f(u32 v) -{ - return (v & 0xffff) << 16; -} -static inline u32 gr_pd_ab_dist_cfg1_max_output_granularity_v(void) -{ - return 0x00000080; -} -static inline u32 gr_pd_ab_dist_cfg2_r(void) -{ - return 0x004064c8; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) -{ - return (v & 0x1fff) << 0; -} -static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) -{ - return 0x000001c0; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) -{ - return (v & 0x1fff) << 16; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) -{ - return 0x00000020; -} -static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) -{ - return 0x00000182; -} -static inline u32 gr_pd_dist_skip_table_r(u32 i) -{ - return 0x004064d0 + i*4; -} -static inline u32 gr_pd_dist_skip_table__size_1_v(void) -{ - return 0x00000008; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n0_mask_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n1_mask_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n2_mask_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 gr_pd_dist_skip_table_gpc_4n3_mask_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 gr_ds_debug_r(void) -{ - return 0x00405800; -} -static inline u32 gr_ds_debug_timeslice_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_debug_timeslice_mode_enable_f(void) -{ - return 0x8000000; -} -static inline u32 gr_ds_zbc_color_r_r(void) -{ - return 0x00405804; -} -static inline u32 gr_ds_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_g_r(void) -{ - return 0x00405808; -} -static inline u32 gr_ds_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_b_r(void) -{ - return 0x0040580c; -} -static inline u32 gr_ds_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_a_r(void) -{ - return 0x00405810; -} -static inline u32 gr_ds_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_color_fmt_r(void) -{ - return 0x00405814; -} -static inline u32 gr_ds_zbc_color_fmt_val_f(u32 v) -{ - return (v & 0x7f) << 0; -} -static inline u32 gr_ds_zbc_color_fmt_val_invalid_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_color_fmt_val_zero_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_zbc_color_fmt_val_unorm_one_v(void) -{ - return 0x00000002; -} -static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void) -{ - return 0x00000004; -} -static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void) -{ - return 0x00000028; -} -static inline u32 gr_ds_zbc_z_r(void) -{ - return 0x00405818; -} -static inline u32 gr_ds_zbc_z_val_s(void) -{ - return 32; -} -static inline u32 gr_ds_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_ds_zbc_z_val_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 gr_ds_zbc_z_val_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gr_ds_zbc_z_val__init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_ds_zbc_z_val__init_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_z_fmt_r(void) -{ - return 0x0040581c; -} -static inline u32 gr_ds_zbc_z_fmt_val_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_ds_zbc_z_fmt_val_invalid_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_z_fmt_val_fp32_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_zbc_tbl_index_r(void) -{ - return 0x00405820; -} -static inline u32 gr_ds_zbc_tbl_index_val_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_ds_zbc_tbl_ld_r(void) -{ - return 0x00405824; -} -static inline u32 gr_ds_zbc_tbl_ld_select_c_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_tbl_ld_select_z_f(void) -{ - return 0x1; -} -static inline u32 gr_ds_zbc_tbl_ld_action_write_f(void) -{ - return 0x0; -} -static inline u32 gr_ds_zbc_tbl_ld_trigger_active_f(void) -{ - return 0x4; -} -static inline u32 gr_ds_tga_constraintlogic_beta_r(void) -{ - return 0x00405830; -} -static inline u32 gr_ds_tga_constraintlogic_beta_cbsize_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_r(void) -{ - return 0x0040585c; -} -static inline u32 gr_ds_tga_constraintlogic_alpha_cbsize_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_ds_hww_esr_r(void) -{ - return 0x00405840; -} -static inline u32 gr_ds_hww_esr_reset_s(void) -{ - return 1; -} -static inline u32 gr_ds_hww_esr_reset_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 gr_ds_hww_esr_reset_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_ds_hww_esr_reset_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_ds_hww_esr_reset_task_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_hww_esr_reset_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_ds_hww_esr_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 gr_ds_hww_esr_2_r(void) -{ - return 0x00405848; -} -static inline u32 gr_ds_hww_esr_2_reset_s(void) -{ - return 1; -} -static inline u32 gr_ds_hww_esr_2_reset_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 gr_ds_hww_esr_2_reset_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_ds_hww_esr_2_reset_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_ds_hww_esr_2_reset_task_v(void) -{ - return 0x00000001; -} -static inline u32 gr_ds_hww_esr_2_reset_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_ds_hww_esr_2_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 gr_ds_hww_report_mask_r(void) -{ - return 0x00405844; -} -static inline u32 gr_ds_hww_report_mask_sph0_err_report_f(void) -{ - return 0x1; -} -static inline u32 gr_ds_hww_report_mask_sph1_err_report_f(void) -{ - return 0x2; -} -static inline u32 gr_ds_hww_report_mask_sph2_err_report_f(void) -{ - return 0x4; -} -static inline u32 gr_ds_hww_report_mask_sph3_err_report_f(void) -{ - return 0x8; -} -static inline u32 gr_ds_hww_report_mask_sph4_err_report_f(void) -{ - return 0x10; -} -static inline u32 gr_ds_hww_report_mask_sph5_err_report_f(void) -{ - return 0x20; -} -static inline u32 gr_ds_hww_report_mask_sph6_err_report_f(void) -{ - return 0x40; -} -static inline u32 gr_ds_hww_report_mask_sph7_err_report_f(void) -{ - return 0x80; -} -static inline u32 gr_ds_hww_report_mask_sph8_err_report_f(void) -{ - return 0x100; -} -static inline u32 gr_ds_hww_report_mask_sph9_err_report_f(void) -{ - return 0x200; -} -static inline u32 gr_ds_hww_report_mask_sph10_err_report_f(void) -{ - return 0x400; -} -static inline u32 gr_ds_hww_report_mask_sph11_err_report_f(void) -{ - return 0x800; -} -static inline u32 gr_ds_hww_report_mask_sph12_err_report_f(void) -{ - return 0x1000; -} -static inline u32 gr_ds_hww_report_mask_sph13_err_report_f(void) -{ - return 0x2000; -} -static inline u32 gr_ds_hww_report_mask_sph14_err_report_f(void) -{ - return 0x4000; -} -static inline u32 gr_ds_hww_report_mask_sph15_err_report_f(void) -{ - return 0x8000; -} -static inline u32 gr_ds_hww_report_mask_sph16_err_report_f(void) -{ - return 0x10000; -} -static inline u32 gr_ds_hww_report_mask_sph17_err_report_f(void) -{ - return 0x20000; -} -static inline u32 gr_ds_hww_report_mask_sph18_err_report_f(void) -{ - return 0x40000; -} -static inline u32 gr_ds_hww_report_mask_sph19_err_report_f(void) -{ - return 0x80000; -} -static inline u32 gr_ds_hww_report_mask_sph20_err_report_f(void) -{ - return 0x100000; -} -static inline u32 gr_ds_hww_report_mask_sph21_err_report_f(void) -{ - return 0x200000; -} -static inline u32 gr_ds_hww_report_mask_sph22_err_report_f(void) -{ - return 0x400000; -} -static inline u32 gr_ds_hww_report_mask_sph23_err_report_f(void) -{ - return 0x800000; -} -static inline u32 gr_ds_hww_report_mask_2_r(void) -{ - return 0x0040584c; -} -static inline u32 gr_ds_hww_report_mask_2_sph24_err_report_f(void) -{ - return 0x1; -} -static inline u32 gr_ds_num_tpc_per_gpc_r(u32 i) -{ - return 0x00405870 + i*4; -} -static inline u32 gr_scc_bundle_cb_base_r(void) -{ - return 0x00408004; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_scc_bundle_cb_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008; -} -static inline u32 gr_scc_bundle_cb_size_r(void) -{ - return 0x00408008; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ff) << 0; -} -static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) -{ - return 0x00000018; -} -static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) -{ - return 0x00000100; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000; -} -static inline u32 gr_scc_bundle_cb_size_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gr_scc_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_scc_pagepool_base_r(void) -{ - return 0x0040800c; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_scc_pagepool_base_addr_39_8_align_bits_v(void) -{ - return 0x00000008; -} -static inline u32 gr_scc_pagepool_r(void) -{ - return 0x00408010; -} -static inline u32 gr_scc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_v(void) -{ - return 0x00000000; -} -static inline u32 gr_scc_pagepool_total_pages_hwmax_value_v(void) -{ - return 0x00000200; -} -static inline u32 gr_scc_pagepool_total_pages_byte_granularity_v(void) -{ - return 0x00000100; -} -static inline u32 gr_scc_pagepool_max_valid_pages_s(void) -{ - return 10; -} -static inline u32 gr_scc_pagepool_max_valid_pages_f(u32 v) -{ - return (v & 0x3ff) << 10; -} -static inline u32 gr_scc_pagepool_max_valid_pages_m(void) -{ - return 0x3ff << 10; -} -static inline u32 gr_scc_pagepool_max_valid_pages_v(u32 r) -{ - return (r >> 10) & 0x3ff; -} -static inline u32 gr_scc_pagepool_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_scc_init_r(void) -{ - return 0x0040802c; -} -static inline u32 gr_scc_init_ram_trigger_f(void) -{ - return 0x1; -} -static inline u32 gr_scc_hww_esr_r(void) -{ - return 0x00408030; -} -static inline u32 gr_scc_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_scc_hww_esr_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_sked_hww_esr_r(void) -{ - return 0x00407020; -} -static inline u32 gr_sked_hww_esr_reset_active_f(void) -{ - return 0x40000000; -} -static inline u32 gr_cwd_fs_r(void) -{ - return 0x00405b00; -} -static inline u32 gr_cwd_fs_num_gpcs_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_cwd_fs_num_tpcs_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_cwd_gpc_tpc_id_r(u32 i) -{ - return 0x00405b60 + i*4; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc0_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_cwd_gpc_tpc_id_tpc1_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 gr_cwd_sm_id_r(u32 i) -{ - return 0x00405ba0 + i*4; -} -static inline u32 gr_cwd_sm_id_tpc0_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_cwd_sm_id_tpc1_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpc0_fs_gpc_r(void) -{ - return 0x00502608; -} -static inline u32 gr_gpc0_fs_gpc_num_available_tpcs_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 gr_gpc0_fs_gpc_num_available_zculls_v(u32 r) -{ - return (r >> 16) & 0x1f; -} -static inline u32 gr_gpc0_cfg_r(void) -{ - return 0x00502620; -} -static inline u32 gr_gpc0_cfg_imem_sz_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_gpccs_rc_lanes_r(void) -{ - return 0x00502880; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_s(void) -{ - return 6; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_m(void) -{ - return 0x3f << 0; -} -static inline u32 gr_gpccs_rc_lanes_num_chains_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 gr_gpccs_rc_lane_size_r(void) -{ - return 0x00502910; -} -static inline u32 gr_gpccs_rc_lane_size_v_s(void) -{ - return 24; -} -static inline u32 gr_gpccs_rc_lane_size_v_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 gr_gpccs_rc_lane_size_v_m(void) -{ - return 0xffffff << 0; -} -static inline u32 gr_gpccs_rc_lane_size_v_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpccs_rc_lane_size_v_0_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_zcull_fs_r(void) -{ - return 0x00500910; -} -static inline u32 gr_gpc0_zcull_fs_num_sms_f(u32 v) -{ - return (v & 0x1ff) << 0; -} -static inline u32 gr_gpc0_zcull_fs_num_active_banks_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 gr_gpc0_zcull_ram_addr_r(void) -{ - return 0x00500914; -} -static inline u32 gr_gpc0_zcull_ram_addr_tiles_per_hypertile_row_per_gpc_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_gpc0_zcull_ram_addr_row_offset_f(u32 v) -{ - return (v & 0xf) << 8; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_r(void) -{ - return 0x00500918; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 gr_gpc0_zcull_sm_num_rcp_conservative__max_v(void) -{ - return 0x00800000; -} -static inline u32 gr_gpc0_zcull_total_ram_size_r(void) -{ - return 0x00500920; -} -static inline u32 gr_gpc0_zcull_total_ram_size_num_aliquots_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_zcull_zcsize_r(u32 i) -{ - return 0x00500a04 + i*32; -} -static inline u32 gr_gpc0_zcull_zcsize_height_subregion__multiple_v(void) -{ - return 0x00000040; -} -static inline u32 gr_gpc0_zcull_zcsize_width_subregion__multiple_v(void) -{ - return 0x00000010; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_r(u32 i) -{ - return 0x00500c10 + i*4; -} -static inline u32 gr_gpc0_gpm_pd_sm_id_id_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_r(u32 i) -{ - return 0x00500c30 + i*4; -} -static inline u32 gr_gpc0_gpm_pd_pes_tpc_id_mask_mask_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_r(void) -{ - return 0x00504088; -} -static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) -{ - return 0x00504698; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_gpc0_tpc0_sm_arch_r(void) -{ - return 0x0050469c; -} -static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 gr_gpc0_tpc0_sm_arch_spa_version_v(u32 r) -{ - return (r >> 8) & 0xfff; -} -static inline u32 gr_gpc0_tpc0_sm_arch_sm_version_v(u32 r) -{ - return (r >> 20) & 0xfff; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_r(void) -{ - return 0x00503018; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpc0_ppc0_pes_vsc_strem_master_pe_true_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_r(void) -{ - return 0x005030c0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) -{ - return 0x3fffff << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) -{ - return 0x00030000; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) -{ - return 0x00030a00; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) -{ - return 0x00000020; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_cb_offset_r(void) -{ - return 0x005030f4; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_r(void) -{ - return 0x005030e4; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_m(void) -{ - return 0xffff << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(void) -{ - return 0x00000800; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_size_v_granularity_v(void) -{ - return 0x00000020; -} -static inline u32 gr_gpc0_ppc0_cbm_alpha_cb_offset_r(void) -{ - return 0x005030f8; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void) -{ - return 0x005030f0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) -{ - return 0x00030000; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) -{ - return 0x00419b00; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) -{ - return 0x00419b04; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) -{ - return 21; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v) -{ - return (v & 0x1fffff) << 0; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void) -{ - return 0x1fffff << 0; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r) -{ - return (r >> 0) & 0x1fffff; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void) -{ - return 0x80; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void) -{ - return 1; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpccs_falcon_addr_r(void) -{ - return 0x0041a0ac; -} -static inline u32 gr_gpccs_falcon_addr_lsb_s(void) -{ - return 6; -} -static inline u32 gr_gpccs_falcon_addr_lsb_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 gr_gpccs_falcon_addr_lsb_m(void) -{ - return 0x3f << 0; -} -static inline u32 gr_gpccs_falcon_addr_lsb_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpccs_falcon_addr_lsb_init_f(void) -{ - return 0x0; -} -static inline u32 gr_gpccs_falcon_addr_msb_s(void) -{ - return 6; -} -static inline u32 gr_gpccs_falcon_addr_msb_f(u32 v) -{ - return (v & 0x3f) << 6; -} -static inline u32 gr_gpccs_falcon_addr_msb_m(void) -{ - return 0x3f << 6; -} -static inline u32 gr_gpccs_falcon_addr_msb_v(u32 r) -{ - return (r >> 6) & 0x3f; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpccs_falcon_addr_msb_init_f(void) -{ - return 0x0; -} -static inline u32 gr_gpccs_falcon_addr_ext_s(void) -{ - return 12; -} -static inline u32 gr_gpccs_falcon_addr_ext_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_gpccs_falcon_addr_ext_m(void) -{ - return 0xfff << 0; -} -static inline u32 gr_gpccs_falcon_addr_ext_v(u32 r) -{ - return (r >> 0) & 0xfff; -} -static inline u32 gr_gpccs_cpuctl_r(void) -{ - return 0x0041a100; -} -static inline u32 gr_gpccs_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 gr_gpccs_dmactl_r(void) -{ - return 0x0041a10c; -} -static inline u32 gr_gpccs_dmactl_require_ctx_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpccs_dmactl_dmem_scrubbing_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_gpccs_dmactl_imem_scrubbing_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_gpccs_imemc_r(u32 i) -{ - return 0x0041a180 + i*16; -} -static inline u32 gr_gpccs_imemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_gpccs_imemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpccs_imemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_gpccs_imemd_r(u32 i) -{ - return 0x0041a184 + i*16; -} -static inline u32 gr_gpccs_imemt_r(u32 i) -{ - return 0x0041a188 + i*16; -} -static inline u32 gr_gpccs_imemt__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 gr_gpccs_imemt_tag_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpccs_dmemc_r(u32 i) -{ - return 0x0041a1c0 + i*8; -} -static inline u32 gr_gpccs_dmemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 gr_gpccs_dmemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpccs_dmemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 gr_gpccs_dmemd_r(u32 i) -{ - return 0x0041a1c4 + i*8; -} -static inline u32 gr_gpccs_ctxsw_mailbox_r(u32 i) -{ - return 0x0041a800 + i*4; -} -static inline u32 gr_gpccs_ctxsw_mailbox_value_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_r(void) -{ - return 0x00418e24; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_s(void) -{ - return 32; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpcs_swdx_bundle_cb_base_addr_39_8_init_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_r(void) -{ - return 0x00418e28; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_s(void) -{ - return 11; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_f(u32 v) -{ - return (v & 0x7ff) << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_m(void) -{ - return 0x7ff << 0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) -{ - return (r >> 0) & 0x7ff; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) -{ - return 0x00000018; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) -{ - return 0x18; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) -{ - return 1; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_false_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) -{ - return 0x00500ee4; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) -{ - return (v & 0xffff) << 0; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) -{ - return 0x00000250; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) -{ - return 0x00000100; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) -{ - return 0x00500ee0; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) -{ - return 0x00000008; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) -{ - return 0x00418eec; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_gfxp_v(void) -{ - return 0x00000100; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_r(void) -{ - return 0x0041befc; -} -static inline u32 gr_gpcs_ppcs_cbm_beta_cb_ctrl_cbes_reserve_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_r(u32 i) -{ - return 0x00418ea0 + i*4; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_f(u32 v) -{ - return (v & 0x3fffff) << 0; -} -static inline u32 gr_gpcs_swdx_tc_beta_cb_size_v_m(void) -{ - return 0x3fffff << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_r(u32 i) -{ - return 0x00418010 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_r_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_r(u32 i) -{ - return 0x0041804c + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_g_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_r(u32 i) -{ - return 0x00418088 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_b_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_r(u32 i) -{ - return 0x004180c4 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_color_a_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(void) -{ - return 0x00500100; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_r(u32 i) -{ - return 0x00418110 + i*4; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(void) -{ - return 0x0050014c; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_r(void) -{ - return 0x00418810; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_addr_39_12_align_bits_v(void) -{ - return 0x0000000c; -} -static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 gr_crstr_gpc_map0_r(void) -{ - return 0x00418b08; -} -static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map1_r(void) -{ - return 0x00418b0c; -} -static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map2_r(void) -{ - return 0x00418b10; -} -static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map3_r(void) -{ - return 0x00418b14; -} -static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map4_r(void) -{ - return 0x00418b18; -} -static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_gpc_map5_r(void) -{ - return 0x00418b1c; -} -static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) -{ - return (v & 0x7) << 5; -} -static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) -{ - return (v & 0x7) << 10; -} -static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) -{ - return (v & 0x7) << 15; -} -static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) -{ - return (v & 0x7) << 25; -} -static inline u32 gr_crstr_map_table_cfg_r(void) -{ - return 0x00418bb8; -} -static inline u32 gr_crstr_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) -{ - return 0x00418980; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) -{ - return 0x00418984; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) -{ - return 0x00418988; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) -{ - return 3; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) -{ - return 0x7 << 28; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) -{ - return (r >> 28) & 0x7; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) -{ - return 0x0041898c; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) -{ - return (v & 0x7) << 0; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) -{ - return (v & 0x7) << 4; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) -{ - return (v & 0x7) << 16; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) -{ - return (v & 0x7) << 20; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) -{ - return (v & 0x7) << 24; -} -static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) -{ - return (v & 0x7) << 28; -} -static inline u32 gr_gpcs_gpm_pd_cfg_r(void) -{ - return 0x00418c6c; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) -{ - return 0x1; -} -static inline u32 gr_gpcs_gcc_pagepool_base_r(void) -{ - return 0x00419004; -} -static inline u32 gr_gpcs_gcc_pagepool_base_addr_39_8_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_gpcs_gcc_pagepool_r(void) -{ - return 0x00419008; -} -static inline u32 gr_gpcs_gcc_pagepool_total_pages_f(u32 v) -{ - return (v & 0x3ff) << 0; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_r(void) -{ - return 0x0041980c; -} -static inline u32 gr_gpcs_tpcs_pe_vaf_fast_mode_switch_true_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_r(void) -{ - return 0x00419848; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 gr_gpcs_tpcs_pe_pin_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_r(void) -{ - return 0x00419c00; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_debug_timeslice_mode_enabled_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(void) -{ - return 0x00419c2c; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_f(u32 v) -{ - return (v & 0x1) << 28; -} -static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) -{ - return 0x10000000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) -{ - return 0x00419e44; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) -{ - return 0x80; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) -{ - return 0x100; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) -{ - return 0x200; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) -{ - return 0x400; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) -{ - return 0x800; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) -{ - return 0x1000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) -{ - return 0x2000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) -{ - return 0x4000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) -{ - return 0x8000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) -{ - return 0x10000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) -{ - return 0x20000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) -{ - return 0x40000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) -{ - return 0x800000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) -{ - return 0x400000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) -{ - return 0x80000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) -{ - return 0x100000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) -{ - return 0x00419e4c; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) -{ - return 0x1; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) -{ - return 0x20000000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) -{ - return 0x40000000; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_r(void) -{ - return 0x00419d0c; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_tpccs_tpc_exception_en_tex_enabled_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) -{ - return 0x0050450c; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) -{ - return 0x0041ac94; -} -static inline u32 gr_gpcs_gpccs_gpc_exception_en_tpc_f(u32 v) -{ - return (v & 0xff) << 16; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_r(void) -{ - return 0x00502c90; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 gr_gpc0_gpccs_gpc_exception_tpc_0_pending_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_r(void) -{ - return 0x00504508; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_tex_pending_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) -{ - return 0x00504610; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) -{ - return (r >> 1) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) -{ - return 0x00504614; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) -{ - return 0x00504624; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) -{ - return 0x00504634; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) -{ - return 0x0050460c; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) -{ - return 0x00419e50; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) -{ - return 0x00504650; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) -{ - return 0x10; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) -{ - return 0x20000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) -{ - return 0x40000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) -{ - return 0x20; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) -{ - return 0x40; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) -{ - return 0x00504224; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) -{ - return 0x80; -} -static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) -{ - return 0x100; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) -{ - return 0x1; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) -{ - return 0x2; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) -{ - return 0x4; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) -{ - return 0x8; -} -static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) -{ - return 0x00504648; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) -{ - return 0x1 << 24; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) -{ - return 0x7 << 25; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) -{ - return 0x0; -} -static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) -{ - return 0x00504654; -} -static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) -{ - return 0x00504770; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) -{ - return 0x00419f70; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) -{ - return 0x1 << 4; -} -static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) -{ - return 0x0050477c; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) -{ - return 0x00419f7c; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_r(void) -{ - return 0x0041be08; -} -static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) -{ - return 0x4; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) -{ - return 0x0041bf00; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) -{ - return 0x0041bf04; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) -{ - return 0x0041bf08; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) -{ - return 0x0041bf0c; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) -{ - return 0x0041bf10; -} -static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) -{ - return 0x0041bf14; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) -{ - return 0x0041bfd0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_row_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_num_entries_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_num_entries_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) -{ - return (v & 0x7) << 21; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) -{ - return (v & 0x1f) << 24; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) -{ - return 0x0041bfd4; -} -static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) -{ - return 0x0041bfe4; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) -{ - return (v & 0x1f) << 0; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) -{ - return (v & 0x1f) << 5; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) -{ - return (v & 0x1f) << 10; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) -{ - return (v & 0x1f) << 15; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) -{ - return (v & 0x1f) << 20; -} -static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) -{ - return (v & 0x1f) << 25; -} -static inline u32 gr_bes_zrop_settings_r(void) -{ - return 0x00408850; -} -static inline u32 gr_bes_zrop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_be0_crop_debug3_r(void) -{ - return 0x00410108; -} -static inline u32 gr_bes_crop_debug3_r(void) -{ - return 0x00408908; -} -static inline u32 gr_bes_crop_debug3_comp_vdc_4to2_disable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_bes_crop_settings_r(void) -{ - return 0x00408958; -} -static inline u32 gr_bes_crop_settings_num_active_ltcs_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 gr_zcull_bytes_per_aliquot_per_gpu_v(void) -{ - return 0x00000020; -} -static inline u32 gr_zcull_save_restore_header_bytes_per_gpc_v(void) -{ - return 0x00000020; -} -static inline u32 gr_zcull_save_restore_subregion_header_bytes_per_gpc_v(void) -{ - return 0x000000c0; -} -static inline u32 gr_zcull_subregion_qty_v(void) -{ - return 0x00000010; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) -{ - return 0x00504604; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) -{ - return 0x00504608; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) -{ - return 0x0050465c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) -{ - return 0x00504660; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) -{ - return 0x00504664; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) -{ - return 0x00504668; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) -{ - return 0x0050466c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) -{ - return 0x00504658; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) -{ - return 0x00504730; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) -{ - return 0x00504734; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) -{ - return 0x00504738; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) -{ - return 0x0050473c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) -{ - return 0x00504740; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) -{ - return 0x00504744; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) -{ - return 0x00504748; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) -{ - return 0x0050474c; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) -{ - return 0x00504678; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) -{ - return 0x00504694; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) -{ - return 0x005046f0; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) -{ - return 0x00504700; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) -{ - return 0x005046f4; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) -{ - return 0x00504704; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) -{ - return 0x005046f8; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) -{ - return 0x00504708; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) -{ - return 0x005046fc; -} -static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) -{ - return 0x0050470c; -} -static inline u32 gr_fe_pwr_mode_r(void) -{ - return 0x00404170; -} -static inline u32 gr_fe_pwr_mode_mode_auto_f(void) -{ - return 0x0; -} -static inline u32 gr_fe_pwr_mode_mode_force_on_f(void) -{ - return 0x2; -} -static inline u32 gr_fe_pwr_mode_req_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 gr_fe_pwr_mode_req_send_f(void) -{ - return 0x10; -} -static inline u32 gr_fe_pwr_mode_req_done_v(void) -{ - return 0x00000000; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_r(void) -{ - return 0x00418880; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vm_pg_size_m(void) -{ - return 0x1 << 0; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m(void) -{ - return 0x1 << 11; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_vol_fault_m(void) -{ - return 0x1 << 1; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_comp_fault_m(void) -{ - return 0x1 << 2; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_miss_gran_m(void) -{ - return 0x3 << 3; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_cache_mode_m(void) -{ - return 0x3 << 5; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_aperture_m(void) -{ - return 0x3 << 28; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_vol_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_pri_mmu_ctrl_mmu_disable_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_pri_mmu_pm_unit_mask_r(void) -{ - return 0x00418890; -} -static inline u32 gr_gpcs_pri_mmu_pm_req_mask_r(void) -{ - return 0x00418894; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void) -{ - return 0x004188b0; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) -{ - return (r >> 16) & 0x1; -} -static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) -{ - return 0x004188b4; -} -static inline u32 gr_gpcs_pri_mmu_debug_rd_r(void) -{ - return 0x004188b8; -} -static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) -{ - return 0x004188ac; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) -{ - return 0x00419e10; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) -{ - return 0x00000001; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) -{ - return 0x1 << 31; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) -{ - return 0x80000000; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) -{ - return 0x1 << 3; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) -{ - return 0x8; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) -{ - return 0x1 << 30; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) -{ - return 0x40000000; -} -static inline u32 gr_fe_gfxp_wfi_timeout_r(void) -{ - return 0x004041c0; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) -{ - return 0x0; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) -{ - return 0x00419c84; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_m(void) -{ - return 0x7 << 8; -} -static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f(void) -{ - return 0x100; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) -{ - return 0x00419f78; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) -{ - return 0x3 << 11; -} -static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_disable_f(void) -{ - return 0x1000; -} -static inline u32 gr_gpcs_tc_debug0_r(void) -{ - return 0x00418708; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) -{ - return 0xff << 0; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h deleted file mode 100644 index 5916f6952..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_ltc_gp10b.h +++ /dev/null @@ -1,561 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ltc_gp10b_h_ -#define _hw_ltc_gp10b_h_ - -static inline u32 ltc_ltcs_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046c; -} -static inline u32 ltc_ltc0_lts0_dstg_cfg0_r(void) -{ - return 0x00140518; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_r(void) -{ - return 0x0017e318; -} -static inline u32 ltc_ltcs_ltss_dstg_cfg0_vdc_4to2_disable_m(void) -{ - return 0x1 << 15; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_r(void) -{ - return 0x00140494; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_ways_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_v(u32 r) -{ - return (r >> 16) & 0x3; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_all_v(void) -{ - return 0x00000000; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_half_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v(void) -{ - return 0x00000002; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_r(void) -{ - return 0x0017e26c; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clean_active_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_invalidate_active_f(void) -{ - return 0x2; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl1_clear_active_f(void) -{ - return 0x4; -} -static inline u32 ltc_ltc0_lts0_cbc_ctrl1_r(void) -{ - return 0x0014046c; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_r(void) -{ - return 0x0017e270; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl2_clear_lower_bound_f(u32 v) -{ - return (v & 0x3ffff) << 0; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_r(void) -{ - return 0x0017e274; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_f(u32 v) -{ - return (v & 0x3ffff) << 0; -} -static inline u32 ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(void) -{ - return 0x0003ffff; -} -static inline u32 ltc_ltcs_ltss_cbc_base_r(void) -{ - return 0x0017e278; -} -static inline u32 ltc_ltcs_ltss_cbc_base_alignment_shift_v(void) -{ - return 0x0000000b; -} -static inline u32 ltc_ltcs_ltss_cbc_base_address_v(u32 r) -{ - return (r >> 0) & 0x3ffffff; -} -static inline u32 ltc_ltcs_ltss_cbc_num_active_ltcs_r(void) -{ - return 0x0017e27c; -} -static inline u32 ltc_ltcs_misc_ltc_num_active_ltcs_r(void) -{ - return 0x0017e000; -} -static inline u32 ltc_ltcs_ltss_cbc_param_r(void) -{ - return 0x0017e280; -} -static inline u32 ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltcs_ltss_cbc_param_cache_line_size_v(u32 r) -{ - return (r >> 24) & 0xf; -} -static inline u32 ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(u32 r) -{ - return (r >> 28) & 0xf; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_r(void) -{ - return 0x0017e3f4; -} -static inline u32 ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_r(void) -{ - return 0x0017e2ac; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_max_ways_evict_last_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_r(void) -{ - return 0x0017e338; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_index_address_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(u32 i) -{ - return 0x0017e33c + i*4; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(void) -{ - return 0x0017e34c; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_s(void) -{ - return 32; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 ltc_ltcs_ltss_dstg_zbc_depth_clear_value_field_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_r(void) -{ - return 0x0017e2b0; -} -static inline u32 ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(void) -{ - return 0x10000000; -} -static inline u32 ltc_ltcs_ltss_g_elpg_r(void) -{ - return 0x0017e214; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc0_ltss_g_elpg_r(void) -{ - return 0x00140214; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc1_ltss_g_elpg_r(void) -{ - return 0x00142214; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc1_ltss_g_elpg_flush_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_intr_r(void) -{ - return 0x0017e20c; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_sec_error_pending_f(void) -{ - return 0x100; -} -static inline u32 ltc_ltcs_ltss_intr_ecc_ded_error_pending_f(void) -{ - return 0x200; -} -static inline u32 ltc_ltcs_ltss_intr_en_evicted_cb_m(void) -{ - return 0x1 << 20; -} -static inline u32 ltc_ltcs_ltss_intr_en_illegal_compstat_access_m(void) -{ - return 0x1 << 30; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f(void) -{ - return 0x1000000; -} -static inline u32 ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(void) -{ - return 0x2000000; -} -static inline u32 ltc_ltc0_lts0_intr_r(void) -{ - return 0x0014040c; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_r(void) -{ - return 0x0014051c; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_m(void) -{ - return 0xff << 0; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_m(void) -{ - return 0xff << 16; -} -static inline u32 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(u32 r) -{ - return (r >> 16) & 0xff; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_r(void) -{ - return 0x0017e2a0; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_v(u32 r) -{ - return (r >> 8) & 0xf; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_v(void) -{ - return 0x00000003; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_max_cycles_between_invalidates_3_f(void) -{ - return 0x300; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_last_class_true_f(void) -{ - return 0x10000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_normal_class_true_f(void) -{ - return 0x20000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt0_invalidate_evict_first_class_true_f(void) -{ - return 0x40000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_r(void) -{ - return 0x0017e2a4; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_v(u32 r) -{ - return (r >> 8) & 0xf; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_v(void) -{ - return 0x00000003; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_max_cycles_between_cleans_3_f(void) -{ - return 0x300; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_v(u32 r) -{ - return (r >> 16) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_wait_for_fb_to_pull_true_f(void) -{ - return 0x10000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_v(u32 r) -{ - return (r >> 28) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_last_class_true_f(void) -{ - return 0x10000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_v(u32 r) -{ - return (r >> 29) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_normal_class_true_f(void) -{ - return 0x20000000; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_v(u32 r) -{ - return (r >> 30) & 0x1; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltcs_ltss_tstg_cmgmt1_clean_evict_first_class_true_f(void) -{ - return 0x40000000; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_r(void) -{ - return 0x001402a0; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_r(void) -{ - return 0x001402a4; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc0_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_r(void) -{ - return 0x001422a0; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt0_invalidate_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_r(void) -{ - return 0x001422a4; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_v(void) -{ - return 0x00000001; -} -static inline u32 ltc_ltc1_ltss_tstg_cmgmt1_clean_pending_f(void) -{ - return 0x1; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_r(void) -{ - return 0x0014058c; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(u32 r) -{ - return (r >> 0) & 0xffff; -} -static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) -{ - return (r >> 16) & 0x1f; -} -static inline u32 ltc_ltca_g_axi_pctrl_r(void) -{ - return 0x00160000; -} -static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) -{ - return (v & 0xff) << 2; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h deleted file mode 100644 index 30165e66d..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ /dev/null @@ -1,245 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_mc_gp10b_h_ -#define _hw_mc_gp10b_h_ - -static inline u32 mc_boot_0_r(void) -{ - return 0x00000000; -} -static inline u32 mc_boot_0_architecture_v(u32 r) -{ - return (r >> 24) & 0x1f; -} -static inline u32 mc_boot_0_implementation_v(u32 r) -{ - return (r >> 20) & 0xf; -} -static inline u32 mc_boot_0_major_revision_v(u32 r) -{ - return (r >> 4) & 0xf; -} -static inline u32 mc_boot_0_minor_revision_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 mc_intr_r(u32 i) -{ - return 0x00000100 + i*4; -} -static inline u32 mc_intr_pfifo_pending_f(void) -{ - return 0x100; -} -static inline u32 mc_intr_replayable_fault_pending_f(void) -{ - return 0x200; -} -static inline u32 mc_intr_pgraph_pending_f(void) -{ - return 0x1000; -} -static inline u32 mc_intr_pmu_pending_f(void) -{ - return 0x1000000; -} -static inline u32 mc_intr_ltc_pending_f(void) -{ - return 0x2000000; -} -static inline u32 mc_intr_priv_ring_pending_f(void) -{ - return 0x40000000; -} -static inline u32 mc_intr_pbus_pending_f(void) -{ - return 0x10000000; -} -static inline u32 mc_intr_en_r(u32 i) -{ - return 0x00000140 + i*4; -} -static inline u32 mc_intr_en_set_r(u32 i) -{ - return 0x00000160 + i*4; -} -static inline u32 mc_intr_en_clear_r(u32 i) -{ - return 0x00000180 + i*4; -} -static inline u32 mc_enable_r(void) -{ - return 0x00000200; -} -static inline u32 mc_enable_xbar_enabled_f(void) -{ - return 0x4; -} -static inline u32 mc_enable_l2_enabled_f(void) -{ - return 0x8; -} -static inline u32 mc_enable_pmedia_s(void) -{ - return 1; -} -static inline u32 mc_enable_pmedia_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 mc_enable_pmedia_m(void) -{ - return 0x1 << 4; -} -static inline u32 mc_enable_pmedia_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 mc_enable_priv_ring_enabled_f(void) -{ - return 0x20; -} -static inline u32 mc_enable_ce0_m(void) -{ - return 0x1 << 6; -} -static inline u32 mc_enable_pfifo_enabled_f(void) -{ - return 0x100; -} -static inline u32 mc_enable_pgraph_enabled_f(void) -{ - return 0x1000; -} -static inline u32 mc_enable_pwr_v(u32 r) -{ - return (r >> 13) & 0x1; -} -static inline u32 mc_enable_pwr_disabled_v(void) -{ - return 0x00000000; -} -static inline u32 mc_enable_pwr_enabled_f(void) -{ - return 0x2000; -} -static inline u32 mc_enable_pfb_enabled_f(void) -{ - return 0x100000; -} -static inline u32 mc_enable_ce2_m(void) -{ - return 0x1 << 21; -} -static inline u32 mc_enable_ce2_enabled_f(void) -{ - return 0x200000; -} -static inline u32 mc_enable_blg_enabled_f(void) -{ - return 0x8000000; -} -static inline u32 mc_enable_perfmon_enabled_f(void) -{ - return 0x10000000; -} -static inline u32 mc_enable_hub_enabled_f(void) -{ - return 0x20000000; -} -static inline u32 mc_intr_ltc_r(void) -{ - return 0x000001c0; -} -static inline u32 mc_enable_pb_r(void) -{ - return 0x00000204; -} -static inline u32 mc_enable_pb_0_s(void) -{ - return 1; -} -static inline u32 mc_enable_pb_0_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 mc_enable_pb_0_m(void) -{ - return 0x1 << 0; -} -static inline u32 mc_enable_pb_0_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 mc_enable_pb_0_enabled_v(void) -{ - return 0x00000001; -} -static inline u32 mc_enable_pb_sel_f(u32 v, u32 i) -{ - return (v & 0x1) << (0 + i*1); -} -static inline u32 mc_elpg_enable_r(void) -{ - return 0x0000020c; -} -static inline u32 mc_elpg_enable_xbar_enabled_f(void) -{ - return 0x4; -} -static inline u32 mc_elpg_enable_pfb_enabled_f(void) -{ - return 0x100000; -} -static inline u32 mc_elpg_enable_hub_enabled_f(void) -{ - return 0x20000000; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h deleted file mode 100644 index f66fa9345..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_pbdma_gp10b.h +++ /dev/null @@ -1,577 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pbdma_gp10b_h_ -#define _hw_pbdma_gp10b_h_ - -static inline u32 pbdma_gp_entry1_r(void) -{ - return 0x10000004; -} -static inline u32 pbdma_gp_entry1_get_hi_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 pbdma_gp_entry1_length_f(u32 v) -{ - return (v & 0x1fffff) << 10; -} -static inline u32 pbdma_gp_entry1_length_v(u32 r) -{ - return (r >> 10) & 0x1fffff; -} -static inline u32 pbdma_gp_base_r(u32 i) -{ - return 0x00040048 + i*8192; -} -static inline u32 pbdma_gp_base__size_1_v(void) -{ - return 0x00000001; -} -static inline u32 pbdma_gp_base_offset_f(u32 v) -{ - return (v & 0x1fffffff) << 3; -} -static inline u32 pbdma_gp_base_rsvd_s(void) -{ - return 3; -} -static inline u32 pbdma_gp_base_hi_r(u32 i) -{ - return 0x0004004c + i*8192; -} -static inline u32 pbdma_gp_base_hi_offset_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pbdma_gp_base_hi_limit2_f(u32 v) -{ - return (v & 0x1f) << 16; -} -static inline u32 pbdma_gp_fetch_r(u32 i) -{ - return 0x00040050 + i*8192; -} -static inline u32 pbdma_gp_get_r(u32 i) -{ - return 0x00040014 + i*8192; -} -static inline u32 pbdma_gp_put_r(u32 i) -{ - return 0x00040000 + i*8192; -} -static inline u32 pbdma_pb_fetch_r(u32 i) -{ - return 0x00040054 + i*8192; -} -static inline u32 pbdma_pb_fetch_hi_r(u32 i) -{ - return 0x00040058 + i*8192; -} -static inline u32 pbdma_get_r(u32 i) -{ - return 0x00040018 + i*8192; -} -static inline u32 pbdma_get_hi_r(u32 i) -{ - return 0x0004001c + i*8192; -} -static inline u32 pbdma_put_r(u32 i) -{ - return 0x0004005c + i*8192; -} -static inline u32 pbdma_put_hi_r(u32 i) -{ - return 0x00040060 + i*8192; -} -static inline u32 pbdma_formats_r(u32 i) -{ - return 0x0004009c + i*8192; -} -static inline u32 pbdma_formats_gp_fermi0_f(void) -{ - return 0x0; -} -static inline u32 pbdma_formats_pb_fermi1_f(void) -{ - return 0x100; -} -static inline u32 pbdma_formats_mp_fermi0_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_r(u32 i) -{ - return 0x00040084 + i*8192; -} -static inline u32 pbdma_pb_header_priv_user_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_method_zero_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_subchannel_zero_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_level_main_f(void) -{ - return 0x0; -} -static inline u32 pbdma_pb_header_first_true_f(void) -{ - return 0x400000; -} -static inline u32 pbdma_pb_header_type_inc_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_pb_header_type_non_inc_f(void) -{ - return 0x60000000; -} -static inline u32 pbdma_hdr_shadow_r(u32 i) -{ - return 0x00040118 + i*8192; -} -static inline u32 pbdma_subdevice_r(u32 i) -{ - return 0x00040094 + i*8192; -} -static inline u32 pbdma_subdevice_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 pbdma_subdevice_status_active_f(void) -{ - return 0x10000000; -} -static inline u32 pbdma_subdevice_channel_dma_enable_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_method0_r(u32 i) -{ - return 0x000400c0 + i*8192; -} -static inline u32 pbdma_method0_fifo_size_v(void) -{ - return 0x00000004; -} -static inline u32 pbdma_method0_addr_f(u32 v) -{ - return (v & 0xfff) << 2; -} -static inline u32 pbdma_method0_addr_v(u32 r) -{ - return (r >> 2) & 0xfff; -} -static inline u32 pbdma_method0_subch_v(u32 r) -{ - return (r >> 16) & 0x7; -} -static inline u32 pbdma_method0_first_true_f(void) -{ - return 0x400000; -} -static inline u32 pbdma_method0_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_method1_r(u32 i) -{ - return 0x000400c8 + i*8192; -} -static inline u32 pbdma_method2_r(u32 i) -{ - return 0x000400d0 + i*8192; -} -static inline u32 pbdma_method3_r(u32 i) -{ - return 0x000400d8 + i*8192; -} -static inline u32 pbdma_data0_r(u32 i) -{ - return 0x000400c4 + i*8192; -} -static inline u32 pbdma_target_r(u32 i) -{ - return 0x000400ac + i*8192; -} -static inline u32 pbdma_target_engine_sw_f(void) -{ - return 0x1f; -} -static inline u32 pbdma_acquire_r(u32 i) -{ - return 0x00040030 + i*8192; -} -static inline u32 pbdma_acquire_retry_man_2_f(void) -{ - return 0x2; -} -static inline u32 pbdma_acquire_retry_exp_2_f(void) -{ - return 0x100; -} -static inline u32 pbdma_acquire_timeout_exp_f(u32 v) -{ - return (v & 0xf) << 11; -} -static inline u32 pbdma_acquire_timeout_exp_max_v(void) -{ - return 0x0000000f; -} -static inline u32 pbdma_acquire_timeout_exp_max_f(void) -{ - return 0x7800; -} -static inline u32 pbdma_acquire_timeout_man_f(u32 v) -{ - return (v & 0xffff) << 15; -} -static inline u32 pbdma_acquire_timeout_man_max_v(void) -{ - return 0x0000ffff; -} -static inline u32 pbdma_acquire_timeout_man_max_f(void) -{ - return 0x7fff8000; -} -static inline u32 pbdma_acquire_timeout_en_enable_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_acquire_timeout_en_disable_f(void) -{ - return 0x0; -} -static inline u32 pbdma_status_r(u32 i) -{ - return 0x00040100 + i*8192; -} -static inline u32 pbdma_channel_r(u32 i) -{ - return 0x00040120 + i*8192; -} -static inline u32 pbdma_signature_r(u32 i) -{ - return 0x00040010 + i*8192; -} -static inline u32 pbdma_signature_hw_valid_f(void) -{ - return 0xface; -} -static inline u32 pbdma_signature_sw_zero_f(void) -{ - return 0x0; -} -static inline u32 pbdma_userd_r(u32 i) -{ - return 0x00040008 + i*8192; -} -static inline u32 pbdma_userd_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 pbdma_userd_addr_f(u32 v) -{ - return (v & 0x7fffff) << 9; -} -static inline u32 pbdma_userd_hi_r(u32 i) -{ - return 0x0004000c + i*8192; -} -static inline u32 pbdma_userd_hi_addr_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pbdma_hce_ctrl_r(u32 i) -{ - return 0x000400e4 + i*8192; -} -static inline u32 pbdma_hce_ctrl_hce_priv_mode_yes_f(void) -{ - return 0x20; -} -static inline u32 pbdma_intr_0_r(u32 i) -{ - return 0x00040108 + i*8192; -} -static inline u32 pbdma_intr_0_memreq_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pbdma_intr_0_memreq_pending_f(void) -{ - return 0x1; -} -static inline u32 pbdma_intr_0_memack_timeout_pending_f(void) -{ - return 0x2; -} -static inline u32 pbdma_intr_0_memack_extra_pending_f(void) -{ - return 0x4; -} -static inline u32 pbdma_intr_0_memdat_timeout_pending_f(void) -{ - return 0x8; -} -static inline u32 pbdma_intr_0_memdat_extra_pending_f(void) -{ - return 0x10; -} -static inline u32 pbdma_intr_0_memflush_pending_f(void) -{ - return 0x20; -} -static inline u32 pbdma_intr_0_memop_pending_f(void) -{ - return 0x40; -} -static inline u32 pbdma_intr_0_lbconnect_pending_f(void) -{ - return 0x80; -} -static inline u32 pbdma_intr_0_lbreq_pending_f(void) -{ - return 0x100; -} -static inline u32 pbdma_intr_0_lback_timeout_pending_f(void) -{ - return 0x200; -} -static inline u32 pbdma_intr_0_lback_extra_pending_f(void) -{ - return 0x400; -} -static inline u32 pbdma_intr_0_lbdat_timeout_pending_f(void) -{ - return 0x800; -} -static inline u32 pbdma_intr_0_lbdat_extra_pending_f(void) -{ - return 0x1000; -} -static inline u32 pbdma_intr_0_gpfifo_pending_f(void) -{ - return 0x2000; -} -static inline u32 pbdma_intr_0_gpptr_pending_f(void) -{ - return 0x4000; -} -static inline u32 pbdma_intr_0_gpentry_pending_f(void) -{ - return 0x8000; -} -static inline u32 pbdma_intr_0_gpcrc_pending_f(void) -{ - return 0x10000; -} -static inline u32 pbdma_intr_0_pbptr_pending_f(void) -{ - return 0x20000; -} -static inline u32 pbdma_intr_0_pbentry_pending_f(void) -{ - return 0x40000; -} -static inline u32 pbdma_intr_0_pbcrc_pending_f(void) -{ - return 0x80000; -} -static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) -{ - return 0x100000; -} -static inline u32 pbdma_intr_0_method_pending_f(void) -{ - return 0x200000; -} -static inline u32 pbdma_intr_0_methodcrc_pending_f(void) -{ - return 0x400000; -} -static inline u32 pbdma_intr_0_device_pending_f(void) -{ - return 0x800000; -} -static inline u32 pbdma_intr_0_semaphore_pending_f(void) -{ - return 0x2000000; -} -static inline u32 pbdma_intr_0_acquire_pending_f(void) -{ - return 0x4000000; -} -static inline u32 pbdma_intr_0_pri_pending_f(void) -{ - return 0x8000000; -} -static inline u32 pbdma_intr_0_no_ctxsw_seg_pending_f(void) -{ - return 0x20000000; -} -static inline u32 pbdma_intr_0_pbseg_pending_f(void) -{ - return 0x40000000; -} -static inline u32 pbdma_intr_0_signature_pending_f(void) -{ - return 0x80000000; -} -static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) -{ - return 0x10000000; -} -static inline u32 pbdma_intr_1_r(u32 i) -{ - return 0x00040148 + i*8192; -} -static inline u32 pbdma_intr_en_0_r(u32 i) -{ - return 0x0004010c + i*8192; -} -static inline u32 pbdma_intr_en_0_lbreq_enabled_f(void) -{ - return 0x100; -} -static inline u32 pbdma_intr_en_1_r(u32 i) -{ - return 0x0004014c + i*8192; -} -static inline u32 pbdma_intr_stall_r(u32 i) -{ - return 0x0004013c + i*8192; -} -static inline u32 pbdma_intr_stall_lbreq_enabled_f(void) -{ - return 0x100; -} -static inline u32 pbdma_udma_nop_r(void) -{ - return 0x00000008; -} -static inline u32 pbdma_allowed_syncpoints_r(u32 i) -{ - return 0x000400e8 + i*8192; -} -static inline u32 pbdma_allowed_syncpoints_0_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pbdma_allowed_syncpoints_0_index_f(u32 v) -{ - return (v & 0x7fff) << 16; -} -static inline u32 pbdma_allowed_syncpoints_0_index_v(u32 r) -{ - return (r >> 16) & 0x7fff; -} -static inline u32 pbdma_allowed_syncpoints_1_valid_f(u32 v) -{ - return (v & 0x1) << 15; -} -static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) -{ - return (v & 0x7fff) << 0; -} -static inline u32 pbdma_syncpointa_r(u32 i) -{ - return 0x000400a4 + i*8192; -} -static inline u32 pbdma_syncpointa_payload_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pbdma_syncpointb_r(u32 i) -{ - return 0x000400a8 + i*8192; -} -static inline u32 pbdma_syncpointb_op_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pbdma_syncpointb_op_wait_v(void) -{ - return 0x00000000; -} -static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 pbdma_syncpointb_wait_switch_en_v(void) -{ - return 0x00000001; -} -static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) -{ - return (r >> 8) & 0xfff; -} -static inline u32 pbdma_runlist_timeslice_r(u32 i) -{ - return 0x000400f8 + i*8192; -} -static inline u32 pbdma_runlist_timeslice_timeout_128_f(void) -{ - return 0x80; -} -static inline u32 pbdma_runlist_timeslice_timescale_3_f(void) -{ - return 0x3000; -} -static inline u32 pbdma_runlist_timeslice_enable_true_f(void) -{ - return 0x10000000; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h deleted file mode 100644 index ea1a61d27..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_perf_gp10b.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_perf_gp10b_h_ -#define _hw_perf_gp10b_h_ - -static inline u32 perf_pmasys_control_r(void) -{ - return 0x001b4000; -} -static inline u32 perf_pmasys_control_membuf_status_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_control_membuf_status_overflowed_f(void) -{ - return 0x10; -} -static inline u32 perf_pmasys_control_membuf_clear_status_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 perf_pmasys_control_membuf_clear_status_v(u32 r) -{ - return (r >> 5) & 0x1; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) -{ - return 0x20; -} -static inline u32 perf_pmasys_mem_block_r(void) -{ - return 0x001b4070; -} -static inline u32 perf_pmasys_mem_block_base_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 perf_pmasys_mem_block_target_f(u32 v) -{ - return (v & 0x3) << 28; -} -static inline u32 perf_pmasys_mem_block_target_v(u32 r) -{ - return (r >> 28) & 0x3; -} -static inline u32 perf_pmasys_mem_block_target_lfb_v(void) -{ - return 0x00000000; -} -static inline u32 perf_pmasys_mem_block_target_lfb_f(void) -{ - return 0x0; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_v(void) -{ - return 0x00000002; -} -static inline u32 perf_pmasys_mem_block_target_sys_coh_f(void) -{ - return 0x20000000; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_v(void) -{ - return 0x00000003; -} -static inline u32 perf_pmasys_mem_block_target_sys_ncoh_f(void) -{ - return 0x30000000; -} -static inline u32 perf_pmasys_mem_block_valid_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 perf_pmasys_mem_block_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 perf_pmasys_mem_block_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_mem_block_valid_true_f(void) -{ - return 0x80000000; -} -static inline u32 perf_pmasys_mem_block_valid_false_v(void) -{ - return 0x00000000; -} -static inline u32 perf_pmasys_mem_block_valid_false_f(void) -{ - return 0x0; -} -static inline u32 perf_pmasys_outbase_r(void) -{ - return 0x001b4074; -} -static inline u32 perf_pmasys_outbase_ptr_f(u32 v) -{ - return (v & 0x7ffffff) << 5; -} -static inline u32 perf_pmasys_outbaseupper_r(void) -{ - return 0x001b4078; -} -static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 perf_pmasys_outsize_r(void) -{ - return 0x001b407c; -} -static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) -{ - return (v & 0x7ffffff) << 5; -} -static inline u32 perf_pmasys_mem_bytes_r(void) -{ - return 0x001b4084; -} -static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 perf_pmasys_mem_bump_r(void) -{ - return 0x001b4088; -} -static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) -{ - return (v & 0xfffffff) << 4; -} -static inline u32 perf_pmasys_enginestatus_r(void) -{ - return 0x001b40a4; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_v(void) -{ - return 0x00000001; -} -static inline u32 perf_pmasys_enginestatus_rbufempty_empty_f(void) -{ - return 0x10; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h deleted file mode 100644 index 7a4588585..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_pri_ringmaster_gp10b.h +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringmaster_gp10b_h_ -#define _hw_pri_ringmaster_gp10b_h_ - -static inline u32 pri_ringmaster_command_r(void) -{ - return 0x0012004c; -} -static inline u32 pri_ringmaster_command_cmd_m(void) -{ - return 0x3f << 0; -} -static inline u32 pri_ringmaster_command_cmd_v(u32 r) -{ - return (r >> 0) & 0x3f; -} -static inline u32 pri_ringmaster_command_cmd_no_cmd_v(void) -{ - return 0x00000000; -} -static inline u32 pri_ringmaster_command_cmd_start_ring_f(void) -{ - return 0x1; -} -static inline u32 pri_ringmaster_command_cmd_ack_interrupt_f(void) -{ - return 0x2; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_f(void) -{ - return 0x3; -} -static inline u32 pri_ringmaster_command_cmd_enumerate_stations_bc_grp_all_f(void) -{ - return 0x0; -} -static inline u32 pri_ringmaster_command_data_r(void) -{ - return 0x00120048; -} -static inline u32 pri_ringmaster_start_results_r(void) -{ - return 0x00120050; -} -static inline u32 pri_ringmaster_start_results_connectivity_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pri_ringmaster_start_results_connectivity_pass_v(void) -{ - return 0x00000001; -} -static inline u32 pri_ringmaster_intr_status0_r(void) -{ - return 0x00120058; -} -static inline u32 pri_ringmaster_intr_status1_r(void) -{ - return 0x0012005c; -} -static inline u32 pri_ringmaster_global_ctl_r(void) -{ - return 0x00120060; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_asserted_f(void) -{ - return 0x1; -} -static inline u32 pri_ringmaster_global_ctl_ring_reset_deasserted_f(void) -{ - return 0x0; -} -static inline u32 pri_ringmaster_enum_fbp_r(void) -{ - return 0x00120074; -} -static inline u32 pri_ringmaster_enum_fbp_count_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 pri_ringmaster_enum_gpc_r(void) -{ - return 0x00120078; -} -static inline u32 pri_ringmaster_enum_gpc_count_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 pri_ringmaster_enum_ltc_r(void) -{ - return 0x0012006c; -} -static inline u32 pri_ringmaster_enum_ltc_count_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h deleted file mode 100644 index eb711452f..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_pri_ringstation_sys_gp10b.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pri_ringstation_sys_gp10b_h_ -#define _hw_pri_ringstation_sys_gp10b_h_ - -static inline u32 pri_ringstation_sys_master_config_r(u32 i) -{ - return 0x00122300 + i*4; -} -static inline u32 pri_ringstation_sys_decode_config_r(void) -{ - return 0x00122204; -} -static inline u32 pri_ringstation_sys_decode_config_ring_m(void) -{ - return 0x7 << 0; -} -static inline u32 pri_ringstation_sys_decode_config_ring_drop_on_ring_not_started_f(void) -{ - return 0x1; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h deleted file mode 100644 index a315ae2d6..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_proj_gp10b.h +++ /dev/null @@ -1,141 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_proj_gp10b_h_ -#define _hw_proj_gp10b_h_ - -static inline u32 proj_gpc_base_v(void) -{ - return 0x00500000; -} -static inline u32 proj_gpc_shared_base_v(void) -{ - return 0x00418000; -} -static inline u32 proj_gpc_stride_v(void) -{ - return 0x00008000; -} -static inline u32 proj_ltc_stride_v(void) -{ - return 0x00002000; -} -static inline u32 proj_lts_stride_v(void) -{ - return 0x00000200; -} -static inline u32 proj_ppc_in_gpc_base_v(void) -{ - return 0x00003000; -} -static inline u32 proj_ppc_in_gpc_stride_v(void) -{ - return 0x00000200; -} -static inline u32 proj_rop_base_v(void) -{ - return 0x00410000; -} -static inline u32 proj_rop_shared_base_v(void) -{ - return 0x00408800; -} -static inline u32 proj_rop_stride_v(void) -{ - return 0x00000400; -} -static inline u32 proj_tpc_in_gpc_base_v(void) -{ - return 0x00004000; -} -static inline u32 proj_tpc_in_gpc_stride_v(void) -{ - return 0x00000800; -} -static inline u32 proj_tpc_in_gpc_shared_base_v(void) -{ - return 0x00001800; -} -static inline u32 proj_host_num_pbdma_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) -{ - return 0x00000002; -} -static inline u32 proj_scal_litter_num_fbps_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_gpcs_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) -{ - return 0x00000001; -} -static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) -{ - return 0x00000002; -} -static inline u32 proj_scal_litter_num_zcull_banks_v(void) -{ - return 0x00000004; -} -static inline u32 proj_scal_max_gpcs_v(void) -{ - return 0x00000020; -} -static inline u32 proj_scal_max_tpc_per_gpc_v(void) -{ - return 0x00000008; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h deleted file mode 100644 index 75bf59a30..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_pwr_gp10b.h +++ /dev/null @@ -1,821 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_pwr_gp10b_h_ -#define _hw_pwr_gp10b_h_ - -static inline u32 pwr_falcon_irqsset_r(void) -{ - return 0x0010a000; -} -static inline u32 pwr_falcon_irqsset_swgen0_set_f(void) -{ - return 0x40; -} -static inline u32 pwr_falcon_irqsclr_r(void) -{ - return 0x0010a004; -} -static inline u32 pwr_falcon_irqstat_r(void) -{ - return 0x0010a008; -} -static inline u32 pwr_falcon_irqstat_halt_true_f(void) -{ - return 0x10; -} -static inline u32 pwr_falcon_irqstat_exterr_true_f(void) -{ - return 0x20; -} -static inline u32 pwr_falcon_irqstat_swgen0_true_f(void) -{ - return 0x40; -} -static inline u32 pwr_falcon_irqmode_r(void) -{ - return 0x0010a00c; -} -static inline u32 pwr_falcon_irqmset_r(void) -{ - return 0x0010a010; -} -static inline u32 pwr_falcon_irqmset_gptmr_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 pwr_falcon_irqmset_wdtmr_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_irqmset_mthd_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_falcon_irqmset_ctxsw_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 pwr_falcon_irqmset_halt_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_irqmset_exterr_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_irqmset_swgen0_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_irqmset_swgen1_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 pwr_falcon_irqmclr_r(void) -{ - return 0x0010a014; -} -static inline u32 pwr_falcon_irqmclr_gptmr_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 pwr_falcon_irqmclr_wdtmr_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_irqmclr_mthd_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_falcon_irqmclr_ctxsw_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 pwr_falcon_irqmclr_halt_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_irqmclr_exterr_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_irqmclr_swgen0_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_irqmclr_swgen1_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 pwr_falcon_irqmclr_ext_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_irqmask_r(void) -{ - return 0x0010a018; -} -static inline u32 pwr_falcon_irqdest_r(void) -{ - return 0x0010a01c; -} -static inline u32 pwr_falcon_irqdest_host_gptmr_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 pwr_falcon_irqdest_host_wdtmr_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_irqdest_host_mthd_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_falcon_irqdest_host_ctxsw_f(u32 v) -{ - return (v & 0x1) << 3; -} -static inline u32 pwr_falcon_irqdest_host_halt_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_irqdest_host_exterr_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_irqdest_host_swgen0_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_irqdest_host_swgen1_f(u32 v) -{ - return (v & 0x1) << 7; -} -static inline u32 pwr_falcon_irqdest_host_ext_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_irqdest_target_gptmr_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 pwr_falcon_irqdest_target_wdtmr_f(u32 v) -{ - return (v & 0x1) << 17; -} -static inline u32 pwr_falcon_irqdest_target_mthd_f(u32 v) -{ - return (v & 0x1) << 18; -} -static inline u32 pwr_falcon_irqdest_target_ctxsw_f(u32 v) -{ - return (v & 0x1) << 19; -} -static inline u32 pwr_falcon_irqdest_target_halt_f(u32 v) -{ - return (v & 0x1) << 20; -} -static inline u32 pwr_falcon_irqdest_target_exterr_f(u32 v) -{ - return (v & 0x1) << 21; -} -static inline u32 pwr_falcon_irqdest_target_swgen0_f(u32 v) -{ - return (v & 0x1) << 22; -} -static inline u32 pwr_falcon_irqdest_target_swgen1_f(u32 v) -{ - return (v & 0x1) << 23; -} -static inline u32 pwr_falcon_irqdest_target_ext_f(u32 v) -{ - return (v & 0xff) << 24; -} -static inline u32 pwr_falcon_curctx_r(void) -{ - return 0x0010a050; -} -static inline u32 pwr_falcon_nxtctx_r(void) -{ - return 0x0010a054; -} -static inline u32 pwr_falcon_mailbox0_r(void) -{ - return 0x0010a040; -} -static inline u32 pwr_falcon_mailbox1_r(void) -{ - return 0x0010a044; -} -static inline u32 pwr_falcon_itfen_r(void) -{ - return 0x0010a048; -} -static inline u32 pwr_falcon_itfen_ctxen_enable_f(void) -{ - return 0x1; -} -static inline u32 pwr_falcon_idlestate_r(void) -{ - return 0x0010a04c; -} -static inline u32 pwr_falcon_idlestate_falcon_busy_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 pwr_falcon_idlestate_ext_busy_v(u32 r) -{ - return (r >> 1) & 0x7fff; -} -static inline u32 pwr_falcon_os_r(void) -{ - return 0x0010a080; -} -static inline u32 pwr_falcon_engctl_r(void) -{ - return 0x0010a0a4; -} -static inline u32 pwr_falcon_cpuctl_r(void) -{ - return 0x0010a100; -} -static inline u32 pwr_falcon_cpuctl_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_m(void) -{ - return 0x1 << 4; -} -static inline u32 pwr_falcon_cpuctl_halt_intr_v(u32 r) -{ - return (r >> 4) & 0x1; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_f(u32 v) -{ - return (v & 0x1) << 6; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_m(void) -{ - return 0x1 << 6; -} -static inline u32 pwr_falcon_cpuctl_cpuctl_alias_en_v(u32 r) -{ - return (r >> 6) & 0x1; -} -static inline u32 pwr_falcon_cpuctl_alias_r(void) -{ - return 0x0010a130; -} -static inline u32 pwr_falcon_cpuctl_alias_startcpu_f(u32 v) -{ - return (v & 0x1) << 1; -} -static inline u32 pwr_pmu_scpctl_stat_r(void) -{ - return 0x0010ac08; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_f(u32 v) -{ - return (v & 0x1) << 20; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_m(void) -{ - return 0x1 << 20; -} -static inline u32 pwr_pmu_scpctl_stat_debug_mode_v(u32 r) -{ - return (r >> 20) & 0x1; -} -static inline u32 pwr_falcon_imemc_r(u32 i) -{ - return 0x0010a180 + i*16; -} -static inline u32 pwr_falcon_imemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 pwr_falcon_imemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_imemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 pwr_falcon_imemd_r(u32 i) -{ - return 0x0010a184 + i*16; -} -static inline u32 pwr_falcon_imemt_r(u32 i) -{ - return 0x0010a188 + i*16; -} -static inline u32 pwr_falcon_sctl_r(void) -{ - return 0x0010a240; -} -static inline u32 pwr_falcon_mmu_phys_sec_r(void) -{ - return 0x00100ce4; -} -static inline u32 pwr_falcon_bootvec_r(void) -{ - return 0x0010a104; -} -static inline u32 pwr_falcon_bootvec_vec_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_falcon_dmactl_r(void) -{ - return 0x0010a10c; -} -static inline u32 pwr_falcon_dmactl_dmem_scrubbing_m(void) -{ - return 0x1 << 1; -} -static inline u32 pwr_falcon_dmactl_imem_scrubbing_m(void) -{ - return 0x1 << 2; -} -static inline u32 pwr_falcon_hwcfg_r(void) -{ - return 0x0010a108; -} -static inline u32 pwr_falcon_hwcfg_imem_size_v(u32 r) -{ - return (r >> 0) & 0x1ff; -} -static inline u32 pwr_falcon_hwcfg_dmem_size_v(u32 r) -{ - return (r >> 9) & 0x1ff; -} -static inline u32 pwr_falcon_dmatrfbase_r(void) -{ - return 0x0010a110; -} -static inline u32 pwr_falcon_dmatrfbase1_r(void) -{ - return 0x0010a128; -} -static inline u32 pwr_falcon_dmatrfmoffs_r(void) -{ - return 0x0010a114; -} -static inline u32 pwr_falcon_dmatrfcmd_r(void) -{ - return 0x0010a118; -} -static inline u32 pwr_falcon_dmatrfcmd_imem_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 pwr_falcon_dmatrfcmd_write_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 pwr_falcon_dmatrfcmd_size_f(u32 v) -{ - return (v & 0x7) << 8; -} -static inline u32 pwr_falcon_dmatrfcmd_ctxdma_f(u32 v) -{ - return (v & 0x7) << 12; -} -static inline u32 pwr_falcon_dmatrffboffs_r(void) -{ - return 0x0010a11c; -} -static inline u32 pwr_falcon_exterraddr_r(void) -{ - return 0x0010a168; -} -static inline u32 pwr_falcon_exterrstat_r(void) -{ - return 0x0010a16c; -} -static inline u32 pwr_falcon_exterrstat_valid_m(void) -{ - return 0x1 << 31; -} -static inline u32 pwr_falcon_exterrstat_valid_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 pwr_falcon_exterrstat_valid_true_v(void) -{ - return 0x00000001; -} -static inline u32 pwr_pmu_falcon_icd_cmd_r(void) -{ - return 0x0010a200; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_s(void) -{ - return 4; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_f(u32 v) -{ - return (v & 0xf) << 0; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_m(void) -{ - return 0xf << 0; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_v(u32 r) -{ - return (r >> 0) & 0xf; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rreg_f(void) -{ - return 0x8; -} -static inline u32 pwr_pmu_falcon_icd_cmd_opc_rstat_f(void) -{ - return 0xe; -} -static inline u32 pwr_pmu_falcon_icd_cmd_idx_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 pwr_pmu_falcon_icd_rdata_r(void) -{ - return 0x0010a20c; -} -static inline u32 pwr_falcon_dmemc_r(u32 i) -{ - return 0x0010a1c0 + i*8; -} -static inline u32 pwr_falcon_dmemc_offs_f(u32 v) -{ - return (v & 0x3f) << 2; -} -static inline u32 pwr_falcon_dmemc_offs_m(void) -{ - return 0x3f << 2; -} -static inline u32 pwr_falcon_dmemc_blk_f(u32 v) -{ - return (v & 0xff) << 8; -} -static inline u32 pwr_falcon_dmemc_blk_m(void) -{ - return 0xff << 8; -} -static inline u32 pwr_falcon_dmemc_aincw_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 pwr_falcon_dmemc_aincr_f(u32 v) -{ - return (v & 0x1) << 25; -} -static inline u32 pwr_falcon_dmemd_r(u32 i) -{ - return 0x0010a1c4 + i*8; -} -static inline u32 pwr_pmu_new_instblk_r(void) -{ - return 0x0010a480; -} -static inline u32 pwr_pmu_new_instblk_ptr_f(u32 v) -{ - return (v & 0xfffffff) << 0; -} -static inline u32 pwr_pmu_new_instblk_target_fb_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_new_instblk_target_sys_coh_f(void) -{ - return 0x20000000; -} -static inline u32 pwr_pmu_new_instblk_valid_f(u32 v) -{ - return (v & 0x1) << 30; -} -static inline u32 pwr_pmu_mutex_id_r(void) -{ - return 0x0010a488; -} -static inline u32 pwr_pmu_mutex_id_value_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 pwr_pmu_mutex_id_value_init_v(void) -{ - return 0x00000000; -} -static inline u32 pwr_pmu_mutex_id_value_not_avail_v(void) -{ - return 0x000000ff; -} -static inline u32 pwr_pmu_mutex_id_release_r(void) -{ - return 0x0010a48c; -} -static inline u32 pwr_pmu_mutex_id_release_value_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pwr_pmu_mutex_id_release_value_m(void) -{ - return 0xff << 0; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_v(void) -{ - return 0x00000000; -} -static inline u32 pwr_pmu_mutex_id_release_value_init_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_mutex_r(u32 i) -{ - return 0x0010a580 + i*4; -} -static inline u32 pwr_pmu_mutex__size_1_v(void) -{ - return 0x00000010; -} -static inline u32 pwr_pmu_mutex_value_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 pwr_pmu_mutex_value_v(u32 r) -{ - return (r >> 0) & 0xff; -} -static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_queue_head_r(u32 i) -{ - return 0x0010a4a0 + i*4; -} -static inline u32 pwr_pmu_queue_head__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 pwr_pmu_queue_head_address_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_queue_head_address_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_queue_tail_r(u32 i) -{ - return 0x0010a4b0 + i*4; -} -static inline u32 pwr_pmu_queue_tail__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 pwr_pmu_queue_tail_address_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_queue_tail_address_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_msgq_head_r(void) -{ - return 0x0010a4c8; -} -static inline u32 pwr_pmu_msgq_head_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_msgq_head_val_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_msgq_tail_r(void) -{ - return 0x0010a4cc; -} -static inline u32 pwr_pmu_msgq_tail_val_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 pwr_pmu_msgq_tail_val_v(u32 r) -{ - return (r >> 0) & 0xffffffff; -} -static inline u32 pwr_pmu_idle_mask_r(u32 i) -{ - return 0x0010a504 + i*16; -} -static inline u32 pwr_pmu_idle_mask_gr_enabled_f(void) -{ - return 0x1; -} -static inline u32 pwr_pmu_idle_mask_ce_2_enabled_f(void) -{ - return 0x200000; -} -static inline u32 pwr_pmu_idle_count_r(u32 i) -{ - return 0x0010a508 + i*16; -} -static inline u32 pwr_pmu_idle_count_value_f(u32 v) -{ - return (v & 0x7fffffff) << 0; -} -static inline u32 pwr_pmu_idle_count_value_v(u32 r) -{ - return (r >> 0) & 0x7fffffff; -} -static inline u32 pwr_pmu_idle_count_reset_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 pwr_pmu_idle_ctrl_r(u32 i) -{ - return 0x0010a50c + i*16; -} -static inline u32 pwr_pmu_idle_ctrl_value_m(void) -{ - return 0x3 << 0; -} -static inline u32 pwr_pmu_idle_ctrl_value_busy_f(void) -{ - return 0x2; -} -static inline u32 pwr_pmu_idle_ctrl_value_always_f(void) -{ - return 0x3; -} -static inline u32 pwr_pmu_idle_ctrl_filter_m(void) -{ - return 0x1 << 2; -} -static inline u32 pwr_pmu_idle_ctrl_filter_disabled_f(void) -{ - return 0x0; -} -static inline u32 pwr_pmu_idle_mask_supp_r(u32 i) -{ - return 0x0010a9f0 + i*8; -} -static inline u32 pwr_pmu_idle_mask_1_supp_r(u32 i) -{ - return 0x0010a9f4 + i*8; -} -static inline u32 pwr_pmu_idle_ctrl_supp_r(u32 i) -{ - return 0x0010aa30 + i*8; -} -static inline u32 pwr_pmu_debug_r(u32 i) -{ - return 0x0010a5c0 + i*4; -} -static inline u32 pwr_pmu_debug__size_1_v(void) -{ - return 0x00000004; -} -static inline u32 pwr_pmu_mailbox_r(u32 i) -{ - return 0x0010a450 + i*4; -} -static inline u32 pwr_pmu_mailbox__size_1_v(void) -{ - return 0x0000000c; -} -static inline u32 pwr_pmu_bar0_addr_r(void) -{ - return 0x0010a7a0; -} -static inline u32 pwr_pmu_bar0_data_r(void) -{ - return 0x0010a7a4; -} -static inline u32 pwr_pmu_bar0_ctl_r(void) -{ - return 0x0010a7ac; -} -static inline u32 pwr_pmu_bar0_timeout_r(void) -{ - return 0x0010a7a8; -} -static inline u32 pwr_pmu_bar0_fecs_error_r(void) -{ - return 0x0010a988; -} -static inline u32 pwr_pmu_bar0_error_status_r(void) -{ - return 0x0010a7b0; -} -static inline u32 pwr_pmu_pg_idlefilth_r(u32 i) -{ - return 0x0010a6c0 + i*4; -} -static inline u32 pwr_pmu_pg_ppuidlefilth_r(u32 i) -{ - return 0x0010a6e8 + i*4; -} -static inline u32 pwr_pmu_pg_idle_cnt_r(u32 i) -{ - return 0x0010a710 + i*4; -} -static inline u32 pwr_pmu_pg_intren_r(u32 i) -{ - return 0x0010a760 + i*4; -} -static inline u32 pwr_fbif_transcfg_r(u32 i) -{ - return 0x0010ae00 + i*4; -} -static inline u32 pwr_fbif_transcfg_target_local_fb_f(void) -{ - return 0x0; -} -static inline u32 pwr_fbif_transcfg_target_coherent_sysmem_f(void) -{ - return 0x1; -} -static inline u32 pwr_fbif_transcfg_target_noncoherent_sysmem_f(void) -{ - return 0x2; -} -static inline u32 pwr_fbif_transcfg_mem_type_s(void) -{ - return 1; -} -static inline u32 pwr_fbif_transcfg_mem_type_f(u32 v) -{ - return (v & 0x1) << 2; -} -static inline u32 pwr_fbif_transcfg_mem_type_m(void) -{ - return 0x1 << 2; -} -static inline u32 pwr_fbif_transcfg_mem_type_v(u32 r) -{ - return (r >> 2) & 0x1; -} -static inline u32 pwr_fbif_transcfg_mem_type_virtual_f(void) -{ - return 0x0; -} -static inline u32 pwr_fbif_transcfg_mem_type_physical_f(void) -{ - return 0x4; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h deleted file mode 100644 index 863b15b85..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_ram_gp10b.h +++ /dev/null @@ -1,481 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_ram_gp10b_h_ -#define _hw_ram_gp10b_h_ - -static inline u32 ram_in_ramfc_s(void) -{ - return 4096; -} -static inline u32 ram_in_ramfc_w(void) -{ - return 0; -} -static inline u32 ram_in_page_dir_base_target_f(u32 v) -{ - return (v & 0x3) << 0; -} -static inline u32 ram_in_page_dir_base_target_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_target_vid_mem_f(void) -{ - return 0x0; -} -static inline u32 ram_in_page_dir_base_vol_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_vol_true_f(void) -{ - return 0x4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) -{ - return (v & 0x1) << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) -{ - return 0x1 << 4; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) -{ - return 0x10; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) -{ - return (v & 0x1) << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) -{ - return 0x1 << 5; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) -{ - return 0x20; -} -static inline u32 ram_in_big_page_size_f(u32 v) -{ - return (v & 0x1) << 11; -} -static inline u32 ram_in_big_page_size_m(void) -{ - return 0x1 << 11; -} -static inline u32 ram_in_big_page_size_w(void) -{ - return 128; -} -static inline u32 ram_in_big_page_size_128kb_f(void) -{ - return 0x0; -} -static inline u32 ram_in_big_page_size_64kb_f(void) -{ - return 0x800; -} -static inline u32 ram_in_page_dir_base_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_in_page_dir_base_lo_w(void) -{ - return 128; -} -static inline u32 ram_in_page_dir_base_hi_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 ram_in_page_dir_base_hi_w(void) -{ - return 129; -} -static inline u32 ram_in_adr_limit_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_in_adr_limit_lo_w(void) -{ - return 130; -} -static inline u32 ram_in_adr_limit_hi_f(u32 v) -{ - return (v & 0xffffffff) << 0; -} -static inline u32 ram_in_adr_limit_hi_w(void) -{ - return 131; -} -static inline u32 ram_in_engine_cs_w(void) -{ - return 132; -} -static inline u32 ram_in_engine_cs_wfi_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_engine_cs_wfi_f(void) -{ - return 0x0; -} -static inline u32 ram_in_engine_cs_fg_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_engine_cs_fg_f(void) -{ - return 0x8; -} -static inline u32 ram_in_gr_cs_w(void) -{ - return 132; -} -static inline u32 ram_in_gr_cs_wfi_f(void) -{ - return 0x0; -} -static inline u32 ram_in_gr_wfi_target_w(void) -{ - return 132; -} -static inline u32 ram_in_gr_wfi_mode_w(void) -{ - return 132; -} -static inline u32 ram_in_gr_wfi_mode_physical_v(void) -{ - return 0x00000000; -} -static inline u32 ram_in_gr_wfi_mode_physical_f(void) -{ - return 0x0; -} -static inline u32 ram_in_gr_wfi_mode_virtual_v(void) -{ - return 0x00000001; -} -static inline u32 ram_in_gr_wfi_mode_virtual_f(void) -{ - return 0x4; -} -static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) -{ - return (v & 0xfffff) << 12; -} -static inline u32 ram_in_gr_wfi_ptr_lo_w(void) -{ - return 132; -} -static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) -{ - return (v & 0xff) << 0; -} -static inline u32 ram_in_gr_wfi_ptr_hi_w(void) -{ - return 133; -} -static inline u32 ram_in_base_shift_v(void) -{ - return 0x0000000c; -} -static inline u32 ram_in_alloc_size_v(void) -{ - return 0x00001000; -} -static inline u32 ram_fc_size_val_v(void) -{ - return 0x00000200; -} -static inline u32 ram_fc_gp_put_w(void) -{ - return 0; -} -static inline u32 ram_fc_userd_w(void) -{ - return 2; -} -static inline u32 ram_fc_userd_hi_w(void) -{ - return 3; -} -static inline u32 ram_fc_signature_w(void) -{ - return 4; -} -static inline u32 ram_fc_gp_get_w(void) -{ - return 5; -} -static inline u32 ram_fc_pb_get_w(void) -{ - return 6; -} -static inline u32 ram_fc_pb_get_hi_w(void) -{ - return 7; -} -static inline u32 ram_fc_pb_top_level_get_w(void) -{ - return 8; -} -static inline u32 ram_fc_pb_top_level_get_hi_w(void) -{ - return 9; -} -static inline u32 ram_fc_acquire_w(void) -{ - return 12; -} -static inline u32 ram_fc_semaphorea_w(void) -{ - return 14; -} -static inline u32 ram_fc_semaphoreb_w(void) -{ - return 15; -} -static inline u32 ram_fc_semaphorec_w(void) -{ - return 16; -} -static inline u32 ram_fc_semaphored_w(void) -{ - return 17; -} -static inline u32 ram_fc_gp_base_w(void) -{ - return 18; -} -static inline u32 ram_fc_gp_base_hi_w(void) -{ - return 19; -} -static inline u32 ram_fc_gp_fetch_w(void) -{ - return 20; -} -static inline u32 ram_fc_pb_fetch_w(void) -{ - return 21; -} -static inline u32 ram_fc_pb_fetch_hi_w(void) -{ - return 22; -} -static inline u32 ram_fc_pb_put_w(void) -{ - return 23; -} -static inline u32 ram_fc_pb_put_hi_w(void) -{ - return 24; -} -static inline u32 ram_fc_pb_header_w(void) -{ - return 33; -} -static inline u32 ram_fc_pb_count_w(void) -{ - return 34; -} -static inline u32 ram_fc_subdevice_w(void) -{ - return 37; -} -static inline u32 ram_fc_formats_w(void) -{ - return 39; -} -static inline u32 ram_fc_allowed_syncpoints_w(void) -{ - return 58; -} -static inline u32 ram_fc_syncpointa_w(void) -{ - return 41; -} -static inline u32 ram_fc_syncpointb_w(void) -{ - return 42; -} -static inline u32 ram_fc_target_w(void) -{ - return 43; -} -static inline u32 ram_fc_hce_ctrl_w(void) -{ - return 57; -} -static inline u32 ram_fc_chid_w(void) -{ - return 58; -} -static inline u32 ram_fc_chid_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_fc_chid_id_w(void) -{ - return 0; -} -static inline u32 ram_fc_runlist_timeslice_w(void) -{ - return 62; -} -static inline u32 ram_userd_base_shift_v(void) -{ - return 0x00000009; -} -static inline u32 ram_userd_chan_size_v(void) -{ - return 0x00000200; -} -static inline u32 ram_userd_put_w(void) -{ - return 16; -} -static inline u32 ram_userd_get_w(void) -{ - return 17; -} -static inline u32 ram_userd_ref_w(void) -{ - return 18; -} -static inline u32 ram_userd_put_hi_w(void) -{ - return 19; -} -static inline u32 ram_userd_ref_threshold_w(void) -{ - return 20; -} -static inline u32 ram_userd_top_level_get_w(void) -{ - return 22; -} -static inline u32 ram_userd_top_level_get_hi_w(void) -{ - return 23; -} -static inline u32 ram_userd_get_hi_w(void) -{ - return 24; -} -static inline u32 ram_userd_gp_get_w(void) -{ - return 34; -} -static inline u32 ram_userd_gp_put_w(void) -{ - return 35; -} -static inline u32 ram_userd_gp_top_level_get_w(void) -{ - return 22; -} -static inline u32 ram_userd_gp_top_level_get_hi_w(void) -{ - return 23; -} -static inline u32 ram_rl_entry_size_v(void) -{ - return 0x00000008; -} -static inline u32 ram_rl_entry_chid_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_rl_entry_id_f(u32 v) -{ - return (v & 0xfff) << 0; -} -static inline u32 ram_rl_entry_type_f(u32 v) -{ - return (v & 0x1) << 13; -} -static inline u32 ram_rl_entry_type_chid_f(void) -{ - return 0x0; -} -static inline u32 ram_rl_entry_type_tsg_f(void) -{ - return 0x2000; -} -static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) -{ - return (v & 0xf) << 14; -} -static inline u32 ram_rl_entry_timeslice_scale_3_f(void) -{ - return 0xc000; -} -static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) -{ - return (v & 0xff) << 18; -} -static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) -{ - return 0x2000000; -} -static inline u32 ram_rl_entry_tsg_length_f(u32 v) -{ - return (v & 0x3f) << 26; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h deleted file mode 100644 index 8a587b7c5..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_therm_gp10b.h +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_therm_gp10b_h_ -#define _hw_therm_gp10b_h_ - -static inline u32 therm_use_a_r(void) -{ - return 0x00020798; -} -static inline u32 therm_use_a_ext_therm_0_enable_f(void) -{ - return 0x1; -} -static inline u32 therm_use_a_ext_therm_1_enable_f(void) -{ - return 0x2; -} -static inline u32 therm_use_a_ext_therm_2_enable_f(void) -{ - return 0x4; -} -static inline u32 therm_evt_ext_therm_0_r(void) -{ - return 0x00020700; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) -{ - return (v & 0x3) << 30; -} -static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) -{ - return 0x00000000; -} -static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) -{ - return 0x00000003; -} -static inline u32 therm_evt_ext_therm_1_r(void) -{ - return 0x00020704; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) -{ - return (v & 0x3) << 30; -} -static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) -{ - return 0x00000000; -} -static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) -{ - return 0x00000003; -} -static inline u32 therm_evt_ext_therm_2_r(void) -{ - return 0x00020708; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) -{ - return 0x00000003; -} -static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) -{ - return (v & 0x3) << 30; -} -static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) -{ - return 0x00000000; -} -static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) -{ - return 0x00000001; -} -static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) -{ - return 0x00000002; -} -static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) -{ - return 0x00000003; -} -static inline u32 therm_weight_1_r(void) -{ - return 0x00020024; -} -static inline u32 therm_config1_r(void) -{ - return 0x00020050; -} -static inline u32 therm_config2_r(void) -{ - return 0x00020130; -} -static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) -{ - return (v & 0x1) << 24; -} -static inline u32 therm_config2_grad_enable_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 therm_gate_ctrl_r(u32 i) -{ - return 0x00020200 + i*4; -} -static inline u32 therm_gate_ctrl_eng_clk_m(void) -{ - return 0x3 << 0; -} -static inline u32 therm_gate_ctrl_eng_clk_run_f(void) -{ - return 0x0; -} -static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) -{ - return 0x1; -} -static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) -{ - return 0x2; -} -static inline u32 therm_gate_ctrl_blk_clk_m(void) -{ - return 0x3 << 2; -} -static inline u32 therm_gate_ctrl_blk_clk_run_f(void) -{ - return 0x0; -} -static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) -{ - return 0x4; -} -static inline u32 therm_gate_ctrl_eng_pwr_m(void) -{ - return 0x3 << 4; -} -static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) -{ - return 0x10; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) -{ - return 0x00000002; -} -static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) -{ - return 0x20; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) -{ - return (v & 0x1f) << 8; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) -{ - return 0x1f << 8; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) -{ - return (v & 0x7) << 13; -} -static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) -{ - return 0x7 << 13; -} -static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) -{ - return (v & 0xf) << 16; -} -static inline u32 therm_gate_ctrl_eng_delay_before_m(void) -{ - return 0xf << 16; -} -static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) -{ - return (v & 0xf) << 20; -} -static inline u32 therm_gate_ctrl_eng_delay_after_m(void) -{ - return 0xf << 20; -} -static inline u32 therm_fecs_idle_filter_r(void) -{ - return 0x00020288; -} -static inline u32 therm_fecs_idle_filter_value_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 therm_hubmmu_idle_filter_r(void) -{ - return 0x0002028c; -} -static inline u32 therm_hubmmu_idle_filter_value_m(void) -{ - return 0xffffffff << 0; -} -static inline u32 therm_clk_slowdown_r(u32 i) -{ - return 0x00020160 + i*4; -} -static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) -{ - return (v & 0x3f) << 16; -} -static inline u32 therm_clk_slowdown_idle_factor_m(void) -{ - return 0x3f << 16; -} -static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) -{ - return (r >> 16) & 0x3f; -} -static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) -{ - return 0x0; -} -static inline u32 therm_grad_stepping_table_r(u32 i) -{ - return 0x000202c8 + i*4; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) -{ - return (v & 0x3f) << 0; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) -{ - return 0x3f << 0; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) -{ - return 0x1; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) -{ - return 0x2; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) -{ - return 0x6; -} -static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) -{ - return 0xe; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) -{ - return (v & 0x3f) << 6; -} -static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) -{ - return 0x3f << 6; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) -{ - return (v & 0x3f) << 12; -} -static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) -{ - return 0x3f << 12; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) -{ - return (v & 0x3f) << 18; -} -static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) -{ - return 0x3f << 18; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) -{ - return (v & 0x3f) << 24; -} -static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) -{ - return 0x3f << 24; -} -static inline u32 therm_grad_stepping0_r(void) -{ - return 0x000202c0; -} -static inline u32 therm_grad_stepping0_feature_s(void) -{ - return 1; -} -static inline u32 therm_grad_stepping0_feature_f(u32 v) -{ - return (v & 0x1) << 0; -} -static inline u32 therm_grad_stepping0_feature_m(void) -{ - return 0x1 << 0; -} -static inline u32 therm_grad_stepping0_feature_v(u32 r) -{ - return (r >> 0) & 0x1; -} -static inline u32 therm_grad_stepping0_feature_enable_f(void) -{ - return 0x1; -} -static inline u32 therm_grad_stepping1_r(void) -{ - return 0x000202c4; -} -static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) -{ - return (v & 0x1ffff) << 0; -} -static inline u32 therm_clk_timing_r(u32 i) -{ - return 0x000203c0 + i*4; -} -static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) -{ - return (v & 0x1) << 16; -} -static inline u32 therm_clk_timing_grad_slowdown_m(void) -{ - return 0x1 << 16; -} -static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) -{ - return 0x10000; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h deleted file mode 100644 index df27154ff..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_timer_gp10b.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_timer_gp10b_h_ -#define _hw_timer_gp10b_h_ - -static inline u32 timer_pri_timeout_r(void) -{ - return 0x00009080; -} -static inline u32 timer_pri_timeout_period_f(u32 v) -{ - return (v & 0xffffff) << 0; -} -static inline u32 timer_pri_timeout_period_m(void) -{ - return 0xffffff << 0; -} -static inline u32 timer_pri_timeout_period_v(u32 r) -{ - return (r >> 0) & 0xffffff; -} -static inline u32 timer_pri_timeout_en_f(u32 v) -{ - return (v & 0x1) << 31; -} -static inline u32 timer_pri_timeout_en_m(void) -{ - return 0x1 << 31; -} -static inline u32 timer_pri_timeout_en_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 timer_pri_timeout_en_en_enabled_f(void) -{ - return 0x80000000; -} -static inline u32 timer_pri_timeout_en_en_disabled_f(void) -{ - return 0x0; -} -static inline u32 timer_pri_timeout_save_0_r(void) -{ - return 0x00009084; -} -static inline u32 timer_pri_timeout_save_1_r(void) -{ - return 0x00009088; -} -static inline u32 timer_pri_timeout_fecs_errcode_r(void) -{ - return 0x0000908c; -} -static inline u32 timer_time_0_r(void) -{ - return 0x00009400; -} -static inline u32 timer_time_1_r(void) -{ - return 0x00009410; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h deleted file mode 100644 index ab6f63736..000000000 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ /dev/null @@ -1,161 +0,0 @@ -/* - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -/* - * Function naming determines intended use: - * - * _r(void) : Returns the offset for register . - * - * _o(void) : Returns the offset for element . - * - * _w(void) : Returns the word offset for word (4 byte) element . - * - * __s(void) : Returns size of field of register in bits. - * - * __f(u32 v) : Returns a value based on 'v' which has been shifted - * and masked to place it at field of register . This value - * can be |'d with others to produce a full register value for - * register . - * - * __m(void) : Returns a mask for field of register . This - * value can be ~'d and then &'d to clear the value of field for - * register . - * - * ___f(void) : Returns the constant value after being shifted - * to place it at field of register . This value can be |'d - * with others to produce a full register value for . - * - * __v(u32 r) : Returns the value of field from a full register - * value 'r' after being shifted to place its LSB at bit 0. - * This value is suitable for direct comparison with other unshifted - * values appropriate for use in field of register . - * - * ___v(void) : Returns the constant value for defined for - * field of register . This value is suitable for direct - * comparison with unshifted values appropriate for use in field - * of register . - */ -#ifndef _hw_top_gp10b_h_ -#define _hw_top_gp10b_h_ - -static inline u32 top_num_gpcs_r(void) -{ - return 0x00022430; -} -static inline u32 top_num_gpcs_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_tpc_per_gpc_r(void) -{ - return 0x00022434; -} -static inline u32 top_tpc_per_gpc_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_num_fbps_r(void) -{ - return 0x00022438; -} -static inline u32 top_num_fbps_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_ltc_per_fbp_r(void) -{ - return 0x00022450; -} -static inline u32 top_ltc_per_fbp_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_slices_per_ltc_r(void) -{ - return 0x0002245c; -} -static inline u32 top_slices_per_ltc_value_v(u32 r) -{ - return (r >> 0) & 0x1f; -} -static inline u32 top_num_ltcs_r(void) -{ - return 0x00022454; -} -static inline u32 top_device_info_r(u32 i) -{ - return 0x00022700 + i*4; -} -static inline u32 top_device_info__size_1_v(void) -{ - return 0x00000040; -} -static inline u32 top_device_info_chain_v(u32 r) -{ - return (r >> 31) & 0x1; -} -static inline u32 top_device_info_chain_enable_v(void) -{ - return 0x00000001; -} -static inline u32 top_device_info_engine_enum_v(u32 r) -{ - return (r >> 26) & 0xf; -} -static inline u32 top_device_info_runlist_enum_v(u32 r) -{ - return (r >> 21) & 0xf; -} -static inline u32 top_device_info_intr_enum_v(u32 r) -{ - return (r >> 15) & 0x1f; -} -static inline u32 top_device_info_reset_enum_v(u32 r) -{ - return (r >> 9) & 0x1f; -} -static inline u32 top_device_info_type_enum_v(u32 r) -{ - return (r >> 2) & 0x1fffffff; -} -static inline u32 top_device_info_type_enum_graphics_v(void) -{ - return 0x00000000; -} -static inline u32 top_device_info_type_enum_graphics_f(void) -{ - return 0x0; -} -static inline u32 top_device_info_type_enum_copy0_v(void) -{ - return 0x00000001; -} -static inline u32 top_device_info_type_enum_copy0_f(void) -{ - return 0x4; -} -static inline u32 top_device_info_entry_v(u32 r) -{ - return (r >> 0) & 0x3; -} -static inline u32 top_device_info_entry_not_valid_v(void) -{ - return 0x00000000; -} -static inline u32 top_device_info_entry_enum_v(void) -{ - return 0x00000002; -} -#endif diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c deleted file mode 100644 index e68e762d3..000000000 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * GP10B L2 - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include - -#include - -#include "gk20a/gk20a.h" -#include "gm20b/ltc_gm20b.h" -#include "hw_proj_gp10b.h" -#include "hw_mc_gp10b.h" -#include "hw_ltc_gp10b.h" - -#include "gk20a/ltc_common.c" - -static int gp10b_determine_L2_size_bytes(struct gk20a *g) -{ - u32 tmp; - int ret; - - gk20a_dbg_fn(""); - - tmp = gk20a_readl(g, ltc_ltc0_lts0_tstg_info_1_r()); - - ret = g->ltc_count * - ltc_ltc0_lts0_tstg_info_1_slice_size_in_kb_v(tmp)*1024 * - ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(tmp); - - gk20a_dbg(gpu_dbg_info, "L2 size: %d\n", ret); - - gk20a_dbg_fn("done"); - - return ret; -} - -static int gp10b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) -{ - /* max memory size (MB) to cover */ - u32 max_size = gr->max_comptag_mem; - /* one tag line covers 64KB */ - u32 max_comptag_lines = max_size << 4; - - u32 hw_max_comptag_lines = - ltc_ltcs_ltss_cbc_ctrl3_clear_upper_bound_init_v(); - - u32 cbc_param = - gk20a_readl(g, ltc_ltcs_ltss_cbc_param_r()); - u32 comptags_per_cacheline = - ltc_ltcs_ltss_cbc_param_comptags_per_cache_line_v(cbc_param); - u32 cacheline_size = - 512 << ltc_ltcs_ltss_cbc_param_cache_line_size_v(cbc_param); - u32 slices_per_ltc = - ltc_ltcs_ltss_cbc_param_slices_per_ltc_v(cbc_param); - u32 cbc_param2 = - gk20a_readl(g, ltc_ltcs_ltss_cbc_param2_r()); - u32 gobs_per_comptagline_per_slice = - ltc_ltcs_ltss_cbc_param2_gobs_per_comptagline_per_slice_v(cbc_param2); - - u32 compbit_backing_size; - - int err; - - gk20a_dbg_fn(""); - - if (max_comptag_lines == 0) - return 0; - - if (max_comptag_lines > hw_max_comptag_lines) - max_comptag_lines = hw_max_comptag_lines; - - compbit_backing_size = - roundup(max_comptag_lines * gobs_per_comptagline_per_slice, - cacheline_size); - compbit_backing_size = - roundup(compbit_backing_size * slices_per_ltc * g->ltc_count, - g->ops.fb.compressible_page_size(g)); - - /* aligned to 2KB * ltc_count */ - compbit_backing_size += - g->ltc_count << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); - - /* must be a multiple of 64KB */ - compbit_backing_size = roundup(compbit_backing_size, 64*1024); - - gk20a_dbg_info("compbit backing store size : %d", - compbit_backing_size); - gk20a_dbg_info("max comptag lines : %d", - max_comptag_lines); - gk20a_dbg_info("gobs_per_comptagline_per_slice: %d", - gobs_per_comptagline_per_slice); - - if (tegra_platform_is_linsim()) - err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); - else - err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); - - if (err) - return err; - - err = gk20a_comptag_allocator_init(&gr->comp_tags, max_comptag_lines); - if (err) - return err; - - gr->comptags_per_cacheline = comptags_per_cacheline; - gr->slices_per_ltc = slices_per_ltc; - gr->cacheline_size = cacheline_size; - gr->gobs_per_comptagline_per_slice = gobs_per_comptagline_per_slice; - - return 0; -} - -static void gp10b_ltc_isr(struct gk20a *g) -{ - u32 mc_intr, ltc_intr; - int ltc, slice; - - mc_intr = gk20a_readl(g, mc_intr_ltc_r()); - gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x", - mc_intr); - for (ltc = 0; ltc < g->ltc_count; ltc++) { - if ((mc_intr & 1 << ltc) == 0) - continue; - for (slice = 0; slice < g->gr.slices_per_ltc; slice++) { - u32 offset = proj_ltc_stride_v() * ltc + - proj_lts_stride_v() * slice; - ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + offset); - - /* Detect and handle ECC errors */ - if (ltc_intr & - ltc_ltcs_ltss_intr_ecc_sec_error_pending_f()) { - u32 ecc_stats_reg_val; - - gk20a_err(dev_from_gk20a(g), - "Single bit error detected in GPU L2!"); - - ecc_stats_reg_val = - gk20a_readl(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset); - g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] += - ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); - ecc_stats_reg_val &= - ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); - gk20a_writel(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset, - ecc_stats_reg_val); - - g->ops.mm.l2_flush(g, true); - } - if (ltc_intr & - ltc_ltcs_ltss_intr_ecc_ded_error_pending_f()) { - u32 ecc_stats_reg_val; - - gk20a_err(dev_from_gk20a(g), - "Double bit error detected in GPU L2!"); - - ecc_stats_reg_val = - gk20a_readl(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset); - g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] += - ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); - ecc_stats_reg_val &= - ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); - gk20a_writel(g, - ltc_ltc0_lts0_dstg_ecc_report_r() + offset, - ecc_stats_reg_val); - } - - gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", - ltc, slice, ltc_intr); - gk20a_writel(g, ltc_ltc0_lts0_intr_r() + - proj_ltc_stride_v() * ltc + - proj_lts_stride_v() * slice, - ltc_intr); - } - } -} - -static void gp10b_ltc_init_fs_state(struct gk20a *g) -{ - u32 ltc_intr; - - gm20b_ltc_init_fs_state(g); - - gk20a_writel(g, ltc_ltca_g_axi_pctrl_r(), - ltc_ltca_g_axi_pctrl_user_sid_f(TEGRA_SID_GPUB)); - - /* Enable ECC interrupts */ - ltc_intr = gk20a_readl(g, ltc_ltcs_ltss_intr_r()); - ltc_intr |= ltc_ltcs_ltss_intr_en_ecc_sec_error_enabled_f() | - ltc_ltcs_ltss_intr_en_ecc_ded_error_enabled_f(); - gk20a_writel(g, ltc_ltcs_ltss_intr_r(), - ltc_intr); -} - -void gp10b_init_ltc(struct gpu_ops *gops) -{ - gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; - gops->ltc.set_max_ways_evict_last = gk20a_ltc_set_max_ways_evict_last; - gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; - gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; - gops->ltc.init_cbc = gk20a_ltc_init_cbc; - - /* GM20b specific ops. */ - gops->ltc.init_fs_state = gp10b_ltc_init_fs_state; - gops->ltc.init_comptags = gp10b_ltc_init_comptags; - gops->ltc.cbc_ctrl = gm20b_ltc_cbc_ctrl; - gops->ltc.elpg_flush = gm20b_ltc_g_elpg_flush_locked; - gops->ltc.isr = gp10b_ltc_isr; - gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; - gops->ltc.flush = gm20b_flush_ltc; -#ifdef CONFIG_DEBUG_FS - gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; -#endif -} diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h deleted file mode 100644 index 7408348e7..000000000 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef LTC_GP10B_H -#define LTC_GP10B_H -struct gpu_ops; - -void gp10b_init_ltc(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c deleted file mode 100644 index 47c8fcc6f..000000000 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ /dev/null @@ -1,167 +0,0 @@ -/* - * GP20B master - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include - -#include "gk20a/gk20a.h" -#include "mc_gp10b.h" -#include "hw_mc_gp10b.h" - -void mc_gp10b_intr_enable(struct gk20a *g) -{ - u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), - 0xffffffff); - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = - mc_intr_pfifo_pending_f() - | mc_intr_replayable_fault_pending_f() - | eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), - 0xffffffff); - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = - mc_intr_pfifo_pending_f() - | mc_intr_priv_ring_pending_f() - | mc_intr_ltc_pending_f() - | mc_intr_pbus_pending_f() - | eng_intr_mask; - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); -} - -void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, - bool is_stalling, u32 mask) -{ - u32 intr_index = 0; - u32 reg = 0; - - intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : - NVGPU_MC_INTR_NONSTALLING); - if (enable) { - reg = mc_intr_en_set_r(intr_index); - g->ops.mc.intr_mask_restore[intr_index] |= mask; - - } else { - reg = mc_intr_en_clear_r(intr_index); - g->ops.mc.intr_mask_restore[intr_index] &= ~mask; - } - - gk20a_writel(g, reg, mask); -} - -irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) -{ - u32 mc_intr_0; - - if (!g->power_on) - return IRQ_NONE; - - /* not from gpu when sharing irq with others */ - mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); - if (unlikely(!mc_intr_0)) - return IRQ_NONE; - - gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); - - return IRQ_WAKE_THREAD; -} - -irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) -{ - u32 mc_intr_1; - - if (!g->power_on) - return IRQ_NONE; - - /* not from gpu when sharing irq with others */ - mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); - if (unlikely(!mc_intr_1)) - return IRQ_NONE; - - gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); - - return IRQ_WAKE_THREAD; -} - -irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) -{ - u32 mc_intr_0; - - gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); - - mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); - - gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); - - if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) - gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); - if (mc_intr_0 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) - && g->ops.ce2.isr_stall) - g->ops.ce2.isr_stall(g); - if (mc_intr_0 & mc_intr_pfifo_pending_f()) - gk20a_fifo_isr(g); - if (mc_intr_0 & mc_intr_pmu_pending_f()) - gk20a_pmu_isr(g); - if (mc_intr_0 & mc_intr_priv_ring_pending_f()) - gk20a_priv_ring_isr(g); - if (mc_intr_0 & mc_intr_ltc_pending_f()) - g->ops.ltc.isr(g); - if (mc_intr_0 & mc_intr_pbus_pending_f()) - gk20a_pbus_isr(g); - - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); - - return IRQ_HANDLED; -} - -irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) -{ - u32 mc_intr_1; - - gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); - - mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); - - gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1); - - if (mc_intr_1 & mc_intr_pfifo_pending_f()) - gk20a_fifo_nonstall_isr(g); - if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) - gk20a_gr_nonstall_isr(g); - if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) - && g->ops.ce2.isr_nonstall) - g->ops.ce2.isr_nonstall(g); - - - - gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), - g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); - - return IRQ_HANDLED; -} - -void gp10b_init_mc(struct gpu_ops *gops) -{ - gops->mc.intr_enable = mc_gp10b_intr_enable; - gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; - gops->mc.isr_stall = mc_gp10b_isr_stall; - gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; - gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; - gops->mc.isr_thread_nonstall = mc_gp10b_intr_thread_nonstall; -} diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h deleted file mode 100644 index b2ec4be4c..000000000 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef MC_GP20B_H -#define MC_GP20B_H -struct gk20a; - -enum MC_INTERRUPT_REGLIST { - NVGPU_MC_INTR_STALLING = 0, - NVGPU_MC_INTR_NONSTALLING, -}; - -void gp10b_init_mc(struct gpu_ops *gops); -void mc_gp10b_intr_enable(struct gk20a *g); -void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, - bool is_stalling, u32 mask); -irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); -irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); -irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); -irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c deleted file mode 100644 index d4a4e7f3d..000000000 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * GP10B MMU - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include "gk20a/gk20a.h" -#include "mm_gp10b.h" -#include "rpfb_gp10b.h" -#include "hw_ram_gp10b.h" -#include "hw_bus_gp10b.h" -#include "hw_gmmu_gp10b.h" -#include "gk20a/semaphore_gk20a.h" - -static u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g) -{ - return 36; -} - -static int gp10b_init_mm_setup_hw(struct gk20a *g) -{ - struct mm_gk20a *mm = &g->mm; - struct mem_desc *inst_block = &mm->bar1.inst_block; - phys_addr_t inst_pa = gk20a_mem_phys(inst_block); - int err = 0; - - gk20a_dbg_fn(""); - - g->ops.fb.set_mmu_page_size(g); - - inst_pa = (u32)(inst_pa >> bar1_instance_block_shift_gk20a()); - gk20a_dbg_info("bar1 inst block ptr: 0x%08x", (u32)inst_pa); - - gk20a_writel(g, bus_bar1_block_r(), - bus_bar1_block_target_vid_mem_f() | - bus_bar1_block_mode_virtual_f() | - bus_bar1_block_ptr_f(inst_pa)); - - if (g->ops.mm.init_bar2_mm_hw_setup) { - err = g->ops.mm.init_bar2_mm_hw_setup(g); - if (err) - return err; - } - - if (gk20a_mm_fb_flush(g) || gk20a_mm_fb_flush(g)) - return -EBUSY; - - err = gp10b_replayable_pagefault_buffer_init(g); - - gk20a_dbg_fn("done"); - return err; - -} - -static int gb10b_init_bar2_vm(struct gk20a *g) -{ - int err; - struct mm_gk20a *mm = &g->mm; - struct vm_gk20a *vm = &mm->bar2.vm; - struct mem_desc *inst_block = &mm->bar2.inst_block; - u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size; - - /* BAR2 aperture size is 32MB */ - mm->bar2.aperture_size = 32 << 20; - gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size); - gk20a_init_vm(mm, vm, big_page_size, SZ_4K, - mm->bar2.aperture_size - SZ_4K, - mm->bar2.aperture_size, false, false, "bar2"); - - /* allocate instance mem for bar2 */ - err = gk20a_alloc_inst_block(g, inst_block); - if (err) - goto clean_up_va; - - gk20a_init_inst_block(inst_block, vm, big_page_size); - - return 0; - -clean_up_va: - gk20a_deinit_vm(vm); - return err; -} - - -static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g) -{ - struct mm_gk20a *mm = &g->mm; - struct mem_desc *inst_block = &mm->bar2.inst_block; - phys_addr_t inst_pa = gk20a_mem_phys(inst_block); - - gk20a_dbg_fn(""); - - g->ops.fb.set_mmu_page_size(g); - - inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v()); - gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa); - - gk20a_writel(g, bus_bar2_block_r(), - bus_bar2_block_target_vid_mem_f() | - bus_bar2_block_mode_virtual_f() | - bus_bar2_block_ptr_f(inst_pa)); - - gk20a_dbg_fn("done"); - return 0; -} - -static u64 gp10b_mm_phys_addr_translate(struct gk20a *g, u64 phys_addr, - u32 flags) -{ - if (!device_is_iommuable(dev_from_gk20a(g))) - if (flags & NVGPU_AS_MAP_BUFFER_FLAGS_IO_COHERENT) - return phys_addr | - 1ULL << NVGPU_MM_GET_IO_COHERENCE_BIT; - - return phys_addr; -} - -static u64 gp10b_mm_iova_addr(struct gk20a *g, struct scatterlist *sgl, - u32 flags) -{ - if (!device_is_iommuable(dev_from_gk20a(g))) - return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags); - - if (sg_dma_address(sgl) == 0) - return gp10b_mm_phys_addr_translate(g, sg_phys(sgl), flags); - - if (sg_dma_address(sgl) == DMA_ERROR_CODE) - return 0; - - return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl)); -} - -static u32 *pde3_from_index(struct gk20a_mm_entry *entry, u32 i) -{ - return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_pde__size_v()); -} - -static int update_gmmu_pde3_locked(struct vm_gk20a *vm, - struct gk20a_mm_entry *parent, - u32 i, u32 gmmu_pgsz_idx, - struct scatterlist **sgl, - u64 *offset, - u64 *iova, - u32 kind_v, u64 *ctag, - bool cacheable, bool unmapped_pte, - int rw_flag, bool sparse, bool priv) -{ - u64 pte_addr = 0; - u64 pde_addr = 0; - struct gk20a_mm_entry *pte = parent->entries + i; - u32 pde_v[2] = {0, 0}; - u32 *pde; - - gk20a_dbg_fn(""); - - pte_addr = sg_phys(pte->sgt->sgl) >> gmmu_new_pde_address_shift_v(); - pde_addr = sg_phys(parent->sgt->sgl); - - pde_v[0] |= gmmu_new_pde_aperture_video_memory_f(); - pde_v[0] |= gmmu_new_pde_address_sys_f(u64_lo32(pte_addr)); - pde_v[0] |= gmmu_new_pde_vol_true_f(); - pde_v[1] |= pte_addr >> 24; - pde = pde3_from_index(parent, i); - - gk20a_mem_wr32(pde, 0, pde_v[0]); - gk20a_mem_wr32(pde, 1, pde_v[1]); - - gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d = 0x%x,0x%08x", - i, gmmu_pgsz_idx, pde_v[1], pde_v[0]); - gk20a_dbg_fn("done"); - return 0; -} - -static u32 *pde0_from_index(struct gk20a_mm_entry *entry, u32 i) -{ - return (u32 *) (((u8 *)entry->cpu_va) + i*gmmu_new_dual_pde__size_v()); -} - -static int update_gmmu_pde0_locked(struct vm_gk20a *vm, - struct gk20a_mm_entry *pte, - u32 i, u32 gmmu_pgsz_idx, - struct scatterlist **sgl, - u64 *offset, - u64 *iova, - u32 kind_v, u64 *ctag, - bool cacheable, bool unmapped_pte, - int rw_flag, bool sparse, bool priv) -{ - bool small_valid, big_valid; - u32 pte_addr_small = 0, pte_addr_big = 0; - struct gk20a_mm_entry *entry = pte->entries + i; - u32 pde_v[4] = {0, 0, 0, 0}; - u32 *pde; - - gk20a_dbg_fn(""); - - small_valid = entry->size && entry->pgsz == gmmu_page_size_small; - big_valid = entry->size && entry->pgsz == gmmu_page_size_big; - - if (small_valid) - pte_addr_small = sg_phys(entry->sgt->sgl) - >> gmmu_new_dual_pde_address_shift_v(); - - if (big_valid) - pte_addr_big = sg_phys(entry->sgt->sgl) - >> gmmu_new_dual_pde_address_big_shift_v(); - - if (small_valid) { - pde_v[2] |= gmmu_new_dual_pde_address_small_sys_f(pte_addr_small); - pde_v[2] |= gmmu_new_dual_pde_aperture_small_video_memory_f(); - pde_v[2] |= gmmu_new_dual_pde_vol_small_true_f(); - pde_v[3] |= pte_addr_small >> 24; - } - - if (big_valid) { - pde_v[0] |= gmmu_new_dual_pde_address_big_sys_f(pte_addr_big); - pde_v[0] |= gmmu_new_dual_pde_vol_big_true_f(); - pde_v[0] |= gmmu_new_dual_pde_aperture_big_video_memory_f(); - pde_v[1] |= pte_addr_big >> 28; - } - - pde = pde0_from_index(pte, i); - - gk20a_mem_wr32(pde, 0, pde_v[0]); - gk20a_mem_wr32(pde, 1, pde_v[1]); - gk20a_mem_wr32(pde, 2, pde_v[2]); - gk20a_mem_wr32(pde, 3, pde_v[3]); - - gk20a_dbg(gpu_dbg_pte, "pde:%d,sz=%d [0x%08x, 0x%08x, 0x%x, 0x%08x]", - i, gmmu_pgsz_idx, pde_v[3], pde_v[2], pde_v[1], pde_v[0]); - gk20a_dbg_fn("done"); - return 0; -} - -static int update_gmmu_pte_locked(struct vm_gk20a *vm, - struct gk20a_mm_entry *pte, - u32 i, u32 gmmu_pgsz_idx, - struct scatterlist **sgl, - u64 *offset, - u64 *iova, - u32 kind_v, u64 *ctag, - bool cacheable, bool unmapped_pte, - int rw_flag, bool sparse, bool priv) -{ - struct gk20a *g = vm->mm->g; - u32 page_size = vm->gmmu_page_sizes[gmmu_pgsz_idx]; - u64 ctag_granularity = g->ops.fb.compression_page_size(g); - u32 pte_w[2] = {0, 0}; /* invalid pte */ - - gk20a_dbg_fn(""); - - if (*iova) { - if (unmapped_pte) - pte_w[0] = gmmu_new_pte_valid_false_f(); - else - pte_w[0] = gmmu_new_pte_valid_true_f(); - pte_w[0] |= gmmu_new_pte_aperture_video_memory_f() | - gmmu_new_pte_address_sys_f(*iova - >> gmmu_new_pte_address_shift_v()); - - if (priv) - pte_w[0] |= gmmu_new_pte_privilege_true_f(); - - pte_w[1] = *iova >> (24 + gmmu_new_pte_address_shift_v()) | - gmmu_new_pte_kind_f(kind_v) | - gmmu_new_pte_comptagline_f((u32)(*ctag / ctag_granularity)); - - if (rw_flag == gk20a_mem_flag_read_only) - pte_w[0] |= gmmu_new_pte_read_only_true_f(); - if (unmapped_pte && !cacheable) - pte_w[0] |= gmmu_new_pte_read_only_true_f(); - else if (!cacheable) - pte_w[0] |= gmmu_new_pte_vol_true_f(); - - gk20a_dbg(gpu_dbg_pte, "pte=%d iova=0x%llx kind=%d" - " ctag=%d vol=%d" - " [0x%08x, 0x%08x]", - i, *iova, - kind_v, (u32)(*ctag / ctag_granularity), !cacheable, - pte_w[1], pte_w[0]); - - if (*ctag) - *ctag += page_size; - } else if (sparse) { - pte_w[0] = gmmu_new_pte_valid_false_f(); - pte_w[0] |= gmmu_new_pte_vol_true_f(); - } else { - gk20a_dbg(gpu_dbg_pte, "pte_cur=%d [0x0,0x0]", i); - } - - gk20a_mem_wr32(pte->cpu_va + i*8, 0, pte_w[0]); - gk20a_mem_wr32(pte->cpu_va + i*8, 1, pte_w[1]); - - if (*iova) { - *iova += page_size; - *offset += page_size; - if (*sgl && *offset + page_size > (*sgl)->length) { - u64 new_iova; - *sgl = sg_next(*sgl); - if (*sgl) { - new_iova = sg_phys(*sgl); - gk20a_dbg(gpu_dbg_pte, "chunk address %llx, size %d", - new_iova, (*sgl)->length); - if (new_iova) { - *offset = 0; - *iova = new_iova; - } - } - } - } - gk20a_dbg_fn("done"); - return 0; -} - -static const struct gk20a_mmu_level gp10b_mm_levels[] = { - {.hi_bit = {48, 48}, - .lo_bit = {47, 47}, - .update_entry = update_gmmu_pde3_locked, - .entry_size = 8}, - {.hi_bit = {46, 46}, - .lo_bit = {38, 38}, - .update_entry = update_gmmu_pde3_locked, - .entry_size = 8}, - {.hi_bit = {37, 37}, - .lo_bit = {29, 29}, - .update_entry = update_gmmu_pde3_locked, - .entry_size = 8}, - {.hi_bit = {28, 28}, - .lo_bit = {21, 21}, - .update_entry = update_gmmu_pde0_locked, - .entry_size = 16}, - {.hi_bit = {20, 20}, - .lo_bit = {12, 16}, - .update_entry = update_gmmu_pte_locked, - .entry_size = 8}, - {.update_entry = NULL} -}; - -static const struct gk20a_mmu_level *gp10b_mm_get_mmu_levels(struct gk20a *g, - u32 big_page_size) -{ - return gp10b_mm_levels; -} - -static void gp10b_mm_init_pdb(struct gk20a *g, void *inst_ptr, u64 pdb_addr) -{ - u32 pdb_addr_lo = u64_lo32(pdb_addr >> ram_in_base_shift_v()); - u32 pdb_addr_hi = u64_hi32(pdb_addr); - - gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_lo_w(), - ram_in_page_dir_base_target_vid_mem_f() | - ram_in_page_dir_base_vol_true_f() | - ram_in_page_dir_base_lo_f(pdb_addr_lo) | - 1 << 10); - - gk20a_mem_wr32(inst_ptr, ram_in_page_dir_base_hi_w(), - ram_in_page_dir_base_hi_f(pdb_addr_hi)); -} - -static void gp10b_remove_bar2_vm(struct gk20a *g) -{ - struct mm_gk20a *mm = &g->mm; - - gp10b_replayable_pagefault_buffer_deinit(g); - gk20a_remove_vm(&mm->bar2.vm, &mm->bar2.inst_block); -} - - -void gp10b_init_mm(struct gpu_ops *gops) -{ - gm20b_init_mm(gops); - gops->mm.get_physical_addr_bits = gp10b_mm_get_physical_addr_bits; - gops->mm.init_mm_setup_hw = gp10b_init_mm_setup_hw; - gops->mm.init_bar2_vm = gb10b_init_bar2_vm; - gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup; - gops->mm.get_iova_addr = gp10b_mm_iova_addr; - gops->mm.get_mmu_levels = gp10b_mm_get_mmu_levels; - gops->mm.init_pdb = gp10b_mm_init_pdb; - gops->mm.remove_bar2_vm = gp10b_remove_bar2_vm; -} diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h deleted file mode 100644 index 034944e05..000000000 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef MM_GP10B_H -#define MM_GP10B_H - -#define NVGPU_MM_GET_IO_COHERENCE_BIT 35 - -struct gpu_ops; - -void gp10b_init_mm(struct gpu_ops *gops); -#endif diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c deleted file mode 100644 index 27274e955..000000000 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ /dev/null @@ -1,737 +0,0 @@ -/* - * drivers/video/tegra/host/gk20a/platform_gk20a_tegra.c - * - * GK20A Tegra Platform Interface - * - * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "gk20a/platform_gk20a.h" -#include "gk20a/gk20a.h" -#include "gk20a/gk20a_scale.h" -#include "platform_tegra.h" -#include "gr_gp10b.h" -#include "ltc_gp10b.h" -#include "hw_gr_gp10b.h" -#include "hw_ltc_gp10b.h" -#include "gp10b_sysfs.h" -#include - -#define GP10B_MAX_SUPPORTED_FREQS 11 -static unsigned long gp10b_freq_table[GP10B_MAX_SUPPORTED_FREQS]; - -#define TEGRA_GP10B_BW_PER_FREQ 64 -#define TEGRA_DDR4_BW_PER_FREQ 16 - -#define EMC_BW_RATIO (TEGRA_GP10B_BW_PER_FREQ / TEGRA_DDR4_BW_PER_FREQ) - -static struct { - char *name; - unsigned long default_rate; -} tegra_gp10b_clocks[] = { - {"gpu", 1000000000}, - {"gpu_sys", 204000000} }; - -static void gr_gp10b_remove_sysfs(struct device *dev); - -/* - * gp10b_tegra_get_clocks() - * - * This function finds clocks in tegra platform and populates - * the clock information to gp10b platform data. - */ - -static int gp10b_tegra_get_clocks(struct platform_device *pdev) -{ - struct gk20a_platform *platform = platform_get_drvdata(pdev); - struct gk20a *g = get_gk20a(pdev); - struct device *dev = dev_from_gk20a(g); - int i; - - if (tegra_platform_is_linsim()) - return 0; - - platform->num_clks = 0; - for (i = 0; i < ARRAY_SIZE(tegra_gp10b_clocks); i++) { - long rate = tegra_gp10b_clocks[i].default_rate; - struct clk *c; - - c = clk_get(dev, tegra_gp10b_clocks[i].name); - if (IS_ERR(c)) { - gk20a_err(&pdev->dev, "cannot get clock %s", - tegra_gp10b_clocks[i].name); - } else { - clk_set_rate(c, rate); - platform->clk[i] = c; - } - } - platform->num_clks = i; - - return 0; -} - -static void gp10b_tegra_scale_init(struct platform_device *pdev) -{ - struct gk20a_platform *platform = gk20a_get_platform(pdev); - struct gk20a_scale_profile *profile = platform->g->scale_profile; - struct tegra_bwmgr_client *bwmgr_handle; - - bwmgr_handle = tegra_bwmgr_register(TEGRA_BWMGR_CLIENT_GPU); - if (!bwmgr_handle) - return; - - profile->private_data = (void *)bwmgr_handle; -} - -static void gp10b_tegra_scale_exit(struct platform_device *pdev) -{ - struct gk20a_platform *platform = gk20a_get_platform(pdev); - struct gk20a_scale_profile *profile = platform->g->scale_profile; - - if (profile) - tegra_bwmgr_unregister( - (struct tegra_bwmgr_client *)profile->private_data); -} - - -static int gp10b_tegra_probe(struct platform_device *pdev) -{ - struct gk20a_platform *platform = gk20a_get_platform(pdev); - struct device_node *np = pdev->dev.of_node; - struct device_node *host1x_node; - struct platform_device *host1x_pdev; - const __be32 *host1x_ptr; - - host1x_ptr = of_get_property(np, "nvidia,host1x", NULL); - if (!host1x_ptr) { - gk20a_err(&pdev->dev, "host1x device not available"); - return -ENOSYS; - } - - host1x_node = of_find_node_by_phandle(be32_to_cpup(host1x_ptr)); - host1x_pdev = of_find_device_by_node(host1x_node); - if (!host1x_pdev) { - gk20a_err(&pdev->dev, "host1x device not available"); - return -ENOSYS; - } - - platform->g->host1x_dev = host1x_pdev; - platform->bypass_smmu = !device_is_iommuable(&pdev->dev); - platform->disable_bigpage = platform->bypass_smmu; - - platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close - = false; - platform->g->gr.t18x.ctx_vars.dump_ctxsw_stats_on_channel_close - = false; - - platform->g->gr.t18x.ctx_vars.force_preemption_gfxp = false; - platform->g->gr.t18x.ctx_vars.force_preemption_cilp = false; - - platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_gfxp = - debugfs_create_bool("force_preemption_gfxp", S_IRUGO|S_IWUSR, - platform->debugfs, - &platform->g->gr.t18x.ctx_vars.force_preemption_gfxp); - - platform->g->gr.t18x.ctx_vars.debugfs_force_preemption_cilp = - debugfs_create_bool("force_preemption_cilp", S_IRUGO|S_IWUSR, - platform->debugfs, - &platform->g->gr.t18x.ctx_vars.force_preemption_cilp); - - platform->g->gr.t18x.ctx_vars.debugfs_dump_ctxsw_stats = - debugfs_create_bool("dump_ctxsw_stats_on_channel_close", - S_IRUGO|S_IWUSR, - platform->debugfs, - &platform->g->gr.t18x. - ctx_vars.dump_ctxsw_stats_on_channel_close); - - gp10b_tegra_get_clocks(pdev); - - return 0; -} - -static int gp10b_tegra_late_probe(struct platform_device *pdev) -{ - /* Make gk20a power domain a subdomain of host1x */ - nvhost_register_client_domain(dev_to_genpd(&pdev->dev)); - /*Create GP10B specific sysfs*/ - gp10b_create_sysfs(pdev); - - /* Initialise tegra specific scaling quirks */ - gp10b_tegra_scale_init(pdev); - return 0; -} - -static int gp10b_tegra_remove(struct platform_device *pdev) -{ - /* remove gk20a power subdomain from host1x */ - nvhost_unregister_client_domain(dev_to_genpd(&pdev->dev)); - gr_gp10b_remove_sysfs(&pdev->dev); - /*Remove GP10B specific sysfs*/ - gp10b_remove_sysfs(&pdev->dev); - - /* deinitialise tegra specific scaling quirks */ - gp10b_tegra_scale_exit(pdev); - - return 0; - -} - -static bool gp10b_tegra_is_railgated(struct platform_device *pdev) -{ - bool ret = false; - - if (tegra_bpmp_running()) - ret = !tegra_powergate_is_powered(TEGRA_POWERGATE_GPU); - - return ret; -} - -static int gp10b_tegra_railgate(struct platform_device *pdev) -{ - struct gk20a_platform *platform = gk20a_get_platform(pdev); - - if (tegra_bpmp_running() && - tegra_powergate_is_powered(TEGRA_POWERGATE_GPU)) { - int i; - for (i = 0; i < platform->num_clks; i++) { - if (platform->clk[i]) - clk_disable_unprepare(platform->clk[i]); - } - tegra_powergate_partition(TEGRA_POWERGATE_GPU); - } - return 0; -} - -static int gp10b_tegra_unrailgate(struct platform_device *pdev) -{ - int ret = 0; - struct gk20a_platform *platform = gk20a_get_platform(pdev); - - if (tegra_bpmp_running()) { - int i; - ret = tegra_unpowergate_partition(TEGRA_POWERGATE_GPU); - for (i = 0; i < platform->num_clks; i++) { - if (platform->clk[i]) - clk_prepare_enable(platform->clk[i]); - } - } - return ret; -} - -static int gp10b_tegra_suspend(struct device *dev) -{ - return 0; -} - -static int gp10b_tegra_reset_assert(struct platform_device *dev) -{ - struct gk20a_platform *platform = gk20a_get_platform(dev); - int ret = 0; - - if (!platform->reset_control) - return -EINVAL; - - ret = reset_control_assert(platform->reset_control); - - return ret; -} - -static int gp10b_tegra_reset_deassert(struct platform_device *dev) -{ - struct gk20a_platform *platform = gk20a_get_platform(dev); - int ret = 0; - - if (!platform->reset_control) - return -EINVAL; - - ret = reset_control_deassert(platform->reset_control); - - return ret; -} - -static void gp10b_tegra_prescale(struct platform_device *pdev) -{ - struct gk20a *g = get_gk20a(pdev); - u32 avg = 0; - - gk20a_dbg_fn(""); - - gk20a_pmu_load_norm(g, &avg); - - gk20a_dbg_fn("done"); -} - -static void gp10b_tegra_postscale(struct platform_device *pdev, - unsigned long freq) -{ - struct gk20a_platform *platform = gk20a_get_platform(pdev); - struct gk20a_scale_profile *profile = platform->g->scale_profile; - struct gk20a *g = get_gk20a(pdev); - unsigned long emc_rate; - - gk20a_dbg_fn(""); - if (profile) { - emc_rate = (freq * EMC_BW_RATIO * g->emc3d_ratio) / 1000; - - if (emc_rate > tegra_bwmgr_get_max_emc_rate()) - emc_rate = tegra_bwmgr_get_max_emc_rate(); - - tegra_bwmgr_set_emc( - (struct tegra_bwmgr_client *)profile->private_data, - emc_rate, TEGRA_BWMGR_SET_EMC_FLOOR); - } - gk20a_dbg_fn("done"); -} - -static unsigned long gp10b_get_clk_rate(struct platform_device *dev) -{ - struct gk20a_platform *platform = gk20a_get_platform(dev); - - return clk_get_rate(platform->clk[0]); - -} - -static long gp10b_round_clk_rate(struct platform_device *dev, - unsigned long rate) -{ - struct gk20a_platform *platform = gk20a_get_platform(dev); - - return clk_round_rate(platform->clk[0], rate); -} - -static int gp10b_set_clk_rate(struct platform_device *dev, unsigned long rate) -{ - struct gk20a_platform *platform = gk20a_get_platform(dev); - - return clk_set_rate(platform->clk[0], rate); -} - -static int gp10b_clk_get_freqs(struct platform_device *pdev, - unsigned long **freqs, int *num_freqs) -{ - struct gk20a_platform *platform = gk20a_get_platform(pdev); - unsigned long min_rate, max_rate, freq_step, rate; - int i; - - min_rate = clk_round_rate(platform->clk[0], 0); - max_rate = clk_round_rate(platform->clk[0], (UINT_MAX - 1)); - freq_step = (max_rate - min_rate)/(GP10B_MAX_SUPPORTED_FREQS - 1); - gk20a_dbg_info("min rate: %ld max rate: %ld freq step %ld\n", - min_rate, max_rate, freq_step); - - for (i = 0; i < GP10B_MAX_SUPPORTED_FREQS; i++) { - rate = min_rate + i * freq_step; - gp10b_freq_table[i] = clk_round_rate(platform->clk[0], rate); - } - /* Fill freq table */ - *freqs = gp10b_freq_table; - *num_freqs = GP10B_MAX_SUPPORTED_FREQS; - return 0; -} - -struct gk20a_platform t18x_gpu_tegra_platform = { - .has_syncpoints = true, - - /* power management configuration */ - .railgate_delay = 500, - .clockgate_delay = 50, - - /* power management configuration */ - .can_railgate = true, - .enable_elpg = true, - .enable_blcg = true, - .enable_slcg = true, - .enable_elcg = true, - .enable_aelpg = true, - - /* ptimer src frequency in hz*/ - .ptimer_src_freq = 31250000, - - .ch_wdt_timeout_ms = 5000, - - .probe = gp10b_tegra_probe, - .late_probe = gp10b_tegra_late_probe, - .remove = gp10b_tegra_remove, - - /* power management callbacks */ - .suspend = gp10b_tegra_suspend, - .railgate = gp10b_tegra_railgate, - .unrailgate = gp10b_tegra_unrailgate, - .is_railgated = gp10b_tegra_is_railgated, - - .busy = gk20a_tegra_busy, - .idle = gk20a_tegra_idle, - - .dump_platform_dependencies = gk20a_tegra_debug_dump, - - .default_big_page_size = SZ_64K, - - .has_cde = true, - - .clk_get_rate = gp10b_get_clk_rate, - .clk_round_rate = gp10b_round_clk_rate, - .clk_set_rate = gp10b_set_clk_rate, - .get_clk_freqs = gp10b_clk_get_freqs, - - /* frequency scaling configuration */ - .prescale = gp10b_tegra_prescale, - .postscale = gp10b_tegra_postscale, - - .devfreq_governor = "nvhost_podgov", - .qos_id = PM_QOS_GPU_FREQ_MIN, - - .secure_alloc = gk20a_tegra_secure_alloc, - .secure_page_alloc = gk20a_tegra_secure_page_alloc, - - .reset_assert = gp10b_tegra_reset_assert, - .reset_deassert = gp10b_tegra_reset_deassert, - - .force_reset_in_do_idle = true, -}; - - -#define ECC_STAT_NAME_MAX_SIZE 100 - - -static DEFINE_HASHTABLE(ecc_hash_table, 5); - -static struct device_attribute *dev_attr_sm_lrf_ecc_single_err_count_array; -static struct device_attribute *dev_attr_sm_lrf_ecc_double_err_count_array; - -static struct device_attribute *dev_attr_sm_shm_ecc_sec_count_array; -static struct device_attribute *dev_attr_sm_shm_ecc_sed_count_array; -static struct device_attribute *dev_attr_sm_shm_ecc_ded_count_array; - -static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe0_count_array; -static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe0_count_array; -static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe0_count_array; -static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe0_count_array; -static struct device_attribute *dev_attr_tex_ecc_total_sec_pipe1_count_array; -static struct device_attribute *dev_attr_tex_ecc_total_ded_pipe1_count_array; -static struct device_attribute *dev_attr_tex_ecc_unique_sec_pipe1_count_array; -static struct device_attribute *dev_attr_tex_ecc_unique_ded_pipe1_count_array; - -static struct device_attribute *dev_attr_l2_ecc_sec_count_array; -static struct device_attribute *dev_attr_l2_ecc_ded_count_array; - - -static u32 gen_ecc_hash_key(char *str) -{ - int i = 0; - u32 hash_key = 0; - - while (str[i]) { - hash_key += (u32)(str[i]); - i++; - }; - - return hash_key; -} - -static ssize_t ecc_stat_show(struct device *dev, - struct device_attribute *attr, - char *buf) -{ - const char *ecc_stat_full_name = attr->attr.name; - const char *ecc_stat_base_name; - unsigned int hw_unit; - struct ecc_stat *ecc_stat; - u32 hash_key; - - if (sscanf(ecc_stat_full_name, "ltc%u", &hw_unit) == 1) { - ecc_stat_base_name = &(ecc_stat_full_name[strlen("ltc0_")]); - } else if (sscanf(ecc_stat_full_name, "gpc0_tpc%u", &hw_unit) == 1) { - ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_tpc0_")]); - } else { - return snprintf(buf, - PAGE_SIZE, - "Error: Invalid ECC stat name!\n"); - } - - hash_key = gen_ecc_hash_key((char *)ecc_stat_base_name); - hash_for_each_possible(ecc_hash_table, - ecc_stat, - hash_node, - hash_key) { - if (!strcmp(ecc_stat_full_name, ecc_stat->names[hw_unit])) - return snprintf(buf, PAGE_SIZE, "%u\n", ecc_stat->counters[hw_unit]); - } - - return snprintf(buf, PAGE_SIZE, "Error: No ECC stat found!\n"); -} - -static int ecc_stat_create(struct platform_device *dev, - int is_l2, - char *ecc_stat_name, - struct ecc_stat *ecc_stat, - struct device_attribute *dev_attr_array) -{ - int error = 0; - struct gk20a *g = get_gk20a(dev); - int num_hw_units = 0; - int hw_unit = 0; - u32 hash_key = 0; - - if (is_l2) - num_hw_units = g->ltc_count; - else - num_hw_units = g->gr.tpc_count; - - /* Allocate arrays */ - dev_attr_array = kzalloc(sizeof(struct device_attribute) * num_hw_units, GFP_KERNEL); - ecc_stat->counters = kzalloc(sizeof(u32) * num_hw_units, GFP_KERNEL); - ecc_stat->names = kzalloc(sizeof(char *) * num_hw_units, GFP_KERNEL); - for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { - ecc_stat->names[hw_unit] = kzalloc(sizeof(char) * ECC_STAT_NAME_MAX_SIZE, GFP_KERNEL); - } - - for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { - /* Fill in struct device_attribute members */ - if (is_l2) - snprintf(ecc_stat->names[hw_unit], - ECC_STAT_NAME_MAX_SIZE, - "ltc%d_%s", - hw_unit, - ecc_stat_name); - else - snprintf(ecc_stat->names[hw_unit], - ECC_STAT_NAME_MAX_SIZE, - "gpc0_tpc%d_%s", - hw_unit, - ecc_stat_name); - dev_attr_array[hw_unit].attr.name = ecc_stat->names[hw_unit]; - dev_attr_array[hw_unit].attr.mode = VERIFY_OCTAL_PERMISSIONS(S_IRUGO); - dev_attr_array[hw_unit].show = ecc_stat_show; - dev_attr_array[hw_unit].store = NULL; - - /* Create sysfs file */ - error |= device_create_file(&dev->dev, - &dev_attr_array[hw_unit]); - } - - /* Add hash table entry */ - hash_key = gen_ecc_hash_key(ecc_stat_name); - hash_add(ecc_hash_table, - &ecc_stat->hash_node, - hash_key); - - return error; -} - -static void ecc_stat_remove(struct device *dev, - int is_l2, - struct ecc_stat *ecc_stat, - struct device_attribute *dev_attr_array) -{ - struct platform_device *ndev = to_platform_device(dev); - struct gk20a *g = get_gk20a(ndev); - int num_hw_units = 0; - int hw_unit = 0; - - if (is_l2) - num_hw_units = g->ltc_count; - else - num_hw_units = g->gr.tpc_count; - - /* Remove sysfs files */ - for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { - device_remove_file(dev, &dev_attr_array[hw_unit]); - } - - /* Remove hash table entry */ - hash_del(&ecc_stat->hash_node); - - /* Free arrays */ - kfree(ecc_stat->counters); - for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { - kfree(ecc_stat->names[hw_unit]); - } - kfree(ecc_stat->names); - kfree(dev_attr_array); -} - -void gr_gp10b_create_sysfs(struct platform_device *dev) -{ - int error = 0; - struct gk20a *g = get_gk20a(dev); - - /* This stat creation function is called on GR init. GR can get - initialized multiple times but we only need to create the ECC - stats once. Therefore, add the following check to avoid - creating duplicate stat sysfs nodes. */ - if (g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters != NULL) - return; - - error |= ecc_stat_create(dev, - 0, - "sm_lrf_ecc_single_err_count", - &g->gr.t18x.ecc_stats.sm_lrf_single_err_count, - dev_attr_sm_lrf_ecc_single_err_count_array); - error |= ecc_stat_create(dev, - 0, - "sm_lrf_ecc_double_err_count", - &g->gr.t18x.ecc_stats.sm_lrf_double_err_count, - dev_attr_sm_lrf_ecc_double_err_count_array); - - error |= ecc_stat_create(dev, - 0, - "sm_shm_ecc_sec_count", - &g->gr.t18x.ecc_stats.sm_shm_sec_count, - dev_attr_sm_shm_ecc_sec_count_array); - error |= ecc_stat_create(dev, - 0, - "sm_shm_ecc_sed_count", - &g->gr.t18x.ecc_stats.sm_shm_sed_count, - dev_attr_sm_shm_ecc_sed_count_array); - error |= ecc_stat_create(dev, - 0, - "sm_shm_ecc_ded_count", - &g->gr.t18x.ecc_stats.sm_shm_ded_count, - dev_attr_sm_shm_ecc_ded_count_array); - - error |= ecc_stat_create(dev, - 0, - "tex_ecc_total_sec_pipe0_count", - &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count, - dev_attr_tex_ecc_total_sec_pipe0_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_total_ded_pipe0_count", - &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count, - dev_attr_tex_ecc_total_ded_pipe0_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_unique_sec_pipe0_count", - &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count, - dev_attr_tex_ecc_unique_sec_pipe0_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_unique_ded_pipe0_count", - &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count, - dev_attr_tex_ecc_unique_ded_pipe0_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_total_sec_pipe1_count", - &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count, - dev_attr_tex_ecc_total_sec_pipe1_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_total_ded_pipe1_count", - &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count, - dev_attr_tex_ecc_total_ded_pipe1_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_unique_sec_pipe1_count", - &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count, - dev_attr_tex_ecc_unique_sec_pipe1_count_array); - error |= ecc_stat_create(dev, - 0, - "tex_ecc_unique_ded_pipe1_count", - &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count, - dev_attr_tex_ecc_unique_ded_pipe1_count_array); - - error |= ecc_stat_create(dev, - 1, - "lts0_ecc_sec_count", - &g->gr.t18x.ecc_stats.l2_sec_count, - dev_attr_l2_ecc_sec_count_array); - error |= ecc_stat_create(dev, - 1, - "lts0_ecc_ded_count", - &g->gr.t18x.ecc_stats.l2_ded_count, - dev_attr_l2_ecc_ded_count_array); - - if (error) - dev_err(&dev->dev, "Failed to create sysfs attributes!\n"); -} - -static void gr_gp10b_remove_sysfs(struct device *dev) -{ - struct platform_device *ndev = to_platform_device(dev); - struct gk20a *g = get_gk20a(ndev); - - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.sm_lrf_single_err_count, - dev_attr_sm_lrf_ecc_single_err_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.sm_lrf_double_err_count, - dev_attr_sm_lrf_ecc_double_err_count_array); - - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.sm_shm_sec_count, - dev_attr_sm_shm_ecc_sec_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.sm_shm_sed_count, - dev_attr_sm_shm_ecc_sed_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.sm_shm_ded_count, - dev_attr_sm_shm_ecc_ded_count_array); - - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count, - dev_attr_tex_ecc_total_sec_pipe0_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count, - dev_attr_tex_ecc_total_ded_pipe0_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count, - dev_attr_tex_ecc_unique_sec_pipe0_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count, - dev_attr_tex_ecc_unique_ded_pipe0_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count, - dev_attr_tex_ecc_total_sec_pipe1_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count, - dev_attr_tex_ecc_total_ded_pipe1_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count, - dev_attr_tex_ecc_unique_sec_pipe1_count_array); - ecc_stat_remove(dev, - 0, - &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count, - dev_attr_tex_ecc_unique_ded_pipe1_count_array); - - ecc_stat_remove(dev, - 1, - &g->gr.t18x.ecc_stats.l2_sec_count, - dev_attr_l2_ecc_sec_count_array); - ecc_stat_remove(dev, - 1, - &g->gr.t18x.ecc_stats.l2_ded_count, - dev_attr_l2_ecc_ded_count_array); -} diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c deleted file mode 100644 index 6a7048130..000000000 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * GP10B PMU - * - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include /* for udelay */ -#include -#include "gk20a/gk20a.h" -#include "gk20a/pmu_gk20a.h" -#include "gm20b/acr_gm20b.h" -#include "gm20b/pmu_gm20b.h" - -#include "pmu_gp10b.h" -#include "hw_pwr_gp10b.h" -#include "gp10b_sysfs.h" - -#define gp10b_dbg_pmu(fmt, arg...) \ - gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) -/*! - * Structure/object which single register write need to be done during PG init - * sequence to set PROD values. - */ -struct pg_init_sequence_list { - u32 regaddr; - u32 writeval; -}; - -/* PROD settings for ELPG sequencing registers*/ -static struct pg_init_sequence_list _pginitseq_gp10b[] = { - {0x0010ab10, 0x0000868B} , - {0x0010e118, 0x8590848F} , - {0x0010e000, 0} , - {0x0010e06c, 0x000000A3} , - {0x0010e06c, 0x000000A0} , - {0x0010e06c, 0x00000095} , - {0x0010e06c, 0x000000A6} , - {0x0010e06c, 0x0000008C} , - {0x0010e06c, 0x00000080} , - {0x0010e06c, 0x00000081} , - {0x0010e06c, 0x00000087} , - {0x0010e06c, 0x00000088} , - {0x0010e06c, 0x0000008D} , - {0x0010e06c, 0x00000082} , - {0x0010e06c, 0x00000083} , - {0x0010e06c, 0x00000089} , - {0x0010e06c, 0x0000008A} , - {0x0010e06c, 0x000000A2} , - {0x0010e06c, 0x00000097} , - {0x0010e06c, 0x00000092} , - {0x0010e06c, 0x00000099} , - {0x0010e06c, 0x0000009B} , - {0x0010e06c, 0x0000009D} , - {0x0010e06c, 0x0000009F} , - {0x0010e06c, 0x000000A1} , - {0x0010e06c, 0x00000096} , - {0x0010e06c, 0x00000091} , - {0x0010e06c, 0x00000098} , - {0x0010e06c, 0x0000009A} , - {0x0010e06c, 0x0000009C} , - {0x0010e06c, 0x0000009E} , - {0x0010ab14, 0x00000000} , - {0x0010e024, 0x00000000} , - {0x0010e028, 0x00000000} , - {0x0010e11c, 0x00000000} , - {0x0010ab1c, 0x140B0BFF} , - {0x0010e020, 0x0E2626FF} , - {0x0010e124, 0x251010FF} , - {0x0010ab20, 0x89abcdef} , - {0x0010ab24, 0x00000000} , - {0x0010e02c, 0x89abcdef} , - {0x0010e030, 0x00000000} , - {0x0010e128, 0x89abcdef} , - {0x0010e12c, 0x00000000} , - {0x0010ab28, 0x7FFFFFFF} , - {0x0010ab2c, 0x70000000} , - {0x0010e034, 0x7FFFFFFF} , - {0x0010e038, 0x70000000} , - {0x0010e130, 0x7FFFFFFF} , - {0x0010e134, 0x70000000} , - {0x0010ab30, 0x00000000} , - {0x0010ab34, 0x00000001} , - {0x00020004, 0x00000000} , - {0x0010e138, 0x00000000} , - {0x0010e040, 0x00000000} , - {0x0010e168, 0x00000000} , - {0x0010e114, 0x0000A5A4} , - {0x0010e110, 0x00000000} , - {0x0010e10c, 0x8590848F} , - {0x0010e05c, 0x00000000} , - {0x0010e044, 0x00000000} , - {0x0010a644, 0x0000868B} , - {0x0010a648, 0x00000000} , - {0x0010a64c, 0x00829493} , - {0x0010a650, 0x00000000} , - {0x0010e000, 0} , - {0x0010e068, 0x000000A3} , - {0x0010e068, 0x000000A0} , - {0x0010e068, 0x00000095} , - {0x0010e068, 0x000000A6} , - {0x0010e068, 0x0000008C} , - {0x0010e068, 0x00000080} , - {0x0010e068, 0x00000081} , - {0x0010e068, 0x00000087} , - {0x0010e068, 0x00000088} , - {0x0010e068, 0x0000008D} , - {0x0010e068, 0x00000082} , - {0x0010e068, 0x00000083} , - {0x0010e068, 0x00000089} , - {0x0010e068, 0x0000008A} , - {0x0010e068, 0x000000A2} , - {0x0010e068, 0x00000097} , - {0x0010e068, 0x00000092} , - {0x0010e068, 0x00000099} , - {0x0010e068, 0x0000009B} , - {0x0010e068, 0x0000009D} , - {0x0010e068, 0x0000009F} , - {0x0010e068, 0x000000A1} , - {0x0010e068, 0x00000096} , - {0x0010e068, 0x00000091} , - {0x0010e068, 0x00000098} , - {0x0010e068, 0x0000009A} , - {0x0010e068, 0x0000009C} , - {0x0010e068, 0x0000009E} , - {0x0010e000, 0} , - {0x0010e004, 0x0000008E}, -}; - -static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, - u32 flags) -{ - struct pmu_gk20a *pmu = &g->pmu; - struct pmu_cmd cmd; - u32 seq; - - gk20a_dbg_fn(""); - - gp10b_dbg_pmu("wprinit status = %x\n", g->ops.pmu.lspmuwprinitdone); - if (g->ops.pmu.lspmuwprinitdone) { - /* send message to load FECS falcon */ - memset(&cmd, 0, sizeof(struct pmu_cmd)); - cmd.hdr.unit_id = PMU_UNIT_ACR; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_acr_cmd_bootstrap_multiple_falcons); - cmd.cmd.acr.boot_falcons.cmd_type = - PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS; - cmd.cmd.acr.boot_falcons.flags = flags; - cmd.cmd.acr.boot_falcons.falconidmask = - falconidmask; - cmd.cmd.acr.boot_falcons.usevamask = 0; - cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = - u64_lo32(g->pmu.wpr_buf.gpu_va); - cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = - u64_hi32(g->pmu.wpr_buf.gpu_va); - gp10b_dbg_pmu("PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS:%x\n", - falconidmask); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, - pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); - } - - gk20a_dbg_fn("done"); - return; -} - -static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) -{ - u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; - - /* GM20B PMU supports loading FECS and GPCCS only */ - if (falconidmask == 0) - return -EINVAL; - if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | - (1 << LSF_FALCON_ID_GPCCS))) - return -EINVAL; - g->ops.pmu.lsfloadedfalconid = 0; - /* check whether pmu is ready to bootstrap lsf if not wait for it */ - if (!g->ops.pmu.lspmuwprinitdone) { - pmu_wait_message_cond(&g->pmu, - gk20a_get_gr_idle_timeout(g), - &g->ops.pmu.lspmuwprinitdone, 1); - /* check again if it still not ready indicate an error */ - if (!g->ops.pmu.lspmuwprinitdone) { - gk20a_err(dev_from_gk20a(g), - "PMU not ready to load LSF"); - return -ETIMEDOUT; - } - } - /* load falcon(s) */ - gp10b_pmu_load_multiple_falcons(g, falconidmask, flags); - pmu_wait_message_cond(&g->pmu, - gk20a_get_gr_idle_timeout(g), - &g->ops.pmu.lsfloadedfalconid, falconidmask); - if (g->ops.pmu.lsfloadedfalconid != falconidmask) - return -ETIMEDOUT; - return 0; -} - -static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, - void *param, u32 handle, u32 status) -{ - gk20a_dbg_fn(""); - - if (status != 0) { - gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted"); - /* TBD: disable ELPG */ - return; - } - - gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n", - msg->msg.pg.msg_type); - - return; -} - -static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) -{ - struct pmu_gk20a *pmu = &g->pmu; - struct pmu_cmd cmd; - u32 seq; - - memset(&cmd, 0, sizeof(struct pmu_cmd)); - cmd.hdr.unit_id = PMU_UNIT_PG; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_pg_cmd_gr_init_param); - cmd.cmd.pg.gr_init_param.cmd_type = - PMU_PG_CMD_ID_PG_PARAM; - cmd.cmd.pg.gr_init_param.sub_cmd_id = - PMU_PG_PARAM_CMD_GR_INIT_PARAM; - cmd.cmd.pg.gr_init_param.featuremask = - grfeaturemask; - - gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask); - gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, - pmu_handle_gr_param_msg, pmu, &seq, ~0); - - return 0; -} -static void gp10b_pmu_elpg_statistics(struct gk20a *g, - u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) -{ - struct pmu_gk20a *pmu = &g->pmu; - struct pmu_pg_stats_v1 stats; - - pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, - (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0); - - *ingating_time = stats.total_sleep_timeus; - *ungating_time = stats.total_nonsleep_timeus; - *gating_cnt = stats.entry_count; -} - -static int gp10b_pmu_setup_elpg(struct gk20a *g) -{ - int ret = 0; - u32 reg_writes; - u32 index; - - gk20a_dbg_fn(""); - - if (g->elpg_enabled) { - reg_writes = ((sizeof(_pginitseq_gp10b) / - sizeof((_pginitseq_gp10b)[0]))); - /* Initialize registers with production values*/ - for (index = 0; index < reg_writes; index++) { - gk20a_writel(g, _pginitseq_gp10b[index].regaddr, - _pginitseq_gp10b[index].writeval); - } - } - - gk20a_dbg_fn("done"); - return ret; -} - -static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) -{ - gk20a_writel(g, pwr_falcon_dmatrfbase_r(), - addr); - gk20a_writel(g, pwr_falcon_dmatrfbase1_r(), - 0x0); -} - -static int gp10b_init_pmu_setup_hw1(struct gk20a *g) -{ - struct pmu_gk20a *pmu = &g->pmu; - int err; - - gk20a_dbg_fn(""); - - mutex_lock(&pmu->isr_mutex); - pmu_reset(pmu); - pmu->isr_enabled = true; - mutex_unlock(&pmu->isr_mutex); - - /* setup apertures - virtual */ - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), - pwr_fbif_transcfg_mem_type_virtual_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), - pwr_fbif_transcfg_mem_type_virtual_f()); - - /* setup apertures - physical */ - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_local_fb_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_coherent_sysmem_f()); - gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), - pwr_fbif_transcfg_mem_type_physical_f() | - pwr_fbif_transcfg_target_noncoherent_sysmem_f()); - - err = pmu_bootstrap(pmu); - if (err) - return err; - - gk20a_dbg_fn("done"); - return 0; - -} - -static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg, - void *param, u32 handle, u32 status) -{ - struct pmu_gk20a *pmu = &g->pmu; - struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc = - &msg->msg.lrf_tex_ltc_dram.en_dis; - gk20a_dbg_fn(""); - - if (status != 0) { - gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted"); - return; - } - if (msg->msg.lrf_tex_ltc_dram.msg_type != - PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) { - gk20a_err(dev_from_gk20a(g), - "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd"); - return; - } else if (ecc->pmu_status != 0) { - gk20a_err(dev_from_gk20a(g), - "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x", - ecc->pmu_status); - gk20a_err(dev_from_gk20a(g), - "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x", - ecc->en_fail_mask); - gk20a_err(dev_from_gk20a(g), - "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x", - ecc->dis_fail_mask); - } else - pmu->override_done = 1; - gk20a_dbg_fn("done"); -} - -static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) -{ - struct pmu_gk20a *pmu = &g->pmu; - struct pmu_cmd cmd; - u32 seq; - int status; - gk20a_dbg_fn(""); - - if (!tegra_fuse_readl(FUSE_OPT_ECC_EN)) { - gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); - return -1; - } - if (!(g->acr.capabilities & - ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) { - gk20a_err(dev_from_gk20a(g), "check ACR capabilities"); - return -1; - } - memset(&cmd, 0, sizeof(struct pmu_cmd)); - cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE; - cmd.hdr.size = PMU_CMD_HDR_SIZE + - sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis); - cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type = - PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS; - cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff); - - gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC"); - pmu->override_done = 0; - status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, - pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0); - if (status) - gk20a_err(dev_from_gk20a(g), "ECC override failed"); - else - pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), - &pmu->override_done, 1); - gk20a_dbg_fn("done"); - return status; -} - -void gp10b_init_pmu_ops(struct gpu_ops *gops) -{ - if (gops->privsecurity) { - gm20b_init_secure_pmu(gops); - gops->pmu.init_wpr_region = gm20b_pmu_init_acr; - gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; - } else { - gk20a_init_pmu_ops(gops); - gops->pmu.load_lsfalcon_ucode = NULL; - gops->pmu.init_wpr_region = NULL; - gops->pmu.pmu_setup_hw_and_bootstrap = gp10b_init_pmu_setup_hw1; - } - gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; - gops->pmu.lspmuwprinitdone = false; - gops->pmu.fecsbootstrapdone = false; - gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; - gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; - gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; - gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = - send_ecc_overide_en_dis_cmd; -} diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h deleted file mode 100644 index f61f6a93c..000000000 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * GP10B PMU - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __PMU_GP10B_H_ -#define __PMU_GP10B_H_ - -void gp10b_init_pmu_ops(struct gpu_ops *gops); - -#endif /*__PMU_GP10B_H_*/ diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c b/drivers/gpu/nvgpu/gp10b/regops_gp10b.c deleted file mode 100644 index 8934c3248..000000000 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.c +++ /dev/null @@ -1,505 +0,0 @@ -/* - * Tegra GK20A GPU Debugger Driver Register Ops - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include - -#include "gk20a/gk20a.h" -#include "gk20a/dbg_gpu_gk20a.h" -#include "gk20a/regops_gk20a.h" -#include "regops_gp10b.h" - -static const struct regop_offset_range gp10b_global_whitelist_ranges[] = { - { 0x000004f0, 1}, - { 0x00001a00, 3}, - { 0x00002800, 128}, - { 0x00009400, 1}, - { 0x00009410, 1}, - { 0x00009480, 1}, - { 0x00020200, 24}, - { 0x00021c00, 4}, - { 0x00021c14, 3}, - { 0x00021c24, 1}, - { 0x00021c2c, 69}, - { 0x00021d44, 1}, - { 0x00021d4c, 1}, - { 0x00021d54, 1}, - { 0x00021d5c, 1}, - { 0x00021d64, 2}, - { 0x00021d70, 16}, - { 0x00022430, 7}, - { 0x00022450, 1}, - { 0x0002245c, 1}, - { 0x00070000, 5}, - { 0x000884e0, 1}, - { 0x0008e00c, 1}, - { 0x00100c18, 3}, - { 0x00100c84, 1}, - { 0x0010a0a8, 1}, - { 0x0010a4f0, 1}, - { 0x0013cc14, 1}, - { 0x00140028, 1}, - { 0x00140280, 1}, - { 0x001402a0, 1}, - { 0x00140350, 1}, - { 0x00140480, 1}, - { 0x001404a0, 1}, - { 0x00140550, 1}, - { 0x00142028, 1}, - { 0x00142280, 1}, - { 0x001422a0, 1}, - { 0x00142350, 1}, - { 0x00142480, 1}, - { 0x001424a0, 1}, - { 0x00142550, 1}, - { 0x0017e028, 1}, - { 0x0017e280, 1}, - { 0x0017e294, 1}, - { 0x0017e29c, 2}, - { 0x0017e2ac, 1}, - { 0x0017e350, 1}, - { 0x0017e39c, 1}, - { 0x0017e480, 1}, - { 0x0017e4a0, 1}, - { 0x0017e550, 1}, - { 0x00180040, 41}, - { 0x001800ec, 10}, - { 0x00180240, 41}, - { 0x001802ec, 10}, - { 0x00180440, 41}, - { 0x001804ec, 10}, - { 0x00180640, 41}, - { 0x001806ec, 10}, - { 0x00180840, 41}, - { 0x001808ec, 10}, - { 0x00180a40, 41}, - { 0x00180aec, 10}, - { 0x00180c40, 41}, - { 0x00180cec, 10}, - { 0x00180e40, 41}, - { 0x00180eec, 10}, - { 0x001a0040, 41}, - { 0x001a00ec, 10}, - { 0x001a0240, 41}, - { 0x001a02ec, 10}, - { 0x001a0440, 41}, - { 0x001a04ec, 10}, - { 0x001a0640, 41}, - { 0x001a06ec, 10}, - { 0x001a0840, 41}, - { 0x001a08ec, 10}, - { 0x001a0a40, 41}, - { 0x001a0aec, 10}, - { 0x001a0c40, 41}, - { 0x001a0cec, 10}, - { 0x001a0e40, 41}, - { 0x001a0eec, 10}, - { 0x001b0040, 41}, - { 0x001b00ec, 10}, - { 0x001b0240, 41}, - { 0x001b02ec, 10}, - { 0x001b0440, 41}, - { 0x001b04ec, 10}, - { 0x001b0640, 41}, - { 0x001b06ec, 10}, - { 0x001b0840, 41}, - { 0x001b08ec, 10}, - { 0x001b0a40, 41}, - { 0x001b0aec, 10}, - { 0x001b0c40, 41}, - { 0x001b0cec, 10}, - { 0x001b0e40, 41}, - { 0x001b0eec, 10}, - { 0x001b4000, 1}, - { 0x001b4008, 1}, - { 0x001b4010, 3}, - { 0x001b4020, 3}, - { 0x001b4030, 3}, - { 0x001b4040, 3}, - { 0x001b4050, 3}, - { 0x001b4060, 4}, - { 0x001b4074, 7}, - { 0x001b4094, 3}, - { 0x001b40a4, 1}, - { 0x001b4100, 6}, - { 0x001b4124, 2}, - { 0x001b8000, 1}, - { 0x001b8008, 1}, - { 0x001b8010, 3}, - { 0x001bc000, 1}, - { 0x001bc008, 1}, - { 0x001bc010, 3}, - { 0x001be000, 1}, - { 0x001be008, 1}, - { 0x001be010, 3}, - { 0x00400500, 1}, - { 0x0040415c, 1}, - { 0x00404468, 1}, - { 0x00404498, 1}, - { 0x00405800, 1}, - { 0x00405840, 2}, - { 0x00405850, 1}, - { 0x00405908, 1}, - { 0x00405b40, 1}, - { 0x00405b50, 1}, - { 0x00406024, 5}, - { 0x00407010, 1}, - { 0x00407808, 1}, - { 0x0040803c, 1}, - { 0x00408804, 1}, - { 0x0040880c, 1}, - { 0x00408900, 2}, - { 0x00408910, 1}, - { 0x00408944, 1}, - { 0x00408984, 1}, - { 0x004090a8, 1}, - { 0x004098a0, 1}, - { 0x00409b00, 1}, - { 0x0041000c, 1}, - { 0x00410110, 1}, - { 0x00410184, 1}, - { 0x0041040c, 1}, - { 0x00410510, 1}, - { 0x00410584, 1}, - { 0x00418000, 1}, - { 0x00418008, 1}, - { 0x00418380, 2}, - { 0x00418400, 2}, - { 0x004184a0, 1}, - { 0x00418604, 1}, - { 0x00418680, 1}, - { 0x00418704, 1}, - { 0x00418714, 1}, - { 0x00418800, 1}, - { 0x0041881c, 1}, - { 0x00418830, 1}, - { 0x00418884, 1}, - { 0x004188b0, 1}, - { 0x004188c8, 3}, - { 0x004188fc, 1}, - { 0x00418b04, 1}, - { 0x00418c04, 1}, - { 0x00418c10, 8}, - { 0x00418c88, 1}, - { 0x00418d00, 1}, - { 0x00418e00, 1}, - { 0x00418e08, 1}, - { 0x00418e34, 1}, - { 0x00418e40, 4}, - { 0x00418e58, 16}, - { 0x00418f08, 1}, - { 0x00419000, 1}, - { 0x0041900c, 1}, - { 0x00419018, 1}, - { 0x00419854, 1}, - { 0x00419864, 1}, - { 0x00419a04, 2}, - { 0x00419a14, 1}, - { 0x00419ab0, 1}, - { 0x00419ab8, 3}, - { 0x00419c0c, 1}, - { 0x00419c8c, 2}, - { 0x00419d00, 1}, - { 0x00419d08, 2}, - { 0x00419e00, 11}, - { 0x00419e34, 2}, - { 0x00419e44, 11}, - { 0x00419e74, 10}, - { 0x00419ea4, 1}, - { 0x00419eac, 2}, - { 0x00419ee8, 1}, - { 0x00419ef0, 28}, - { 0x00419f70, 1}, - { 0x00419f78, 2}, - { 0x00419f98, 2}, - { 0x00419fdc, 1}, - { 0x0041a02c, 2}, - { 0x0041a0a0, 1}, - { 0x0041a0a8, 1}, - { 0x0041a890, 2}, - { 0x0041a8a0, 3}, - { 0x0041a8b0, 2}, - { 0x0041b014, 1}, - { 0x0041b0cc, 1}, - { 0x0041b1dc, 1}, - { 0x0041be0c, 3}, - { 0x0041becc, 1}, - { 0x0041bfdc, 1}, - { 0x0041c054, 1}, - { 0x0041c2b0, 1}, - { 0x0041c2b8, 3}, - { 0x0041c40c, 1}, - { 0x0041c48c, 2}, - { 0x0041c500, 1}, - { 0x0041c508, 2}, - { 0x0041c600, 11}, - { 0x0041c634, 2}, - { 0x0041c644, 11}, - { 0x0041c674, 10}, - { 0x0041c6a4, 1}, - { 0x0041c6ac, 2}, - { 0x0041c6e8, 1}, - { 0x0041c6f0, 28}, - { 0x0041c770, 1}, - { 0x0041c778, 2}, - { 0x0041c798, 2}, - { 0x0041c7dc, 1}, - { 0x0041c854, 1}, - { 0x0041cab0, 1}, - { 0x0041cab8, 3}, - { 0x0041cc0c, 1}, - { 0x0041cc8c, 2}, - { 0x0041cd00, 1}, - { 0x0041cd08, 2}, - { 0x0041ce00, 11}, - { 0x0041ce34, 2}, - { 0x0041ce44, 11}, - { 0x0041ce74, 10}, - { 0x0041cea4, 1}, - { 0x0041ceac, 2}, - { 0x0041cee8, 1}, - { 0x0041cef0, 28}, - { 0x0041cf70, 1}, - { 0x0041cf78, 2}, - { 0x0041cf98, 2}, - { 0x0041cfdc, 1}, - { 0x00500384, 1}, - { 0x005004a0, 1}, - { 0x00500604, 1}, - { 0x00500680, 1}, - { 0x00500714, 1}, - { 0x0050081c, 1}, - { 0x00500884, 1}, - { 0x005008b0, 1}, - { 0x005008c8, 3}, - { 0x005008fc, 1}, - { 0x00500b04, 1}, - { 0x00500c04, 1}, - { 0x00500c10, 8}, - { 0x00500c88, 1}, - { 0x00500d00, 1}, - { 0x00500e08, 1}, - { 0x00500f08, 1}, - { 0x00501000, 1}, - { 0x0050100c, 1}, - { 0x00501018, 1}, - { 0x00501854, 1}, - { 0x00501ab0, 1}, - { 0x00501ab8, 3}, - { 0x00501c0c, 1}, - { 0x00501c8c, 2}, - { 0x00501d00, 1}, - { 0x00501d08, 2}, - { 0x00501e00, 11}, - { 0x00501e34, 2}, - { 0x00501e44, 11}, - { 0x00501e74, 10}, - { 0x00501ea4, 1}, - { 0x00501eac, 2}, - { 0x00501ee8, 1}, - { 0x00501ef0, 28}, - { 0x00501f70, 1}, - { 0x00501f78, 2}, - { 0x00501f98, 2}, - { 0x00501fdc, 1}, - { 0x0050202c, 2}, - { 0x005020a0, 1}, - { 0x005020a8, 1}, - { 0x00502890, 2}, - { 0x005028a0, 3}, - { 0x005028b0, 2}, - { 0x00503014, 1}, - { 0x005030cc, 1}, - { 0x005031dc, 1}, - { 0x00503e14, 1}, - { 0x00503ecc, 1}, - { 0x00503fdc, 1}, - { 0x00504054, 1}, - { 0x005042b0, 1}, - { 0x005042b8, 3}, - { 0x0050440c, 1}, - { 0x0050448c, 2}, - { 0x00504500, 1}, - { 0x00504508, 2}, - { 0x00504600, 11}, - { 0x00504634, 2}, - { 0x00504644, 11}, - { 0x00504674, 10}, - { 0x005046a4, 1}, - { 0x005046ac, 2}, - { 0x005046e8, 1}, - { 0x005046f0, 28}, - { 0x00504770, 1}, - { 0x00504778, 2}, - { 0x00504798, 2}, - { 0x005047dc, 1}, - { 0x00504854, 1}, - { 0x00504ab0, 1}, - { 0x00504ab8, 3}, - { 0x00504c0c, 1}, - { 0x00504c8c, 2}, - { 0x00504d00, 1}, - { 0x00504d08, 2}, - { 0x00504e00, 11}, - { 0x00504e34, 2}, - { 0x00504e44, 11}, - { 0x00504e74, 10}, - { 0x00504ea4, 1}, - { 0x00504eac, 2}, - { 0x00504ee8, 1}, - { 0x00504ef0, 28}, - { 0x00504f70, 1}, - { 0x00504f78, 2}, - { 0x00504f98, 2}, - { 0x00504fdc, 1}, - { 0x00900100, 1}, - { 0x009a0100, 1}, -}; - -static const u32 gp10b_global_whitelist_ranges_count = - ARRAY_SIZE(gp10b_global_whitelist_ranges); - -/* context */ - -/* runcontrol */ -static const u32 gp10b_runcontrol_whitelist[] = { -}; -static const u32 gp10b_runcontrol_whitelist_count = - ARRAY_SIZE(gp10b_runcontrol_whitelist); - -static const struct regop_offset_range gp10b_runcontrol_whitelist_ranges[] = { -}; -static const u32 gp10b_runcontrol_whitelist_ranges_count = - ARRAY_SIZE(gp10b_runcontrol_whitelist_ranges); - - -/* quad ctl */ -static const u32 gp10b_qctl_whitelist[] = { -}; -static const u32 gp10b_qctl_whitelist_count = - ARRAY_SIZE(gp10b_qctl_whitelist); - -static const struct regop_offset_range gp10b_qctl_whitelist_ranges[] = { -}; -static const u32 gp10b_qctl_whitelist_ranges_count = - ARRAY_SIZE(gp10b_qctl_whitelist_ranges); - -static const struct regop_offset_range *gp10b_get_global_whitelist_ranges(void) -{ - return gp10b_global_whitelist_ranges; -} - -static int gp10b_get_global_whitelist_ranges_count(void) -{ - return gp10b_global_whitelist_ranges_count; -} - -static const struct regop_offset_range *gp10b_get_context_whitelist_ranges(void) -{ - return gp10b_global_whitelist_ranges; -} - -static int gp10b_get_context_whitelist_ranges_count(void) -{ - return gp10b_global_whitelist_ranges_count; -} - -static const u32 *gp10b_get_runcontrol_whitelist(void) -{ - return gp10b_runcontrol_whitelist; -} - -static int gp10b_get_runcontrol_whitelist_count(void) -{ - return gp10b_runcontrol_whitelist_count; -} - -static const -struct regop_offset_range *gp10b_get_runcontrol_whitelist_ranges(void) -{ - return gp10b_runcontrol_whitelist_ranges; -} - -static int gp10b_get_runcontrol_whitelist_ranges_count(void) -{ - return gp10b_runcontrol_whitelist_ranges_count; -} - -static const u32 *gp10b_get_qctl_whitelist(void) -{ - return gp10b_qctl_whitelist; -} - -static int gp10b_get_qctl_whitelist_count(void) -{ - return gp10b_qctl_whitelist_count; -} - -static const struct regop_offset_range *gp10b_get_qctl_whitelist_ranges(void) -{ - return gp10b_qctl_whitelist_ranges; -} - -static int gp10b_get_qctl_whitelist_ranges_count(void) -{ - return gp10b_qctl_whitelist_ranges_count; -} - -static int gp10b_apply_smpc_war(struct dbg_session_gk20a *dbg_s) -{ - /* Not needed on gp10b */ - return 0; -} - -void gp10b_init_regops(struct gpu_ops *gops) -{ - gops->regops.get_global_whitelist_ranges = - gp10b_get_global_whitelist_ranges; - gops->regops.get_global_whitelist_ranges_count = - gp10b_get_global_whitelist_ranges_count; - - gops->regops.get_context_whitelist_ranges = - gp10b_get_context_whitelist_ranges; - gops->regops.get_context_whitelist_ranges_count = - gp10b_get_context_whitelist_ranges_count; - - gops->regops.get_runcontrol_whitelist = - gp10b_get_runcontrol_whitelist; - gops->regops.get_runcontrol_whitelist_count = - gp10b_get_runcontrol_whitelist_count; - - gops->regops.get_runcontrol_whitelist_ranges = - gp10b_get_runcontrol_whitelist_ranges; - gops->regops.get_runcontrol_whitelist_ranges_count = - gp10b_get_runcontrol_whitelist_ranges_count; - - gops->regops.get_qctl_whitelist = - gp10b_get_qctl_whitelist; - gops->regops.get_qctl_whitelist_count = - gp10b_get_qctl_whitelist_count; - - gops->regops.get_qctl_whitelist_ranges = - gp10b_get_qctl_whitelist_ranges; - gops->regops.get_qctl_whitelist_ranges_count = - gp10b_get_qctl_whitelist_ranges_count; - - gops->regops.apply_smpc_war = - gp10b_apply_smpc_war; -} diff --git a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h b/drivers/gpu/nvgpu/gp10b/regops_gp10b.h deleted file mode 100644 index 8727951a6..000000000 --- a/drivers/gpu/nvgpu/gp10b/regops_gp10b.h +++ /dev/null @@ -1,24 +0,0 @@ -/* - * - * Tegra GP10B GPU Debugger Driver Register Ops - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ -#ifndef __REGOPS_GP10B_H_ -#define __REGOPS_GP10B_H_ - -void gp10b_init_regops(struct gpu_ops *gops); - -#endif /* __REGOPS_GP10B_H_ */ diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c deleted file mode 100644 index 59af5cded..000000000 --- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.c +++ /dev/null @@ -1,150 +0,0 @@ -/* - * GP10B RPFB - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include "gk20a/gk20a.h" -#include "rpfb_gp10b.h" -#include "hw_fifo_gp10b.h" -#include "hw_fb_gp10b.h" -#include "hw_bus_gp10b.h" -#include "hw_gmmu_gp10b.h" - -int gp10b_replayable_pagefault_buffer_init(struct gk20a *g) -{ - u32 addr_lo; - u32 addr_hi; - struct vm_gk20a *vm = &g->mm.bar2.vm; - int err; - size_t rbfb_size = NV_UVM_FAULT_BUF_SIZE * - fifo_replay_fault_buffer_size_hw_entries_v(); - - gk20a_dbg_fn(""); - - if (!g->mm.bar2_desc.gpu_va) { - err = gk20a_gmmu_alloc_map(vm, rbfb_size, - &g->mm.bar2_desc); - if (err) { - dev_err(dev_from_gk20a(g), - "%s Error in replayable fault buffer\n", __func__); - return err; - } - } - addr_lo = u64_lo32(g->mm.bar2_desc.gpu_va >> 12); - addr_hi = u64_hi32(g->mm.bar2_desc.gpu_va); - gk20a_writel(g, fifo_replay_fault_buffer_hi_r(), - fifo_replay_fault_buffer_hi_base_f(addr_hi)); - - gk20a_writel(g, fifo_replay_fault_buffer_lo_r(), - fifo_replay_fault_buffer_lo_base_f(addr_lo) | - fifo_replay_fault_buffer_lo_enable_true_v()); - gk20a_dbg_fn("done"); - return 0; -} - -void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g) -{ - struct vm_gk20a *vm = &g->mm.bar2.vm; - - gk20a_gmmu_unmap_free(vm, &g->mm.bar2_desc); -} - -u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g) -{ - u32 get_idx = 0; - - gk20a_dbg_fn(""); - - get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); - - if (get_idx >= fifo_replay_fault_buffer_size_hw_entries_v()) - dev_err(dev_from_gk20a(g), "%s Error in replayable fault buffer\n", - __func__); - gk20a_dbg_fn("done"); - return get_idx; -} - -u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g) -{ - u32 put_idx = 0; - - gk20a_dbg_fn(""); - put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r()); - - if (put_idx >= fifo_replay_fault_buffer_size_hw_entries_v()) - dev_err(dev_from_gk20a(g), "%s Error in UVM\n", - __func__); - gk20a_dbg_fn("done"); - return put_idx; -} - -bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g) -{ - u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); - u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r()); - - return (get_idx == put_idx ? true : false); -} - -bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g) -{ - u32 get_idx = gk20a_readl(g, fifo_replay_fault_buffer_get_r()); - u32 put_idx = gk20a_readl(g, fifo_replay_fault_buffer_put_r()); - u32 hw_entries = gk20a_readl(g, fifo_replay_fault_buffer_size_r()); - - return (get_idx == ((put_idx + 1) % hw_entries) ? true : false); -} - -bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g) -{ - u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r()); - - return fifo_replay_fault_buffer_info_overflow_f(info); -} - -void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g) -{ - u32 info = gk20a_readl(g, fifo_replay_fault_buffer_info_r()); - - info |= fifo_replay_fault_buffer_info_overflow_clear_v(); - gk20a_writel(g, fifo_replay_fault_buffer_info_r(), info); - -} - -void gp10b_replayable_pagefault_buffer_info(struct gk20a *g) -{ - - gk20a_dbg_fn(""); - pr_info("rpfb low: 0x%x\n", - (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) >> 12)); - pr_info("rpfb hi: 0x%x\n", - gk20a_readl(g, fifo_replay_fault_buffer_hi_r())); - pr_info("rpfb enabled: 0x%x\n", - (gk20a_readl(g, fifo_replay_fault_buffer_lo_r()) & 0x1)); - pr_info("rpfb size: %d\n", - gk20a_readl(g, fifo_replay_fault_buffer_size_r())); - pr_info("rpfb get index: %d\n", - gp10b_replayable_pagefault_buffer_get_index(g)); - pr_info("rpfb put index: %d\n", - gp10b_replayable_pagefault_buffer_put_index(g)); - pr_info("rpfb empty: %d\n", - gp10b_replayable_pagefault_buffer_is_empty(g)); - pr_info("rpfb full %d\n", - gp10b_replayable_pagefault_buffer_is_full(g)); - pr_info("rpfb overflow %d\n", - gp10b_replayable_pagefault_buffer_is_overflow(g)); - - gk20a_dbg_fn("done"); -} diff --git a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h b/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h deleted file mode 100644 index 965c9573c..000000000 --- a/drivers/gpu/nvgpu/gp10b/rpfb_gp10b.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef RPFB_GP20B_H -#define RPFB_GP20B_H -struct gk20a; - -#define NV_UVM_FAULT_BUF_SIZE 32 - -int gp10b_replayable_pagefault_buffer_init(struct gk20a *g); -u32 gp10b_replayable_pagefault_buffer_get_index(struct gk20a *g); -u32 gp10b_replayable_pagefault_buffer_put_index(struct gk20a *g); -bool gp10b_replayable_pagefault_buffer_is_empty(struct gk20a *g); -bool gp10b_replayable_pagefault_buffer_is_full(struct gk20a *g); -bool gp10b_replayable_pagefault_buffer_is_overflow(struct gk20a *g); -void gp10b_replayable_pagefault_buffer_clear_overflow(struct gk20a *g); -void gp10b_replayable_pagefault_buffer_info(struct gk20a *g); -void gp10b_replayable_pagefault_buffer_deinit(struct gk20a *g); - -#endif diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c b/drivers/gpu/nvgpu/gp10b/therm_gp10b.c deleted file mode 100644 index 687593b05..000000000 --- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * drivers/gpu/nvgpu/gm20b/therm_gk20a.c - * - * GP10B Therm - * - * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "gk20a/gk20a.h" -#include "hw_therm_gp10b.h" - -static int gp10b_init_therm_setup_hw(struct gk20a *g) -{ - u32 v; - - gk20a_dbg_fn(""); - - /* program NV_THERM registers */ - gk20a_writel(g, therm_use_a_r(), therm_use_a_ext_therm_0_enable_f() | - therm_use_a_ext_therm_1_enable_f() | - therm_use_a_ext_therm_2_enable_f()); - gk20a_writel(g, therm_evt_ext_therm_0_r(), - therm_evt_ext_therm_0_slow_factor_f(0x2)); - gk20a_writel(g, therm_evt_ext_therm_1_r(), - therm_evt_ext_therm_1_slow_factor_f(0x6)); - gk20a_writel(g, therm_evt_ext_therm_2_r(), - therm_evt_ext_therm_2_slow_factor_f(0xe)); - - gk20a_writel(g, therm_grad_stepping_table_r(0), - therm_grad_stepping_table_slowdown_factor0_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f()) | - therm_grad_stepping_table_slowdown_factor1_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f()) | - therm_grad_stepping_table_slowdown_factor2_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f()) | - therm_grad_stepping_table_slowdown_factor3_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor4_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); - - gk20a_writel(g, therm_grad_stepping_table_r(1), - therm_grad_stepping_table_slowdown_factor0_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor1_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor2_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor3_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f()) | - therm_grad_stepping_table_slowdown_factor4_f( - therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f())); - - v = gk20a_readl(g, therm_clk_timing_r(0)); - v |= therm_clk_timing_grad_slowdown_enabled_f(); - gk20a_writel(g, therm_clk_timing_r(0), v); - - v = gk20a_readl(g, therm_config2_r()); - v |= therm_config2_grad_enable_f(1); - v |= therm_config2_slowdown_factor_extended_f(1); - gk20a_writel(g, therm_config2_r(), v); - - gk20a_writel(g, therm_grad_stepping1_r(), - therm_grad_stepping1_pdiv_duration_f(32)); - - v = gk20a_readl(g, therm_grad_stepping0_r()); - v |= therm_grad_stepping0_feature_enable_f(); - gk20a_writel(g, therm_grad_stepping0_r(), v); - - return 0; -} - -static int gp10b_update_therm_gate_ctrl(struct gk20a *g) -{ - u32 gate_ctrl; - - gate_ctrl = gk20a_readl(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A)); - gate_ctrl = set_field(gate_ctrl, - therm_gate_ctrl_eng_delay_before_m(), - therm_gate_ctrl_eng_delay_before_f(4)); - gk20a_writel(g, therm_gate_ctrl_r(ENGINE_CE2_GK20A), gate_ctrl); - - return 0; -} - -void gp10b_init_therm_ops(struct gpu_ops *gops) -{ - gops->therm.init_therm_setup_hw = gp10b_init_therm_setup_hw; - gops->therm.update_therm_gate_ctrl = gp10b_update_therm_gate_ctrl; - -} diff --git a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h b/drivers/gpu/nvgpu/gp10b/therm_gp10b.h deleted file mode 100644 index 18c102fe4..000000000 --- a/drivers/gpu/nvgpu/gp10b/therm_gp10b.h +++ /dev/null @@ -1,19 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef THERM_GP10B_H -#define THERM_GP10B_H - -struct gpu_ops; -void gp10b_init_therm_ops(struct gpu_ops *gops); - -#endif /* THERM_GP10B_H */ diff --git a/drivers/gpu/nvgpu/gr_t18x.h b/drivers/gpu/nvgpu/gr_t18x.h deleted file mode 100644 index 95601116f..000000000 --- a/drivers/gpu/nvgpu/gr_t18x.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * NVIDIA T18x GR - * - * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _NVGPU_GR_T18X_H_ -#define _NVGPU_GR_T18X_H_ - -#include "gp10b/gr_gp10b.h" - -#endif diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h deleted file mode 100644 index 96f021252..000000000 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t18x.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * NVIDIA GPU ID functions, definitions. - * - * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ -#ifndef _NVGPU_GPUID_T18X_H_ -#define _NVGPU_GPUID_T18X_H_ - -#define NVGPU_GPUID_GP10B \ - GK20A_GPUID(NVGPU_GPU_ARCH_GP100, NVGPU_GPU_IMPL_GP10B) - -#define NVGPU_COMPAT_TEGRA_GP10B "nvidia,tegra186-gp10b" -#define NVGPU_COMPAT_GENERIC_GP10B "nvidia,generic-gp10b" - -#define TEGRA_18x_GPUID NVGPU_GPUID_GP10B -#define TEGRA_18x_GPUID_HAL gp10b_init_hal -#define TEGRA_18x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GP10B -#define TEGRA_18x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GP10B -struct gpu_ops; -extern int gp10b_init_hal(struct gk20a *); -extern struct gk20a_platform t18x_gpu_tegra_platform; - -#ifdef CONFIG_TEGRA_GR_VIRTUALIZATION -#define TEGRA_18x_GPUID_VGPU_HAL vgpu_gp10b_init_hal -extern int vgpu_gp10b_init_hal(struct gk20a *); -#endif -#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c deleted file mode 100644 index 34d942c15..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "vgpu_fifo_gp10b.h" - -void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops) -{ - /* syncpoint protection not supported yet */ - gops->fifo.resetup_ramfc = NULL; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h deleted file mode 100644 index 4ede0b6df..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_fifo_gp10b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __VGPU_FIFO_GP10B_H__ -#define __VGPU_FIFO_GP10B_H__ - -#include "gk20a/gk20a.h" - -void vgpu_gp10b_init_fifo_ops(struct gpu_ops *gops); - -#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c deleted file mode 100644 index 3023ef4b1..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.c +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "vgpu/vgpu.h" -#include "vgpu_gr_gp10b.h" -#include "vgpu/gm20b/vgpu_gr_gm20b.h" - -#include "gp10b/hw_gr_gp10b.h" - -static void vgpu_gr_gp10b_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, - struct gr_ctx_desc *gr_ctx) -{ - struct gk20a_platform *platform = gk20a_get_platform(g->dev); - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; - int err; - - gk20a_dbg_fn(""); - - if (!gr_ctx || !gr_ctx->mem.gpu_va) - return; - - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; - msg.handle = platform->virt_handle; - p->handle = gr_ctx->virt_ctx; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - WARN_ON(err || msg.ret); - - gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, 0); - - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.pagepool_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.betacb_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.spill_ctxsw_buffer); - gk20a_gmmu_unmap_free(vm, &gr_ctx->t18x.preempt_ctxsw_buffer); - - kfree(gr_ctx); -} - -static int vgpu_gr_gp10b_alloc_gr_ctx(struct gk20a *g, - struct gr_ctx_desc **__gr_ctx, - struct vm_gk20a *vm, - u32 class, - u32 flags) -{ - struct gk20a_platform *platform = gk20a_get_platform(g->dev); - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_gr_bind_ctxsw_buffers_params *p = - &msg.params.gr_bind_ctxsw_buffers; - struct gr_ctx_desc *gr_ctx = *__gr_ctx; - int err; - - gk20a_dbg_fn(""); - - WARN_ON(TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAX != - TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST); - - err = vgpu_gr_alloc_gr_ctx(g, __gr_ctx, vm, class, flags); - if (err) - return err; - - if (class == PASCAL_A && g->gr.t18x.ctx_vars.force_preemption_gfxp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_GFXP; - - if (class == PASCAL_COMPUTE_A && - g->gr.t18x.ctx_vars.force_preemption_cilp) - flags |= NVGPU_ALLOC_OBJ_FLAGS_CILP; - - if (flags & NVGPU_ALLOC_OBJ_FLAGS_GFXP) { - u32 spill_size = - gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v() * - gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(); - u32 pagepool_size = g->ops.gr.pagepool_default_size(g) * - gr_scc_pagepool_total_pages_byte_granularity_v(); - u32 betacb_size = g->gr.attrib_cb_default_size + - (gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v() - - gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v()); - u32 attrib_cb_size = (betacb_size + g->gr.alpha_cb_size) * - gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v() * - g->gr.max_tpc_count; - struct mem_desc *desc; - - attrib_cb_size = ALIGN(attrib_cb_size, 128); - - gk20a_dbg_info("gfxp context preempt size=%d", - g->gr.t18x.ctx_vars.preempt_image_size); - gk20a_dbg_info("gfxp context spill size=%d", spill_size); - gk20a_dbg_info("gfxp context pagepool size=%d", pagepool_size); - gk20a_dbg_info("gfxp context attrib cb size=%d", - attrib_cb_size); - - err = gr_gp10b_alloc_buffer(vm, - g->gr.t18x.ctx_vars.preempt_image_size, - &gr_ctx->t18x.preempt_ctxsw_buffer); - if (err) { - err = -ENOMEM; - goto fail; - } - desc = &gr_ctx->t18x.preempt_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN] = desc->size; - - err = gr_gp10b_alloc_buffer(vm, - spill_size, - &gr_ctx->t18x.spill_ctxsw_buffer); - if (err) { - err = -ENOMEM; - goto fail; - } - desc = &gr_ctx->t18x.spill_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL] = desc->size; - - err = gr_gp10b_alloc_buffer(vm, - pagepool_size, - &gr_ctx->t18x.pagepool_ctxsw_buffer); - if (err) { - err = -ENOMEM; - goto fail; - } - desc = &gr_ctx->t18x.pagepool_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = - desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL] = desc->size; - - err = gr_gp10b_alloc_buffer(vm, - attrib_cb_size, - &gr_ctx->t18x.betacb_ctxsw_buffer); - if (err) { - err = -ENOMEM; - goto fail; - } - desc = &gr_ctx->t18x.betacb_ctxsw_buffer; - p->gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = - desc->gpu_va; - p->size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB] = desc->size; - - gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_GFXP; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP; - } - - if (class == PASCAL_COMPUTE_A) { - if (flags & NVGPU_ALLOC_OBJ_FLAGS_CILP) { - gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CILP; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP; - } else { - gr_ctx->preempt_mode = NVGPU_GR_PREEMPTION_MODE_CTA; - p->mode = TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA; - } - } - - if (gr_ctx->preempt_mode) { - msg.cmd = TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS; - msg.handle = platform->virt_handle; - p->handle = gr_ctx->virt_ctx; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - if (err || msg.ret) { - err = -ENOMEM; - goto fail; - } - } - - gk20a_dbg_fn("done"); - return err; - -fail: - vgpu_gr_gp10b_free_gr_ctx(g, vm, gr_ctx); - return err; -} - -static int vgpu_gr_gp10b_init_ctx_state(struct gk20a *g) -{ - struct gk20a_platform *platform = gk20a_get_platform(g->dev); - int err; - - gk20a_dbg_fn(""); - - err = vgpu_gr_init_ctx_state(g); - if (err) - return err; - - vgpu_get_attribute(platform->virt_handle, - TEGRA_VGPU_ATTRIB_PREEMPT_CTX_SIZE, - &g->gr.t18x.ctx_vars.preempt_image_size); - if (!g->gr.t18x.ctx_vars.preempt_image_size) - return -ENXIO; - - return 0; -} - -void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops) -{ - vgpu_gm20b_init_gr_ops(gops); - gops->gr.alloc_gr_ctx = vgpu_gr_gp10b_alloc_gr_ctx; - gops->gr.free_gr_ctx = vgpu_gr_gp10b_free_gr_ctx; - gops->gr.init_ctx_state = vgpu_gr_gp10b_init_ctx_state; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h deleted file mode 100644 index b3be49a77..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_gr_gp10b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __VGPU_GR_GP10B_H__ -#define __VGPU_GR_GP10B_H__ - -#include "gk20a/gk20a.h" - -void vgpu_gp10b_init_gr_ops(struct gpu_ops *gops); - -#endif diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c deleted file mode 100644 index b665a8dd6..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include "vgpu/vgpu.h" -#include "gp10b/hal_gp10b.h" -#include "vgpu_gr_gp10b.h" -#include "vgpu_fifo_gp10b.h" -#include "vgpu_mm_gp10b.h" -#include "nvgpu_gpuid_t18x.h" - -int vgpu_gp10b_init_hal(struct gk20a *g) -{ - int err; - - gk20a_dbg_fn(""); - - err = gp10b_init_hal(g); - if (err) - return err; - - vgpu_init_hal_common(g); - vgpu_gp10b_init_gr_ops(&g->ops); - vgpu_gp10b_init_fifo_ops(&g->ops); - vgpu_gp10b_init_mm_ops(&g->ops); - return 0; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c deleted file mode 100644 index 3a286249c..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.c +++ /dev/null @@ -1,185 +0,0 @@ -/* - * Virtualized GPU Memory Management - * - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include "vgpu/vgpu.h" -#include "vgpu_mm_gp10b.h" -#include "gk20a/semaphore_gk20a.h" -#include "gk20a/mm_gk20a.h" - -static int vgpu_gp10b_init_mm_setup_hw(struct gk20a *g) -{ - g->mm.bypass_smmu = true; - g->mm.disable_bigpage = true; - return 0; -} - -static inline int add_mem_desc(struct tegra_vgpu_mem_desc *mem_desc, - u64 addr, u64 size, size_t *oob_size) -{ - if (*oob_size < sizeof(*mem_desc)) - return -ENOMEM; - - mem_desc->addr = addr; - mem_desc->length = size; - *oob_size -= sizeof(*mem_desc); - return 0; -} - -static u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, - u64 map_offset, - struct sg_table *sgt, - u64 buffer_offset, - u64 size, - int pgsz_idx, - u8 kind_v, - u32 ctag_offset, - u32 flags, - int rw_flag, - bool clear_ctags, - bool sparse, - bool priv, - struct vm_gk20a_mapping_batch *batch) -{ - int err = 0; - struct device *d = dev_from_vm(vm); - struct gk20a *g = gk20a_from_vm(vm); - struct gk20a_platform *platform = gk20a_get_platform(g->dev); - struct tegra_vgpu_cmd_msg msg; - struct tegra_vgpu_as_map_ex_params *p = &msg.params.as_map_ex; - struct tegra_vgpu_mem_desc *mem_desc; - u32 page_size = vm->gmmu_page_sizes[pgsz_idx]; - u64 space_to_skip = buffer_offset; - u64 buffer_size = 0; - u32 mem_desc_count = 0; - struct scatterlist *sgl; - void *handle = NULL; - size_t oob_size; - u8 prot; - - gk20a_dbg_fn(""); - - /* FIXME: add support for sparse mappings */ - - if (WARN_ON(!sgt) || WARN_ON(!g->mm.bypass_smmu)) - return -EINVAL; - - if (space_to_skip & (page_size - 1)) - return -EINVAL; - - /* Allocate (or validate when map_offset != 0) the virtual address. */ - if (!map_offset) { - map_offset = gk20a_vm_alloc_va(vm, size, pgsz_idx); - if (!map_offset) { - gk20a_err(d, "failed to allocate va space"); - err = -ENOMEM; - goto fail; - } - } - - handle = tegra_gr_comm_oob_get_ptr(TEGRA_GR_COMM_CTX_CLIENT, - tegra_gr_comm_get_server_vmid(), - TEGRA_VGPU_QUEUE_CMD, - (void **)&mem_desc, &oob_size); - if (!handle) { - err = -EINVAL; - goto fail; - } - - sgl = sgt->sgl; - while (space_to_skip && sgl && - (space_to_skip + page_size > sgl->length)) { - space_to_skip -= sgl->length; - sgl = sg_next(sgl); - } - WARN_ON(!sgl); - - if (add_mem_desc(&mem_desc[mem_desc_count++], - sg_phys(sgl) + space_to_skip, - sgl->length - space_to_skip, - &oob_size)) { - err = -ENOMEM; - goto fail; - } - buffer_size += sgl->length - space_to_skip; - - sgl = sg_next(sgl); - while (sgl && buffer_size < size) { - if (add_mem_desc(&mem_desc[mem_desc_count++], sg_phys(sgl), - sgl->length, &oob_size)) { - err = -ENOMEM; - goto fail; - } - - buffer_size += sgl->length; - sgl = sg_next(sgl); - } - - if (rw_flag == gk20a_mem_flag_read_only) - prot = TEGRA_VGPU_MAP_PROT_READ_ONLY; - else if (rw_flag == gk20a_mem_flag_write_only) - prot = TEGRA_VGPU_MAP_PROT_WRITE_ONLY; - else - prot = TEGRA_VGPU_MAP_PROT_NONE; - - if (pgsz_idx == gmmu_page_size_kernel) { - if (page_size == vm->gmmu_page_sizes[gmmu_page_size_small]) { - pgsz_idx = gmmu_page_size_small; - } else if (page_size == - vm->gmmu_page_sizes[gmmu_page_size_big]) { - pgsz_idx = gmmu_page_size_big; - } else { - gk20a_err(d, "invalid kernel page size %d\n", - page_size); - goto fail; - } - } - - msg.cmd = TEGRA_VGPU_CMD_AS_MAP_EX; - msg.handle = platform->virt_handle; - p->handle = vm->handle; - p->gpu_va = map_offset; - p->size = size; - p->mem_desc_count = mem_desc_count; - p->pgsz_idx = pgsz_idx; - p->iova = 0; - p->kind = kind_v; - p->cacheable = - (flags & NVGPU_MAP_BUFFER_FLAGS_CACHEABLE_TRUE) ? 1 : 0; - p->prot = prot; - p->ctag_offset = ctag_offset; - p->clear_ctags = clear_ctags; - err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); - if (err || msg.ret) - goto fail; - - /* TLB invalidate handled on server side */ - - tegra_gr_comm_oob_put_ptr(handle); - return map_offset; -fail: - if (handle) - tegra_gr_comm_oob_put_ptr(handle); - gk20a_err(d, "%s: failed with err=%d\n", __func__, err); - return 0; -} - -void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops) -{ - gk20a_dbg_fn(""); - - gops->mm.gmmu_map = vgpu_gp10b_locked_gmmu_map; - gops->mm.init_mm_setup_hw = vgpu_gp10b_init_mm_setup_hw; -} diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h deleted file mode 100644 index 5bdc9d1b5..000000000 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_mm_gp10b.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __VGPU_MM_GP10B_H__ -#define __VGPU_MM_GP10B_H__ - -#include "gk20a/gk20a.h" - -void vgpu_gp10b_init_mm_ops(struct gpu_ops *gops); - -#endif -- cgit v1.2.2 From 56f912544949067f7cb26563d7aafb93a501390a Mon Sep 17 00:00:00 2001 From: Pritesh Raithatha Date: Mon, 9 May 2016 12:30:15 +0530 Subject: kernel: t18x: change kernel path All kernel versions are getting moved inside $TOP/kernel folder. Changing kernel paths accordingly. Bug 200190733 Change-Id: Ia0353dd4be3fb3d76bbfc82609be99546a217f92 Signed-off-by: Pritesh Raithatha Reviewed-on: http://git-master/r/1143409 Reviewed-by: Bharat Nihalani Tested-by: Bharat Nihalani --- drivers/gpu/drm/tegra/Makefile | 2 +- drivers/gpu/host1x/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile index 048a3f3c2..ee133616a 100644 --- a/drivers/gpu/drm/tegra/Makefile +++ b/drivers/gpu/drm/tegra/Makefile @@ -1,5 +1,5 @@ ccflags-y += -Idrivers/gpu/drm/tegra -ccflags-y += -I../kernel-t18x/drivers/gpu/drm/tegra +ccflags-y += -I../t18x/drivers/gpu/drm/tegra tegra-drm-t186-y = \ vic_t186.o \ diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile index 9c8c6467b..25d54f73a 100644 --- a/drivers/gpu/host1x/Makefile +++ b/drivers/gpu/host1x/Makefile @@ -1,5 +1,5 @@ ccflags-y += -Idrivers/gpu/host1x -ccflags-y += -I../kernel-t18x/drivers/gpu/host1x +ccflags-y += -I../t18x/drivers/gpu/host1x host1x-t186-y = \ dev_t186.o \ -- cgit v1.2.2 From acba77976c6aa0553111dc8bf384eac148d7ffce Mon Sep 17 00:00:00 2001 From: dmitry pervushin Date: Sun, 3 Jul 2016 18:29:49 +0200 Subject: t18x: renaming KConfigs & Makefiles to add suffix Bug 1783210 Signed-off-by: dmitry pervushin Change-Id: I20c29b4dd5947d296a6ab1e83d47e569e386855b Reviewed-on: http://git-master/r/1176347 Reviewed-on: http://git-master/r/1177303 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt Tested-by: Alexander Van Brunt Reviewed-on: http://git-master/r/1183017 --- drivers/gpu/drm/tegra/Makefile | 11 ----------- drivers/gpu/drm/tegra/Makefile.t18x | 11 +++++++++++ drivers/gpu/host1x/Makefile | 8 -------- drivers/gpu/host1x/Makefile.t18x | 8 ++++++++ 4 files changed, 19 insertions(+), 19 deletions(-) delete mode 100644 drivers/gpu/drm/tegra/Makefile create mode 100644 drivers/gpu/drm/tegra/Makefile.t18x delete mode 100644 drivers/gpu/host1x/Makefile create mode 100644 drivers/gpu/host1x/Makefile.t18x (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/Makefile b/drivers/gpu/drm/tegra/Makefile deleted file mode 100644 index ee133616a..000000000 --- a/drivers/gpu/drm/tegra/Makefile +++ /dev/null @@ -1,11 +0,0 @@ -ccflags-y += -Idrivers/gpu/drm/tegra -ccflags-y += -I../t18x/drivers/gpu/drm/tegra - -tegra-drm-t186-y = \ - vic_t186.o \ - nvenc_t186.o \ - nvdec_t186.o \ - nvjpg_t186.o \ - tsec_t186.o - -obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/drm/tegra/Makefile.t18x b/drivers/gpu/drm/tegra/Makefile.t18x new file mode 100644 index 000000000..ee133616a --- /dev/null +++ b/drivers/gpu/drm/tegra/Makefile.t18x @@ -0,0 +1,11 @@ +ccflags-y += -Idrivers/gpu/drm/tegra +ccflags-y += -I../t18x/drivers/gpu/drm/tegra + +tegra-drm-t186-y = \ + vic_t186.o \ + nvenc_t186.o \ + nvdec_t186.o \ + nvjpg_t186.o \ + tsec_t186.o + +obj-$(CONFIG_TEGRA_HOST1X) += tegra-drm-t186.o diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile deleted file mode 100644 index 25d54f73a..000000000 --- a/drivers/gpu/host1x/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -ccflags-y += -Idrivers/gpu/host1x -ccflags-y += -I../t18x/drivers/gpu/host1x - -host1x-t186-y = \ - dev_t186.o \ - hw/host1x05.o - -obj-$(CONFIG_TEGRA_HOST1X) += host1x-t186.o diff --git a/drivers/gpu/host1x/Makefile.t18x b/drivers/gpu/host1x/Makefile.t18x new file mode 100644 index 000000000..25d54f73a --- /dev/null +++ b/drivers/gpu/host1x/Makefile.t18x @@ -0,0 +1,8 @@ +ccflags-y += -Idrivers/gpu/host1x +ccflags-y += -I../t18x/drivers/gpu/host1x + +host1x-t186-y = \ + dev_t186.o \ + hw/host1x05.o + +obj-$(CONFIG_TEGRA_HOST1X) += host1x-t186.o -- cgit v1.2.2 From 804c7ac23dcc26b4ab63dc1c821d36b842c4f7df Mon Sep 17 00:00:00 2001 From: Laxman Dewangan Date: Sat, 21 Jan 2017 16:34:07 +0530 Subject: drm/tegra: nvdec: se soc/tegra/kfuse header for kfuse Use the header for kfuse defines instead of legacy header . The legacy header for kfuse is going to be removed. bug 200257381 Change-Id: I83b894e1d912b87fde7b24b78c54a633027e0c09 Signed-off-by: Laxman Dewangan Reviewed-on: http://git-master/r/1291988 Reviewed-by: svccoveritychecker Reviewed-by: Shardar Mohammed Reviewed-by: Sujeet Baranwal GVS: Gerrit_Virtual_Submit --- drivers/gpu/drm/tegra/nvdec_t186.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu') diff --git a/drivers/gpu/drm/tegra/nvdec_t186.c b/drivers/gpu/drm/tegra/nvdec_t186.c index 7d9e846c3..78d2235c1 100644 --- a/drivers/gpu/drm/tegra/nvdec_t186.c +++ b/drivers/gpu/drm/tegra/nvdec_t186.c @@ -18,7 +18,7 @@ #include "nvdec_t186.h" #include -#include +#include static int nvdec_load_streamid_regs(struct tegra_drm_client *client) { -- cgit v1.2.2