From cf09fec01be5d52bc857d2cc446cdb33534dcb01 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Fri, 31 Jan 2020 18:46:26 +0530 Subject: PCI: tegra: Fix bandwidth setting in EP mode Refactor code to set the EMC bandwidth request based on link speed and width as the first thing once the BME is set by the host. Having the other part of the code as the first thing i.e. sending LTR message to the host has a check where it just returns if ASPM is not enabled in the EP system and this is causing the EMC bandwidth request code to get skipped. Bug 200587858 Change-Id: I22469c4da5197a2474c4ea45e8b27c8991ddbdb8 Signed-off-by: Vidya Sagar Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2288242 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Bibek Basu Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/pci/dwc/pcie-tegra.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/pci/dwc/pcie-tegra.c b/drivers/pci/dwc/pcie-tegra.c index a1dcfb194..6f3919f85 100644 --- a/drivers/pci/dwc/pcie-tegra.c +++ b/drivers/pci/dwc/pcie-tegra.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017 - 2019, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2017 - 2020, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -3765,6 +3765,21 @@ static void pex_ep_event_bme_change(struct tegra_pcie_dw *pcie) u32 val = 0, width = 0, speed = 0; unsigned long freq; + /* Make EMC FLOOR freq request based on link width and speed */ + val = readl(pci->dbi_base + CFG_LINK_STATUS_CONTROL); + width = ((val >> 16) & PCI_EXP_LNKSTA_NLW) >> 4; + width = find_first_bit((const unsigned long *)&width, + sizeof(width)); + speed = ((val >> 16) & PCI_EXP_LNKSTA_CLS); + freq = pcie->dvfs_tbl[width][speed - 1]; + dev_dbg(pcie->dev, "EMC Freq requested = %lu\n", freq); + + if (tegra_bwmgr_set_emc(pcie->emc_bw, freq, TEGRA_BWMGR_SET_EMC_FLOOR)) + dev_err(pcie->dev, "can't set emc clock[%lu]\n", freq); + + speed = ((val >> 16) & PCI_EXP_LNKSTA_CLS); + clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); + /* If EP doesn't advertise L1SS, just return */ val = readl(pci->dbi_base + pcie->cfg_link_cap_l1sub); if (!(val & (PCI_L1SS_CAP_ASPM_L1_1 | PCI_L1SS_CAP_ASPM_L1_2))) @@ -3796,21 +3811,6 @@ static void pex_ep_event_bme_change(struct tegra_pcie_dw *pcie) if (val & APPL_LTR_MSG_2_LTR_MSG_REQ_STATE) dev_err(pcie->dev, "LTR_MSG sending failed\n"); } - - /* Make EMC FLOOR freq request based on link width and speed */ - val = readl(pci->dbi_base + CFG_LINK_STATUS_CONTROL); - width = ((val >> 16) & PCI_EXP_LNKSTA_NLW) >> 4; - width = find_first_bit((const unsigned long *)&width, - sizeof(width)); - speed = ((val >> 16) & PCI_EXP_LNKSTA_CLS); - freq = pcie->dvfs_tbl[width][speed - 1]; - dev_dbg(pcie->dev, "EMC Freq requested = %lu\n", freq); - - if (tegra_bwmgr_set_emc(pcie->emc_bw, freq, TEGRA_BWMGR_SET_EMC_FLOOR)) - dev_err(pcie->dev, "can't set emc clock[%lu]\n", freq); - - speed = ((val >> 16) & PCI_EXP_LNKSTA_CLS); - clk_set_rate(pcie->core_clk, pcie_gen_freq[speed - 1]); } static int pcie_ep_work_thread(void *p) -- cgit v1.2.2