From bfce2e5d4c0ec8015eb5051a8259fb0e73a2f511 Mon Sep 17 00:00:00 2001 From: Vidya Sagar Date: Tue, 28 Nov 2017 12:38:43 +0530 Subject: PCI: tegra: EP: update programming sequence change enables core_clk as the first thing as part of controller initialization sequence as per the change is programming sequence Bug 200367869 Change-Id: I2d93b2635a1a25e434abfda62cc514ede77b9bfb Signed-off-by: Vidya Sagar Reviewed-on: https://git-master.nvidia.com/r/1606081 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity GVS: Gerrit_Virtual_Submit Reviewed-by: Manikanta Maddireddy Reviewed-by: Bharat Nihalani Reviewed-by: mobile promotions Tested-by: mobile promotions --- drivers/pci/endpoint/pcie-tegra-dw-ep.c | 36 ++++++++++++++++++--------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/drivers/pci/endpoint/pcie-tegra-dw-ep.c b/drivers/pci/endpoint/pcie-tegra-dw-ep.c index 68ca06dfd..43f4b2ef5 100644 --- a/drivers/pci/endpoint/pcie-tegra-dw-ep.c +++ b/drivers/pci/endpoint/pcie-tegra-dw-ep.c @@ -391,22 +391,36 @@ static int tegra_pcie_dw_ep_probe(struct platform_device *pdev) pcie->dev = &pdev->dev; + pcie->core_clk = devm_clk_get(&pdev->dev, "core_clk"); + if (IS_ERR(pcie->core_clk)) { + dev_err(&pdev->dev, "Failed to get core clock\n"); + return PTR_ERR(pcie->core_clk); + } + ret = clk_prepare_enable(pcie->core_clk); + if (ret) { + dev_err(&pdev->dev, "Failed to enable core clock\n"); + return ret; + } + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "appl"); if (!pcie->appl_res) { dev_err(&pdev->dev, "missing appl space\n"); - return PTR_ERR(pcie->appl_res); + ret = PTR_ERR(pcie->appl_res); + goto fail_appl_res; } pcie->appl_base = devm_ioremap_resource(&pdev->dev, pcie->appl_res); if (IS_ERR(pcie->appl_base)) { dev_err(&pdev->dev, "mapping appl space failed\n"); - return PTR_ERR(pcie->appl_base); + ret = PTR_ERR(pcie->appl_base); + goto fail_appl_res; } pcie->core_apb_rst = devm_reset_control_get(pcie->dev, "core_apb_rst"); if (IS_ERR(pcie->core_apb_rst)) { dev_err(pcie->dev, "PCIE : core_apb_rst reset is missing\n"); - return PTR_ERR(pcie->core_apb_rst); + ret = PTR_ERR(pcie->core_apb_rst); + goto fail_appl_res; } reset_control_deassert(pcie->core_apb_rst); @@ -539,33 +553,23 @@ static int tegra_pcie_dw_ep_probe(struct platform_device *pdev) INIT_WORK(&pcie->pcie_ep_work, pcie_ep_work_fn); - pcie->core_clk = devm_clk_get(&pdev->dev, "core_clk"); - if (IS_ERR(pcie->core_clk)) { - dev_err(&pdev->dev, "Failed to get core clock\n"); - ret = PTR_ERR(pcie->core_clk); - goto fail_dbi_res; - } - ret = clk_prepare_enable(pcie->core_clk); - if (ret) - goto fail_dbi_res; - pcie->core_rst = devm_reset_control_get(pcie->dev, "core_rst"); if (IS_ERR(pcie->core_rst)) { dev_err(pcie->dev, "PCIE : core_rst reset is missing\n"); ret = PTR_ERR(pcie->core_rst); - goto fail_core_rst_get; + goto fail_dbi_res; } reset_control_deassert(pcie->core_rst); return ret; -fail_core_rst_get: - clk_disable_unprepare(pcie->core_clk); fail_dbi_res: tegra_pcie_disable_phy(pcie); fail_phy: reset_control_assert(pcie->core_apb_rst); +fail_appl_res: + clk_disable_unprepare(pcie->core_clk); return ret; } -- cgit v1.2.2