From 28f161a7886c439db5c19d60fb0f02a09e89c8ae Mon Sep 17 00:00:00 2001 From: Om Prakash Singh Date: Mon, 13 Apr 2020 12:09:39 +0530 Subject: PCI: tvnet: fix memory barrier usage replace smp_mb() memory barrier with mb() to take care of IO and Memory access synchronization as well. Bug 200600954 Change-Id: I2526c1b972166f241339e25f5ae8722a8d532bd6 Signed-off-by: Om Prakash Singh Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2327768 Reviewed-by: automaticguardword Reviewed-by: Manikanta Maddireddy Reviewed-by: Bibek Basu Reviewed-by: mobile promotions Tested-by: mobile promotions GVS: Gerrit_Virtual_Submit --- drivers/net/ethernet/nvidia/pcie/tegra_vnet.c | 18 +++++++++--------- drivers/pci/endpoint/functions/pci-epf-tegra-vnet.c | 8 ++++---- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/nvidia/pcie/tegra_vnet.c b/drivers/net/ethernet/nvidia/pcie/tegra_vnet.c index 6f5cdd510..b1f6f5d7a 100644 --- a/drivers/net/ethernet/nvidia/pcie/tegra_vnet.c +++ b/drivers/net/ethernet/nvidia/pcie/tegra_vnet.c @@ -79,7 +79,7 @@ static void tvnet_host_raise_ep_ctrl_irq(struct tvnet_priv *tvnet) /* BAR0 mmio address is wc mem, add mb to make sure * multiple interrupt writes are not combined. */ - smp_mb(); + mb(); } else { pr_err("%s: invalid irq type: %d\n", __func__, irq->irq_type); } @@ -95,7 +95,7 @@ static void tvnet_host_raise_ep_data_irq(struct tvnet_priv *tvnet) /* BAR0 mmio address is wc mem, add mb to make sure * multiple interrupt writes are not combined. */ - smp_mb(); + mb(); } else { pr_err("%s: invalid irq type: %d\n", __func__, irq->irq_type); } @@ -138,7 +138,7 @@ static int tvnet_host_write_ctrl_msg(struct tvnet_priv *tvnet, /* BAR0 mmio address is wc mem, add mb to make sure ctrl msg is written * before updating counters. */ - smp_mb(); + mb(); tvnet_ivc_advance_wr(&tvnet->h2ep_ctrl); tvnet_host_raise_ep_ctrl_irq(tvnet); @@ -192,7 +192,7 @@ static void tvnet_host_alloc_empty_buffers(struct tvnet_priv *tvnet) /* BAR0 mmio address is wc mem, add mb to make sure that empty * buffers are updated before updating counters. */ - smp_mb(); + mb(); tvnet_ivc_advance_wr(&tvnet->ep2h_empty); tvnet_host_raise_ep_ctrl_irq(tvnet); @@ -472,7 +472,7 @@ static netdev_tx_t tvnet_host_start_xmit(struct sk_buff *skb, dma_desc[desc_widx].dar_low = lower_32_bits(dst_iova); dma_desc[desc_widx].dar_high = upper_32_bits(dst_iova); /* CB bit should be set at the end */ - smp_mb(); + mb(); /* RIE is not required for polling mode */ ctrl_d = DMA_CH_CONTROL1_OFF_RDCH_RIE; ctrl_d |= DMA_CH_CONTROL1_OFF_RDCH_LIE; @@ -485,7 +485,7 @@ static netdev_tx_t tvnet_host_start_xmit(struct sk_buff *skb, ctrl_d = dma_desc[desc_widx].ctrl_reg.ctrl_d; /* DMA write should not go out of order wrt CB bit set */ - smp_mb(); + mb(); timeout = jiffies + msecs_to_jiffies(1000); dma_common_wr8(tvnet->dma_base, DMA_RD_DATA_CH, DMA_READ_DOORBELL_OFF); @@ -516,7 +516,7 @@ static netdev_tx_t tvnet_host_start_xmit(struct sk_buff *skb, desc_ridx = tvnet->desc_cnt.rd_cnt % DMA_DESC_COUNT; /* Clear DMA cycle bit and increment rd_cnt */ dma_desc[desc_ridx].ctrl_reg.ctrl_e.cb = 0; - smp_mb(); + mb(); tvnet->desc_cnt.rd_cnt++; #else @@ -525,7 +525,7 @@ static netdev_tx_t tvnet_host_start_xmit(struct sk_buff *skb, /* BAR0 mmio address is wc mem, add mb to make sure that complete * skb->data is written before updating counters. */ - smp_mb(); + mb(); #endif /* Push dst to H2EP full ring */ @@ -537,7 +537,7 @@ static netdev_tx_t tvnet_host_start_xmit(struct sk_buff *skb, /* BAR0 mmio address is wc mem, add mb to make sure that full * buffer is written before updating counters. */ - smp_mb(); + mb(); tvnet_ivc_advance_wr(&tvnet->h2ep_full); tvnet_host_raise_ep_data_irq(tvnet); diff --git a/drivers/pci/endpoint/functions/pci-epf-tegra-vnet.c b/drivers/pci/endpoint/functions/pci-epf-tegra-vnet.c index 8d0886d49..f55790f8c 100644 --- a/drivers/pci/endpoint/functions/pci-epf-tegra-vnet.c +++ b/drivers/pci/endpoint/functions/pci-epf-tegra-vnet.c @@ -584,13 +584,13 @@ static netdev_tx_t tvnet_ep_start_xmit(struct sk_buff *skb, ep_dma_virt[desc_widx].dar_low = lower_32_bits(dst_iova); ep_dma_virt[desc_widx].dar_high = upper_32_bits(dst_iova); /* CB bit should be set at the end */ - smp_mb(); + mb(); ctrl_d = DMA_CH_CONTROL1_OFF_WRCH_LIE; ctrl_d |= DMA_CH_CONTROL1_OFF_WRCH_CB; ep_dma_virt[desc_widx].ctrl_reg.ctrl_d = ctrl_d; /* DMA write should not go out of order wrt CB bit set */ - smp_mb(); + mb(); timeout = jiffies + msecs_to_jiffies(1000); dma_common_wr8(tvnet->dma_base, DMA_WR_DATA_CH, DMA_WRITE_DOORBELL_OFF); @@ -622,7 +622,7 @@ static netdev_tx_t tvnet_ep_start_xmit(struct sk_buff *skb, desc_ridx = tvnet->desc_cnt.rd_cnt % DMA_DESC_COUNT; /* Clear DMA cycle bit and increment rd_cnt */ ep_dma_virt[desc_ridx].ctrl_reg.ctrl_e.cb = 0; - smp_mb(); + mb(); tvnet->desc_cnt.rd_cnt++; #else @@ -632,7 +632,7 @@ static netdev_tx_t tvnet_ep_start_xmit(struct sk_buff *skb, * tx_dst_va is ioremap_wc() mem, add mb to make sure complete skb->data * written to dst before adding it to full buffer */ - smp_mb(); + mb(); #endif /* Push dst to EP2H full ring */ -- cgit v1.2.2