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* tegra: mc: Add resume function for mcKetan Patil2021-12-10
| | | | | | | | | | | | | | | | | | | | mc_err is not reported after device resume as MC_INTMASK register is in reset state. Restore this register in resume. Bug 3418979 Change-Id: I04884b81164a4b95e1f11e6e78e35499b6f5e977 Signed-off-by: Ketan Patil <ketanp@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2622984 (cherry picked from commit c9638f54e8b3dc48158cce548c24bae6dbf09adc) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2638812 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: safety: Phase notification commandMantravadi Karthik2021-07-01
| | | | | | | | | | | | | | | | | | | | | | Why? SCE HB working starts with Init done phase notification from CCPLEX. How? The init done phase notification is scheduled at the end of safety-ivc drver probe as all the necessary items for l1ss are initialized by then. Bug 200700400 Change-Id: I18cb66b2cbe6c3184c9c23c9b7ee6f6c53f62c06 Signed-off-by: Mantravadi Karthik <mkarthik@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2542621 Reviewed-by: Preetham Chandru <pchandru@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
* tegra: safety: Move header files to include/linuxPreetham Chandru Ramchandra2021-05-19
| | | | | | | | | | | | | | | | Move tegra_nv_guard_group_id.h and tegra_nv_guard_service_id.h header files to include/linux path. Also move l1ss_submit_rq() to tegra_l1ss_kernel_interface.h Bug 200700404 Change-Id: Ib609c3f3cbaebb495729eba6d607c340c9a2f185 Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2530519 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: safety: Enable L1SSPreetham Chandru Ramchandra2021-05-12
| | | | | | | | | | | | | | | | This change enable L1SS with minimal functionality. Currently it only supports sending sw error to SCE (SERVICESTATUS_NOTIFICATION) and IST erros. Bug 200700404 Change-Id: I4a33756dd2f4b6715157a39d3dbc4d0d968fc52b Signed-off-by: Preetham Chandru Ramchandra <pchandru@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2525248 Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: cbb: mask SError due to CBB errorSumit Gupta2020-12-14
| | | | | | | | | | | | | | | | | | | | | | | Mask SError for illegal accesses from CCPLEX master. Interrupts will be generated for access from CCPLEX and error info will be printed within the interrupt handler instead of SError callback. Also, call BUG() to crash the system if illegal access is from CCPLEX master. For illegal accesses from other masters, interrupt is already getting generated instead of SError. Bug 3191922 Change-Id: Ie03f4f0f0ca58fb695a54183456861dd98931855 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2118672 (cherry picked from commit ef8df45ba078e6d9ab2d648c4c122e38b600c77d) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2458251 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: Add API to check VPR resizeVedashree Vidwans2019-08-30
| | | | | | | | | | | | | | | | | | This patch adds a new API to check if vpr resize is supported. This will be used in nvgpu driver module. Bug 200532122 Change-Id: I4513c2bbdadd5b1db747216ab99bb6d8466268b1 Signed-off-by: Vedashree Vidwans <vvidwans@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2167079 Reviewed-on: https://git-master.nvidia.com/r/2180579 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Sungwook Kim <sungwookk@nvidia.com> Reviewed-by: Vinayak Pane <vpane@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra2: Support EMC/CPU ratio src switchSomdutta Roy2019-03-08
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added support for switching the EMC/CPU ratio src. Src could be either the DT table or default. The DT generally will have values tuned for perf/power balance. But in less demanding use cases like display off, a low power subset of the table can be used. Provide ability to userspace HALs to notify the kernel of the change in interactivity for it to switch the src. Sysfs Node /sys/kernel/tegra_cpu_emc/table_src Use DT values echo 1 > /sys/kernel/tegra_cpu_emc/table_src Use default values echo 0 > /sys/kernel/tegra_cpu_emc/table_src Bug 2384717 Bug 1758252 Change-Id: I9bafddf2b401567d8f7976f9a8a8be21d8c08ad8 Signed-off-by: Somdutta Roy <somduttar@nvidia.com> Reviewed-on: http://git-master/r/1131520 (cherry picked from commit 029c1cf1ceb7039f4090a098f4172f59d2874e67) Signed-off-by: Biao Cao <bcao@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2032522 Reviewed-by: Daniel Fu <danifu@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vinayak Pane <vpane@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: parse userbits for cluster NOC'ssumitg2018-09-14
| | | | | | | | | | | | | | | | Parse failed transaction's userbits separately for Cluster Fabric NOC's from CBB central NOC's. Bug 200340783 Change-Id: I8d635b5a28b3e15e6a86978b2dc8325e131f476d Signed-off-by: sumitg <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1821397 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* t194: bwmgr: add nvdla as bwmgr clientSharif Inamdar2018-09-12
| | | | | | | | | | | | | | | This patch updates bwmgr with nvdla as the new client for setting the emc bandwidth. Each nvdla client can independently make floor request for their bw requirement. Jira DLA-1187 Change-Id: I600812e2ae0c81111207fcd0a8a621362c770a99 Signed-off-by: Sharif Inamdar <isharif@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1814145 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: camera: rtcpu: fix boot timeoutsPekka Pessi2018-09-12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The t186-sce boot time sometimes exceeds 2000 milliseconds. The undue boot time is because the memory bandwidth problems. During the boot the DRAM image is read twice (once when copying, once when calculating SHA1). Calculate time from deasserting resets to the first mailbox handshake with camrtc. Add a dedicated bandwidth manager client for camrtc. Request for extra memory bandwidth during boot time. Retry camrtc boot if it fails. Report failed boot handshake correctly to the platform, avoid corruption. Bug 2305627 Change-Id: Ia96e369ee1b09d6298268f7bd309db1c8f326564 Signed-off-by: Pekka Pessi <ppessi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1803895 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Semi Malinen <smalinen@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: cast removes address space of expressionAjay Nandakumar2018-09-06
| | | | | | | | | | | | | | | | Fixing the sparce warning, which results as result of casting a void * iomem to u64. Although the data sizes are same, moving the u64 data type to void * iomem. Bug 200434802 Change-Id: I9821decc620e69f0ac752f7d0be3ac9b10e074f7 Signed-off-by: Ajay Nandakumar <anandakumarm@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809907 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: Disable 1/8th mode for all t19x topologiesPetlozu Pravareshwar2018-08-30
| | | | | | | | | | | | | | | Disable single-lane(1/8th) mode for all the t19x nvlink topologies. Also make sure we enable single-lane mode on nvlink only when both of the devices connected on either side of the link supports single lane mode. Bug 2341788 Change-Id: I95eae827cc6a3b748dd91637cdef27509a840c87 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805191 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: check clock enabled before register accessSumit Gupta2018-08-09
| | | | | | | | | | | | | | | | | | | Adding check for clock enabled by calling __clk_is_enabled() before accessing registers for CV-NOC. This was causing additional CBB errors on reading error valid register of CV-NOC while reporting original SError cause due to any illegal access in other cluster NOC's. Bug 200340783 Change-Id: I819f99264c4e934e6ae0facf39d35fed15e79957 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1794891 GVS: Gerrit_Virtual_Submit Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: add cbb noirq resume callbackSumit Gupta2018-08-02
| | | | | | | | | | | | | | | | | | | | Adding noirq phase callback in cbb to enable faults during resume. Also added no rumtime pm functions in cvsram driver to enable/disable CV clock before setting its NOC's registers in cbb resume/suspend noirq. This was required as the existing runtime pm used in cvnas driver is not up during noirq phase. Bug 200422155 Bug 200340783 Change-Id: I6ca19eec2bcad3254508c594a6d4e96e063c2cd0 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772791 GVS: Gerrit_Virtual_Submit Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* t19x: cpuidle: c6 exit latency measurementSanjay Chandrashekara2018-07-24
| | | | | | | | | | | | | | | | | | | Add support to measure C6 exit latency. This patch implements some of the helper functions required for this functionality. Measurement technique 1. Force cores 1 to 7 to enter C6 state. 2. Send an IPI from core 0 to wake all other cores 3. Measure exit latency based on trace printks 4. Check C6 entry count before and after "wfi" to make sure C6 was entered. JIRA: TPM-1217 Change-Id: I1d9943b09cf880631ad17f915bbf84959b899d2f Signed-off-by: Sanjay Chandrashekara <sanjayc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1757458 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: t19x: Remove 25GBPS speed supportSeema Khowala2018-07-19
| | | | | | | | | | | | | | Based on A01 Silicon Characterization, we cannot meet Nvlink POR speeds of 25G across 100% bin and hence 25GBPS is defeatured. Bug 200425755 Bug 2083356 Change-Id: Ia2166370413571787040e57ade299e3c136f4d5e Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1775462 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: create generic debugfs for RAS error injectSumit Gupta2018-07-18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Creating generic debugfs node for injecting RAS errors(one of each type). How to use: - reading the node gives help info about using. cat /d/RAS_MCA_ERR-trip - write node to cause error. e.g: echo EEDDCCBBAA > /d/RAS_MCA_ERR-trip where: EE[32-39] - L3_Bank_ID DD[24-31] - Logical_Cluster_ID CC[16-23] - Logical_CPU_ID BB[08-15] - Error type(Corr is 0, UnCorr is 1) AA[00-07] - Unit Unit numbers will be printed in help info on reading same node Bug 200420692 Change-Id: Ib83548b1781a55e9b980b0a506b93d5ef14b5119 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1770600 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* kernel: remove trace_printk usersdmitry pervushin2018-07-16
| | | | | | | | | | | | | | | | | | | Bug 2089957 Change-Id: I1e5c869a19133918effd20d3bb76e10c7f4634a5 Signed-off-by: dmitry pervushin <dpervushin@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698695 Reviewed-on: https://git-master.nvidia.com/r/1776084 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-by: Vipin Kumar <vipink@nvidia.com> Reviewed-by: Puneet Saxena <puneets@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: update RAS error codesSumit Gupta2018-07-13
| | | | | | | | | | | | | | | | | | | | Updating ERR<x>CTLR bits and IERR codes to report correct error. RAS/MCA error codes and bits have been changed in recent MTS code due to which error info will not be reported correctly. So, updating related codevalues and bits in RAS driver as per latest sheet from MTS member "New_MCA_20180619_0114.xlsx". Bug 200420692 Change-Id: If5268a8f0b8005cf97b147b154b9249529c108ec Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1774516 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-by: Bo Yan <byan@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: Import header files to nvidia repoNicolin Chen2018-06-27
| | | | | | | | | | | | | | | | | | This patch imports downstream header files from K4.4, K4.9 and K4.14. Most of the header files are copied from K4.4 as it contains more files than the other two. But this change also merges additional changes from K4.9 and K4.14. Meanwhile it updates of license year. Bug 200424912 Change-Id: I6802a0d8c390bdbf430fe06f00dc174cc2b98a7d Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1761105 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: tegra: add support for CV NOC errorsSumit Gupta2018-06-26
| | | | | | | | | | | | | | | | | | | adding support to handle errors from CV NOC. Enabling clock and using PROBE_DEFER for NOC's which are not probed yet e.g: CV-NOC here as it depends on cvnas driver which gets probed later. Bug 200340783 Bug 200389874 Change-Id: I2608aff0956a67f15426773c6ae0d471e5f645eb Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1678123 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* cpu-tegra: remove obsolete header inclusionBo Yan2018-06-21
| | | | | | | | | | | | | | | In addition, remove the obsolete declaration of tegra_vc_get_cdev bug 2099599 Change-Id: I77b2dccc49793fccabfe7de604c8ab6226406e92 Signed-off-by: Bo Yan <byan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1756394 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: add support for kernel testsAdeel Raza2018-06-19
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for NVLINK kernel test modules: - Create an NVLINK tests debugfs directory which will be used as the parent directory for all test related debugfs nodes - Export NVLINK logging APIs - Rename the NVLINK_DRV_NAME macros to NVLINK_MODULE_NAME. This was done because now the NVLINK logging APIs are being used by non-driver modules (i.e. tests) as well. - Export an ARM64 cache flush API - this API is needed by the Tegra loopback test Bug 2133882 Jira NVLINK-107 Change-Id: I587b704ff44327ee4d9767156cb87cbe27408e08 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1704230 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: add shim driver shutdown IOCTLsAdeel Raza2018-06-07
| | | | | | | | | | | | | | | | | | | | | For the shim driver mode, RM needs to perform a graceful shutdown of NVLINK during RM unload. Export the following T19x NVLINK endpoint IOCTLs for shim driver NVLINK shutdown: - INTERFACE_DISABLE IOCTL: Disables the NVLINK aperture - FINALIZE_SHUTDOWN IOCTL: Does shutdown related SW cleanup Bug 2113729 Jira NVLINK-173 Change-Id: I60e3f5fffd0b1e6cc87476b047ef1b761b5174d1 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1714177 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: actmon: Implement the dummy actmon APIsLaxman Dewangan2018-06-01
| | | | | | | | | | | | | | | | | | | | | | The actmon implement the actmon_{register/remove} with config CONFIG_TEGRA_CENTRAL_ACTMON. Add dummy implementation of these APIs if this config is not enabled so that there will not be any build error from defconfig if the config CONFIG_TEGRA_CENTRAL_ACTMON is not enabled. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Reviewed-on: http://git-master/r/1293965 (cherry picked from commit 6e61fa97d8ea04579bfb8eb86813ee73ef7dc4ba) Change-Id: I2b6a59ad8885219c88bc8a9e152dce2178d92830 Reviewed-on: https://git-master.nvidia.com/r/1499981 Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730874 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: central_actmon: refactor driverHoang Pham2018-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | - Convert module platform actmon common driver into actmon core driver - Convert dependent drivers into SoCs module platform actmon drivers - This allows for the kernel to support multiple SoCs without a namespace clash avoiding need for different compile time options and no need to change actmon core driver for future chips Reviewed-on: http://git-master/r/1268709 (cherry picked from commit 7198bd1f18319d867f541f63cc282ac90a290e8f) Change-Id: I9ff5966c090b8faf3c6f2cc5c6a0308b864b9f7e Reviewed-on: https://git-master.nvidia.com/r/1499976 Reviewed-by: Timo Alho <talho@nvidia.com> Tested-by: Timo Alho <talho@nvidia.com> Signed-off-by: Hoang Pham <hopham@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1730873 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: t19x: correct compatible string for NOC'sSumit Gupta2018-05-30
| | | | | | | | | | | | | | | | | | Correcting compatible string name from bridge to NOC. Also, adding is_ax2apb_bridge_connected flag to check if the cluster is connected to CBB through any AXI2APB bridge. Currently, AON cluster is only one which is not connected. So, no need to read AXI2APB bridge registers for that NOC. Bug 200340783 Change-Id: Iea89b6a3daff1dd30b6d43a9e8254ed362a841d0 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1686705 GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: ras: Fix L2 Error Record bitsRohit Khanna2018-05-21
| | | | | | | | | | | | | | | | | | | | | | This patch does the following:- 1. This patch combines L2 URD_ECCUC(ERRCTLR bit 37) and URD_ECCUD(ERRCTLR bit 35) to a single bit called L2 URD_ECCU(ERRCTLR bit 35). 2. Set error message for IERR = 0x53 to "L2 URD Uncorrectable" 3. Remove IERR == 0x55 for L2. Bug 2061430 Change-Id: I46ea4fa5edaba13fe96fedbd8309fed03db5f5d8 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1710654 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: fd: Add wrapper for __alloc_fdPritesh Raithatha2018-05-21
| | | | | | | | | | | | | | | | | | Modules like nvgpu and nvmap should to be able to allocate all open fds and for this they need to call __alloc_fd() rather than alloc_fd. However, as __alloc_fd is not exported to modules, a wrapper is being created and exported to the respective modules. bug 200290850 Change-Id: Id245040842f71aadfc484711a23e8ce9dbfa872f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1701552 GVS: Gerrit_Virtual_Submit Reviewed-by: Sachin Nikam <snikam@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: export MINION fieldsAdeel Raza2018-05-16
| | | | | | | | | | | | | | | | | Move MINION related fields from the T19x NVLINK endpoint's header file to the common NVLINK driver stack header file. This is needed because going forward all NVLINK endpoint drivers will use the same MINION ucode format. Bug 2113404 Change-Id: I8fc332fde3eac835694f2a270ca91223b8556a5b Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1711612 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: Implement nvlink shutdown during SC0/SC7Suresh Mangipudi2018-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change implements below nvlink shutdown steps: * Ensure nvlink is idle and no pending transactions * Turn off MSS Nvlink slave aperture * Turn off MSS Nvlink core clocks * Transition the link to SWCFG * Transition the link to OFF * Assert t19x nvlink resets and disable the clks Also this change adds "shutdown" debugfs node that can be used to shutdown t19x nvlink. Bug 200402583 Bug 200389569 Change-Id: I7312f3c49ed643a66325b9280b392394008276d4 Signed-off-by: Suresh Mangipudi <smangipudi@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1661191 Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Tested-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Tejal Kudav <tkudav@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: Add support for 16G nvlink speedPetlozu Pravareshwar2018-05-07
| | | | | | | | | | | | | | | | | | This change adds support for 16G nvlink speed. For this purpose, INITPLL8 MINION DL command is used for 156MHz refclk rate config and INITPLL9 MINION DL command is used for 150MHz refclk rate config. Bug 2101745 Change-Id: Iccad4aba2602db6ab188f475d3ff57cf9cf4f500 Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1698352 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: ras: Add test for Correctable ErrorsRohit Khanna2018-05-04
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch does the following: - Add a test for triggering below Correctable Errors: 1. SCF_IOB-PUTDATA_CECC_ERR 2. L3_0_CECC_ERR-trip How to trigger? 1. cat /d/carmel_ras/SCF_IOB-PUTDATA_CECC_ERR-trip gives value echo value > /d/carmel_ras/SCF_IOB-PUTDATA_CECC_ERR-trip 2. cat /d/carmel_ras/L3_0_CECC_ERR-trip gives value echo value > /d/carmel_ras/L3_0_CECC_ERR-trip - Fix value of bit ERR_CTL_SCFL3_CECC_ERR - Rename registers RAS_IFU_CTL* to ERR_CTL_IFU* - Remove hard-coded values Bug 200368651 Bug 200319716 Bug 200368651 Change-Id: Id3833d15e2c485f499b0b3538efbf6e237f8a983 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1667697 GVS: Gerrit_Virtual_Submit Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: add RM shim driver supportAdeel Raza2018-04-23
| | | | | | | | | | | | | | | | | | | | | Add support in the Tegra NVLINK endpoint driver for interfacing with the RM shim driver. Interfacing with RM is necessary in order to enable GPU MODS NVLINK testing of Tegra+dGPU topologies. Jira NVLINK-147 Bug 2090322 Change-Id: I75e23df7293ce0c9157152a7035372d2e080ef41 Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1696116 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-by: Petlozu Pravareshwar <petlozup@nvidia.com> Tested-by: Petlozu Pravareshwar <petlozup@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* platform: tegra: avoid messy WARN log on HVShawn Joo2018-03-26
| | | | | | | | | | | | | | | | | | | | | | while accessing nvlink, warning log comes continuously on HV due to absence of property on mssnvlink node. however the node is not in use on hypervisor. remove WARN log as it is expected. EAVT-301 Bug 2082181 Change-Id: I0b2f166a833aacf7c535bc25154e3f34e08070d2 Signed-off-by: Shawn Joo <sjoo@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1678543 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Puneet Saxena <puneets@nvidia.com> Reviewed-by: Joshua Cha <joshuac@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: t19x: add lookup tables for each NOCSumit Gupta2018-03-19
| | | | | | | | | | | | | | | | | | | | | | Changes to add separate lookup table for each NOC and adding lookup tables for NOC's(AON-NOC, BPMP-NOC, RCE-NOC, SCE-NOC). Earlier CBB_Central_NOC(CBB-NOC) lookup table was used for all NOC's which was resulting in wrong initflow and targflow for errors from NOC's other than CBB central NOC. Also doing some cleanup of driver code. Bug 200340783 Bug 200389874 Change-Id: I53ce9647dd2a7b608e17b9707cac9d8ac8e479a0 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1676664 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: mc: move few MC headers to linux-nvidiaPavan Kunapuli2018-03-09
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A selected set of MC header files are only used by files located in linux-nvidia repository. Hence, remove the files from kernel repository itself and add them to nvidia repository. The added files were introduced and/or modified by following commits in linux-4.9 repository: 3295513 t194: update LA client register list 0856e21 platform: tegra: emc: Remove EMC driver f18e59e platform: tegra: mc: Remove MC timing save/restore b4e813e platform: tegra: mc: include soc mc reg header file in implementation files 692e3e0 platform: tegra: mcerr: Linear addr conversion a8da3c2 platform: tegra: mc: DRAM ECC, EMC register offset 6cd5452 platform: tegra: mc: add T18x LA/PTSA driver 9149ed3 platform: tegra: mc: update t18x mc regs c54ef31 platform: tegra: mc: Add t18x regs 043e45f include: Add necessary include files for tegra drivers Bug 200385931 Change-Id: I7970793c0d2f4ba608557968e8259059fc19306f Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Bitan Biswas <bbiswas@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1657956 GVS: Gerrit_Virtual_Submit Tested-by: Timo Alho <talho@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Timo Alho <talho@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: t19x: support for AXI2APB slave error causeSumit Gupta2018-03-07
| | | | | | | | | | | | | | | | | adding support to get error cause for APB slaves as their errors are logged in error loggers but implemented in APB domain. Bug 200340783 Change-Id: Ic09028838cf15c472dc41e1c0b6704caec01b901 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1645853 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: fix TX clock modelAdeel Raza2018-02-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initially BPMP modeled NVLINK TX clock source mux as clock gate TEGRA194_CLK_NVLINK_TXCLK_CTRL. This allowed NVLINK driver to just enable TEGRA194_CLK_NVLINK_TXCLK_CTRL when it needed to switch to PLL source, and disable TEGRA194_CLK_NVLINK_TXCLK_CTRL in order to switch back to clk_m/oscillator source. This model is incorrect (gate instated of mux). It doesn’t allow proper voltage scaling for NVLINK clock, and it is not consistent with NVLINK clock monitoring. The NVLINK clock model is now fixed in BPMP. The following changes have been made to the NVLINK kernel driver in order to comply with the new clock model: 1. call clk_set_rate() on TEGRA194_CLK_NVLINK_PLL_TXCLK after INITPLL/XAVIER_CALIBRATEPLL DLCMDs 2. Instead of enabling/disabling TEGRA194_CLK_NVLINK_TXCLK_CTRL, the NVLINK driver calls clk_set_parent() on TEGRA194_CLK_NVLINK_TX clock Bug 2048310 Change-Id: I55c23a0b8f07335b8e331442a208288260a8953d Signed-off-by: Adeel Raza <araza@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1649119 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: Cleanup core driver interfaceTejal Kudav2018-02-02
| | | | | | | | | | | | | | | | | The device and link struct shared between core driver and endpoint contains hardware register base addresses, fields to log interrupts and more, which are not required to be shared with core driver. Move these fields to endpoint driver's private structure. JIRA NVLINK-139 Change-Id: I138364de025ef243b7b3a4c7c4a86089b890a3f9 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640796 GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* nvlink: Add nvlink_enumerate to bringup nvlinkTejal Kudav2018-01-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The master device in nvlink topology will call nvlink_enumerate to initialize both the endpoint devices and transition the link to safe and eventually to High speed. Nvlink_enumerate will co-ordinate the state transitions between the two endpoints and get the link ready for data transfer over high speed. The callbacks registered by master and slave for device and link level initialization will be called sequentially. init_state is maintained to allow us to call nvlink_enumerate multiple times. Based on the init state and the link mode, only necessary steps will be executed. Move the interface definitions to /include. Some APIs and struct definition need to exposed to dGPU or other endpoint driver. These represent the interface between the core nvlink driver and the endpoint drivers. As nvlink driver is tegra specific, we move the file to /include/linux/platform/tegra folder. JIRA NVLINK-66 JIRA NVLINK-67 JIRA NVLINK-70 JIRA NVLINK-73 JIRA NVLINK-79 JIRA NVLINK-103 JIRA NVLINK-110 JIRA NVLINK-114 Change-Id: I7907825e4344833344ad6aaa6f2017b58b258649 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1640795 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Adeel Raza <araza@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* tegra: t19x: add handler for cbb errors from other mastersSumit Gupta2017-12-05
| | | | | | | | | | | | | | | | | | | | | | | | adding interrupt handler for CBB errors due to illegal access by masters other than CCPLEX. In handler, printing info about errored transaction from CBB's error logger registers. CBB Errors from other masters are routed over two IRQ lines: - cbb_secure_intr: SEC(system firewall) & SLV errors. - cbb_nonsecure_intr: TMO & DEC errors. For illegal accesses due to CCPLEX only, SError(inband error notification) is used which is already handled in driver. Bug 200340783 Change-Id: Id530d5aeda580a415d01422d66ef922f0d8645d7 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1606341 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Rohit Khanna <rokhanna@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
* Merge remote-tracking branch 'remotes/origin/dev/linux-t19x' into linux-nvidiaDeepak Nibade2017-11-16
|\ | | | | | | | | | | | | Bug 200363166 Change-Id: Id0fcee1cc01fe1648afe7e3f2d44f820563898ca Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
| * tegra: t19x: add CBB driver supportSumit Gupta2017-11-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver adds support for handling SError's from Control Backbone(CBB). In case of SError from a bridge within CBB, the driver checks ErrVld status of all three Error Logger's of CBB. It then prints debug information like Error Code, Error Description, Master, Address, AXI ID etc for failed transaction using ErrLog registers of CBB's error logger having ErrVld status set. Bug 200340783 Change-Id: I4e4d079e9853ba0c4cdc5d9c0eb8854478862b75 Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1570826 GVS: Gerrit_Virtual_Submit Reviewed-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * tegra: add RAS support for CarmelRohit Khanna2017-11-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a driver to handle Carmel RAS errors per core, per core cluster and per CCPLEX. Carmel supports two kinds of errors : Correctable and Uncorrectable Correctable errors are handled using Fault Handling Interrupt (FHI) and Uncorrectable errors using SERROR. For FHI, the driver registers and defines callbacks that interface with arm64_ras driver. For SError, driver registers callbacks and defines callbacks that interface with arm64_traps driver. Driver also provides support for triggering RAS errors for SW testing via debugfs nodes. Bug 1814444 Bug 200319716 Change-Id: Id543bf62d8d00317cc1aaea9fd8c65dd03c29822 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1309006 GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
| * platform: tegra: mcerr: add mcerror handling for t19xKrishna Reddy2017-05-19
| | | | | | | | | | | | | | | | | | | | TMM-31 Change-Id: I68b3e2009704e0f890cff9f8ac08717aa1398b76 Signed-off-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-on: http://git-master/r/1477689 Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit
| * tegra: T194 cpu macroRohit Khanna2017-02-24
| | | | | | | | | | | | | | | | Add a macro to detect if a CPU core is Carmel or not. Bug 1814444 Bug 1827294 Change-Id: I5797f80ff990ffbbb59342a11f68ed22ea2b184c Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Reviewed-on: http://git-master/r/1295512 Reviewed-by: Krishna Sitaraman <ksitaraman@nvidia.com> Tested-by: Krishna Sitaraman <ksitaraman@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
* tegra210: cpufreq: cpufreq platform driverPuneet Saxena2017-11-07
|\ | | | | | | | | | | | | | | | | | | It adds cpufreq platform driver and cpu-emc mapping. Bug 200357442 Change-Id: Ife41f9fadec8f39b4a0c494e98f88c851bbf45ff Signed-off-by: Puneet Saxena <puneets@nvidia.com>
| * video: tegra: dp: Add pc2-disabled bindingJay Bhukhanwala2017-11-07
|/ | | | | | | | | | | | | | | | Since the support for post-cursor2 programming is optional as per the Display Port 1.2 standard, we derive a platform's willingness to support it via a device tree property TDS-2806 Change-Id: Ibab71287c398db8b8700f0e2d480c5234e5a79f0 Signed-off-by: Jay Bhukhanwala <jbhukhanwala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1581311 Reviewed-by: Shu Zhong <shuz@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Ujwal Patel <ujwalp@nvidia.com>
* platform: tegra: move emc related include filesTimo Alho2017-10-18
| | | | | | | | | | | | Few include files related to emc are only referred from linux-nvidia repository. Hence move them to that repository and remove from core kernel repositories. Change-Id: I2541066a2dd9a9b710963ee675ff53887d30f286 Signed-off-by: Timo Alho <talho@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1579719 GVS: Gerrit_Virtual_Submit Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-14 09:53:47 -0500