15 files changed, 4917 insertions, 0 deletions

diff --git a/include/linux/platform/tegra/bwmgr_mc.h b/include/linux/platform/tegra/bwmgr_mc.h
new file mode 100644
index 000000000..2aa7f8a72
--- /dev/null
+++ b/include/linux/platform/tegra/bwmgr_mc.h
@@ -0,0 +1,37 @@
+/**
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __BWMGR_MC_H
+#define __BWMGR_MC_H
+
+#include <linux/types.h>
+#include <linux/platform/tegra/iso_client.h>
+
+unsigned long bwmgr_apply_efficiency(
+                unsigned long bw, unsigned long iso_bw,
+                unsigned long emc_max, u64 usage_flags,
+                unsigned long *iso_bw_min, unsigned long iso_bw_nvdis,
+                unsigned long iso_bw_vi);
+
+void bwmgr_eff_init(void);
+
+unsigned long bwmgr_freq_to_bw(unsigned long freq);
+unsigned long bwmgr_bw_to_freq(unsigned long bw);
+unsigned long bwmgr_get_lowest_iso_emc_freq(long iso_bw,
+                long iso_bw_nvdis, long iso_bw_vi);
+u32 tegra_bwmgr_get_max_iso_bw(enum tegra_iso_client);
+
+u32 bwmgr_dvfs_latency(u32 ufreq);
+int bwmgr_iso_bw_percentage_max(void);
+int bwmgr_get_emc_to_dram_freq_factor(void);
+#endif /* __BWMGR_MC_H */
diff --git a/include/linux/platform/tegra/clock.h b/include/linux/platform/tegra/clock.h
new file mode 100644
index 000000000..896bb01bc
--- /dev/null
+++ b/include/linux/platform/tegra/clock.h
@@ -0,0 +1,629 @@
+/*
+ * include/linux/platform/tegra/clock.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * Copyright (c) 2010-2016, NVIDIA Corporation.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_CLOCK_H
+#define __MACH_TEGRA_CLOCK_H
+
+#define USE_PLL_LOCK_BITS 1     /* Use lock bits for PLL stabiliation */
+#define USE_PLLE_SS 1           /* Use spread spectrum coefficients for PLLE */
+#define PLL_PRE_LOCK_DELAY  2   /* Delay 1st lock bit read after pll enabled */
+#define USE_PLLE_SWCTL 0        /* Use s/w controls for PLLE */
+#define PLL_POST_LOCK_DELAY 10  /* Safety delay after lock is detected */
+
+#define RESET_PROPAGATION_DELAY 5
+
+#ifndef __ASSEMBLY__
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/lockdep.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/clk/tegra.h>
+#include <trace/events/power.h>
+#include <asm/cputime.h>
+
+#define MAX_SAME_LIMIT_SKU_IDS  16
+#define STATS_USERS_LIST_SIZE   16
+
+struct clk;
+
+#define DIV_BUS                 (1 << 0)        /* system bus clock */
+#define DIV_U71                 (1 << 1)        /* divider is U7.1 (N/2 + 1) */
+#define DIV_U71_FIXED           (1 << 2)        /* divider is U7.1 and fixed unless reprogrammed by SW */
+#define DIV_2                   (1 << 3)        /* clock output is divided by 2 */
+#define DIV_U16                 (1 << 4)        /* divider is (N + 1) */
+#define PLL_FIXED               (1 << 5)        /* PLL runs at fixed rate */
+#define PLL_HAS_CPCON           (1 << 6)        /* PLL has CPCON value in its configuration register */
+#define MUX                     (1 << 7)        /* this clock uses a mux to select one of the input sources */
+#define PLLD                    (1 << 8)        /* clock is PLLD */
+#define PERIPH_NO_RESET         (1 << 9)        /* doesn't have separate reset bit in the register */
+#define PERIPH_NO_ENB           (1 << 10)       /* does not have clock enable bit in the register */
+#define PERIPH_EMC_ENB          (1 << 11)       /* this peripheral clock is EMC */
+#define PERIPH_MANUAL_RESET     (1 << 12)       /* don't take module out of reset automatically, when enabling clock */
+#define PLL_ALT_MISC_REG        (1 << 13)       /* use alternate offset for PLL misc registers */
+#define PLLU                    (1 << 14)       /* PLL is PLLU */
+#define PLLX                    (1 << 15)       /* PLL is PLLX */
+#define MUX_PWM                 (1 << 16)       /* deprecated for T124 onwards */
+#define MUX8                    (1 << 17)       /* used in simulator setting for T124 onwards */
+#define DIV_U151_UART           (1 << 18)       /* 16-bit uart divider with dual CAR/UART control */
+#define MUX_CLK_OUT             (1 << 19)       /* used to locate extperiph clock registers */
+#define PLLM                    (1 << 20)       /* PLL is PLLM */
+#define DIV_U71_INT             (1 << 21)       /* fractional divider is not allowed for this clock */
+#define DIV_U71_IDLE            (1 << 22)       /* clock has a  separate idle state divider that is automatically
+                                                   engaged when module is idle */
+#define DIV_U151                (1 << 23)       /* divider will be U15.1 for this clock */
+#define DFLL                    (1 << 24)       /* this clock has closed loop control in h/w */
+#define ENABLE_ON_INIT          (1 << 28)       /* enable during initialization (deprecated) */
+#define PERIPH_ON_APB           (1 << 29)       /* this peripheral is on APB */
+#define PERIPH_ON_CBUS          (1 << 30)       /* this peripheral is on one of the PLLCx bus */
+#define BUS_RATE_LIMIT          (1 << 31)       /* Clock used to apply constraints on shared buses
+                                                   (don't propagate enable/disable to the bus) */
+
+#define SHARED_BUS_RETENTION    (1 << 0)
+#define SHARED_BUS_USE_SKIPPERS (1 << 1)
+
+#define PERIPH_DIV              (DIV_U71 | DIV_U151 | DIV_U16)
+#define PERIPH_INIT_SAFE_RATE   12000000
+
+#ifdef CONFIG_COMMON_CLK
+struct clk_tegra;
+#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
+#endif
+
+struct clk_mux_sel {
+        struct clk      *input;
+        u32             value;
+};
+
+struct clk_backup {
+        struct clk      *input;
+        u32             value;
+        unsigned long   bus_rate;
+};
+
+struct clk_pll_freq_table {
+        unsigned long   input_rate;
+        unsigned long   output_rate;
+        u16             n;
+        u16             m;
+        u8              p;
+        u8              cpcon;
+        u16             sdm_data;
+};
+
+struct clk_pll_div_layout {
+        /* base dividers */
+        u32             ndiv_shift;
+        u32             ndiv_mask;
+        u32             mdiv_shift;
+        u32             mdiv_mask;
+        u32             pdiv_shift;
+        u32             pdiv_mask;
+        u8              *pdiv_to_p;
+        u8              pdiv_max;
+
+        /* misc dividers */
+        u32             ndiv_new_shift;
+        u32             ndiv_new_reg_idx;
+        u32             sdm_din_mask;
+        u32             sdm_din_shift;
+        u32             sdm_din_reg_idx;
+};
+
+struct clk_pll_controls {
+        u32             enable_mask;
+        u32             bypass_mask;
+
+        u32             reset_mask;
+        u32             reset_reg_idx;
+        u32             iddq_mask;
+        u32             iddq_reg_idx;
+        u32             lock_mask;
+        u32             lock_reg_idx;
+
+        u32             dramp_en_mask;
+        u32             dramp_done_mask;
+        u32             dramp_ctrl_reg_idx;
+        u32             sdm_en_mask;
+        u32             ssc_en_mask;
+        u32             sdm_ctrl_reg_idx;
+};
+
+enum pll_reg_indx {
+        PLL_BASE_IDX = 0,
+        PLL_MISC0_IDX,
+        PLL_MISC1_IDX,
+        PLL_MISC2_IDX,
+        PLL_MISC3_IDX,
+        PLL_MISC4_IDX,
+        PLL_MISC5_IDX,
+};
+
+enum clk_state {
+        UNINITIALIZED = 0,
+        ON,
+        OFF,
+};
+
+struct tegra_pto_table {
+        char *name;
+        int divider;
+        u32 pto_id;
+        u32 presel_value;
+        u32 presel_reg;
+        u32 presel_mask;
+};
+
+#ifndef CONFIG_COMMON_CLK
+struct clk_ops {
+        void            (*init)(struct clk *);
+        int             (*enable)(struct clk *);
+        void            (*disable)(struct clk *);
+        int             (*set_parent)(struct clk *, struct clk *);
+        int             (*set_rate)(struct clk *, unsigned long);
+        long            (*round_rate)(struct clk *, unsigned long);
+        void            (*reset)(struct clk *, bool);
+        int             (*shared_bus_update)(struct clk *);
+        int             (*clk_cfg_ex)(struct clk *,
+                                enum tegra_clk_ex_param, u32);
+        long            (*round_rate_updown)(struct clk *, unsigned long, bool);
+};
+
+struct bus_stats {
+        cputime64_t     *time_table;
+        struct clk      *users_list[STATS_USERS_LIST_SIZE];
+        int             users_num;
+        int             rates_num;
+        int             new_cap_idx;
+        int             new_floor_idx;
+        int             new_rate_idx;
+        int             last_user_idx;
+        int             last_rate_idx;
+        u64             last_update;
+};
+
+struct clk_stats {
+        struct bus_stats *histogram;
+        cputime64_t     time_on;
+        u64             last_update;
+};
+
+enum cpu_mode {
+        MODE_G = 0,
+        MODE_LP,
+};
+
+enum shared_bus_users_mode {
+        SHARED_FLOOR = 0,
+        SHARED_BW,
+        SHARED_CEILING,
+        SHARED_AUTO,
+        SHARED_OVERRIDE,
+        SHARED_ISO_BW,
+        SHARED_CEILING_BUT_ISO,
+};
+
+struct clk {
+        /* node for master clocks list */
+        struct list_head        node;           /* node for list of all clocks */
+        struct dvfs             *dvfs;
+        struct clk_lookup       lookup;
+
+#ifdef CONFIG_DEBUG_FS
+        struct dentry           *dent;
+        struct tegra_pto_table  *pto_entry;
+#endif
+        bool                    set;
+        struct clk_ops          *ops;
+        unsigned long           dvfs_rate;
+        unsigned long           rate;
+        unsigned long           boot_rate;
+        unsigned long           max_rate;
+        unsigned long           min_rate;
+        bool                    auto_dvfs;
+        bool                    cansleep;
+        bool                    set_disabled_div;
+        u32                     flags;
+        u32                     clk_id;
+        const char              *name;
+
+        u32                     refcnt;
+        enum clk_state          state;
+        struct clk              *parent;
+        u32                     div;
+        u32                     mul;
+        struct clk              *skipper;
+        struct clk_stats        stats;
+
+        const struct clk_mux_sel        *inputs;
+        u32                             reg;
+        u32                             reg_shift;
+
+#ifdef CONFIG_LOCKDEP
+        struct lock_class_key   lockdep_class;
+#endif
+
+        struct list_head                shared_bus_list;
+        struct clk_backup               shared_bus_backup;
+        struct clk                      *child_bus;
+        unsigned long                   override_rate;
+        u32                             shared_bus_flags;
+
+        union {
+                struct {
+                        unsigned int                    clk_num;
+                        u32                             src_mask;
+                        u32                             src_shift;
+                        struct clk                      *pll_low;
+                        struct clk                      *pll_high;
+                        struct clk                      *pll_selected;
+                        unsigned long                   threshold;
+                        int                             min_div_low;
+                        int                             min_div_high;
+                } periph;
+                struct {
+                        unsigned long                   input_min;
+                        unsigned long                   input_max;
+                        unsigned long                   cf_min;
+                        unsigned long                   cf_max;
+                        unsigned long                   vco_min;
+                        unsigned long                   vco_max;
+                        u16                             mdiv_default;
+                        u8                              cpcon_default;
+                        const struct clk_pll_freq_table *freq_table;
+                        int                             lock_delay;
+                        unsigned long                   fixed_rate;
+                        u32                             misc0;
+                        u32                             misc1;
+                        u32                             misc2;
+                        u32                             misc3;
+                        u32                             misc4;
+                        u32                             misc5;
+                        bool                            defaults_set;
+                        bool                            vco_out;
+                        struct clk_pll_controls         *controls;
+                        struct clk_pll_div_layout       *div_layout;
+                        u32     (*round_p_to_pdiv)(u32 p, u32 *pdiv);
+                        int     (*dyn_ramp)(struct clk *c,
+                                            struct clk_pll_freq_table *cfg);
+                        void    (*set_defaults)(struct clk *c,
+                                                unsigned long input_rate);
+                } pll;
+                struct {
+                        void                            *cl_dvfs;
+                        struct clk                      *consumer;
+                } dfll;
+                struct {
+                        unsigned long                   default_rate;
+                } pll_div;
+                struct {
+                        u32                             sel;
+                        u32                             reg_mask;
+                } mux;
+                struct {
+                        struct clk                      *main;
+                        struct clk                      *backup;
+                        struct clk                      *dynamic;
+                        unsigned long                   edp_safe_rate;
+                        unsigned long                   backup_rate;
+                        seqcount_t                      backup_seqcnt;
+                        enum cpu_mode                   mode;
+                } cpu;
+                struct {
+                        u32                             div71;
+                } cclk;
+                struct {
+                        struct clk                      *pclk;
+                        struct clk                      *hclk;
+                        struct clk                      *sclk_low;
+                        struct clk                      *sclk_high;
+                        unsigned long                   threshold;
+                } system;
+                struct {
+                        struct clk                      *top_user;
+                        struct clk                      *slow_user;
+                } cbus;
+                struct {
+                        struct list_head                node;
+                        bool                            enabled;
+                        unsigned long                   rate;
+                        const char                      *client_id;
+                        struct clk                      *client;
+                        u32                             client_div;
+                        enum shared_bus_users_mode      mode;
+                        u32                             usage_flag;
+                        int                             stats_idx;
+                } shared_bus_user;
+                struct {
+                        struct tegra_clk_export_ops     *ops;
+                } export_clk;
+        } u;
+
+        struct raw_notifier_head                        *rate_change_nh;
+        wait_queue_head_t                               *debug_poll_qh;
+        int                                             rate_changed;
+
+        struct mutex *cross_clk_mutex;
+        struct mutex mutex;
+        spinlock_t spinlock;
+        unsigned long fixed_target_rate;
+};
+
+#else
+
+struct clk_tegra {
+        /* node for master clocks list */
+        struct list_head        node;   /* node for list of all clocks */
+        struct clk_lookup       lookup;
+        struct clk_hw           hw;
+
+        bool                    set;
+        unsigned long           fixed_rate;
+        unsigned long           max_rate;
+        unsigned long           min_rate;
+        u32                     flags;
+        const char              *name;
+
+        enum clk_state          state;
+        u32                     div;
+        u32                     mul;
+
+        u32                             reg;
+        u32                             reg_shift;
+
+        struct list_head                shared_bus_list;
+
+        union {
+                struct {
+                        unsigned int                    clk_num;
+                } periph;
+                struct {
+                        unsigned long                   input_min;
+                        unsigned long                   input_max;
+                        unsigned long                   cf_min;
+                        unsigned long                   cf_max;
+                        unsigned long                   vco_min;
+                        unsigned long                   vco_max;
+                        const struct clk_pll_freq_table *freq_table;
+                        int                             lock_delay;
+                        unsigned long                   fixed_rate;
+                } pll;
+                struct {
+                        u32                             sel;
+                        u32                             reg_mask;
+                } mux;
+                struct {
+                        struct clk                      *main;
+                        struct clk                      *backup;
+                } cpu;
+                struct {
+                        struct list_head                node;
+                        bool                            enabled;
+                        unsigned long                   rate;
+                } shared_bus_user;
+        } u;
+
+        void (*reset)(struct clk_hw *, bool);
+        int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
+};
+#endif /* !CONFIG_COMMON_CLK */
+
+struct clk_duplicate {
+        const char *name;
+        struct clk_lookup lookup;
+};
+
+struct tegra_clk_init_table {
+        const char *name;
+        const char *parent;
+        unsigned long rate;
+        bool enabled;
+        unsigned long platform;
+        struct clk *c;          /* clock to be initialized */
+        struct clk *p;          /* clock parent specified in the table */
+};
+
+#define TEGRA_CLK_INIT_PLATFORM_ALL     0
+#define TEGRA_CLK_INIT_PLATFORM_SI      BIT(0)
+#define TEGRA_CLK_INIT_PLATFORM_QT      BIT(1)
+#define TEGRA_CLK_INIT_PLATFORM_FPGA    BIT(2)
+#define TEGRA_CLK_INIT_PLATFORM_LINSIM  BIT(3)
+#define TEGRA_CLK_INIT_CPU_ASIM         BIT(4)
+#define TEGRA_CLK_INIT_PLATFORM_NON_SI  (BIT(1) | BIT(2) | BIT(3))
+
+#ifndef CONFIG_COMMON_CLK
+void tegra_init_max_rate(struct clk *c, unsigned long max_rate);
+void tegra_init_min_rate(struct clk *c, unsigned long min_rate);
+void tegra_clk_preset_emc_monitor(unsigned long rate);
+void tegra_periph_clk_safe_rate_init(struct clk *c);
+void tegra_clk_verify_parents(void);
+void tegra_clk_set_disabled_div_all(void);
+void clk_init(struct clk *clk);
+unsigned long tegra_clk_measure_input_freq(void);
+unsigned long clk_get_rate_locked(struct clk *c);
+void tegra_clk_init_from_dt(const char *dt_table_name);
+void tegra_clk_init_cbus_plls_from_table(struct tegra_clk_init_table *table);
+void clk_set_cansleep(struct clk *c);
+unsigned long clk_get_min_rate(struct clk *c);
+unsigned long clk_get_max_rate(struct clk *c);
+bool tegra_is_clk_initialized(struct clk *c);
+
+int clk_set_rate_locked(struct clk *c, unsigned long rate);
+int clk_rate_change_notify(struct clk *c, unsigned long rate);
+int clk_set_parent_locked(struct clk *c, struct clk *parent);
+int clk_reparent(struct clk *c, struct clk *parent);
+long clk_round_rate_locked(struct clk *c, unsigned long rate);
+int tegra_clk_shared_bus_update(struct clk *c);
+int tegra_clk_shared_bus_update_locked(struct clk *c);
+void tegra3_set_cpu_skipper_delay(int delay);
+unsigned long tegra_clk_measure_input_freq(void);
+int clk_enable_locked(struct clk *c);
+void clk_disable_locked(struct clk *c);
+bool tegra_clk_is_parent_allowed(struct clk *c, struct clk *p);
+#endif /* !CONFIG_COMMON_CLK */
+
+struct tegra_sku_rate_limit {
+        const char *clk_name;
+        unsigned long max_rate;
+        int sku_ids[MAX_SAME_LIMIT_SKU_IDS];
+};
+
+void tegra2_init_clocks(void);
+void tegra30_init_clocks(void);
+void tegra11x_init_clocks(void);
+void tegra12x_init_clocks(void);
+void tegra21x_init_clocks(void);
+void tegra11x_clk_init_la(void);
+void tegra_common_init_clock(void);
+struct clk *tegra_get_clock_by_name(const char *name);
+
+void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
+
+/* Reset driver through Reset framework */
+extern int tegra_non_dt_clock_reset_init(void);
+
+/**
+  * Returns dfll requested booting frequency, which
+  * is configured by bootloader as cpu clock source.
+  * If booting with different cpu clock source then,
+  * returns 0.
+  */
+unsigned long int tegra_dfll_boot_req_khz(void);
+
+#ifndef CONFIG_COMMON_CLK
+void tegra_shared_bus_stats_allocate(struct clk *c, struct bus_stats *stats);
+int tegra_shared_bus_stats_copy_to_buffer(
+        struct clk *c, struct bus_stats *stats, char *buf, int len);
+void tegra_shared_bus_stats_update(
+        struct bus_stats *stats, int user_idx, int rate_idx);
+
+int clk_config_cpu_edp_safe_rate(struct clk *cpu, struct clk *cluster_clk,
+                                 unsigned long rate);
+
+static inline unsigned long clk_get_cpu_edp_safe_rate(struct clk *cluster_clk)
+{
+        return cluster_clk->u.cpu.edp_safe_rate;
+}
+
+static inline void tegra_dfll_set_cl_dvfs_data(struct clk *c, void *cld)
+{
+        if (c->flags & DFLL)
+                c->u.dfll.cl_dvfs = cld;
+}
+
+static inline void *tegra_dfll_get_cl_dvfs_data(struct clk *c)
+{
+        return c->flags & DFLL ? c->u.dfll.cl_dvfs : ERR_PTR(-ENODATA);
+}
+
+static inline bool clk_is_auto_dvfs(struct clk *c)
+{
+        return c->auto_dvfs;
+}
+
+static inline bool clk_is_dvfs(struct clk *c)
+{
+        return (c->dvfs != NULL);
+}
+
+static inline bool clk_cansleep(struct clk *c)
+{
+        return c->cansleep;
+}
+
+static inline bool clk_can_set_disabled_div(struct clk *c)
+{
+        return c->set_disabled_div;
+}
+
+static inline void clk_lock_save(struct clk *c, unsigned long *flags)
+{
+        if (clk_cansleep(c)) {
+                *flags = 0;
+                mutex_lock(&c->mutex);
+                if (c->cross_clk_mutex)
+                        mutex_lock(c->cross_clk_mutex);
+        } else {
+                spin_lock_irqsave(&c->spinlock, *flags);
+        }
+}
+
+static inline void clk_unlock_restore(struct clk *c, unsigned long *flags)
+{
+        if (clk_cansleep(c)) {
+                if (c->cross_clk_mutex)
+                        mutex_unlock(c->cross_clk_mutex);
+                mutex_unlock(&c->mutex);
+        } else {
+                spin_unlock_irqrestore(&c->spinlock, *flags);
+        }
+}
+
+static inline int tegra_clk_prepare_enable(struct clk *c)
+{
+        if (clk_cansleep(c))
+                return clk_prepare_enable(c);
+        return clk_enable(c);
+}
+
+static inline void tegra_clk_disable_unprepare(struct clk *c)
+{
+        if (clk_cansleep(c))
+                clk_disable_unprepare(c);
+        else
+                clk_disable(c);
+}
+
+static inline void clk_lock_init(struct clk *c)
+{
+        mutex_init(&c->mutex);
+        spin_lock_init(&c->spinlock);
+}
+#endif
+
+#ifdef CONFIG_DEBUG_FS
+
+/* Extended version of the standard macro with poll function setting */
+#define DEFINE_SIMPLE_POLL_ATTRIBUTE(__fops, __get, __set, __poll, __fmt) \
+static int __fops ## _open(struct inode *inode, struct file *file)      \
+{                                                                       \
+        __simple_attr_check_format(__fmt, 0ull);                        \
+        return simple_attr_open(inode, file, __get, __set, __fmt);      \
+}                                                                       \
+static const struct file_operations __fops = {                          \
+        .owner   = THIS_MODULE,                                         \
+        .open    = __fops ## _open,                                     \
+        .release = simple_attr_release,                                 \
+        .read    = simple_attr_read,                                    \
+        .write   = simple_attr_write,                                   \
+        .llseek  = generic_file_llseek,                                 \
+        .poll    = __poll,                                              \
+};
+
+void tegra_clk_add_pto_entries(struct tegra_pto_table *pto_table);
+
+#endif
+
+#endif
+#endif
diff --git a/include/linux/platform/tegra/common.h b/include/linux/platform/tegra/common.h
new file mode 100644
index 000000000..1743d67d7
--- /dev/null
+++ b/include/linux/platform/tegra/common.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2011-2018, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_COMMON_H
+#define __MACH_TEGRA_COMMON_H
+
+extern struct smp_operations tegra_smp_ops;
+
+extern phys_addr_t tegra_tsec_start;
+extern phys_addr_t tegra_tsec_size;
+
+#ifdef CONFIG_CACHE_L2X0
+void tegra_init_cache(bool init);
+#else
+static inline void tegra_init_cache(bool init) {}
+#endif
+
+extern void tegra_cpu_die(unsigned int cpu);
+extern int tegra_cpu_kill(unsigned int cpu);
+extern phys_addr_t tegra_avp_kernel_start;
+extern phys_addr_t tegra_avp_kernel_size;
+void ahb_gizmo_writel(unsigned long val, void __iomem *reg);
+
+extern struct device tegra_generic_cma_dev;
+extern struct device tegra_vpr_cma_dev;
+extern int tegra_with_secure_firmware;
+
+extern struct device tegra_generic_dev;
+extern struct device tegra_vpr_dev;
+extern struct device tegra_iram_dev;
+extern struct dma_resize_notifier_ops vpr_dev_ops;
+
+u32 tegra_get_bct_strapping(void);
+u32 tegra_get_fuse_opt_subrevision(void);
+enum tegra_revision tegra_chip_get_revision(void);
+void __init display_tegra_dt_info(void);
+
+void tegra_register_idle_unidle(int (*do_idle)(void *),
+                                int (*do_unidle)(void *),
+                                void *data);
+void tegra_unregister_idle_unidle(int (*do_idle)(void *));
+
+static inline int tegra_cpu_is_secure(void)
+{
+        return tegra_with_secure_firmware;
+}
+
+int tegra_state_idx_from_name(char *state_name);
+#endif
diff --git a/include/linux/platform/tegra/cpu-tegra.h b/include/linux/platform/tegra/cpu-tegra.h
index 344ab94d5..494939887 100644
--- a/include/linux/platform/tegra/cpu-tegra.h
+++ b/include/linux/platform/tegra/cpu-tegra.h
@@ -22,6 +22,7 @@
 #define __MACH_TEGRA_CPU_TEGRA_H
 
 #include <linux/fs.h>
+#include <linux/tegra_throttle.h>
 
 unsigned int tegra_getspeed(unsigned int cpu);
 int tegra_update_cpu_speed(unsigned long rate);
@@ -88,6 +89,13 @@ static inline int tegra_cpu_reg_mode_force_normal(bool force)
 { return 0; }
 #endif
 
+#ifdef CONFIG_TEGRA_CPU_VOLT_CAP
+struct tegra_cooling_device *tegra_vc_get_cdev(void);
+#else
+static inline struct tegra_cooling_device *tegra_vc_get_cdev(void)
+{ return NULL; }
+#endif
+
 #ifdef CONFIG_TEGRA_HMP_CLUSTER_CONTROL
 unsigned long lp_to_virtual_gfreq(unsigned long lp_freq);
 int tegra_cpu_volt_cap_apply(int *cap_idx, int new_idx, int level);
diff --git a/include/linux/platform/tegra/denver_mca.h b/include/linux/platform/tegra/denver_mca.h
new file mode 100644
index 000000000..9262015cd
--- /dev/null
+++ b/include/linux/platform/tegra/denver_mca.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+/* Template for MCA bank register accessors */
+#define DENVER_MCA_OP(bank, reg, crm, op2)                              \
+static u64 denver_mca_ ##reg##_##bank(void)                             \
+{                                                                       \
+        u64 ret;                                                        \
+        asm volatile ("mrs %0, s3_0_c15_c" #crm "_" #op2 : "=r"(ret));  \
+        return ret;                                                     \
+}
+
+/* A macro to instanciate all of the register accessors in the bank */
+#define DEFINE_DENVER_MCA_OPS(bank,                                     \
+        crm_ctrl, op2_ctrl,                                             \
+        crm_stat, op2_stat,                                             \
+        crm_addr, op2_addr,                                             \
+        crm_msc1, op2_msc1,                                             \
+        crm_msc2, op2_msc2)                                             \
+        DENVER_MCA_OP(bank, ctrl, crm_ctrl, op2_ctrl)                   \
+        DENVER_MCA_OP(bank, stat, crm_stat, op2_stat)                   \
+        DENVER_MCA_OP(bank, addr, crm_addr, op2_addr)                   \
+        DENVER_MCA_OP(bank, msc1, crm_msc1, op2_msc1)                   \
+        DENVER_MCA_OP(bank, msc2, crm_msc2, op2_msc2)
+
+struct denver_mca_error {
+        char *name;
+        u16 error_code;
+};
+
+struct denver_mca_bank {
+        struct list_head node;
+        char *name;
+        u64 bank;
+        struct denver_mca_error *errors;
+        u64 (*ctrl)(void);
+        u64 (*stat)(void);
+        u64 (*addr)(void);
+        u64 (*msc1)(void);
+        u64 (*msc2)(void);
+        u8 processed;
+};
+
+/* Helper macro for filling in struct denver_mca_bank */
+#define DENVER_MCA_OP_ENTRY(_bank)                                      \
+        .bank = _bank,                                                  \
+        .ctrl = denver_mca_ctrl_ ## _bank,                              \
+        .stat = denver_mca_stat_ ## _bank,                              \
+        .addr = denver_mca_addr_ ## _bank,                              \
+        .msc1 = denver_mca_msc1_ ## _bank,                              \
+        .msc2 = denver_mca_msc2_ ## _bank
+
+/* Helper macro for a denver_mca_bank without a denver_mca_error */
+#define SIMPLE_DENVER_MCA_OP_ENTRY(_name, _bank)                        \
+        .name = _name,                                                  \
+        DENVER_MCA_OP_ENTRY(_bank)
+
+void register_denver_mca_bank(struct denver_mca_bank *bank);
+void unregister_denver_mca_bank(struct denver_mca_bank *bank);
diff --git a/include/linux/platform/tegra/dvfs.h b/include/linux/platform/tegra/dvfs.h
new file mode 100644
index 000000000..23253edb0
--- /dev/null
+++ b/include/linux/platform/tegra/dvfs.h
@@ -0,0 +1,443 @@
+/*
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Colin Cross <ccross@google.com>
+ *
+ * Copyright (c) 2010-2016 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _TEGRA_DVFS_H_
+#define _TEGRA_DVFS_H_
+
+#include <linux/of.h>
+#include <linux/tegra_throttle.h>
+
+#define MAX_DVFS_FREQS  40
+#define MAX_DVFS_TABLES 80
+#define DVFS_RAIL_STATS_TOP_BIN 100
+#define MAX_THERMAL_LIMITS      8
+#define MAX_THERMAL_RANGES      (MAX_THERMAL_LIMITS + 1)
+
+struct clk;
+struct dvfs_rail;
+
+/*
+ * dvfs_relationship between to rails, "from" and "to"
+ * when the rail changes, it will call dvfs_rail_update on the rails
+ * in the relationship_to list.
+ * when determining the voltage to set a rail to, it will consider each
+ * rail in the relationship_from list.
+ */
+struct dvfs_relationship {
+        struct dvfs_rail *to;
+        struct dvfs_rail *from;
+        int (*solve)(struct dvfs_rail *, struct dvfs_rail *);
+
+        struct list_head to_node; /* node in relationship_to list */
+        struct list_head from_node; /* node in relationship_from list */
+        bool solved_at_nominal;
+        bool solved_at_suspend;
+};
+
+struct rail_stats {
+        ktime_t time_at_mv[DVFS_RAIL_STATS_TOP_BIN + 1];
+        ktime_t last_update;
+        int last_index;
+        bool off;
+        int bin_uV;
+};
+
+struct rail_alignment {
+        int offset_uv;
+        int step_uv; /* Step voltage */
+};
+
+struct dvfs_rail {
+        const char *reg_id;
+        int min_millivolts;
+        int max_millivolts;
+        int reg_max_millivolts;
+        int nominal_millivolts; /* Max DVFS voltage */
+        int fixed_millivolts;
+        int override_millivolts;
+        int min_override_millivolts;
+        int override_unresolved;
+        int (*resolve_override)(int mv);
+
+        const int *therm_mv_floors;
+        const int *therm_mv_dfll_floors;
+        int therm_mv_floors_num;
+        const int *therm_mv_caps;
+        int therm_mv_caps_num;
+        const int *simon_vmin_offsets;
+        int simon_vmin_offs_num;
+        int simon_domain;
+
+        int step;
+        int step_up;
+        bool jmp_to_zero;
+        bool in_band_pm;
+        bool disabled;
+        bool updating;
+        bool resolving_to;
+        bool rate_set;
+        bool dt_reg_fixed;
+        bool dt_reg_pwm;
+
+        struct device_node *dt_node; /* device tree rail node */
+        struct list_head node;  /* node in dvfs_rail_list */
+        struct list_head dvfs;  /* list head of attached dvfs clocks */
+        struct list_head relationships_to;
+        struct list_head relationships_from;
+        struct regulator *reg;
+        int millivolts;
+        int new_millivolts;
+        int dbg_mv_offs;
+        int boot_millivolts;
+        int disable_millivolts;
+        int suspend_millivolts; /* voltage setting set during suspend */
+
+        bool suspended;
+        bool dfll_mode; /* DFLL mode ON/OFF */
+        bool dfll_mode_updating;
+
+        int therm_floor_idx;    /* index of vmin thermal range */
+        int therm_cap_idx;      /* index of vmax thermal range */
+        int therm_scale_idx;    /* index of thermal DVFS or clk source range */
+
+        /* Trips for vmin cooling device */
+        struct tegra_cooling_device *vmin_cdev;
+
+        /* Trips for vmax cooling device */
+        struct tegra_cooling_device *vmax_cdev;
+
+        /* Trips for thermal DVFS cooling device */
+        struct tegra_cooling_device *vts_cdev;
+
+        /* Trips for clock source switch cooling device */
+        struct tegra_cooling_device *clk_switch_cdev;
+
+        /* Vmax capping method */
+        int (*apply_vmax_cap)(int *cap_idx, int new_idx, int cap_mv);
+
+        struct rail_alignment alignment;
+        struct rail_stats stats;
+        const char *version;
+};
+
+/*
+ * dfll_range -
+ *      DFLL_RANGE_NONE       : DFLL is not used
+ *      DFLL_RANGE_ALL_RATES  : DFLL is is used for all CPU rates
+ *      DFLL_RANGE_HIGH_RATES : DFLL is used only for high rates
+ *                              above crossover with PLL dvfs curve
+ */
+enum dfll_range {
+        DFLL_RANGE_NONE = 0,
+        DFLL_RANGE_ALL_RATES,
+        DFLL_RANGE_HIGH_RATES,
+};
+
+/* DFLL usage is under thermal cooling device control */
+#define TEGRA_USE_DFLL_CDEV_CNTRL 3
+
+extern int tegra_override_dfll_range;
+
+/* DVFS settings specific for DFLL clock source */
+struct dvfs_dfll_data {
+        u32             tune0;
+        u32             tune0_high_mv;
+        u32             tune0_simon_mask;
+        u32             tune1;
+        bool            tune0_low_at_cold;
+
+        unsigned long   droop_rate_min;
+        unsigned long   use_dfll_rate_min;
+        unsigned long   out_rate_min;
+        unsigned long   max_rate_boost;
+        /* Boot frequency if DFLL is enabled by boot-loader; zero otherwise */
+        unsigned long   dfll_boot_khz;
+
+        int tune_high_min_millivolts;
+        int tune_high_margin_mv;
+        int min_millivolts;
+        enum dfll_range range;
+        void (*tune_trimmers)(bool trim_high);
+        unsigned int (*is_bypass_down)(void);
+};
+
+/* DVFS settings specific for PLL clock source */
+struct dvfs_pll_data {
+        int min_millivolts;
+};
+
+struct dvfs {
+        const char *clk_name;
+        struct clk *clk;
+        int speedo_id;
+        int process_id;
+
+        /* Must be initialized before tegra_dvfs_init */
+        int freqs_mult;
+        unsigned long freqs[MAX_DVFS_FREQS];
+        const int *millivolts;
+        const int *peak_millivolts;
+        /* voltage settings as per DFLL clock source */
+        const int *dfll_millivolts;
+        struct dvfs_rail *dvfs_rail;
+        bool auto_dvfs;
+        bool can_override;
+        bool defer_override;
+        bool boost_table;
+
+        /* Filled in by tegra_dvfs_init */
+        int max_millivolts;
+        int num_freqs;
+        struct dvfs_dfll_data dfll_data;
+
+        /* Set if clock rate is adapted by h/w to voltage noise (noise-aware) */
+        bool na_dvfs;
+        /* Indicates thermal DVFS on/off */
+        bool therm_dvfs;
+        /* Maximum rate safe at minimum voltage across all thermal ranges */
+        unsigned long fmax_at_vmin_safe_t;
+
+        /*
+         * Current dvfs point = { index into V/F arrays, voltage, rate request }
+         * cur_index is invalid - set to MAX_DVFS_FREQS - if cur_rate and
+         * cur_millivolts are set to zero (may happen when dvfs rate is not set
+         * initially, or clock is disabled).
+         */
+        int cur_index;
+        int cur_millivolts;
+        unsigned long cur_rate;
+
+        unsigned long *alt_freqs;
+        bool use_alt_freqs;
+        long dbg_hz_offs;
+        struct list_head node;
+        struct list_head debug_node;
+        struct list_head reg_node;
+        struct mutex *lock;
+};
+
+/* CVB coefficients */
+struct cvb_dvfs_parameters {
+        int     c0;
+        int     c1;
+        int     c2;
+        int     c3;
+        int     c4;
+        int     c5;
+};
+
+struct cvb_dvfs_table {
+        unsigned long freq;
+
+        /* Coeffs for voltage calculation, when dfll clock source is selected */
+        struct cvb_dvfs_parameters cvb_dfll_param;
+
+        /* Coeffs for voltage calculation, when pll clock source is selected */
+        struct cvb_dvfs_parameters cvb_pll_param;
+};
+
+struct cvb_dvfs {
+        int speedo_id;
+        int process_id;
+
+        /* Tuning parameters for dfll */
+        struct dvfs_dfll_data dfll_tune_data;
+
+        /* tuning parameters for pll clock */
+        struct dvfs_pll_data pll_tune_data;
+
+        /* dvfs Max voltage */
+        int max_mv;
+
+        /* dvfs Max frequency */
+        unsigned long max_freq;
+        int freqs_mult;
+
+        /* scaling values for voltage calculation */
+        int speedo_scale;
+        int voltage_scale;
+        int thermal_scale;
+
+        struct cvb_dvfs_table cvb_vmin;
+
+        /* CVB table for various frequencies */
+        struct cvb_dvfs_table cvb_table[MAX_DVFS_FREQS];
+
+        /* Trips for minimal voltage settings per thermal ranges */
+        int vmin_trips_table[MAX_THERMAL_LIMITS];
+        int therm_floors_table[MAX_THERMAL_LIMITS];
+
+        /* Trips for thermal DVFS per thermal ranges */
+        int vts_trips_table[MAX_THERMAL_LIMITS];
+
+        /* Trips for clock source change per thermal ranges */
+        int clk_switch_trips[MAX_THERMAL_LIMITS];
+};
+
+#define cpu_cvb_dvfs    cvb_dvfs
+#define gpu_cvb_dvfs    cvb_dvfs
+#define core_cvb_dvfs   cvb_dvfs
+
+extern struct dvfs_rail *tegra_cpu_rail;
+extern struct dvfs_rail *tegra_gpu_rail;
+extern struct dvfs_rail *tegra_core_rail;
+
+struct dvfs_data {
+        struct dvfs_rail *rail;
+        struct dvfs *tables;
+        int *millivolts;
+        unsigned int num_tables;
+        unsigned int num_voltages;
+};
+
+#ifdef CONFIG_OF
+typedef int (*of_tegra_dvfs_init_cb_t)(struct device_node *);
+int of_tegra_dvfs_init(const struct of_device_id *matches);
+int of_tegra_dvfs_rail_node_parse(struct device_node *rail_dn,
+                                  struct dvfs_rail *rail);
+int of_tegra_dvfs_rail_get_cdev_trips(
+        struct tegra_cooling_device *tegra_cdev, int *therm_trips_table,
+        int *therm_limits_table, struct rail_alignment *align, bool up);
+#else
+static inline int of_tegra_dvfs_init(const struct of_device_id *matches)
+{ return -ENODATA; }
+static inline int of_tegra_dvfs_rail_node_parse(struct device_node *rail_dn,
+                                                struct dvfs_rail *rail)
+{ return -ENODEV; }
+static inline int of_tegra_dvfs_rail_get_cdev_trips(
+        struct tegra_cooling_device *tegra_cdev, int *therm_trips_table,
+        int *therm_limits_table, struct rail_alignment *align, bool up)
+{ return -ENODEV; }
+#endif
+
+void tegra21x_init_dvfs(void);
+int dvfs_debugfs_init(struct dentry *clk_debugfs_root);
+int tegra_dvfs_rail_connect_regulators(void);
+int tegra_dvfs_rail_register_notifiers(void);
+int tegra_dvfs_init_rails(struct dvfs_rail *dvfs_rails[], int n);
+void tegra_dvfs_add_relationships(struct dvfs_relationship *rels, int n);
+
+void tegra_dvfs_rail_enable(struct dvfs_rail *rail);
+void tegra_dvfs_rail_disable(struct dvfs_rail *rail);
+int tegra_dvfs_rail_power_up(struct dvfs_rail *rail);
+int tegra_dvfs_rail_power_down(struct dvfs_rail *rail);
+bool tegra_dvfs_is_rail_up(struct dvfs_rail *rail);
+bool tegra_dvfs_rail_updating(struct clk *clk);
+void tegra_dvfs_rail_off(struct dvfs_rail *rail, ktime_t now);
+void tegra_dvfs_rail_on(struct dvfs_rail *rail, ktime_t now);
+void tegra_dvfs_rail_pause(struct dvfs_rail *rail, ktime_t delta, bool on);
+int tegra_dvfs_rail_set_mode(struct dvfs_rail *rail, unsigned int mode);
+int tegra_dvfs_rail_register_notifier(struct dvfs_rail *rail,
+                                      struct notifier_block *nb);
+int tegra_dvfs_rail_unregister_notifier(struct dvfs_rail *rail,
+                                        struct notifier_block *nb);
+struct dvfs_rail *tegra_dvfs_get_rail_by_name(const char *reg_id);
+int tegra_dvfs_rail_get_current_millivolts(struct dvfs_rail *rail);
+
+int tegra_dvfs_override_core_cap_apply(int level);
+int tegra_dvfs_therm_vmax_core_cap_apply(int *cap_idx, int new_idx, int level);
+
+int tegra_dvfs_alt_freqs_install(struct dvfs *d, unsigned long *alt_freqs);
+void tegra_dvfs_alt_freqs_install_always(
+        struct dvfs *d, unsigned long *alt_freqs);
+int tegra_dvfs_replace_voltage_table(struct dvfs *d, const int *new_millivolts);
+
+int tegra_dvfs_butterfly_throttle(struct clk *c1, unsigned long *rate1,
+                                  struct clk *c2, unsigned long *rate2);
+
+int tegra_dvfs_dfll_mode_set(struct dvfs *d, unsigned long rate);
+int tegra_dvfs_dfll_mode_clear(struct dvfs *d, unsigned long rate);
+int tegra_clk_dfll_range_control(enum dfll_range use_dfll);
+bool tegra_dvfs_is_dfll_scale(struct dvfs *d, unsigned long rate);
+bool tegra_dvfs_is_dfll_range(struct dvfs *d, unsigned long rate);
+int tegra_dvfs_swap_dfll_range(struct dvfs *d, int range, int *old_range);
+int tegra_dvfs_set_dfll_range(struct dvfs *d, int range);
+int tegra_dvfs_rail_set_reg_volatile(struct dvfs_rail *rail, bool set);
+
+void tegra_clip_freqs(u32 *freqs, int *num_freqs, int freqs_mult,
+                     const unsigned long *rates_ladder, int num_rates, bool up);
+
+struct tegra_cooling_device *tegra_dvfs_get_cpu_vmax_cdev(void);
+struct tegra_cooling_device *tegra_dvfs_get_cpu_vmin_cdev(void);
+struct tegra_cooling_device *tegra_dvfs_get_core_vmax_cdev(void);
+struct tegra_cooling_device *tegra_dvfs_get_core_vmin_cdev(void);
+struct tegra_cooling_device *tegra_dvfs_get_gpu_vmin_cdev(void);
+struct tegra_cooling_device *tegra_dvfs_get_gpu_vts_cdev(void);
+struct tegra_cooling_device *tegra_dvfs_get_cpu_clk_switch_cdev(void);
+void tegra_dvfs_rail_init_vmin_thermal_profile(
+        int *therm_trips_table, int *therm_floors_table,
+        struct dvfs_rail *rail, struct dvfs_dfll_data *d);
+void tegra_dvfs_rail_init_vmax_thermal_profile(
+        int *therm_trips_table, int *therm_caps_table,
+        struct dvfs_rail *rail, struct dvfs_dfll_data *d);
+int tegra_dvfs_rail_of_init_vmin_thermal_profile(
+        int *therm_trips_table, int *therm_floors_table,
+        struct dvfs_rail *rail, struct dvfs_dfll_data *d);
+int tegra_dvfs_rail_of_init_vmax_thermal_profile(
+        int *therm_trips_table, int *therm_caps_table,
+        struct dvfs_rail *rail, struct dvfs_dfll_data *d);
+int tegra_dvfs_rail_init_clk_switch_thermal_profile(
+        int *clk_switch_trips, struct dvfs_rail *rail);
+int tegra_dvfs_rail_init_thermal_dvfs_trips(
+        int *therm_trips_table, struct dvfs_rail *rail);
+int tegra_dvfs_init_thermal_dvfs_voltages(int *millivolts,
+        int *peak_millivolts, int freqs_num, int ranges_num, struct dvfs *d);
+int tegra_dvfs_rail_dfll_mode_set_cold(struct dvfs_rail *rail,
+                                       struct clk *dfll_clk);
+int tegra_dvfs_rail_get_thermal_floor(struct dvfs_rail *rail);
+void tegra_dvfs_rail_register_vmax_cdev(struct dvfs_rail *rail);
+
+#ifdef CONFIG_TEGRA_VDD_CORE_OVERRIDE
+int tegra_dvfs_resolve_override(struct clk *c, unsigned long max_rate);
+int tegra_dvfs_rail_get_override_floor(struct dvfs_rail *rail);
+#else
+static inline int tegra_dvfs_resolve_override(struct clk *c, unsigned long rate)
+{ return 0; }
+static inline int tegra_dvfs_rail_get_override_floor(struct dvfs_rail *rail)
+{ return 0; }
+#endif
+
+static inline int tegra_dvfs_rail_disable_prepare(struct dvfs_rail *rail)
+{ return 0; }
+static inline int tegra_dvfs_rail_post_enable(struct dvfs_rail *rail)
+{ return 0; }
+
+bool tegra_dvfs_is_dfll_bypass(void);
+
+static inline bool tegra_dvfs_rail_is_dfll_mode(struct dvfs_rail *rail)
+{
+        return rail ? rail->dfll_mode : false;
+}
+
+static inline void tegra_dvfs_rail_mode_updating(struct dvfs_rail *rail,
+                                                 bool updating)
+{
+        if (rail)
+                rail->dfll_mode_updating = updating;
+}
+
+static inline void tegra_dvfs_set_dfll_tune_trimmers(
+        struct dvfs *d, void (*tune_trimmers)(bool trim_high))
+{
+        if (d->dfll_data.tune_high_min_millivolts)
+                d->dfll_data.tune_trimmers = tune_trimmers;
+}
+
+#endif
diff --git a/include/linux/platform/tegra/emc_bwmgr.h b/include/linux/platform/tegra/emc_bwmgr.h
new file mode 100644
index 000000000..64d6f6f89
--- /dev/null
+++ b/include/linux/platform/tegra/emc_bwmgr.h
@@ -0,0 +1,393 @@
+/**
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __EMC_BWMGR_H
+#define __EMC_BWMGR_H
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/of_address.h>
+#include <linux/platform/tegra/iso_client.h>
+
+/* keep in sync with tegra_bwmgr_client_names */
+enum tegra_bwmgr_client_id {
+        TEGRA_BWMGR_CLIENT_CPU_CLUSTER_0,
+        TEGRA_BWMGR_CLIENT_CPU_CLUSTER_1,
+        TEGRA_BWMGR_CLIENT_CPU_CLUSTER_2,
+        TEGRA_BWMGR_CLIENT_CPU_CLUSTER_3,
+        TEGRA_BWMGR_CLIENT_DISP0,
+        TEGRA_BWMGR_CLIENT_DISP1,
+        TEGRA_BWMGR_CLIENT_DISP2,
+        TEGRA_BWMGR_CLIENT_DISP1_LA_EMC,
+        TEGRA_BWMGR_CLIENT_DISP2_LA_EMC,
+        TEGRA_BWMGR_CLIENT_USBD,
+        TEGRA_BWMGR_CLIENT_XHCI,
+        TEGRA_BWMGR_CLIENT_SDMMC1,
+        TEGRA_BWMGR_CLIENT_SDMMC2,
+        TEGRA_BWMGR_CLIENT_SDMMC3,
+        TEGRA_BWMGR_CLIENT_SDMMC4,
+        TEGRA_BWMGR_CLIENT_MON,
+        TEGRA_BWMGR_CLIENT_GPU,
+        TEGRA_BWMGR_CLIENT_MSENC,
+        TEGRA_BWMGR_CLIENT_NVENC1,
+        TEGRA_BWMGR_CLIENT_NVJPG,
+        TEGRA_BWMGR_CLIENT_NVDEC,
+        TEGRA_BWMGR_CLIENT_NVDEC1,
+        TEGRA_BWMGR_CLIENT_TSEC,
+        TEGRA_BWMGR_CLIENT_TSECB,
+        TEGRA_BWMGR_CLIENT_VI,
+        TEGRA_BWMGR_CLIENT_ISPA,
+        TEGRA_BWMGR_CLIENT_ISPB,
+        TEGRA_BWMGR_CLIENT_CAMERA,
+        TEGRA_BWMGR_CLIENT_CAMERA_NON_ISO,
+        TEGRA_BWMGR_CLIENT_ISOMGR,
+        TEGRA_BWMGR_CLIENT_THERMAL_CAP,
+        TEGRA_BWMGR_CLIENT_VIC,
+        TEGRA_BWMGR_CLIENT_APE_ADSP,
+        TEGRA_BWMGR_CLIENT_APE_ADMA,
+        TEGRA_BWMGR_CLIENT_PCIE,
+        TEGRA_BWMGR_CLIENT_PCIE_1,
+        TEGRA_BWMGR_CLIENT_PCIE_2,
+        TEGRA_BWMGR_CLIENT_PCIE_3,
+        TEGRA_BWMGR_CLIENT_PCIE_4,
+        TEGRA_BWMGR_CLIENT_PCIE_5,
+        TEGRA_BWMGR_CLIENT_BBC_0,
+        TEGRA_BWMGR_CLIENT_EQOS,
+        TEGRA_BWMGR_CLIENT_SE0,
+        TEGRA_BWMGR_CLIENT_SE1,
+        TEGRA_BWMGR_CLIENT_SE2,
+        TEGRA_BWMGR_CLIENT_SE3,
+        TEGRA_BWMGR_CLIENT_SE4,
+        TEGRA_BWMGR_CLIENT_PMQOS,
+        TEGRA_BWMGR_CLIENT_NVPMODEL,
+        TEGRA_BWMGR_CLIENT_DEBUG,
+        TEGRA_BWMGR_CLIENT_COUNT /* Should always be last */
+};
+
+enum tegra_bwmgr_request_type {
+        TEGRA_BWMGR_SET_EMC_FLOOR, /* lower bound */
+        TEGRA_BWMGR_SET_EMC_CAP, /* upper bound */
+        TEGRA_BWMGR_SET_EMC_ISO_CAP, /* upper bound that affects ISO Bw */
+        TEGRA_BWMGR_SET_EMC_SHARED_BW, /* shared bw request */
+        TEGRA_BWMGR_SET_EMC_SHARED_BW_ISO, /* for use by ISO Mgr only */
+        TEGRA_BWMGR_SET_EMC_REQ_COUNT /* Should always be last */
+};
+
+enum bwmgr_dram_types {
+        DRAM_TYPE_NONE,
+        DRAM_TYPE_LPDDR4_16CH_ECC,
+        DRAM_TYPE_LPDDR4_8CH_ECC,
+        DRAM_TYPE_LPDDR4_4CH_ECC,
+        DRAM_TYPE_LPDDR4_2CH_ECC,
+        DRAM_TYPE_LPDDR4_16CH,
+        DRAM_TYPE_LPDDR4_8CH,
+        DRAM_TYPE_LPDDR4_4CH,
+        DRAM_TYPE_LPDDR4_2CH,
+        DRAM_TYPE_LPDDR3_2CH,
+        DRAM_TYPE_DDR3_2CH
+};
+
+extern u8 bwmgr_dram_efficiency;
+extern u8 bwmgr_dram_num_channels;
+/* flag to determine supported memory and channel configuration */
+extern u8 bwmgr_dram_config_supported;
+extern u32 *bwmgr_dram_iso_eff_table;
+extern u32 *bwmgr_dram_noniso_eff_table;
+extern u32 *bwmgr_max_nvdis_bw_reqd;
+extern u32 *bwmgr_max_vi_bw_reqd;
+extern int *bwmgr_slope;
+extern u32 *bwmgr_vi_bw_reqd_offset;
+extern int bwmgr_iso_bw_percentage;
+extern enum bwmgr_dram_types bwmgr_dram_type;
+extern int emc_to_dram_freq_factor;
+
+struct tegra_bwmgr_client;
+
+struct bwmgr_ops {
+        unsigned long (*freq_to_bw)(unsigned long freq);
+        unsigned long (*bw_to_freq)(unsigned long bw);
+        u32 (*dvfs_latency)(u32 ufreq);
+        unsigned long (*bwmgr_apply_efficiency)(
+                unsigned long total_bw, unsigned long iso_bw,
+                unsigned long max_rate, u64 usage_flags,
+                unsigned long *iso_bw_min, unsigned long iso_bw_nvdis,
+                unsigned long iso_bw_vi);
+        unsigned long (*get_best_iso_freq)(long iso_bw,
+                long iso_bw_nvdis, long iso_bw_vi);
+        void (*update_efficiency)(unsigned long dram_refresh_rate);
+        u32 (*get_max_iso_bw)(enum tegra_iso_client client);
+};
+
+struct bwmgr_ops *bwmgr_eff_init_t21x(void);
+struct bwmgr_ops *bwmgr_eff_init_t18x(void);
+struct bwmgr_ops *bwmgr_eff_init_t19x(void);
+
+#if defined(CONFIG_TEGRA_BWMGR)
+/**
+ * tegra_bwmgr_register - register an EMC Bandwidth Manager client.
+ *                        Also see tegra_bwmgr_unregister().
+ * @client      client id from tegra_bwmgr_client_id
+ *
+ * Returns a valid handle on successful registration, NULL on error.
+ */
+struct tegra_bwmgr_client *tegra_bwmgr_register(
+                enum tegra_bwmgr_client_id client);
+
+/**
+ * tegra_bwmgr_unregister - unregister an EMC Bandwidth Manager client.
+ *                          Callers should match register/unregister calls.
+ *                          Persistence of old requests across
+ *                          register/unregister calls is undefined.
+ *                          Also see tegra_bwmgr_set_emc()
+ *
+ * @handle      handle acquired during tegra_bwmgr_register
+ */
+void tegra_bwmgr_unregister(struct tegra_bwmgr_client *handle);
+
+/**
+ * tegra_bwmgr_get_dram_num_channels - get the number of DRAM channels
+ *
+ * Returns the number of DRAM channels that are configured on the underlying
+ * platform.
+ */
+u8 tegra_bwmgr_get_dram_num_channels(void);
+
+/**
+ * tegra_bwmgr_get_emc_rate - get the current EMC rate.
+ *
+ * Returns current memory clock rate in Hz.
+ */
+unsigned long tegra_bwmgr_get_emc_rate(void);
+
+/**
+ * tegra_bwmgr_get_max_emc_rate - get the max EMC rate.
+ *
+ * Returns the max memory clock rate in Hz.
+ */
+unsigned long tegra_bwmgr_get_max_emc_rate(void);
+
+/**
+ * tegra_bwmgr_get_core_emc_rate - get the actual emc frequency calculated
+ *                      using the dram frequency and emc_to_dram
+ *                      conversion factor.
+ *
+ * Returns the core emc rate in Hz.
+ */
+unsigned long tegra_bwmgr_get_core_emc_rate(void);
+
+/**
+ * tegra_bwmgr_round_rate - round up to next EMC rate which can be provided
+ *
+ * @bw          Input rate
+ *
+ * Returns the next higher rate from the Input rate that EMC can run at.
+ */
+unsigned long tegra_bwmgr_round_rate(unsigned long bw);
+
+/**
+ * tegra_bwmgr_set_emc - request to bwmgr to set an EMC rate parameter.
+ *                       Actual clock rate depends on aggregation of
+ *                       requests by all clients. If needed, use
+ *                       tegra_bwmgr_get_emc_rate() to get the rate after
+ *                       a tegra_bwmgr_set_emc() call.
+ *
+ *                       Call tegra_bwmgr_set_emc() with same request type and
+ *                       val = 0 to clear request.
+ *
+ * @handle      handle acquired during tegra_bwmgr_register
+ * @val         value to be set in Hz, 0 to clear old request of the same type
+ * @req         chosen type from tegra_bwmgr_request_type
+ *
+ * Returns success (0) or negative errno.
+ */
+int tegra_bwmgr_set_emc(struct tegra_bwmgr_client *handle, unsigned long val,
+                enum tegra_bwmgr_request_type req);
+
+/**
+ * tegra_bwmgr_get_client_info - outputs the value previously set with
+ *                       tegra_bwmgr_set_emc or 0 if no value has been set.
+ *
+ * @handle      handle acquired during tegra_bwmgr_register
+ * @out_val     bandwidth value in Hz
+ * @req         chosen type from tegra_bwmgr_request_type
+ *
+ * Returns success (0) or negative errno.
+ */
+int tegra_bwmgr_get_client_info(struct tegra_bwmgr_client *handle,
+                unsigned long *out_val,
+                enum tegra_bwmgr_request_type req);
+
+/**
+ * tegra_bwmgr_notifier_register - register a notifier callback when
+ *              emc rate changes. Must be called from non-atomic
+ *              context. The callback must not call any bwmgr API.
+ * @nb          linux notifier block
+ *
+ * Returns success (0) or negative errno.
+ */
+int tegra_bwmgr_notifier_register(struct notifier_block *nb);
+
+/**
+ * tegra_bwmgr_notifier_unregister - unregister a notifier callback.
+ * @nb          linux notifier block
+ *
+ * Returns success (0) or negative errno.
+ */
+int tegra_bwmgr_notifier_unregister(struct notifier_block *nb);
+
+/*
+ * Initialize bwmgr.
+ * This api would be called by .init_machine during boot.
+ * bwmgr clients, don't call this api.
+ */
+int __init bwmgr_init(void);
+
+void __exit bwmgr_exit(void);
+
+/*
+ * Initialize pmqos bwmgr code which registers pmqos as bwmgr client and
+ * registers a notifier which gets called on update to PMQOS_EMC_FREQ_MIN.
+ */
+int __init pmqos_bwmgr_init(void);
+
+#else /* CONFIG_TEGRA_BWMGR */
+
+static inline struct tegra_bwmgr_client *tegra_bwmgr_register(
+                enum tegra_bwmgr_client_id client_id)
+{
+        static int i;
+        /* return a dummy handle to allow client to function
+         * as if bwmgr were enabled.
+         */
+        return (struct tegra_bwmgr_client *) &i;
+}
+
+static inline void tegra_bwmgr_unregister(struct tegra_bwmgr_client *handle) {}
+
+static inline int bwmgr_init(void)
+{
+        return 0;
+}
+
+static inline void bwmgr_exit(void) {}
+
+static inline u8 tegra_bwmgr_get_dram_num_channels(void)
+{
+        return 0;
+}
+
+static inline unsigned long tegra_bwmgr_get_emc_rate(void)
+{
+        static struct clk *bwmgr_emc_clk;
+        struct device_node *dn;
+
+        if (!bwmgr_emc_clk) {
+                dn = of_find_compatible_node(NULL, NULL, "nvidia,bwmgr");
+                if (dn == NULL) {
+                        pr_err("bwmgr: dt node not found.\n");
+                        return 0;
+                }
+
+                bwmgr_emc_clk = of_clk_get(dn, 0);
+                if (IS_ERR_OR_NULL(bwmgr_emc_clk)) {
+                        pr_err("bwmgr: couldn't find emc clock.\n");
+                        bwmgr_emc_clk = NULL;
+                        WARN_ON(true);
+                        return 0;
+                }
+        }
+
+        return clk_get_rate(bwmgr_emc_clk);
+}
+
+static inline unsigned long tegra_bwmgr_get_max_emc_rate(void)
+{
+        static struct clk *bwmgr_emc_clk;
+        struct device_node *dn;
+
+        if (!bwmgr_emc_clk) {
+                dn = of_find_compatible_node(NULL, NULL, "nvidia,bwmgr");
+                if (dn == NULL) {
+                        pr_err("bwmgr: dt node not found.\n");
+                        return 0;
+                }
+
+                bwmgr_emc_clk = of_clk_get(dn, 0);
+                if (IS_ERR_OR_NULL(bwmgr_emc_clk)) {
+                        pr_err("bwmgr: couldn't find emc clock.\n");
+                        bwmgr_emc_clk = NULL;
+                        WARN_ON(true);
+                        return 0;
+                }
+        }
+
+        /* Use LONG_MAX as clk_round_rate treats rate argument as signed */
+        return clk_round_rate(bwmgr_emc_clk, LONG_MAX);
+}
+
+static inline unsigned long tegra_bwmgr_get_core_emc_rate(void)
+{
+        return 0;
+}
+static inline unsigned long tegra_bwmgr_round_rate(unsigned long bw)
+{
+        static struct clk *bwmgr_emc_clk;
+        struct device_node *dn;
+
+        if (!bwmgr_emc_clk) {
+                dn = of_find_compatible_node(NULL, NULL, "nvidia,bwmgr");
+                if (dn == NULL) {
+                        pr_err("bwmgr: dt node not found.\n");
+                        return 0;
+                }
+
+                bwmgr_emc_clk = of_clk_get(dn, 0);
+                if (IS_ERR_OR_NULL(bwmgr_emc_clk)) {
+                        pr_err("bwmgr: couldn't find emc clock.\n");
+                        bwmgr_emc_clk = NULL;
+                        WARN_ON(true);
+                        return 0;
+                }
+        }
+
+        return clk_round_rate(bwmgr_emc_clk, bw);
+}
+
+static inline int tegra_bwmgr_set_emc(struct tegra_bwmgr_client *handle,
+                unsigned long val, enum tegra_bwmgr_request_type req)
+{
+        return 0;
+}
+
+static inline int tegra_bwmgr_get_client_info(struct tegra_bwmgr_client *handle,
+                unsigned long *out_val,
+                enum tegra_bwmgr_request_type req)
+{
+        if (!out_val)
+                return -EINVAL;
+        *out_val = 0;
+        return 0;
+}
+
+static inline int tegra_bwmgr_notifier_register(struct notifier_block *nb)
+{
+        return 0;
+}
+
+static inline int tegra_bwmgr_notifier_unregister(struct notifier_block *nb)
+{
+        return 0;
+}
+
+#endif /* CONFIG_TEGRA_BWMGR */
+#endif /* __EMC_BWMGR_H */
diff --git a/include/linux/platform/tegra/iso_client.h b/include/linux/platform/tegra/iso_client.h
new file mode 100644
index 000000000..d88ee6d92
--- /dev/null
+++ b/include/linux/platform/tegra/iso_client.h
@@ -0,0 +1,33 @@
+/*
+ *
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _INCLUDE_MACH_ISO_CLIENT_H
+#define _INCLUDE_MACH_ISO_CLIENT_H
+
+enum tegra_iso_client {
+        TEGRA_ISO_CLIENT_DISP_0,
+        TEGRA_ISO_CLIENT_DISP_1,
+        TEGRA_ISO_CLIENT_DISP_2,
+        TEGRA_ISO_CLIENT_VI_0,
+        TEGRA_ISO_CLIENT_VI_1,
+        TEGRA_ISO_CLIENT_ISP_A,
+        TEGRA_ISO_CLIENT_ISP_B,
+        TEGRA_ISO_CLIENT_BBC_0,
+        TEGRA_ISO_CLIENT_TEGRA_CAMERA,
+        TEGRA_ISO_CLIENT_APE_ADMA,
+        TEGRA_ISO_CLIENT_EQOS,
+        TEGRA_ISO_CLIENT_COUNT
+};
+
+#endif /* _INCLUDE_MACH_ISO_CLIENT_H */
diff --git a/include/linux/platform/tegra/isomgr.h b/include/linux/platform/tegra/isomgr.h
new file mode 100644
index 000000000..624dbb5ee
--- /dev/null
+++ b/include/linux/platform/tegra/isomgr.h
@@ -0,0 +1,215 @@
+/*
+ * include/mach/isomgr.h
+ *
+ * Copyright (c) 2012-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _INCLUDE_MACH_ISOMGR_H
+#define _INCLUDE_MACH_ISOMGR_H
+
+#include <linux/platform/tegra/emc_bwmgr.h>
+#include <linux/platform/tegra/iso_client.h>
+
+#define ISOMGR_MAGIC  0x150A1C
+
+/* handle to identify registered client */
+#define tegra_isomgr_handle void *
+
+/* callback to client to renegotiate ISO BW allocation */
+typedef void (*tegra_isomgr_renegotiate)(void *priv,
+                                         u32 avail_bw); /* KB/sec */
+
+struct isoclient_info {
+        enum tegra_iso_client client;
+        char *name;
+        char *dev_name;
+        char *emc_clk_name;
+        enum tegra_bwmgr_client_id bwmgr_id;
+};
+
+struct isomgr_client {
+        u32 magic;              /* magic to identify handle */
+        struct kref kref;       /* ref counting */
+        s32 dedi_bw;            /* BW dedicated to this client  (KB/sec) */
+        s32 rsvd_bw;            /* BW reserved for this client  (KB/sec) */
+        s32 real_bw;            /* BW realized for this client  (KB/sec) */
+        s32 lti;                /* Client spec'd Latency Tolerance (usec) */
+        s32 lto;                /* MC calculated Latency Tolerance (usec) */
+        s32 rsvd_mf;            /* reserved minimum freq in support of LT */
+        s32 real_mf;            /* realized minimum freq in support of LT */
+        s32 real_mf_rq;         /* real_mf requested */
+        tegra_isomgr_renegotiate renegotiate;   /* ask client to renegotiate */
+        bool realize;           /* bw realization in progress */
+        s32 sleep_bw;           /* sleeping for realize */
+        s32 margin_bw;          /* BW set aside for this client (KB/sec) */
+        u8 limit_bw_percentage; /* Insufficient HW buffers cause BW to be
+                                 * limited to this percentage of DRAM BW
+                                 */
+        void *priv;             /* client driver's private data */
+        struct completion cmpl; /* so we can sleep waiting for delta BW */
+
+#ifdef CONFIG_COMMON_CLK
+        struct tegra_bwmgr_client *bwmgr_handle;
+#else
+        struct clk *emc_clk;    /* client emc clk for bw */
+#endif
+
+#ifdef CONFIG_TEGRA_ISOMGR_SYSFS
+        struct kobject *client_kobj;
+        struct isomgr_client_attrs {
+                struct kobj_attribute dedi_bw;
+                struct kobj_attribute rsvd_bw;
+                struct kobj_attribute real_bw;
+                struct kobj_attribute lti;
+                struct kobj_attribute lto;
+                struct kobj_attribute rsvd_mf;
+                struct kobj_attribute real_mf;
+                struct kobj_attribute sleep_bw;
+                struct kobj_attribute margin_bw;
+        } client_attrs;
+#endif /* CONFIG_TEGRA_ISOMGR_SYSFS */
+};
+
+struct isomgr {
+        struct mutex lock;              /* to lock ALL isomgr state */
+        struct task_struct *task;       /* check reentrant/mismatched locks */
+
+#ifdef CONFIG_COMMON_CLK
+        struct tegra_bwmgr_client *bwmgr_handle;
+#else
+        struct clk *emc_clk;            /* isomgr emc clock for floor freq */
+#endif
+
+        s32 lt_mf;                      /* min freq to support worst LT */
+        s32 lt_mf_rq;                   /* requested lt_mf */
+        s32 avail_bw;                   /* globally available MC BW */
+        s32 dedi_bw;                    /* total BW 'dedicated' to clients */
+        s32 sleep_bw;                   /* pending bw requirement */
+        u32 max_iso_bw;                 /* max ISO BW MC can accommodate */
+        struct kobject *kobj;           /* for sysfs linkage */
+        struct isomgr_ops *ops;         /* ops structure for isomgr*/
+};
+
+extern struct isoclient_info *isoclient_info;
+/*platform specific flag for requesting max emc floor req for camera client*/
+extern u8 isomgr_camera_max_floor_req;
+extern int isoclients;
+extern bool client_valid[TEGRA_ISO_CLIENT_COUNT];
+extern struct isomgr_client isomgr_clients[TEGRA_ISO_CLIENT_COUNT];
+extern struct isomgr isomgr;
+extern char *cname[];
+
+struct isomgr_ops {
+        void (*isomgr_plat_init)(void);
+        bool (*isomgr_plat_register)(u32 dedi_bw,
+                        enum tegra_iso_client client);
+        void (*isomgr_plat_unregister)(struct isomgr_client *cp);
+        bool (*isomgr_plat_reserve)(struct isomgr_client *cp,
+                        u32 bw, enum tegra_iso_client client);
+        bool (*isomgr_plat_realize)(struct isomgr_client *cp);
+        u32 (*isomgr_max_iso_bw)(enum tegra_iso_client client);
+};
+
+struct isomgr_ops *pre_t19x_isomgr_init(void);
+struct isomgr_ops *t19x_isomgr_init(void);
+
+#if defined(CONFIG_TEGRA_ISOMGR)
+/* Register an ISO BW client */
+tegra_isomgr_handle tegra_isomgr_register(enum tegra_iso_client client,
+                                          u32 dedicated_bw,     /* KB/sec */
+                                          tegra_isomgr_renegotiate renegotiate,
+                                          void *priv);
+
+/* Unregister an ISO BW client */
+void tegra_isomgr_unregister(tegra_isomgr_handle handle);
+
+/* Reserve ISO BW on behalf of client - don't apply, rval is dvfs thresh usec */
+u32 tegra_isomgr_reserve(tegra_isomgr_handle handle,
+                         u32 bw,        /* KB/sec */
+                         u32 lt);       /* usec */
+
+/* Realize client reservation - apply settings, rval is dvfs thresh usec */
+u32 tegra_isomgr_realize(tegra_isomgr_handle handle);
+
+/* This sets bw aside for the client specified. */
+int tegra_isomgr_set_margin(enum tegra_iso_client client, u32 bw, bool wait);
+
+int tegra_isomgr_get_imp_time(enum tegra_iso_client, u32 bw);
+
+/* returns available in iso bw in KB/sec */
+u32 tegra_isomgr_get_available_iso_bw(void);
+
+/* returns total iso bw in KB/sec */
+u32 tegra_isomgr_get_total_iso_bw(enum tegra_iso_client client);
+
+/* Initialize isomgr.
+ * This api would be called by .init_machine during boot.
+ * isomgr clients, don't call this api.
+ */
+int __init isomgr_init(void);
+#else
+static inline tegra_isomgr_handle tegra_isomgr_register(
+                                          enum tegra_iso_client client,
+                                          u32 dedicated_bw,
+                                          tegra_isomgr_renegotiate renegotiate,
+                                          void *priv)
+{
+        /* return a dummy handle to allow client function
+         * as if isomgr were enabled.
+         */
+        return (tegra_isomgr_handle)1;
+}
+
+static inline void tegra_isomgr_unregister(tegra_isomgr_handle handle) {}
+
+static inline u32 tegra_isomgr_reserve(tegra_isomgr_handle handle,
+                         u32 bw, u32 lt)
+{
+        return 1;
+}
+
+static inline u32 tegra_isomgr_realize(tegra_isomgr_handle handle)
+{
+        return 1;
+}
+
+static inline int tegra_isomgr_set_margin(enum tegra_iso_client client, u32 bw)
+{
+        return 0;
+}
+
+static inline int tegra_isomgr_get_imp_time(enum tegra_iso_client client,
+        u32 bw)
+{
+        return 0;
+}
+
+static inline u32 tegra_isomgr_get_available_iso_bw(void)
+{
+        return UINT_MAX;
+}
+
+static inline u32 tegra_isomgr_get_total_iso_bw(enum tegra_iso_client client)
+{
+        return UINT_MAX;
+}
+
+static inline int isomgr_init(void)
+{
+        return 0;
+}
+#endif
+#endif /* _INCLUDE_MACH_ISOMGR_H */
diff --git a/include/linux/platform/tegra/mcerr.h b/include/linux/platform/tegra/mcerr.h
new file mode 100644
index 000000000..4a83dae11
--- /dev/null
+++ b/include/linux/platform/tegra/mcerr.h
@@ -0,0 +1,176 @@
+/*
+ * MC error interrupt handling header file. Various defines and declarations
+ * across tegra chips.
+ *
+ * Copyright (c) 2010-2018, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MCERR_H
+#define __MCERR_H
+
+#include <linux/kernel.h>
+#include <linux/debugfs.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+
+#include <linux/platform/tegra/mc.h>
+
+#define MAX_PRINTS                      5
+
+/* defines that are common across SOC's. */
+#define MC_INTMASK                      0x4
+
+#define MC_ERR_STATUS_WRITE             (1 << 16)
+#define MC_ERR_STATUS_SECURE            (1 << 17)
+#define MC_ERR_STATUS_ADR_HI            (3 << 20)
+
+#define MC_INT_DECERR_EMEM                      (1<<6)
+#define MC_INT_SECURITY_VIOLATION               (1<<8)
+#define MC_INT_ARBITRATION_EMEM                 (1<<9)
+#define MC_INT_DECERR_VPR                       (1<<12)
+#define MC_INT_SECERR_SEC                       (1<<13)
+#define MC_INT_DECERR_GENERALIZED_CARVEOUT      (1<<17)
+
+#define MC_ERR_DECERR_EMEM              (2)
+#define MC_ERR_SECURITY_TRUSTZONE       (3)
+#define MC_ERR_SECURITY_CARVEOUT        (4)
+#define MC_ERR_INVALID_SMMU_PAGE        (6)
+
+struct platform_device;
+int tegra_mcerr_init(struct dentry *mc_paren, struct platform_device *pdev);
+irqreturn_t tegra_mc_handle_general_fault(int src_chan, int intstatus);
+
+/*
+ * This describes errors that can be generated by the MC. One is defined for
+ * each possibility.
+ *
+ * @sig Interrupt signiture for the error.
+ * @msg Error description.
+ * @flags Relevant flags for the error.
+ * @stat_reg Register offset that holds the status of the error.
+ * @addr_reg Register offset that holds the faulting address.
+ */
+struct mc_error {
+        const char *msg;
+        u32         sig;
+        int         flags;
+        u32         stat_reg;
+        u32         addr_reg;
+        u32         addr_hi_reg;
+};
+
+#define E_SMMU       (1<<0)
+#define E_NO_STATUS  (1<<1) /* No status/addr */
+#define E_TWO_STATUS (1<<2) /* Two status registers, no addr */
+#define E_VPR        (1<<3) /* VPR violation */
+#define E_ADR_HI_REG (1<<4) /* Hi Addr bits in hi reg */
+#define E_GSC        (1<<5) /* GSC violation */
+
+extern u32 mc_int_mask;
+extern u32  mcerr_silenced;
+
+struct mcerr_ops {
+        /*
+         * Show the statistics for each client. This is called from a debugfs
+         * context - that means you can sleep and do general kernel stuff here.
+         */
+        int (*mcerr_debugfs_show)(struct seq_file *s, void *v);
+
+        /* Disable MC Error interrupt.
+         *
+         * Called in hard irq context to disable interrupt till
+         * soft irq handler logs the MC Error.
+         */
+        void (*disable_interrupt)(unsigned int irq);
+
+        /* Enable MC Error interrupt.
+         *
+         * Called from soft irq context after MC Error is logged.
+         */
+        void (*enable_interrupt)(unsigned int irq);
+
+        /* Clear MC Error interrupt.
+         *
+         * Called from soft irq context during MC Error print throttle.
+         */
+        void (*clear_interrupt)(unsigned int irq);
+
+        /* Log MC Error fault and clear interrupt source
+         *
+         * Called in soft irq context.
+         * As soon as interrupt status is cleared MC would be ready to
+         * hold next MC Error info.
+         */
+        void (*log_mcerr_fault)(unsigned int irq);
+
+        /* Numeric fields that must be set by the different chips. */
+        unsigned int nr_clients;
+
+        /*
+         * This array lists a string description of each valid interrupt bit.
+         * It must be at least 32 entries long. Entries that are not valid
+         * interrupts should be left as NULL. Each entry should be at most 12
+         * characters long.
+         */
+        const char **intr_descriptions;
+        struct mc_client *mc_clients;
+};
+
+#define client(_swgroup, _name, _swgid)                                 \
+        { .swgroup = _swgroup, .name = _name, .swgid = TEGRA_SWGROUP_##_swgid, }
+
+#define dummy_client   client("dummy", "dummy", INVALID)
+
+#define MC_ERR(_sig, _msg, _flags, _stat_reg, _addr_reg)                \
+        { .sig = _sig, .msg = _msg, .flags = _flags,                    \
+                        .stat_reg = _stat_reg, .addr_reg = _addr_reg }
+
+#define MC_ERR_HI(_sig, _msg, _flags, _stat_reg, _addr_reg, _addr_hi_reg) \
+        { .sig = _sig, .msg = _msg, .flags = (_flags | E_ADR_HI_REG), \
+          .stat_reg = _stat_reg, .addr_reg = _addr_reg, \
+          .addr_hi_reg = _addr_hi_reg}
+
+#define MC_ERR_GSC(_sig, _msg, _flags, _stat_reg, _addr_reg, _addr_hi_reg) \
+        { .sig = _sig, .msg = _msg, .flags = (_flags | E_GSC), \
+          .stat_reg = _stat_reg, .addr_reg = _addr_reg, \
+          .addr_hi_reg = _addr_hi_reg}
+
+#define mcerr_pr(fmt, ...)                                      \
+        do {                                                    \
+                if (!mcerr_silenced) {                          \
+                        trace_printk(fmt, ##__VA_ARGS__);       \
+                        pr_err(fmt, ##__VA_ARGS__);             \
+                }                                               \
+        } while (0)
+
+/*
+ * Error MMA tracking.
+ */
+#define MMA_HISTORY_SAMPLES 20
+struct arb_emem_intr_info {
+        int arb_intr_mma;
+        u64 time;
+        spinlock_t lock;
+};
+
+typedef struct mcerr_ops *(*of_mcerr_init_fn)(struct device_node *);
+
+#define MCERR_OF_DECLARE(name, compat, fn) \
+        _OF_DECLARE(mcerr, name, compat, fn, of_mcerr_init_fn)
+
+#endif /* __MCERR_H */
diff --git a/include/linux/platform/tegra/reset.h b/include/linux/platform/tegra/reset.h
new file mode 100644
index 000000000..9494f000d
--- /dev/null
+++ b/include/linux/platform/tegra/reset.h
@@ -0,0 +1,115 @@
+/*
+ * include/linux/platform/reset.h
+ *
+ * CPU reset dispatcher.
+ *
+ * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TEGRA_RESET_H
+#define __MACH_TEGRA_RESET_H
+
+#define TEGRA_RESET_MASK_PRESENT        0
+#define TEGRA_RESET_MASK_LP1            1
+#define TEGRA_RESET_MASK_LP2            2
+#define TEGRA_RESET_STARTUP_SECONDARY   3
+#define TEGRA_RESET_STARTUP_LP2         4
+#define TEGRA_RESET_STARTUP_LP1         5
+#define TEGRA_RESET_C0_L2_TAG_LATENCY   6
+#define TEGRA_RESET_C0_L2_DATA_LATENCY  7
+#define TEGRA_RESET_C1_L2_TAG_LATENCY   8
+#define TEGRA_RESET_C1_L2_DATA_LATENCY  9
+#define TEGRA_RESET_MASK_MC_CLK         10
+#define TEGRA_RESET_SECURE_FW_PRESENT   11
+#define TEGRA_RESET_DATA_SIZE           12
+
+#ifdef CONFIG_ARM64
+#define RESET_DATA(x)   ((TEGRA_RESET_##x)*8)
+#else
+#define RESET_DATA(x)   ((TEGRA_RESET_##x)*4)
+#endif
+
+#ifndef __ASSEMBLY__
+
+#include <linux/cpumask.h>
+
+extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
+
+void __tegra_cpu_reset_handler_start(void);
+void __tegra_cpu_reset_handler(void);
+void __tegra_cpu_reset_handler_end(void);
+void tegra_secondary_startup(void);
+
+#ifdef CONFIG_PM_SLEEP
+#define tegra_cpu_lp1_mask ((unsigned long *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
+                ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
+                 (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_mc_clk_mask ((unsigned long *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
+                ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_MC_CLK] - \
+                 (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_cpu_reset_handler_ptr ((u32 *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
+                ((ulong)__tegra_cpu_reset_handler_data - \
+                 (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_cpu_lp2_mask ((cpumask_t *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE + \
+                ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
+                 (ulong)__tegra_cpu_reset_handler_start))))
+#endif
+
+#define tegra_cpu_c0_l2_tag_latency \
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_TAG_LATENCY]
+
+#define tegra_cpu_c0_l2_tag_latency_iram \
+        ((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE +                        \
+        ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_TAG_LATENCY] \
+         - (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_cpu_c0_l2_data_latency \
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_DATA_LATENCY]
+
+#define tegra_cpu_c0_l2_data_latency_iram \
+        ((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE +                        \
+        ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C0_L2_DATA_LATENCY] \
+         - (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_cpu_c1_l2_tag_latency \
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_TAG_LATENCY]
+
+#define tegra_cpu_c1_l2_tag_latency_iram \
+        ((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE +                        \
+        ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_TAG_LATENCY] \
+         - (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_cpu_c1_l2_data_latency \
+        __tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_DATA_LATENCY]
+
+#define tegra_cpu_c1_l2_data_latency_iram \
+        ((ulong *)(IO_ADDRESS(TEGRA_RESET_HANDLER_BASE +                        \
+        ((ulong)&__tegra_cpu_reset_handler_data[TEGRA_RESET_C1_L2_DATA_LATENCY] \
+         - (ulong)__tegra_cpu_reset_handler_start))))
+
+#define tegra_cpu_reset_handler_offset \
+                ((ulong)__tegra_cpu_reset_handler - \
+                 (ulong)__tegra_cpu_reset_handler_start)
+
+#define tegra_cpu_reset_handler_size \
+                (__tegra_cpu_reset_handler_end - \
+                 __tegra_cpu_reset_handler_start)
+
+#ifdef CONFIG_PM_SLEEP
+void tegra_cpu_reset_handler_save(void);
+void tegra_cpu_reset_handler_restore(void);
+#endif
+#endif
+#endif
diff --git a/include/linux/platform/tegra/tegra12_emc.h b/include/linux/platform/tegra/tegra12_emc.h
new file mode 100644
index 000000000..c32bdf217
--- /dev/null
+++ b/include/linux/platform/tegra/tegra12_emc.h
@@ -0,0 +1,574 @@
+/*
+ * include/linux/platform/tegra12_emc.h
+ *
+ * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_TEGRA12_EMC_H
+#define _MACH_TEGRA_TEGRA12_EMC_H
+
+#include <linux/platform/tegra/tegra_emc.h>
+#include <linux/platform_data/tegra_emc_pdata.h>
+
+int tegra12_emc_init(void);
+
+enum {
+        DRAM_DEV_SEL_ALL = 0,
+        DRAM_DEV_SEL_0   = (2 << 30),
+        DRAM_DEV_SEL_1   = (1 << 30),
+};
+
+void tegra12_mc_holdoff_enable(void);
+
+#define DRAM_BROADCAST(num)                     \
+        (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
+
+#define EMC_INTSTATUS                           0x0
+#define EMC_INTSTATUS_CLKCHANGE_COMPLETE        (0x1 << 4)
+
+#define EMC_DBG                                 0x8
+#define EMC_DBG_WRITE_MUX_ACTIVE                (0x1 << 1)
+
+#define EMC_CFG                                 0xc
+#define EMC_CFG_DRAM_CLKSTOP_PD         (0x1 << 31)
+#define EMC_CFG_DRAM_CLKSTOP_SR         (0x1 << 30)
+#define EMC_CFG_DRAM_ACPD                       (0x1 << 29)
+#define EMC_CFG_DYN_SREF                        (0x1 << 28)
+#define EMC_CFG_PWR_MASK                        ((0xF << 28) | (0x1 << 18))
+#define EMC_CFG_REQACT_ASYNC            (0x1 << 26)
+#define EMC_CFG_AUTO_PRE_WR                     (0x1 << 25)
+#define EMC_CFG_AUTO_PRE_RD                     (0x1 << 24)
+#define EMC_CFG_MAM_PRE_WR                      (0x1 << 23)
+#define EMC_CFG_MAN_PRE_RD                      (0x1 << 22)
+#define EMC_CFG_PERIODIC_QRST                   (0x1 << 21)
+#define EMC_CFG_EN_DYNAMIC_PUTERM               (0x1 << 20)
+#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK            (0x1 << 19)
+#define EMC_CFG_DSR_VTTGEN_DRV_EN               (0x1 << 18)
+#define EMC_CFG_EMC2MC_CLK_RATIO                (0x3 << 16)
+#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC      (0x1 << 9)
+#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC        (0x1 << 8)
+#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC       (0x1 << 7)
+#define EMC_CFG_INVERT_DQM                      (0x1 << 6)
+#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC (0x1 << 5)
+#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC (0x1 << 4)
+#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2 (0x1 << 3)
+#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1 (0x1 << 2)
+#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE  (0x1 << 1)
+
+
+#define EMC_ADR_CFG                             0x10
+#define EMC_REFCTRL                             0x20
+#define EMC_REFCTRL_DEV_SEL_SHIFT               0
+#define EMC_REFCTRL_DEV_SEL_MASK                \
+        (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
+#define EMC_REFCTRL_ENABLE                      (0x1 << 31)
+#define EMC_REFCTRL_ENABLE_ALL(num)             \
+        (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT) \
+         | EMC_REFCTRL_ENABLE)
+#define EMC_REFCTRL_DISABLE_ALL(num)            \
+        ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
+
+#define EMC_TIMING_CONTROL                      0x28
+#define EMC_RC                                  0x2c
+#define EMC_RFC                                 0x30
+#define EMC_RAS                                 0x34
+#define EMC_RP                                  0x38
+#define EMC_R2W                                 0x3c
+#define EMC_W2R                                 0x40
+#define EMC_R2P                                 0x44
+#define EMC_W2P                                 0x48
+#define EMC_RD_RCD                              0x4c
+#define EMC_WR_RCD                              0x50
+#define EMC_RRD                                 0x54
+#define EMC_REXT                                0x58
+#define EMC_WDV                                 0x5c
+#define EMC_QUSE                                0x60
+#define EMC_QRST                                0x64
+#define EMC_QSAFE                               0x68
+#define EMC_RDV                                 0x6c
+#define EMC_REFRESH                             0x70
+#define EMC_BURST_REFRESH_NUM                   0x74
+#define EMC_PDEX2WR                             0x78
+#define EMC_PDEX2RD                             0x7c
+#define EMC_PCHG2PDEN                           0x80
+#define EMC_ACT2PDEN                            0x84
+#define EMC_AR2PDEN                             0x88
+#define EMC_RW2PDEN                             0x8c
+#define EMC_TXSR                                0x90
+#define EMC_TCKE                                0x94
+#define EMC_TFAW                                0x98
+#define EMC_TRPAB                               0x9c
+#define EMC_TCLKSTABLE                          0xa0
+#define EMC_TCLKSTOP                            0xa4
+#define EMC_TREFBW                              0xa8
+#define EMC_ODT_WRITE                           0xb0
+#define EMC_ODT_READ                            0xb4
+#define EMC_WEXT                                0xb8
+#define EMC_CTT                                 0xbc
+#define EMC_RFC_SLR                             0xc0
+#define EMC_MRS_WAIT_CNT2                       0xc4
+
+#define EMC_MRS_WAIT_CNT                        0xc8
+#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT       0
+#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK        \
+        (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
+#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT        16
+#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK         \
+        (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
+
+#define EMC_MRS                                 0xcc
+#define EMC_MODE_SET_DLL_RESET                  (0x1 << 8)
+#define EMC_MODE_SET_LONG_CNT                   (0x1 << 26)
+#define EMC_EMRS                                0xd0
+#define EMC_REF                                 0xd4
+#define EMC_REF_FORCE_CMD                       1
+#define EMC_PRE                                 0xd8
+#define EMC_NOP                                 0xdc
+
+#define EMC_SELF_REF                            0xe0
+#define EMC_SELF_REF_CMD_ENABLED                (0x1 << 0)
+#define EMC_SELF_REF_DEV_SEL_SHIFT              30
+#define EMC_SELF_REF_DEV_SEL_MASK               \
+        (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
+
+#define EMC_DPD                                 0xe4
+#define EMC_MRW                                 0xe8
+
+#define EMC_MRR                                 0xec
+#define EMC_MRR_DEV_SEL_SHIFT                   30
+#define EMC_MRR_DEV_SEL_MASK                    \
+        (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
+#define EMC_MRR_MA_SHIFT                        16
+#define EMC_MRR_MA_MASK                         (0xFF << EMC_MRR_MA_SHIFT)
+#define EMC_MRR_DATA_MASK                       ((0x1 << EMC_MRR_MA_SHIFT) - 1)
+#define LPDDR2_MR4_TEMP_SHIFT                   0
+#define LPDDR2_MR4_TEMP_MASK                    (0x7 << LPDDR2_MR4_TEMP_SHIFT)
+
+#define EMC_CMDQ                                0xf0
+#define EMC_MC2EMCQ                             0xf4
+#define EMC_XM2DQSPADCTRL3                      0xf8
+#define EMC_XM2DQSPADCTRL3_VREF_ENABLE          (0x1 << 5)
+#define EMC_FBIO_SPARE                          0x100
+
+#define EMC_FBIO_CFG5                           0x104
+#define EMC_CFG5_TYPE_SHIFT                     0x0
+#define EMC_CFG5_TYPE_MASK                      (0x3 << EMC_CFG5_TYPE_SHIFT)
+#define EMC_CFG5_QUSE_MODE_SHIFT                13
+#define EMC_CFG5_QUSE_MODE_MASK                 \
+        (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
+enum {
+        EMC_CFG5_QUSE_MODE_NORMAL = 0,
+        EMC_CFG5_QUSE_MODE_ALWAYS_ON,
+        EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
+        EMC_CFG5_QUSE_MODE_PULSE_INTERN,
+        EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
+        EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
+};
+
+#define EMC_FBIO_WRPTR_EQ_2                     0x108
+#define EMC_FBIO_CFG6                           0x114
+#define EMC_CFG_RSV                             0x120
+#define EMC_ACPD_CONTROL                        0x124
+#define EMC_EMRS2                               0x12c
+#define EMC_EMRS3                               0x130
+#define EMC_MRW2                                0x134
+#define EMC_MRW3                                0x138
+#define EMC_MRW4                                0x13c
+#define EMC_CLKEN_OVERRIDE                      0x140
+#define EMC_R2R                                 0x144
+#define EMC_W2W                                 0x148
+#define EMC_EINPUT                              0x14c
+#define EMC_EINPUT_DURATION                     0x150
+#define EMC_PUTERM_EXTRA                        0x154
+#define EMC_TCKESR                              0x158
+#define EMC_TPD                                 0x15c
+
+#define EMC_AUTO_CAL_CONFIG                     0x2a4
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START_SHIFT 31
+#define EMC_AUTO_CAL_INTERVAL                   0x2a8
+#define EMC_AUTO_CAL_STATUS                     0x2ac
+#define EMC_AUTO_CAL_STATUS_ACTIVE              (0x1 << 31)
+#define EMC_AUTO_CAL_STATUS_SHIFT       31
+#define EMC_REQ_CTRL                            0x2b0
+#define EMC_STATUS                              0x2b4
+#define EMC_STATUS_TIMING_UPDATE_STALLED        (0x1 << 23)
+#define EMC_STATUS_MRR_DIVLD                    (0x1 << 20)
+
+#define EMC_CFG_2                               0x2b8
+#define EMC_CFG_2_MODE_SHIFT                    0
+#define EMC_CFG_2_MODE_MASK                     (0x3 << EMC_CFG_2_MODE_SHIFT)
+#define EMC_CFG_2_SREF_MODE                     0x1
+#define EMC_CFG_2_PD_MODE                       0x3
+#define EMC_CFG_2_DIS_STP_OB_CLK_DURING_NON_WR (0x1 << 6)
+
+#define EMC_CFG_DIG_DLL                         0x2bc
+#define EMC_CFG_DIG_DLL_PERIOD                  0x2c0
+#define EMC_DIG_DLL_STATUS                      0x2c8
+#define EMC_RDV_MASK                            0x2cc
+#define EMC_WDV_MASK                            0x2d0
+#define EMC_CTT_DURATION                        0x2d8
+#define EMC_CTT_TERM_CTRL                       0x2dc
+#define EMC_ZCAL_INTERVAL                       0x2e0
+#define EMC_ZCAL_WAIT_CNT                       0x2e4
+#define EMC_ZCAL_MRW_CMD                        0x2e8
+
+#define EMC_ZQ_CAL                              0x2ec
+#define EMC_ZQ_CAL_DEV_SEL_SHIFT                30
+#define EMC_ZQ_CAL_DEV_SEL_MASK                 \
+        (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
+#define EMC_ZQ_CAL_CMD                          (0x1 << 0)
+#define EMC_ZQ_CAL_LONG                         (0x1 << 4)
+#define EMC_ZQ_CAL_LONG_CMD_DEV0                \
+        (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
+#define EMC_ZQ_CAL_LONG_CMD_DEV1                \
+        (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
+
+#define EMC_XM2CMDPADCTRL                       0x2f0
+#define EMC_XM2CMDPADCTRL2                      0x2f4
+#define EMC_XM2DQSPADCTRL                       0x2f8
+#define EMC_XM2DQSPADCTRL2                      0x2fc
+#define EMC_XM2DQSPADCTRL2_RX_FT_REC_ENABLE     (0x1 << 0)
+#define EMC_XM2DQSPADCTRL2_VREF_ENABLE          (0x1 << 5)
+#define EMC_XM2DQPADCTRL                        0x300
+#define EMC_XM2DQPADCTRL2                       0x304
+#define EMC_XM2CLKPADCTRL                       0x308
+#define EMC_XM2COMPPADCTRL                      0x30c
+#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE      (0x1 << 10)
+#define EMC_XM2VTTGENPADCTRL                    0x310
+#define EMC_XM2VTTGENPADCTRL2                   0x314
+#define EMC_XM2VTTGENPADCTRL3                   0x318
+#define EMC_EMCPADEN                            0x31c
+#define EMC_XM2DQSPADCTRL4                      0x320
+#define EMC_SCRATCH0                            0x324
+#define EMC_DLL_XFORM_DQS0                      0x328
+#define EMC_DLL_XFORM_DQS1                      0x32c
+#define EMC_DLL_XFORM_DQS2                      0x330
+#define EMC_DLL_XFORM_DQS3                      0x334
+#define EMC_DLL_XFORM_DQS4                      0x338
+#define EMC_DLL_XFORM_DQS5                      0x33c
+#define EMC_DLL_XFORM_DQS6                      0x340
+#define EMC_DLL_XFORM_DQS7                      0x344
+#define EMC_DLL_XFORM_QUSE0                     0x348
+#define EMC_DLL_XFORM_QUSE1                     0x34c
+#define EMC_DLL_XFORM_QUSE2                     0x350
+#define EMC_DLL_XFORM_QUSE3                     0x354
+#define EMC_DLL_XFORM_QUSE4                     0x358
+#define EMC_DLL_XFORM_QUSE5                     0x35c
+#define EMC_DLL_XFORM_QUSE6                     0x360
+#define EMC_DLL_XFORM_QUSE7                     0x364
+#define EMC_DLL_XFORM_DQ0                       0x368
+#define EMC_DLL_XFORM_DQ1                       0x36c
+#define EMC_DLL_XFORM_DQ2                       0x370
+#define EMC_DLL_XFORM_DQ3                       0x374
+#define EMC_DLI_RX_TRIM0                        0x378
+#define EMC_DLI_RX_TRIM1                        0x37c
+#define EMC_DLI_RX_TRIM2                        0x380
+#define EMC_DLI_RX_TRIM3                        0x384
+#define EMC_DLI_RX_TRIM4                        0x388
+#define EMC_DLI_RX_TRIM5                        0x38c
+#define EMC_DLI_RX_TRIM6                        0x390
+#define EMC_DLI_RX_TRIM7                        0x394
+#define EMC_DLI_TX_TRIM0                        0x398
+#define EMC_DLI_TX_TRIM1                        0x39c
+#define EMC_DLI_TX_TRIM2                        0x3a0
+#define EMC_DLI_TX_TRIM3                        0x3a4
+#define EMC_DLI_TRIM_TXDQS0                     0x3a8
+#define EMC_DLI_TRIM_TXDQS1                     0x3ac
+#define EMC_DLI_TRIM_TXDQS2                     0x3b0
+#define EMC_DLI_TRIM_TXDQS3                     0x3b4
+#define EMC_DLI_TRIM_TXDQS4                     0x3b8
+#define EMC_DLI_TRIM_TXDQS5                     0x3bc
+#define EMC_DLI_TRIM_TXDQS6                     0x3c0
+#define EMC_DLI_TRIM_TXDQS7                     0x3c4
+#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE      0x3cc
+#define EMC_AUTO_CAL_CLK_STATUS                 0x3d4
+#define EMC_SEL_DPD_CTRL                        0x3d8
+#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD   (0x1 << 8)
+#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD    (0x1 << 5)
+#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD  (0x1 << 4)
+#define EMC_SEL_DPD_CTRL_CA_SEL_DPD     (0x1 << 3)
+#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD    (0x1 << 2)
+#define EMC_SEL_DPD_CTRL_DDR3_MASK      \
+        ((0xf << 2) | (0x1 << 8))
+#define EMC_SEL_DPD_CTRL_MASK \
+        ((0x3 << 2) | (0x1 << 5) | (0x1 << 8))
+#define EMC_PRE_REFRESH_REQ_CNT                 0x3dc
+#define EMC_DYN_SELF_REF_CONTROL                0x3e0
+#define EMC_TXSRDLL                             0x3e4
+#define EMC_CCFIFO_ADDR                         0x3e8
+#define EMC_CCFIFO_DATA                         0x3ec
+#define EMC_CCFIFO_STATUS                       0x3f0
+#define EMC_CDB_CNTL_1                          0x3f4
+#define EMC_CDB_CNTL_2                          0x3f8
+#define EMC_XM2CLKPADCTRL2                      0x3fc
+#define EMC_SWIZZLE_RANK0_BYTE_CFG              0x400
+#define EMC_SWIZZLE_RANK0_BYTE0                 0x404
+#define EMC_SWIZZLE_RANK0_BYTE1                 0x408
+#define EMC_SWIZZLE_RANK0_BYTE2                 0x40c
+#define EMC_SWIZZLE_RANK0_BYTE3                 0x410
+#define EMC_SWIZZLE_RANK1_BYTE_CFG              0x414
+#define EMC_SWIZZLE_RANK1_BYTE0                 0x418
+#define EMC_SWIZZLE_RANK1_BYTE1                 0x41c
+#define EMC_SWIZZLE_RANK1_BYTE2                 0x420
+#define EMC_SWIZZLE_RANK1_BYTE3                 0x424
+#define EMC_CA_TRAINING_START                   0x428
+#define EMC_CA_TRAINING_BUSY                    0x42c
+#define EMC_CA_TRAINING_CFG                     0x430
+#define EMC_CA_TRAINING_TIMING_CNTL1            0x434
+#define EMC_CA_TRAINING_TIMING_CNTL2            0x438
+#define EMC_CA_TRAINING_CA_LEAD_IN              0x43c
+#define EMC_CA_TRAINING_CA                      0x440
+#define EMC_CA_TRAINING_CA_LEAD_OUT             0x444
+#define EMC_CA_TRAINING_RESULT1                 0x448
+#define EMC_CA_TRAINING_RESULT2                 0x44c
+#define EMC_CA_TRAINING_RESULT3                 0x450
+#define EMC_CA_TRAINING_RESULT4                 0x454
+#define EMC_AUTO_CAL_CONFIG2                    0x458
+#define EMC_AUTO_CAL_CONFIG3                    0x45c
+#define EMC_AUTO_CAL_STATUS2                    0x460
+#define EMC_XM2CMDPADCTRL3                      0x464
+#define EMC_IBDLY                               0x468
+#define EMC_DLL_XFORM_ADDR0                     0x46c
+#define EMC_DLL_XFORM_ADDR1                     0x470
+#define EMC_DLL_XFORM_ADDR2                     0x474
+#define EMC_DLI_ADDR_TRIM                       0x478
+#define EMC_DSR_VTTGEN_DRV                      0x47c
+#define EMC_TXDSRVTTGEN                         0x480
+#define EMC_XM2CMDPADCTRL4                      0x484
+#define EMC_XM2CMDPADCTRL5                      0x488
+#define EMC_DLL_XFORM_DQS8                      0x4a0
+#define EMC_DLL_XFORM_DQS9                      0x4a4
+#define EMC_DLL_XFORM_DQS10                     0x4a8
+#define EMC_DLL_XFORM_DQS11                     0x4ac
+#define EMC_DLL_XFORM_DQS12                     0x4b0
+#define EMC_DLL_XFORM_DQS13                     0x4b4
+#define EMC_DLL_XFORM_DQS14                     0x4b8
+#define EMC_DLL_XFORM_DQS15                     0x4bc
+#define EMC_DLL_XFORM_QUSE8                     0x4c0
+#define EMC_DLL_XFORM_QUSE9                     0x4c4
+#define EMC_DLL_XFORM_QUSE10                    0x4c8
+#define EMC_DLL_XFORM_QUSE11                    0x4cc
+#define EMC_DLL_XFORM_QUSE12                    0x4d0
+#define EMC_DLL_XFORM_QUSE13                    0x4d4
+#define EMC_DLL_XFORM_QUSE14                    0x4d8
+#define EMC_DLL_XFORM_QUSE15                    0x4dc
+#define EMC_DLL_XFORM_DQ4                               0x4e0
+#define EMC_DLL_XFORM_DQ5                               0x4e4
+#define EMC_DLL_XFORM_DQ6                               0x4e8
+#define EMC_DLL_XFORM_DQ7                               0x4ec
+#define EMC_DLI_TRIM_TXDQS8                             0x520
+#define EMC_DLI_TRIM_TXDQS9                             0x524
+#define EMC_DLI_TRIM_TXDQS10                            0x528
+#define EMC_DLI_TRIM_TXDQS11                            0x52c
+#define EMC_DLI_TRIM_TXDQS12                            0x530
+#define EMC_DLI_TRIM_TXDQS13                            0x534
+#define EMC_DLI_TRIM_TXDQS14                            0x538
+#define EMC_DLI_TRIM_TXDQS15                            0x53c
+#define EMC_CDB_CNTL_3                          0x540
+#define EMC_XM2DQSPADCTRL5                      0x544
+#define EMC_XM2DQSPADCTRL6                      0x548
+#define EMC_XM2DQPADCTRL3                       0x54c
+#define EMC_DLL_XFORM_ADDR3                     0x550
+#define EMC_DLL_XFORM_ADDR4                     0x554
+#define EMC_DLL_XFORM_ADDR5                     0x558
+#define EMC_CFG_PIPE                            0x560
+#define EMC_QPOP                                        0x564
+#define EMC_QUSE_WIDTH                          0x568
+#define EMC_PUTERM_WIDTH                        0x56c
+#define EMC_BGBIAS_CTL0                         0x570
+#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_RX_SHIFT 0x3
+#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_IBIAS_VTTGEN_SHIFT     0x2
+#define EMC_BGBIAS_CTL0_BIAS0_DSC_E_PWRD_SHIFT  0x1
+#define EMC_PUTERM_ADJ                          0x574
+
+#define MC_EMEM_CFG                             0x50
+#define MC_EMEM_ADR_CFG                         0x54
+#define MC_EMEM_ADR_CFG_DEV0                    0x58
+#define MC_EMEM_ADR_CFG_DEV1                    0x5c
+#define MC_EMEM_ADR_CFG_BANK_MASK_0             0x64
+#define MC_EMEM_ADR_CFG_BANK_MASK_1             0x68
+#define MC_EMEM_ADR_CFG_BANK_MASK_2             0x6c
+
+#define MC_EMEM_ARB_CFG                         0x90
+#define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
+#define MC_EMEM_ARB_TIMING_RCD                  0x98
+#define MC_EMEM_ARB_TIMING_RP                   0x9c
+#define MC_EMEM_ARB_TIMING_RC                   0xa0
+#define MC_EMEM_ARB_TIMING_RAS                  0xa4
+#define MC_EMEM_ARB_TIMING_FAW                  0xa8
+#define MC_EMEM_ARB_TIMING_RRD                  0xac
+#define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
+#define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
+#define MC_EMEM_ARB_TIMING_R2R                  0xb8
+#define MC_EMEM_ARB_TIMING_W2W                  0xbc
+#define MC_EMEM_ARB_TIMING_R2W                  0xc0
+#define MC_EMEM_ARB_TIMING_W2R                  0xc4
+#define MC_EMEM_ARB_DA_TURNS                    0xd0
+#define MC_EMEM_ARB_DA_COVERS                   0xd4
+#define MC_EMEM_ARB_MISC0                       0xd8
+#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (0x1 << 27)
+#define MC_EMEM_ARB_MISC1                       0xdc
+#define MC_EMEM_ARB_RING1_THROTTLE              0xe0
+#define MC_EMEM_ARB_RING3_THROTTLE              0xe4
+#define MC_EMEM_ARB_OVERRIDE                    0xe8
+#define MC_EMEM_ARB_RSV                         0xec
+
+#define MC_CLKEN_OVERRIDE                       0xf4
+#define MC_TIMING_CONTROL_DBG                   0xf8
+#define MC_TIMING_CONTROL                       0xfc
+#define MC_EMEM_ARB_ISOCHRONOUS_0               0x208
+#define MC_EMEM_ARB_ISOCHRONOUS_1               0x20c
+#define MC_EMEM_ARB_ISOCHRONOUS_2               0x210
+#define MC_EMEM_ARB_HYSTERESIS_0_0              0x218
+#define MC_EMEM_ARB_HYSTERESIS_1_0              0x21c
+#define MC_EMEM_ARB_HYSTERESIS_2_0              0x220
+#define MC_EMEM_ARB_HYSTERESIS_3_0              0x224
+
+#define HYST_SATAR                              (0x1 << 31)
+#define HYST_PPCSAHBSLVR                        (0x1 << 30)
+#define HYST_PPCSAHBDMAR                        (0x1 << 29)
+#define HYST_MSENCSRD                           (0x1 << 28)
+#define HYST_HOST1XR                            (0x1 << 23)
+#define HYST_HOST1XDMAR                         (0x1 << 22)
+#define HYST_HDAR                               (0x1 << 21)
+#define HYST_DISPLAYHCB                         (0x1 << 17)
+#define HYST_DISPLAYHC                          (0x1 << 16)
+#define HYST_AVPCARM7R                          (0x1 << 15)
+#define HYST_AFIR                               (0x1 << 14)
+#define HYST_DISPLAY0CB                         (0x1 << 6)
+#define HYST_DISPLAY0C                          (0x1 << 5)
+#define HYST_DISPLAY0BB                         (0x1 << 4)
+#define HYST_DISPLAY0B                          (0x1 << 3)
+#define HYST_DISPLAY0AB                         (0x1 << 2)
+#define HYST_DISPLAY0A                          (0x1 << 1)
+#define HYST_PTCR                               (0x1 << 0)
+
+#define HYST_VDEDBGW                            (0x1 << 31)
+#define HYST_VDEBSEVW                           (0x1 << 30)
+#define HYST_SATAW                              (0x1 << 29)
+#define HYST_PPCSAHBSLVW                        (0x1 << 28)
+#define HYST_PPCSAHBDMAW                        (0x1 << 27)
+#define HYST_MPCOREW                            (0x1 << 25)
+#define HYST_MPCORELPW                          (0x1 << 24)
+#define HYST_HOST1XW                            (0x1 << 22)
+#define HYST_HDAW                               (0x1 << 21)
+#define HYST_AVPCARM7W                          (0x1 << 18)
+#define HYST_AFIW                               (0x1 << 17)
+#define HYST_MSENCSWR                           (0x1 << 11)
+#define HYST_MPCORER                            (0x1 << 7)
+#define HYST_MPCORELPR                          (0x1 << 6)
+#define HYST_VDETPER                            (0x1 << 5)
+#define HYST_VDEMCER                            (0x1 << 4)
+#define HYST_VDEMBER                            (0x1 << 3)
+#define HYST_VDEBSEVR                           (0x1 << 2)
+
+#define HYST_DISPLAYT                           (0x1 << 26)
+#define HYST_GPUSWR                             (0x1 << 25)
+#define HYST_GPUSRD                             (0x1 << 24)
+#define HYST_A9AVPSCW                           (0x1 << 23)
+#define HYST_A9AVPSCR                           (0x1 << 22)
+#define HYST_TSECSWR                            (0x1 << 21)
+#define HYST_TSECSRD                            (0x1 << 20)
+#define HYST_ISPWBB                             (0x1 << 17)
+#define HYST_ISPWAB                             (0x1 << 16)
+#define HYST_ISPRAB                             (0x1 << 14)
+#define HYST_XUSB_DEVW                          (0x1 << 13)
+#define HYST_XUSB_DEVR                          (0x1 << 12)
+#define HYST_XUSB_HOSTW                         (0x1 << 11)
+#define HYST_XUSB_HOSTR                         (0x1 << 10)
+#define HYST_ISPWB                              (0x1 << 7)
+#define HYST_ISPWA                              (0x1 << 6)
+#define HYST_ISPRA                              (0x1 << 4)
+#define HYST_VDETPMW                            (0x1 << 1)
+#define HYST_VDEMBEW                            (0x1 << 0)
+
+#define HYST_DISPLAYD                           (0x1 << 19)
+#define HYST_VIW                                (0x1 << 18)
+#define HYST_VICSWR                             (0x1 << 13)
+#define HYST_VICSRD                             (0x1 << 12)
+#define HYST_SDMMCWAB                           (0x1 << 7)
+#define HYST_SDMMCW                             (0x1 << 6)
+#define HYST_SDMMCWAA                           (0x1 << 5)
+#define HYST_SDMMCWA                            (0x1 << 4)
+#define HYST_SDMMCRAB                           (0x1 << 3)
+#define HYST_SDMMCR                             (0x1 << 2)
+#define HYST_SDMMCRAA                           (0x1 << 1)
+#define HYST_SDMMCRA                            (0x1 << 0)
+
+#define MC_DIS_EXTRA_SNAP_LEVELS                0x2ac
+
+#define MC_LATENCY_ALLOWANCE_AFI_0              0x2e0
+#define MC_LATENCY_ALLOWANCE_AVPC_0             0x2e4
+#define MC_LATENCY_ALLOWANCE_DC_0               0x2e8
+#define MC_LATENCY_ALLOWANCE_DC_1               0x2ec
+#define MC_LATENCY_ALLOWANCE_DC_2               0x2f0
+#define MC_LATENCY_ALLOWANCE_DCB_0              0x2f4
+#define MC_LATENCY_ALLOWANCE_DCB_1              0x2f8
+#define MC_LATENCY_ALLOWANCE_DCB_2              0x2fc
+#define MC_LATENCY_ALLOWANCE_HC_0               0x310
+#define MC_LATENCY_ALLOWANCE_HC_1               0x314
+#define MC_LATENCY_ALLOWANCE_HDA_0              0x318
+#define MC_LATENCY_ALLOWANCE_MPCORE_0   0x320
+#define MC_LATENCY_ALLOWANCE_MPCORELP_0 0x324
+#define MC_LATENCY_ALLOWANCE_MSENC_0    0x328
+#define MC_LATENCY_ALLOWANCE_PPCS_0             0x344
+#define MC_LATENCY_ALLOWANCE_PPCS_1             0x348
+#define MC_LATENCY_ALLOWANCE_PTC_0              0x34c
+#define MC_LATENCY_ALLOWANCE_SATA_0             0x350
+#define MC_LATENCY_ALLOWANCE_VDE_0              0x354
+#define MC_LATENCY_ALLOWANCE_VDE_1              0x358
+#define MC_LATENCY_ALLOWANCE_VDE_2              0x35c
+#define MC_LATENCY_ALLOWANCE_VDE_3              0x360
+#define MC_LATENCY_ALLOWANCE_ISP2_0             0x370
+#define MC_LATENCY_ALLOWANCE_ISP2_1             0x374
+#define MC_LATENCY_ALLOWANCE_XUSB_0             0x37c
+#define MC_LATENCY_ALLOWANCE_XUSB_1             0x380
+#define MC_LATENCY_ALLOWANCE_ISP2B_0    0x384
+#define MC_LATENCY_ALLOWANCE_ISP2B_1    0x388
+#define MC_LATENCY_ALLOWANCE_TSEC_0             0x390
+#define MC_LATENCY_ALLOWANCE_VIC_0              0x394
+#define MC_LATENCY_ALLOWANCE_VI2_0              0x398
+#define MC_LATENCY_ALLOWANCE_A9AVP_0    0x3a4
+#define MC_LATENCY_ALLOWANCE_GPU_0              0x3ac
+#define MC_LATENCY_ALLOWANCE_SDMMCA_0   0x3b8
+#define MC_LATENCY_ALLOWANCE_SDMMCAA_0  0x3bc
+#define MC_LATENCY_ALLOWANCE_SDMMC_0    0x3c0
+#define MC_LATENCY_ALLOWANCE_SDMMCAB_0  0x3c4
+#define MC_LATENCY_ALLOWANCE_DC_3               0x3c8
+
+/* NOTE: this must match the # of MC_LATENCY_XXX above */
+#define T12X_MC_LATENCY_ALLOWANCE_NUM_REGS 38
+
+#define MC_VIDEO_PROTECT_VPR_OVERRIDE           0x418
+#define MC_MLL_MPCORER_PTSA_RATE                        0x44c
+#define MC_VIDEO_PROTECT_BOM                    0x648
+#define MC_VIDEO_PROTECT_SIZE_MB                0x64c
+#define MC_VIDEO_PROTECT_REG_CTRL               0x650
+
+#define MC_SEC_CARVEOUT_BOM                     0x670
+#define MC_SEC_CARVEOUT_SIZE_MB                 0x674
+#define MC_SEC_CARVEOUT_REG_CTRL                0x678
+
+#define MC_PTSA_GRANT_DECREMENT                 0x960
+
+#define MC_RESERVED_RSV                         0x3fc
+#define MC_RESERVED_RSV_1                       0x958
+
+#define MC_EMEM_ARB_OUTSTANDING_REQ_RING3       0x66c
+#define MC_EMEM_ARB_OVERRIDE_1                  0x968
+
+#endif
diff --git a/include/linux/platform/tegra/tegra21_emc.h b/include/linux/platform/tegra/tegra21_emc.h
new file mode 100644
index 000000000..2d15d683e
--- /dev/null
+++ b/include/linux/platform/tegra/tegra21_emc.h
@@ -0,0 +1,1920 @@
+/*
+ * arch/arm/mach-tegra/tegra21_emc.h
+ *
+ * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ *
+ */
+
+#ifndef _MACH_TEGRA_TEGRA21_EMC_H
+#define _MACH_TEGRA_TEGRA21_EMC_H
+
+#include <linux/platform/tegra/tegra_emc.h>
+#include <linux/platform_data/tegra_emc_pdata.h>
+
+#define DVFS_FGCG_HIGH_SPEED_THRESHOLD  1000
+#define IOBRICK_DCC_THRESHOLD           2400
+#define DVFS_FGCG_MID_SPEED_THRESHOLD   600
+
+/* Uncomment to enable emc debugging on boot. */
+/* #define EMC_CC_DBG */
+#define emc_cc_dbg(mask, fmt, ...)                                      \
+        do {                                                            \
+                if (mask & emc_dbg_mask)                                \
+                        pr_info("%s: " fmt, __func__, ##__VA_ARGS__);   \
+        } while (0)
+
+/*
+ * Enable flags for specifying verbosity.
+ */
+#define INFO            (1 << 0)
+#define STEPS           (1 << 1)
+#define SUB_STEPS       (1 << 2)
+#define PRELOCK         (1 << 3)
+#define PRELOCK_STEPS   (1 << 4)
+#define ACTIVE_EN       (1 << 5)
+#define PRAMP_UP        (1 << 6)
+#define PRAMP_DN        (1 << 7)
+#define EMA_WRITES      (1 << 10)
+#define EMA_UPDATES     (1 << 11)
+#define PER_TRAIN       (1 << 16)
+#define CC_PRINT        (1 << 17)
+#define CCFIFO          (1 << 29)
+#define REGS            (1 << 30)
+#define REG_LISTS       (1 << 31)
+
+extern unsigned int emc_dbg_mask;
+
+/*
+ * Miscelaneous registers, fields, etc.
+ */
+#define MHZ 1000000
+#define TEGRA_EMC_ISO_USE_FREQ_MAX_NUM  12
+#define PLL_C_DIRECT_FLOOR              333500000
+#define EMC_STATUS_UPDATE_TIMEOUT       1000
+#define TEGRA_EMC_TABLE_MAX_SIZE        16
+
+#define TEGRA_EMC_MODE_REG_17   0x00110000
+#define TEGRA_EMC_MRW_DEV_SHIFT 30
+#define TEGRA_EMC_MRW_DEV1      2
+#define TEGRA_EMC_MRW_DEV2      1
+
+#define MC_EMEM_DEV_SIZE_MASK   0xF
+#define MC_EMEM_DEV_SIZE_SHIFT  16
+
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC       0x19c
+#define EMC_CLK_EMC_2X_CLK_SRC_SHIFT            29
+#define EMC_CLK_EMC_2X_CLK_SRC_MASK             \
+        (0x7 << EMC_CLK_EMC_2X_CLK_SRC_SHIFT)
+#define EMC_CLK_SOURCE_PLLM                     0x0
+#define EMC_CLK_SOURCE_PLLM_LJ                  0x4
+#define EMC_CLK_SOURCE_PLLMB                    0x6
+#define EMC_CLK_SOURCE_PLLMB_LJ                 0x5
+#define EMC_CLK_FORCE_CC_TRIGGER                (0x1 << 27)
+#define EMC_CLK_MC_EMC_SAME_FREQ                (0x1 << 16)
+#define EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT        0
+#define EMC_CLK_EMC_2X_CLK_DIVISOR_MASK         \
+        (0xff << EMC_CLK_EMC_2X_CLK_DIVISOR_SHIFT)
+
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET    0x284
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR    0x288
+
+#define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL           (1 << 14)
+
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL   0x664
+#define DLL_CLK_EMC_DLL_CLK_SRC_SHIFT           29
+#define DLL_CLK_EMC_DLL_CLK_SRC_MASK            \
+        (0x7 << DLL_CLK_EMC_DLL_CLK_SRC_SHIFT)
+#define DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT      10
+#define DLL_CLK_EMC_DLL_DDLL_CLK_SEL_MASK       \
+        (0x3 << DLL_CLK_EMC_DLL_DDLL_CLK_SEL_SHIFT)
+#define PLLM_VCOA                               0
+#define PLLM_VCOB                               1
+#define EMC_DLL_SWITCH_OUT                      2
+#define DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT       0
+#define DLL_CLK_EMC_DLL_CLK_DIVISOR_MASK        \
+        (0xff << DLL_CLK_EMC_DLL_CLK_DIVISOR_SHIFT)
+
+/*
+ * Lists of MC/EMC registers.
+ */
+#define BURST_PERCH_LIST                        \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_MRW10), \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_MRW10), \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_MRW11), \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_MRW11), \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_MRW12), \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_MRW12), \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_MRW13), \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_MRW13), \
+
+#define BURST_REG_LIST                                                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RC),                             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RFCPB),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_REFCTRL2),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RFC_SLR),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RAS),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RP),                             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_R2W),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_W2R),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_R2P),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_W2P),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_R2R),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TPPD),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CCDMW),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RD_RCD),                         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WR_RCD),                         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RRD),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_REXT),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WEXT),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV_CHK),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WSV),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WEV),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WDV_MASK),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WS_DURATION),                    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_WE_DURATION),                    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_QUSE_WIDTH),                     \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_IBDLY),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_OBDLY),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_EINPUT),                         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRW6),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_EINPUT_DURATION),                \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM_EXTRA),                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PUTERM_WIDTH),                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_QRST),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_QSAFE),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_MASK),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_EARLY),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RDV_EARLY_MASK),                 \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_REFRESH),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_BURST_REFRESH_NUM),              \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PRE_REFRESH_REQ_CNT),            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2WR),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2RD),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PCHG2PDEN),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_ACT2PDEN),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_AR2PDEN),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_RW2PDEN),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CKE2PDEN),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2CKE),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PDEX2MRR),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSR),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TXSRDLL),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKE),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TCKESR),                         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TPD),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TFAW),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRPAB),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTABLE),                     \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TCLKSTOP),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRW7),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TREFBW),                         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_ODT_WRITE),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG5),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_CFG7),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL),                    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_DIG_DLL_PERIOD),             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_RXRT),                 \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_PIPE_1),                     \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_PIPE_2),                     \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK0_4),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK0_5),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK1_4),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK1_5),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRW8),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_LONG_CMD_0),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_LONG_CMD_1),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_LONG_CMD_2),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_LONG_CMD_3),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_LONG_CMD_4),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_SHORT_CMD_0),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_SHORT_CMD_1),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_SHORT_CMD_2),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TXDSRVTTGEN),                    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_FDPD_CTRL_DQ),                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_FDPD_CTRL_CMD),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_SPARE),                     \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_INTERVAL),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_ZCAL_WAIT_CNT),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT),                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRS_WAIT_CNT2),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_AUTO_CAL_CHANNEL),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_CFG_0),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_DLL_CFG_1),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_AUTOCAL_CFG_COMMON),      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_ZCTRL),                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG),                            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_PIPE),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_DYN_SELF_REF_CONTROL),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_QPOP),                           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_DQS_BRLSHFT_0),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_DQS_BRLSHFT_1),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CMD_BRLSHFT_2),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CMD_BRLSHFT_3),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_PAD_CFG_CTRL),            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DATA_PAD_RX_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_PAD_RX_CTRL),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DATA_RX_TERM_MODE),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_RX_TERM_MODE),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_PAD_TX_CTRL),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DATA_PAD_TX_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_COMMON_PAD_TX_CTRL),      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_VTTGEN_CTRL_0),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_VTTGEN_CTRL_1),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_VTTGEN_CTRL_2),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_BRICK_CTRL_RFU1),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_BRICK_CTRL_FDPD),     \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_BRICK_CTRL_RFU2),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DATA_BRICK_CTRL_FDPD),    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_BG_BIAS_CTRL_0),          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_3),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_PWRD_0),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_PWRD_1),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_PWRD_2),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_PWRD_3),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_PWRD_4),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_PWRD_5),               \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_CONFIG_SAMPLE_DELAY),            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_SEL_CLK_SRC_0),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_SEL_CLK_SRC_1),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_SEL_CLK_SRC_2),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_SEL_CLK_SRC_3),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_SEL_CLK_SRC_4),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_TX_SEL_CLK_SRC_5),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_BYPASS),             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_PWRD_0),             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_PWRD_1),             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_DDLL_PWRD_2),             \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_CTRL_0),              \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_CTRL_1),              \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_CMD_CTRL_2),              \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_TIMING_0),                    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_DVFS),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_CTRL_1),                      \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_RDV),                         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_QPOP),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_RDV_MASK),                    \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRW14),                          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_QSAFE),                       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TR_QRST),                        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_CTRL),                  \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_SETTLE),                \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_VREF_SETTLE),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_CA_FINE_CTRL),          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_CA_CTRL_MISC),          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_CA_CTRL_MISC1),         \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_CA_VREF_CTRL),          \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_QUSE_CORS_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_QUSE_FINE_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_QUSE_CTRL_MISC),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_QUSE_VREF_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_READ_FINE_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_READ_CTRL_MISC),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_READ_VREF_CTRL),        \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_WRITE_FINE_CTRL),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_WRITE_CTRL_MISC),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_WRITE_VREF_CTRL),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_TRAINING_MPC),                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_MRW15)
+
+
+#define TRIM_PERCH_REG_LIST                                     \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_CMD_BRLSHFT_0),         \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_CMD_BRLSHFT_1),         \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_DATA_BRLSHFT_0),        \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_DATA_BRLSHFT_0),        \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_DATA_BRLSHFT_1),        \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_DATA_BRLSHFT_1),        \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_QUSE_BRLSHFT_0),        \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_QUSE_BRLSHFT_1),        \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_QUSE_BRLSHFT_2),        \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_QUSE_BRLSHFT_3)
+
+#define TRIM_REG_LIST                                                   \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_VREF_DQS_0),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_VREF_DQS_1),           \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_VREF_DQ_0),            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_IB_VREF_DQ_1),            \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2), \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK0_0),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK0_1),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK0_2),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK0_3),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK1_0),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK1_1),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK1_2),       \
+        DEFINE_REG(TEGRA_EMC_BASE, EMC_PMACRO_QUSE_DDLL_RANK1_3)
+
+#define BURST_MC_REG_LIST                                               \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_CFG),                     \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_OUTSTANDING_REQ),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_REFPB_HP_CTRL),           \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_REFPB_BANK_CTRL),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RCD),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RP),               \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RC),               \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAS),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_FAW),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RRD),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RAP2PRE),          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_WAP2PRE),          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2R),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2W),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_R2W),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_CCDMW),            \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_W2R),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_TIMING_RFCPB),            \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS),                \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS),               \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0),                   \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC1),                   \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC2),                   \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE),          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_CTRL),              \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6),    \
+        DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7),    \
+
+#define BURST_UP_DOWN_REG_LIST                                          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_MLL_MPCORER_PTSA_RATE),            \
+        DEFINE_REG(TEGRA_MC_BASE, MC_FTOP_PTSA_RATE),                   \
+        DEFINE_REG(TEGRA_MC_BASE, MC_PTSA_GRANT_DECREMENT),             \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_XUSB_0),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_XUSB_1),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_TSEC_0),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_SDMMCA_0),       \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_SDMMCAA_0),      \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_SDMMC_0),        \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_SDMMCAB_0),      \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_PPCS_0),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_PPCS_1),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_MPCORE_0),       \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_HC_0),           \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_HC_1),           \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_AVPC_0),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_GPU_0),          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_GPU2_0),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NVENC_0),        \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_NVDEC_0),        \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_VIC_0),          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_VI2_0),          \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_ISP2_0),         \
+        DEFINE_REG(TEGRA_MC_BASE, MC_LATENCY_ALLOWANCE_ISP2_1)
+
+#define VREF_PERCH_REG_LIST                                             \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0), \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_TRAINING_OPT_DQS_IB_VREF_RANK0), \
+        DEFINE_REG(TEGRA_EMC0_BASE, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1), \
+        DEFINE_REG(TEGRA_EMC1_BASE, EMC_TRAINING_OPT_DQS_IB_VREF_RANK1), \
+
+#define DEFINE_REG(base, reg)   reg##_INDEX
+enum {
+        BURST_REG_LIST
+};
+enum {
+        BURST_MC_REG_LIST
+};
+enum {
+        TRIM_REG_LIST
+};
+
+/*
+ * Defines a sequence this driver supports. Used for maintaining a list of
+ * different revisions.
+ */
+struct supported_sequence {
+        u8     table_rev;
+        void (*set_clock)(struct tegra21_emc_table *next_timing,
+                          struct tegra21_emc_table *last_timing,
+                          int training, u32 clksrc);
+        u32  (*periodic_compensation)(struct tegra21_emc_table *last_timing);
+        char  *seq_rev;
+};
+
+/*
+ * Functions common across different CC sequence revisions.
+ */
+void emc_writel(u32 val, unsigned long addr);
+u32  emc_readl(unsigned long addr);
+u32  emc1_readl(unsigned long addr);
+void emc1_writel(u32 val, unsigned long addr);
+void mc_writel(u32 val, unsigned long addr);
+u32  mc_readl(unsigned long addr);
+struct tegra21_emc_table *
+     get_timing_from_freq(unsigned long freq);
+int  wait_for_update(u32 status_reg, u32 bit_mask, bool updated_state,
+                     int chan);
+void emc_timing_update(int dual_chan);
+void do_clock_change(u32 clk_setting);
+void emc_set_shadow_bypass(int set);
+u32  get_dll_state(struct tegra21_emc_table *next_timing);
+u32  div_o3(u32 a, u32 b);
+void ccfifo_writel(u32 val, unsigned long addr, u32 delay);
+struct tegra21_emc_table *emc_get_table(unsigned long over_temp_state);
+void __emc_copy_table_params(struct tegra21_emc_table *src,
+                             struct tegra21_emc_table *dst, int flags);
+void set_over_temp_timing(struct tegra21_emc_table *next_timing,
+                          unsigned long state);
+
+/*
+ * Only share these functions between the V21015 and V21021 sequences. Those
+ * specific C files declare these defines before including tegra_emc.h.
+ */
+#if defined(__TEGRA_EMC_V21015) || defined(__TEGRA_EMC_V21021)
+u32 actual_osc_clocks(u32 in);
+void __reset_dram_clktree_values(struct tegra21_emc_table *table);
+u32 apply_periodic_compensation_trimmer(
+                struct tegra21_emc_table *next_timing, u32 offset);
+void __update_emc_alt_timing(struct tegra21_emc_table *current_timing);
+void start_periodic_compensation(void);
+u32 do_dvfs_power_ramp_down(u32 clk, int flip_backward,
+                            struct tegra21_emc_table *last_timing,
+                            struct tegra21_emc_table *next_timing);
+u32 do_dvfs_power_ramp_up(u32 clk, int flip_backward,
+                          struct tegra21_emc_table *last_timing,
+                          struct tegra21_emc_table *next_timing);
+void change_dll_src(struct tegra21_emc_table *next_timing, u32 clksrc);
+u32 dll_prelock(struct tegra21_emc_table *next_timing,
+                int dvfs_with_training, u32 clksrc);
+void dll_disable(int channel_mode);
+void dll_enable(int channel_mode);
+#endif
+
+extern int ccfifo_index;
+extern void __iomem *emc_base;
+extern void __iomem *emc1_base;
+extern void __iomem *mc_base;
+extern void __iomem *clk_base;
+extern unsigned long dram_over_temp_state;
+
+extern struct tegra21_emc_table *tegra_emc_table;
+extern struct tegra21_emc_table *tegra_emc_table_derated;
+extern int tegra_emc_table_size;
+
+/*
+ * EMC register lists.
+ */
+extern void __iomem *burst_reg_off[];
+extern void __iomem *burst_perch_reg_off[];
+extern void __iomem *vref_reg_off[];
+extern void __iomem *trim_reg_off[];
+extern void __iomem *trim_perch_reg_off[];
+extern void __iomem *la_scale_off_regs[];
+extern void __iomem *burst_mc_reg_off[];
+
+/*
+ * Versions of the clock change we support.
+ */
+void emc_set_clock_r21012(struct tegra21_emc_table *next_timing,
+                          struct tegra21_emc_table *last_timing,
+                          int training, u32 clksrc);
+void emc_set_clock_r21015(struct tegra21_emc_table *next_timing,
+                          struct tegra21_emc_table *last_timing,
+                          int training, u32 clksrc);
+void emc_set_clock_r21021(struct tegra21_emc_table *next_timing,
+                          struct tegra21_emc_table *last_timing,
+                          int training, u32 clksrc);
+u32  __do_periodic_emc_compensation_r21015(
+                          struct tegra21_emc_table *current_timing);
+u32  __do_periodic_emc_compensation_r21021(
+                          struct tegra21_emc_table *current_timing);
+
+#define EMC_COPY_TABLE_PARAM_PERIODIC_FIELDS    0x1
+#define EMC_COPY_TABLE_PARAM_TRIM_REGS          0x2
+#define EMC_COPY_TABLE_PARAM_PTFV_FIELDS        0x3
+
+enum {
+        DLL_CHANGE_NONE = 0,
+        DLL_CHANGE_ON,
+        DLL_CHANGE_OFF,
+};
+
+enum {
+        DLL_OFF,
+        DLL_ON
+};
+
+enum {
+        /* Use auto power-down clk change. If CL/WL not changing (cya_mrs=1),
+           fall back to ap20 mode. */
+        AUTO_PD = 0,
+
+        /* SW explicitly enters/exits self-ref in clk change, the only option
+           for ddr3 dll-off sequence. */
+        MAN_SR  = 2
+};
+
+enum {
+        ASSEMBLY = 0, /* I.e shadow registers. */
+        ACTIVE
+};
+
+enum {
+        T_RP = 0,
+        T_FC_LPDDR4,
+        T_RFC,
+        T_PDEX,
+        RL
+};
+
+enum {
+        ONE_RANK = 1,
+        TWO_RANK = 2
+};
+
+enum {
+        SINGLE_CHANNEL = 0,
+        DUAL_CHANNEL
+};
+
+enum {
+        DRAM_DEV_SEL_ALL = 0,
+        DRAM_DEV_SEL_0   = (2 << 30),
+        DRAM_DEV_SEL_1   = (1 << 30),
+};
+#define DRAM_BROADCAST(num)                     \
+        (((num) > 1) ? DRAM_DEV_SEL_ALL : DRAM_DEV_SEL_0)
+
+enum {
+        EMC_CFG5_QUSE_MODE_NORMAL = 0,
+        EMC_CFG5_QUSE_MODE_ALWAYS_ON,
+        EMC_CFG5_QUSE_MODE_INTERNAL_LPBK,
+        EMC_CFG5_QUSE_MODE_PULSE_INTERN,
+        EMC_CFG5_QUSE_MODE_PULSE_EXTERN,
+        EMC_CFG5_QUSE_MODE_DIRECT_QUSE,
+};
+
+enum {
+        DVFS_SEQUENCE = 1,
+        WRITE_TRAINING_SEQUENCE = 2,
+        PERIODIC_TRAINING_SEQUENCE = 3,
+        DVFS_PT1 = 10,
+        DVFS_UPDATE = 11,
+        TRAINING_PT1 = 12,
+        TRAINING_UPDATE = 13,
+        PERIODIC_TRAINING_UPDATE = 14
+};
+
+/*
+ * PTFV defines - basically just indexes into the per table PTFV array.
+ */
+#define PTFV_DQSOSC_MOVAVG_C0D0U0_INDEX         0
+#define PTFV_DQSOSC_MOVAVG_C0D0U1_INDEX         1
+#define PTFV_DQSOSC_MOVAVG_C0D1U0_INDEX         2
+#define PTFV_DQSOSC_MOVAVG_C0D1U1_INDEX         3
+#define PTFV_DQSOSC_MOVAVG_C1D0U0_INDEX         4
+#define PTFV_DQSOSC_MOVAVG_C1D0U1_INDEX         5
+#define PTFV_DQSOSC_MOVAVG_C1D1U0_INDEX         6
+#define PTFV_DQSOSC_MOVAVG_C1D1U1_INDEX         7
+#define PTFV_DVFS_SAMPLES_INDEX                 9
+#define PTFV_MOVAVG_WEIGHT_INDEX                10
+#define PTFV_CONFIG_CTRL_INDEX                  11
+
+#define PTFV_CONFIG_CTRL_USE_PREVIOUS_EMA       (1 << 0)
+
+/* Registers and fields. */
+#define EMC_INTSTATUS                                           0x0
+#define EMC_INTSTATUS_MRR_DIVLD                                 (0x1 << 5)
+#define EMC_INTSTATUS_CLKCHANGE_COMPLETE                        (0x1 << 4)
+
+#define EMC_INTMASK                                             0x4
+#define EMC_DBG                                                 0x8
+#define EMC_DBG_WRITE_MUX_ACTIVE                                (1 << 1)
+#define EMC_DBG_CFG_SWAP_SHIFT                                  26
+#define EMC_DBG_CFG_SWAP_MASK                                   \
+        (0x3 << EMC_DBG_CFG_SWAP_SHIFT)
+#define EMC_DBG_WRITE_ACTIVE_ONLY                               (1 << 30)
+
+#define EMC_CONFIG_SAMPLE_DELAY                                 0x5f0
+#define EMC_CFG_UPDATE                                          0x5f4
+#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT               9
+#define EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_MASK                \
+        (0x3 << EMC_CFG_UPDATE_UPDATE_DLL_IN_UPDATE_SHIFT)
+
+#define EMC_CFG                                                 0xc
+#define EMC_CFG_DRAM_CLKSTOP_PD                                 (1 << 31)
+#define EMC_CFG_DRAM_CLKSTOP_SR                                 (1 << 30)
+#define EMC_CFG_DRAM_ACPD                                       (1 << 29)
+#define EMC_CFG_DYN_SELF_REF                                    (1 << 28)
+#define EMC_CFG_REQACT_ASYNC                                    (1 << 26)
+#define EMC_CFG_AUTO_PRE_WR                                     (1 << 25)
+#define EMC_CFG_AUTO_PRE_RD                                     (1 << 24)
+#define EMC_CFG_MAM_PRE_WR                                      (1 << 23)
+#define EMC_CFG_MAN_PRE_RD                                      (1 << 22)
+#define EMC_CFG_PERIODIC_QRST                                   (1 << 21)
+#define EMC_CFG_PERIODIC_QRST_SHIFT                             (21)
+#define EMC_CFG_EN_DYNAMIC_PUTERM                               (1 << 20)
+#define EMC_CFG_DLY_WR_DQ_HALF_CLOCK                            (1 << 19)
+#define EMC_CFG_DSR_VTTGEN_DRV_EN                               (1 << 18)
+#define EMC_CFG_EMC2MC_CLK_RATIO                                (3 << 16)
+#define EMC_CFG_WAIT_FOR_ISP2B_READY_B4_CC                      (1 << 9)
+#define EMC_CFG_WAIT_FOR_VI2_READY_B4_CC                        (1 << 8)
+#define EMC_CFG_WAIT_FOR_ISP2_READY_B4_CC                       (1 << 7)
+#define EMC_CFG_INVERT_DQM                                      (1 << 6)
+#define EMC_CFG_WAIT_FOR_DISPLAYB_READY_B4_CC                   (1 << 5)
+#define EMC_CFG_WAIT_FOR_DISPLAY_READY_B4_CC                    (1 << 4)
+#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE2                 (1 << 3)
+#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_DATAPIPE1                 (1 << 2)
+#define EMC_CFG_EMC2PMACRO_CFG_BYPASS_ADDRPIPE                  (1 << 1)
+
+#define EMC_ADR_CFG                                             0x10
+#define EMC_REFCTRL                                             0x20
+#define EMC_REFCTRL_DEV_SEL_SHIFT                               0
+#define EMC_REFCTRL_DEV_SEL_MASK                                \
+        (0x3 << EMC_REFCTRL_DEV_SEL_SHIFT)
+#define EMC_REFCTRL_ENABLE                                      (0x1 << 31)
+#define EMC_REFCTRL_ENABLE_ALL(num)                             \
+        (((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)   \
+         | EMC_REFCTRL_ENABLE)
+#define EMC_REFCTRL_DISABLE_ALL(num)                            \
+        ((((num) > 1) ? 0 : 2) << EMC_REFCTRL_DEV_SEL_SHIFT)
+
+#define EMC_PIN                                                 0x24
+#define EMC_PIN_PIN_CKE_PER_DEV                                 (1 << 2)
+#define EMC_PIN_PIN_CKEB                                        (1 << 1)
+#define EMC_PIN_PIN_CKE                                         (1 << 0)
+
+#define EMC_TIMING_CONTROL                                      0x28
+#define EMC_RC                                                  0x2c
+#define EMC_RFC                                                 0x30
+#define EMC_RFCPB                                               0x590
+#define EMC_RAS                                                 0x34
+#define EMC_RP                                                  0x38
+#define EMC_R2W                                                 0x3c
+#define EMC_W2R                                                 0x40
+#define EMC_R2P                                                 0x44
+#define EMC_W2P                                                 0x48
+#define EMC_CCDMW                                               0x5c0
+#define EMC_RD_RCD                                              0x4c
+#define EMC_WR_RCD                                              0x50
+#define EMC_RRD                                                 0x54
+#define EMC_REXT                                                0x58
+#define EMC_WDV                                                 0x5c
+#define EMC_QUSE                                                0x60
+#define EMC_QRST                                                0x64
+#define EMC_ISSUE_QRST                                          0x428
+#define EMC_QSAFE                                               0x68
+#define EMC_RDV                                                 0x6c
+#define EMC_REFRESH                                             0x70
+#define EMC_BURST_REFRESH_NUM                                   0x74
+#define EMC_PDEX2WR                                             0x78
+#define EMC_PDEX2RD                                             0x7c
+#define EMC_PDEX2CKE                                            0x118
+#define EMC_PCHG2PDEN                                           0x80
+#define EMC_ACT2PDEN                                            0x84
+#define EMC_AR2PDEN                                             0x88
+#define EMC_RW2PDEN                                             0x8c
+#define EMC_CKE2PDEN                                            0x11c
+#define EMC_TXSR                                                0x90
+#define EMC_TCKE                                                0x94
+#define EMC_TFAW                                                0x98
+#define EMC_TRPAB                                               0x9c
+#define EMC_TCLKSTABLE                                          0xa0
+#define EMC_TCLKSTOP                                            0xa4
+#define EMC_TREFBW                                              0xa8
+#define EMC_TPPD                                                0xac
+#define EMC_PDEX2MRR                                            0xb4
+#define EMC_ODT_WRITE                                           0xb0
+#define EMC_WEXT                                                0xb8
+#define EMC_RFC_SLR                                             0xc0
+#define EMC_MRS_WAIT_CNT2                                       0xc4
+#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT               16
+#define EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_MASK                \
+        (0x7ff << EMC_MRS_WAIT_CNT2_MRS_EXT2_WAIT_CNT_SHIFT)
+#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT               0
+#define EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_MASK                \
+        (0x3ff << EMC_MRS_WAIT_CNT2_MRS_EXT1_WAIT_CNT_SHIFT)
+
+#define EMC_MRS_WAIT_CNT                                        0xc8
+#define EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT                       0
+#define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK                        \
+        (0x3FF << EMC_MRS_WAIT_CNT_SHORT_WAIT_SHIFT)
+#define EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT                        16
+#define EMC_MRS_WAIT_CNT_LONG_WAIT_MASK                         \
+        (0x3FF << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
+
+#define EMC_MRS                                                 0xcc
+#define EMC_MODE_SET_DLL_RESET                                  (1 << 8)
+#define EMC_MRS_USE_MRS_LONG_CNT                                (1 << 26)
+
+#define EMC_EMRS                                                0xd0
+#define EMC_EMRS_USE_EMRS_LONG_CNT                              (1 << 26)
+
+#define EMC_REF                                                 0xd4
+#define EMC_REF_FORCE_CMD                                       1
+
+#define EMC_PRE                                                 0xd8
+#define EMC_NOP                                                 0xdc
+#define EMC_SELF_REF                                            0xe0
+#define EMC_SELF_REF_CMD_ENABLED                                (1 << 0)
+#define EMC_SELF_REF_ACTIVE_SELF_REF                            (1 << 8)
+#define EMC_SELF_REF_DEV_SEL_SHIFT                              30
+#define EMC_SELF_REF_DEV_SEL_MASK                               \
+        (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
+
+#define EMC_DPD                                                 0xe4
+#define EMC_MRW                                                 0xe8
+#define EMC_MRW_MRW_OP_SHIFT                                    0
+#define EMC_MRW_MRW_OP_MASK                                     \
+        (0xff << EMC_MRW_MRW_OP_SHIFT)
+#define EMC_MRW_MRW_MA_SHIFT                                    16
+#define EMC_MRW_MRW_MA_MASK                                     \
+        (0xff << EMC_MRW_MRW_MA_SHIFT)
+#define EMC_MRW_USE_MRW_LONG_CNT                                26
+#define EMC_MRW_USE_MRW_EXT_CNT                                 27
+#define EMC_MRW_MRW_DEV_SELECTN_SHIFT                           30
+#define EMC_MRW_MRW_DEV_SELECTN_MASK                            \
+        (0x3 << EMC_MRW_MRW_DEV_SELECTN_SHIFT)
+
+#define EMC_MRR                                                 0xec
+#define EMC_MRR_DEV_SEL_SHIFT                                   30
+#define EMC_MRR_DEV_SEL_MASK                                    \
+        (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
+#define EMC_MRR_MA_SHIFT                                        16
+#define EMC_MRR_MA_MASK                                         \
+        (0xff << EMC_MRR_MA_SHIFT)
+#define EMC_MRR_DATA_SHIFT                                      0
+#define EMC_MRR_DATA_MASK                                       \
+        (0xffff << EMC_MRR_DATA_SHIFT)
+#define LPDDR2_MR4_TEMP_SHIFT                                   0
+#define LPDDR2_MR4_TEMP_MASK                                    \
+        (0x7 << LPDDR2_MR4_TEMP_SHIFT)
+
+#define EMC_CMDQ                                                0xf0
+#define EMC_MC2EMCQ                                             0xf4
+#define EMC_FBIO_SPARE                                          0x100
+#define EMC_FBIO_CFG5                                           0x104
+#define EMC_FBIO_CFG5_DRAM_TYPE_SHIFT                           0
+#define EMC_FBIO_CFG5_DRAM_TYPE_MASK                            \
+        (0x3 << EMC_FBIO_CFG5_DRAM_TYPE_SHIFT)
+#define EMC_FBIO_CFG5_CMD_TX_DIS                                (1 << 8)
+#define EMC_FBIO_CFG5_CMD_BUS_RETURN_TO_ZERO                    (1 << 27)
+
+#define EMC_CFG5_QUSE_MODE_SHIFT                                13
+#define EMC_CFG5_QUSE_MODE_MASK                                 \
+        (0x7 << EMC_CFG5_QUSE_MODE_SHIFT)
+
+#define EMC_CFG_RSV                                             0x120
+#define EMC_ACPD_CONTROL                                        0x124
+#define EMC_MPC                                                 0x128
+#define EMC_EMRS2                                               0x12c
+#define EMC_EMRS2_USE_EMRS2_LONG_CNT                            (1 << 26)
+
+#define EMC_EMRS3                                               0x130
+#define EMC_MRW2                                                0x134
+#define EMC_MRW3                                                0x138
+#define EMC_MRW4                                                0x13c
+#define EMC_MRW5                                                0x4a0
+#define EMC_MRW6                                                0x4a4
+#define EMC_MRW7                                                0x4a8
+#define EMC_MRW8                                                0x4ac
+#define EMC_MRW9                                                0x4b0
+#define EMC_MRW10                                               0x4b4
+#define EMC_MRW11                                               0x4b8
+#define EMC_MRW12                                               0x4bc
+#define EMC_MRW13                                               0x4c0
+#define EMC_MRW14                                               0x4c4
+#define EMC_MRW15                                               0x4d0
+#define EMC_CFG_SYNC                                            0x4d4
+#define EMC_CLKEN_OVERRIDE                                      0x140
+#define EMC_R2R                                                 0x144
+#define EMC_W2W                                                 0x148
+#define EMC_EINPUT                                              0x14c
+#define EMC_EINPUT_DURATION                                     0x150
+#define EMC_PUTERM_EXTRA                                        0x154
+#define EMC_TCKESR                                              0x158
+#define EMC_TPD                                                 0x15c
+#define EMC_STAT_CONTROL                                        0x160
+#define EMC_STAT_STATUS                                         0x164
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO                            0x19c
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI                            0x1a0
+#define EMC_STAT_DRAM_CLOCKS_LO                                 0x1a4
+#define EMC_STAT_DRAM_CLOCKS_HI                                 0x1a8
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO                      0x1ac
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI                      0x1b0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO                          0x1b4
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI                          0x1b8
+#define EMC_STAT_DRAM_DEV0_READ8_CNT_LO                         0x1bc
+#define EMC_STAT_DRAM_DEV0_READ8_CNT_HI                         0x1c0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO                         0x1c4
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI                         0x1c8
+#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_LO                        0x1cc
+#define EMC_STAT_DRAM_DEV0_WRITE8_CNT_HI                        0x1d0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO                           0x1d4
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI                           0x1d8
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1dc
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e0
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x1e4
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x1e8
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1ec
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f0
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x1f4
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x1f8
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x1fc
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x200
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x204
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x208
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x20c
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x210
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x214
+#define EMC_STAT_DRAM_DEV0_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x218
+#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_LO                   0x21c
+#define EMC_STAT_DRAM_DEV0_SR_CKE_EQ0_CLKS_HI                   0x220
+#define EMC_STAT_DRAM_DEV0_DSR                                  0x224
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO                      0x228
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI                      0x22c
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO                          0x230
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI                          0x234
+#define EMC_STAT_DRAM_DEV1_READ8_CNT_LO                         0x238
+#define EMC_STAT_DRAM_DEV1_READ8_CNT_HI                         0x23c
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO                         0x240
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI                         0x244
+#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_LO                        0x248
+#define EMC_STAT_DRAM_DEV1_WRITE8_CNT_HI                        0x24c
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO                           0x250
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI                           0x254
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x258
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x25c
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0x260
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0x264
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x268
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x26c
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0x270
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0x274
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x278
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x27c
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0x280
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0x284
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x288
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x28c
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0x290
+#define EMC_STAT_DRAM_DEV1_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0x294
+#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_LO                   0x298
+#define EMC_STAT_DRAM_DEV1_SR_CKE_EQ0_CLKS_HI                   0x29c
+#define EMC_STAT_DRAM_DEV1_DSR                                  0x2a0
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc8c
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc90
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_LO 0xc94
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_NO_BANKS_ACTIVE_CLKS_HI 0xc98
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xc9c
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca0
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_LO 0xca4
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_NO_BANKS_ACTIVE_CLKS_HI 0xca8
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcac
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb0
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_LO 0xcb4
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ0_SOME_BANKS_ACTIVE_CLKS_HI 0xcb8
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcbc
+#define EMC_STAT_DRAM_IO_EXTCLKS_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc0
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_LO 0xcc4
+#define EMC_STAT_DRAM_IO_CLKSTOP_CKE_EQ1_SOME_BANKS_ACTIVE_CLKS_HI 0xcc8
+#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_LO                     0xccc
+#define EMC_STAT_DRAM_IO_SR_CKE_EQ0_CLKS_HI                     0xcd0
+#define EMC_STAT_DRAM_IO_DSR                                    0xcd4
+#define EMC_AUTO_CAL_CONFIG                                     0x2a4
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_COMPUTE_START              (1 << 0)
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_MEASURE_STALL              (1 << 9)
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_UPDATE_STALL               (1 << 10)
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_ENABLE                     (1 << 29)
+#define EMC_AUTO_CAL_CONFIG_AUTO_CAL_START                      (1 << 31)
+
+#define EMC_AUTO_CAL_CONFIG2                                    0x458
+#define EMC_AUTO_CAL_CONFIG3                                    0x45c
+#define EMC_AUTO_CAL_CONFIG4                                    0x5b0
+#define EMC_AUTO_CAL_CONFIG5                                    0x5b4
+#define EMC_AUTO_CAL_CONFIG6                                    0x5cc
+#define EMC_AUTO_CAL_CONFIG7                                    0x574
+#define EMC_AUTO_CAL_CONFIG8                                    0x2dc
+#define EMC_AUTO_CAL_VREF_SEL_0                                 0x2f8
+#define EMC_AUTO_CAL_VREF_SEL_1                                 0x300
+#define EMC_AUTO_CAL_INTERVAL                                   0x2a8
+#define EMC_AUTO_CAL_STATUS                                     0x2ac
+#define EMC_AUTO_CAL_STATUS2                                    0x3d4
+#define EMC_AUTO_CAL_CHANNEL                                    0x464
+#define EMC_PMACRO_RX_TERM                                      0xc48
+#define EMC_PMACRO_DQ_TX_DRV                                    0xc70
+#define EMC_PMACRO_CA_TX_DRV                                    0xc74
+#define EMC_PMACRO_CMD_TX_DRV                                   0xc4c
+#define EMC_PMACRO_AUTOCAL_CFG_0                                0x700
+#define EMC_PMACRO_AUTOCAL_CFG_1                                0x704
+#define EMC_PMACRO_AUTOCAL_CFG_2                                0x708
+#define EMC_PMACRO_AUTOCAL_CFG_COMMON                           0xc78
+#define EMC_PMACRO_AUTOCAL_CFG_COMMON_E_CAL_BYPASS_DVFS         (1 << 16)
+
+#define EMC_PMACRO_ZCTRL                                        0xc44
+#define EMC_XM2COMPPADCTRL                                      0x30c
+#define EMC_XM2COMPPADCTRL_VREF_CAL_ENABLE                      (1 << 10)
+
+#define EMC_XM2COMPPADCTRL2                                     0x578
+#define EMC_XM2COMPPADCTRL3                                     0x2f4
+#define EMC_COMP_PAD_SW_CTRL                                    0x57c
+#define EMC_REQ_CTRL                                            0x2b0
+#define EMC_EMC_STATUS                                          0x2b4
+#define EMC_EMC_STATUS_MRR_DIVLD                                (1 << 20)
+#define EMC_EMC_STATUS_TIMING_UPDATE_STALLED                    (1 << 23)
+#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT                  4
+#define EMC_EMC_STATUS_DRAM_IN_POWERDOWN_MASK                   \
+        (0x3 << EMC_EMC_STATUS_DRAM_IN_POWERDOWN_SHIFT)
+#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT               8
+#define EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_MASK                \
+        (0x3 << EMC_EMC_STATUS_DRAM_IN_SELF_REFRESH_SHIFT)
+
+#define EMC_CFG_2                                               0x2b8
+#define EMC_CFG_DIG_DLL                                         0x2bc
+#define EMC_CFG_DIG_DLL_CFG_DLL_EN                              (1 << 0)
+#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_UNTIL_LOCK            (1 << 1)
+#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_ALL_TRAFFIC               (1 << 3)
+#define EMC_CFG_DIG_DLL_CFG_DLL_STALL_RW_UNTIL_LOCK             (1 << 4)
+#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT                      6
+#define EMC_CFG_DIG_DLL_CFG_DLL_MODE_MASK                       \
+        (0x3 << EMC_CFG_DIG_DLL_CFG_DLL_MODE_SHIFT)
+#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT                8
+#define EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_MASK                 \
+        (0x7 << EMC_CFG_DIG_DLL_CFG_DLL_LOCK_LIMIT_SHIFT)
+
+#define EMC_CFG_DIG_DLL_PERIOD                                  0x2c0
+#define EMC_DIG_DLL_STATUS                                      0x2c4
+#define EMC_DIG_DLL_STATUS_DLL_LOCK                             (1 << 15)
+#define EMC_DIG_DLL_STATUS_DLL_PRIV_UPDATED                     (1 << 17)
+#define EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT                        0
+#define EMC_DIG_DLL_STATUS_DLL_OUT_MASK                         \
+        (0x7ff << EMC_DIG_DLL_STATUS_DLL_OUT_SHIFT)
+
+
+#define EMC_CFG_DIG_DLL_1                                       0x2c8
+#define EMC_RDV_MASK                                            0x2cc
+#define EMC_WDV_MASK                                            0x2d0
+#define EMC_RDV_EARLY_MASK                                      0x2d4
+#define EMC_RDV_EARLY                                           0x2d8
+#define EMC_WDV_CHK                                             0x4e0
+#define EMC_ZCAL_INTERVAL                                       0x2e0
+#define EMC_ZCAL_WAIT_CNT                                       0x2e4
+#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_MASK                    0x7ff
+#define EMC_ZCAL_WAIT_CNT_ZCAL_WAIT_CNT_SHIFT                   0
+
+#define EMC_ZCAL_MRW_CMD                                        0x2e8
+#define EMC_ZQ_CAL                                              0x2ec
+#define EMC_ZQ_CAL_DEV_SEL_SHIFT                                30
+#define EMC_ZQ_CAL_DEV_SEL_MASK                                 \
+        (0x3 << EMC_SELF_REF_DEV_SEL_SHIFT)
+#define EMC_ZQ_CAL_LONG                                         (1 << 4)
+#define EMC_ZQ_CAL_ZQ_LATCH_CMD                                 (1 << 1)
+#define EMC_ZQ_CAL_ZQ_CAL_CMD                                   (1 << 0)
+#define EMC_ZQ_CAL_LONG_CMD_DEV0                                \
+        (DRAM_DEV_SEL_0 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
+#define EMC_ZQ_CAL_LONG_CMD_DEV1                                \
+        (DRAM_DEV_SEL_1 | EMC_ZQ_CAL_LONG | EMC_ZQ_CAL_CMD)
+
+#define EMC_SCRATCH0                                            0x324
+#define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE                     0x3c8
+#define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE                      0x3cc
+#define EMC_UNSTALL_RW_AFTER_CLKCHANGE                          0x3d0
+#define EMC_FDPD_CTRL_CMD_NO_RAMP                               0x4d8
+#define EMC_FDPD_CTRL_CMD_NO_RAMP_CMD_DPD_NO_RAMP_ENABLE        (1 << 0)
+
+#define EMC_SEL_DPD_CTRL                                        0x3d8
+#define EMC_SEL_DPD_CTRL_DATA_SEL_DPD_EN                        (1 << 8)
+#define EMC_SEL_DPD_CTRL_ODT_SEL_DPD_EN                         (1 << 5)
+#define EMC_SEL_DPD_CTRL_RESET_SEL_DPD_EN                       (1 << 4)
+#define EMC_SEL_DPD_CTRL_CA_SEL_DPD_EN                          (1 << 3)
+#define EMC_SEL_DPD_CTRL_CLK_SEL_DPD_EN                         (1 << 2)
+#define EMC_SEL_DPD_CTRL_DDR3_MASK                              \
+        ((0xf << 2) | (0x1 << 8))
+#define EMC_SEL_DPD_CTRL_MAS                                    \
+        ((0x3 << 2) | (0x1 << 5) | (0x1 << 8))
+
+#define EMC_FDPD_CTRL_DQ                                        0x310
+#define EMC_FDPD_CTRL_CMD                                       0x314
+#define EMC_PRE_REFRESH_REQ_CNT                                 0x3dc
+#define EMC_REFCTRL2                                            0x580
+#define EMC_FBIO_CFG7                                           0x584
+#define EMC_FBIO_CFG7_CH0_ENABLE                                (1 << 1)
+#define EMC_FBIO_CFG7_CH1_ENABLE                                (1 << 2)
+
+#define EMC_DATA_BRLSHFT_0                                      0x588
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT       21
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE7_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT       18
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE6_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT       15
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE5_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT       12
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE4_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT       9
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE3_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT       6
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE2_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT       3
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE1_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT       0
+#define EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_0_RANK0_BYTE0_DATA_BRLSHFT_SHIFT)
+
+#define EMC_DATA_BRLSHFT_1                                      0x58c
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT       21
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE7_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT       18
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE6_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT       15
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE5_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT       12
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE4_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT       9
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE3_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT       6
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE2_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT       3
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE1_DATA_BRLSHFT_SHIFT)
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT       0
+#define EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_MASK        \
+        (0x7 << EMC_DATA_BRLSHFT_1_RANK1_BYTE0_DATA_BRLSHFT_SHIFT)
+
+#define EMC_DQS_BRLSHFT_0                                       0x594
+#define EMC_DQS_BRLSHFT_1                                       0x598
+#define EMC_CMD_BRLSHFT_0                                       0x59c
+#define EMC_CMD_BRLSHFT_1                                       0x5a0
+#define EMC_CMD_BRLSHFT_2                                       0x5a4
+#define EMC_CMD_BRLSHFT_3                                       0x5a8
+#define EMC_QUSE_BRLSHFT_0                                      0x5ac
+#define EMC_QUSE_BRLSHFT_1                                      0x5b8
+#define EMC_QUSE_BRLSHFT_2                                      0x5bc
+#define EMC_QUSE_BRLSHFT_3                                      0x5c4
+#define EMC_FBIO_CFG8                                           0x5c8
+#define EMC_CMD_MAPPING_CMD0_0                                  0x380
+#define EMC_CMD_MAPPING_CMD0_1                                  0x384
+#define EMC_CMD_MAPPING_CMD0_2                                  0x388
+#define EMC_CMD_MAPPING_CMD1_0                                  0x38c
+#define EMC_CMD_MAPPING_CMD1_1                                  0x390
+#define EMC_CMD_MAPPING_CMD1_2                                  0x394
+#define EMC_CMD_MAPPING_CMD2_0                                  0x398
+#define EMC_CMD_MAPPING_CMD2_1                                  0x39c
+#define EMC_CMD_MAPPING_CMD2_2                                  0x3a0
+#define EMC_CMD_MAPPING_CMD3_0                                  0x3a4
+#define EMC_CMD_MAPPING_CMD3_1                                  0x3a8
+#define EMC_CMD_MAPPING_CMD3_2                                  0x3ac
+#define EMC_CMD_MAPPING_BYTE                                    0x3b0
+#define EMC_DYN_SELF_REF_CONTROL                                0x3e0
+#define EMC_TXSRDLL                                             0x3e4
+#define EMC_CCFIFO_ADDR                                         0x3e8
+#define EMC_CCFIFO_DATA                                         0x3ec
+#define EMC_CCFIFO_STATUS                                       0x3f0
+#define EMC_SWIZZLE_RANK0_BYTE0                                 0x404
+#define EMC_SWIZZLE_RANK0_BYTE1                                 0x408
+#define EMC_SWIZZLE_RANK0_BYTE2                                 0x40c
+#define EMC_SWIZZLE_RANK0_BYTE3                                 0x410
+#define EMC_SWIZZLE_RANK1_BYTE0                                 0x418
+#define EMC_SWIZZLE_RANK1_BYTE1                                 0x41c
+#define EMC_SWIZZLE_RANK1_BYTE2                                 0x420
+#define EMC_SWIZZLE_RANK1_BYTE3                                 0x424
+#define EMC_TR_TIMING_0                                         0x3b4
+#define EMC_TR_CTRL_0                                           0x3b8
+#define EMC_TR_CTRL_1                                           0x3bc
+#define EMC_TR_DVFS                                             0x460
+#define EMC_TR_DVFS_TRAINING_DVFS                               (1 << 0)
+
+#define EMC_SWITCH_BACK_CTRL                                    0x3c0
+#define EMC_TR_RDV                                              0x3c4
+#define EMC_TR_QPOP                                             0x3f4
+#define EMC_TR_RDV_MASK                                         0x3f8
+#define EMC_TR_QSAFE                                            0x3fc
+#define EMC_TR_QRST                                             0x400
+#define EMC_IBDLY                                               0x468
+#define EMC_OBDLY                                               0x46c
+#define EMC_TXDSRVTTGEN                                         0x480
+#define EMC_WE_DURATION                                         0x48c
+#define EMC_WS_DURATION                                         0x490
+#define EMC_WEV                                                 0x494
+#define EMC_WSV                                                 0x498
+#define EMC_CFG_3                                               0x49c
+#define EMC_CFG_PIPE_2                                          0x554
+#define EMC_CFG_PIPE_CLK                                        0x558
+#define EMC_CFG_PIPE_CLK_CLK_ALWAYS_ON                          (1 << 0)
+
+#define EMC_CFG_PIPE_1                                          0x55c
+#define EMC_CFG_PIPE                                            0x560
+#define EMC_QPOP                                                0x564
+#define EMC_QUSE_WIDTH                                          0x568
+#define EMC_PUTERM_WIDTH                                        0x56c
+#define EMC_PROTOBIST_CONFIG_ADR_1                              0x5d0
+#define EMC_PROTOBIST_CONFIG_ADR_2                              0x5d4
+#define EMC_PROTOBIST_MISC                                      0x5d8
+#define EMC_PROTOBIST_WDATA_LOWER                               0x5dc
+#define EMC_PROTOBIST_WDATA_UPPER                               0x5e0
+#define EMC_PROTOBIST_RDATA                                     0x5ec
+#define EMC_DLL_CFG_0                                           0x5e4
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_IGNORE_START                 (1 << 29)
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_DUAL_PASS_LOCK               (1 << 28)
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT              24
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_MASK               \
+        (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_STEP_SIZE_SHIFT)
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT              20
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_MASK               \
+        (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_END_COUNT_SHIFT)
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT            16
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_MASK             \
+        (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_FILTER_BITS_SHIFT)
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT           12
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_MASK            \
+        (0xf << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_COUNT_SHIFT)
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT           4
+#define EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_MASK            \
+        (0xff << EMC_DLL_CFG_0_DDLLCAL_CTRL_SAMPLE_DELAY_SHIFT)
+#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT            0
+#define EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_MASK             \
+        (0xf << EMC_DLL_CFG_0_DDLLCAL_UPDATE_CNT_LIMIT_SHIFT)
+
+#define EMC_DLL_CFG_1                                           0x5e8
+#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT             10
+#define EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_MASK              \
+        (0x7ff << EMC_DLL_CFG_1_DDLLCAL_CTRL_START_TRIM_SHIFT)
+
+#define EMC_TRAINING_CMD                                        0xe00
+#define EMC_TRAINING_CMD_PRIME                                  (1 << 0)
+#define EMC_TRAINING_CMD_CA                                     (1 << 1)
+#define EMC_TRAINING_CMD_RD                                     (1 << 2)
+#define EMC_TRAINING_CMD_WR                                     (1 << 3)
+#define EMC_TRAINING_CMD_QUSE                                   (1 << 4)
+#define EMC_TRAINING_CMD_CA_VREF                                (1 << 5)
+#define EMC_TRAINING_CMD_RD_VREF                                (1 << 6)
+#define EMC_TRAINING_CMD_WR_VREF                                (1 << 7)
+#define EMC_TRAINING_CMD_QUSE_VREF                              (1 << 8)
+#define EMC_TRAINING_CMD_GO                                     (1 << 31)
+
+#define EMC_TRAINING_CTRL                                       0xe04
+#define EMC_TRAINING_CTRL_SWAP_RANK                             (1 << 14)
+
+#define EMC_TRAINING_STATUS                                     0xe08
+#define EMC_TRAINING_QUSE_CORS_CTRL                             0xe0c
+#define EMC_TRAINING_QUSE_FINE_CTRL                             0xe10
+#define EMC_TRAINING_QUSE_CTRL_MISC                             0xe14
+#define EMC_TRAINING_WRITE_FINE_CTRL                            0xe18
+#define EMC_TRAINING_WRITE_CTRL_MISC                            0xe1c
+#define EMC_TRAINING_WRITE_VREF_CTRL                            0xe20
+#define EMC_TRAINING_READ_FINE_CTRL                             0xe24
+#define EMC_TRAINING_READ_CTRL_MISC                             0xe28
+#define EMC_TRAINING_READ_VREF_CTRL                             0xe2c
+#define EMC_TRAINING_CA_FINE_CTRL                               0xe30
+#define EMC_TRAINING_CA_CTRL_MISC                               0xe34
+#define EMC_TRAINING_CA_CTRL_MISC1                              0xe38
+#define EMC_TRAINING_CA_VREF_CTRL                               0xe3c
+#define EMC_TRAINING_CA_TADR_CTRL                               0xe40
+#define EMC_TRAINING_SETTLE                                     0xe44
+#define EMC_TRAINING_DEBUG_CTRL                                 0xe48
+#define EMC_TRAINING_DEBUG_DQ0                                  0xe4c
+#define EMC_TRAINING_DEBUG_DQ1                                  0xe50
+#define EMC_TRAINING_DEBUG_DQ2                                  0xe54
+#define EMC_TRAINING_DEBUG_DQ3                                  0xe58
+#define EMC_TRAINING_MPC                                        0xe5c
+#define EMC_TRAINING_PATRAM_CTRL                                0xe60
+#define EMC_TRAINING_PATRAM_DQ                                  0xe64
+#define EMC_TRAINING_PATRAM_DMI                                 0xe68
+#define EMC_TRAINING_VREF_SETTLE                                0xe6c
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE0                     0xe70
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE1                     0xe74
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE2                     0xe78
+#define EMC_TRAINING_RW_EYE_CENTER_IB_BYTE3                     0xe7c
+#define EMC_TRAINING_RW_EYE_CENTER_IB_MISC                      0xe80
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE0                     0xe84
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE1                     0xe88
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE2                     0xe8c
+#define EMC_TRAINING_RW_EYE_CENTER_OB_BYTE3                     0xe90
+#define EMC_TRAINING_RW_EYE_CENTER_OB_MISC                      0xe94
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE0                         0xe98
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE1                         0xe9c
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE2                         0xea0
+#define EMC_TRAINING_RW_OFFSET_IB_BYTE3                         0xea4
+#define EMC_TRAINING_RW_OFFSET_IB_MISC                          0xea8
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE0                         0xeac
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE1                         0xeb0
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE2                         0xeb4
+#define EMC_TRAINING_RW_OFFSET_OB_BYTE3                         0xeb8
+#define EMC_TRAINING_RW_OFFSET_OB_MISC                          0xebc
+#define EMC_TRAINING_OPT_CA_VREF                                0xec0
+#define EMC_TRAINING_OPT_DQ_OB_VREF                             0xec4
+#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK0                       0xec8
+#define EMC_TRAINING_OPT_DQ_IB_VREF_RANK1                       0xecc
+#define EMC_TRAINING_QUSE_VREF_CTRL                             0xed0
+#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK0                      0xed4
+#define EMC_TRAINING_OPT_DQS_IB_VREF_RANK1                      0xed8
+#define EMC_TRAINING_DRAMC_TIMING                               0xedc
+#define EMC_PMACRO_QUSE_DDLL_RANK0_0                            0x600
+#define EMC_PMACRO_QUSE_DDLL_RANK0_1                            0x604
+#define EMC_PMACRO_QUSE_DDLL_RANK0_2                            0x608
+#define EMC_PMACRO_QUSE_DDLL_RANK0_3                            0x60c
+#define EMC_PMACRO_QUSE_DDLL_RANK0_4                            0x610
+#define EMC_PMACRO_QUSE_DDLL_RANK0_5                            0x614
+#define EMC_PMACRO_QUSE_DDLL_RANK1_0                            0x620
+#define EMC_PMACRO_QUSE_DDLL_RANK1_1                            0x624
+#define EMC_PMACRO_QUSE_DDLL_RANK1_2                            0x628
+#define EMC_PMACRO_QUSE_DDLL_RANK1_3                            0x62c
+#define EMC_PMACRO_QUSE_DDLL_RANK1_4                            0x630
+#define EMC_PMACRO_QUSE_DDLL_RANK1_5                            0x634
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0                      0x640
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE1_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0_OB_DDLL_LONG_DQ_RANK0_BYTE0_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1                      0x644
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE3_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1_OB_DDLL_LONG_DQ_RANK0_BYTE2_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2                      0x648
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE5_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2_OB_DDLL_LONG_DQ_RANK0_BYTE4_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3                      0x64c
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE7_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3_OB_DDLL_LONG_DQ_RANK0_BYTE6_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4                      0x650
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5                      0x654
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0                      0x660
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE1_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0_OB_DDLL_LONG_DQ_RANK1_BYTE0_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1                      0x664
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE3_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1_OB_DDLL_LONG_DQ_RANK1_BYTE2_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2                      0x668
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE5_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2_OB_DDLL_LONG_DQ_RANK1_BYTE4_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3                      0x66c
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT \
+        16
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE7_SHIFT
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT \
+        0
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_MASK \
+        0x3ff <<                                                        \
+        EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3_OB_DDLL_LONG_DQ_RANK1_BYTE6_SHIFT
+
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_4                      0x670
+#define EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_5                      0x674
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_0                     0x680
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_1                     0x684
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_2                     0x688
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_3                     0x68c
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_4                     0x690
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK0_5                     0x694
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_0                     0x6a0
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_1                     0x6a4
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_2                     0x6a8
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_3                     0x6ac
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_4                     0x6b0
+#define EMC_PMACRO_OB_DDLL_LONG_DQS_RANK1_5                     0x6b4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0                     0x6c0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1                     0x6c4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2                     0x6c8
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3                     0x6cc
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_4                     0x6d0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_5                     0x6d4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0                     0x6e0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1                     0x6e4
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2                     0x6e8
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3                     0x6ec
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_4                     0x6f0
+#define EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_5                     0x6f4
+#define EMC_PMACRO_TX_PWRD_0                                    0x720
+#define EMC_PMACRO_TX_PWRD_1                                    0x724
+#define EMC_PMACRO_TX_PWRD_2                                    0x728
+#define EMC_PMACRO_TX_PWRD_3                                    0x72c
+#define EMC_PMACRO_TX_PWRD_4                                    0x730
+#define EMC_PMACRO_TX_PWRD_5                                    0x734
+#define EMC_PMACRO_TX_SEL_CLK_SRC_0                             0x740
+#define EMC_PMACRO_TX_SEL_CLK_SRC_1                             0x744
+#define EMC_PMACRO_TX_SEL_CLK_SRC_3                             0x74c
+#define EMC_PMACRO_TX_SEL_CLK_SRC_2                             0x748
+#define EMC_PMACRO_TX_SEL_CLK_SRC_4                             0x750
+#define EMC_PMACRO_TX_SEL_CLK_SRC_5                             0x754
+#define EMC_PMACRO_DDLL_BYPASS                                  0x760
+#define EMC_PMACRO_DDLL_PWRD_0                                  0x770
+#define EMC_PMACRO_DDLL_PWRD_1                                  0x774
+#define EMC_PMACRO_DDLL_PWRD_2                                  0x778
+#define EMC_PMACRO_CMD_CTRL_0                                   0x780
+#define EMC_PMACRO_CMD_CTRL_1                                   0x784
+#define EMC_PMACRO_CMD_CTRL_2                                   0x788
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0               0x800
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1               0x804
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2               0x808
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_3               0x80c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0               0x810
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1               0x814
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2               0x818
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_3               0x81c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0               0x820
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1               0x824
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2               0x828
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_3               0x82c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0               0x830
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1               0x834
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2               0x838
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_3               0x83c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0               0x840
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1               0x844
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2               0x848
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_3               0x84c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0               0x850
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1               0x854
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2               0x858
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_3               0x85c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0               0x860
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1               0x864
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2               0x868
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_3               0x86c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0               0x870
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1               0x874
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2               0x878
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_3               0x87c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0                0x880
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1                0x884
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2                0x888
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_3                0x88c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0                0x890
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1                0x894
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2                0x898
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_3                0x89c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0                0x8a0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1                0x8a4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2                0x8a8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_3                0x8ac
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0                0x8b0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1                0x8b4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2                0x8b8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_3                0x8bc
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0               0x900
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1               0x904
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2               0x908
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_3               0x90c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0               0x910
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1               0x914
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2               0x918
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_3               0x91c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0               0x920
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1               0x924
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2               0x928
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_3               0x92c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0               0x930
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1               0x934
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2               0x938
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_3               0x93c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0               0x940
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1               0x944
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2               0x948
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_3               0x94c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0               0x950
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1               0x954
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2               0x958
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_3               0x95c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0               0x960
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1               0x964
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2               0x968
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_3               0x96c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0               0x970
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1               0x974
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2               0x978
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_3               0x97c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_0                0x980
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_1                0x984
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_2                0x988
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD0_3                0x98c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_0                0x990
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_1                0x994
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_2                0x998
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD1_3                0x99c
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_0                0x9a0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_1                0x9a4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_2                0x9a8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD2_3                0x9ac
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_0                0x9b0
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_1                0x9b4
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_2                0x9b8
+#define EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_CMD3_3                0x9bc
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0               0xa00
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1               0xa04
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2               0xa08
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0               0xa10
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1               0xa14
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2               0xa18
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0               0xa20
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1               0xa24
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2               0xa28
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0               0xa30
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1               0xa34
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2               0xa38
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0               0xa40
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1               0xa44
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2               0xa48
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0               0xa50
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1               0xa54
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2               0xa58
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0               0xa60
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1               0xa64
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2               0xa68
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0               0xa70
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1               0xa74
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2               0xa78
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_0                0xa80
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_1                0xa84
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD0_2                0xa88
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_0                0xa90
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_1                0xa94
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD1_2                0xa98
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_0                0xaa0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_1                0xaa4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD2_2                0xaa8
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_0                0xab0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_1                0xab4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_CMD3_2                0xab8
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0               0xb00
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1               0xb04
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2               0xb08
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0               0xb10
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1               0xb14
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2               0xb18
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0               0xb20
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1               0xb24
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2               0xb28
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0               0xb30
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1               0xb34
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2               0xb38
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0               0xb40
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1               0xb44
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2               0xb48
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0               0xb50
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1               0xb54
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2               0xb58
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0               0xb60
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1               0xb64
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2               0xb68
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0               0xb70
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1               0xb74
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2               0xb78
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_0                0xb80
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_1                0xb84
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD0_2                0xb88
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_0                0xb90
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_1                0xb94
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD1_2                0xb98
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_0                0xba0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_1                0xba4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD2_2                0xba8
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_0                0xbb0
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_1                0xbb4
+#define EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_CMD3_2                0xbb8
+#define EMC_PMACRO_IB_VREF_DQ_0                                 0xbe0
+#define EMC_PMACRO_IB_VREF_DQ_1                                 0xbe4
+#define EMC_PMACRO_IB_VREF_DQ_2                                 0xbe8
+#define EMC_PMACRO_IB_VREF_DQS_0                                0xbf0
+#define EMC_PMACRO_IB_VREF_DQS_1                                0xbf4
+#define EMC_PMACRO_IB_VREF_DQS_2                                0xbf8
+#define EMC_PMACRO_IB_RXRT                                      0xcf4
+#define EMC_PMACRO_DDLL_LONG_CMD_0                              0xc00
+#define EMC_PMACRO_DDLL_LONG_CMD_1                              0xc04
+#define EMC_PMACRO_DDLL_LONG_CMD_2                              0xc08
+#define EMC_PMACRO_DDLL_LONG_CMD_3                              0xc0c
+#define EMC_PMACRO_DDLL_LONG_CMD_4                              0xc10
+#define EMC_PMACRO_DDLL_LONG_CMD_5                              0xc14
+#define EMC_PMACRO_DDLL_SHORT_CMD_0                             0xc20
+#define EMC_PMACRO_DDLL_SHORT_CMD_1                             0xc24
+#define EMC_PMACRO_DDLL_SHORT_CMD_2                             0xc28
+#define EMC_PMACRO_CFG_PM_GLOBAL_0                              0xc30
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE0            (1 << 16)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE1            (1 << 17)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE2            (1 << 18)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE3            (1 << 19)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE4            (1 << 20)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE5            (1 << 21)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE6            (1 << 22)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_BYTE7            (1 << 23)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD0             (1 << 24)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD1             (1 << 25)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD2             (1 << 26)
+#define EMC_PMACRO_CFG_PM_GLOBAL_0_DISABLE_CFG_CMD3             (1 << 27)
+
+#define EMC_PMACRO_VTTGEN_CTRL_0                                0xc34
+#define EMC_PMACRO_VTTGEN_CTRL_1                                0xc38
+#define EMC_PMACRO_VTTGEN_CTRL_2                                0xcf0
+#define EMC_PMACRO_BG_BIAS_CTRL_0                               0xc3c
+#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_E_PWRD                     (1 << 0)
+#define EMC_PMACRO_BG_BIAS_CTRL_0_BG_MODE                       (1 << 1)
+#define EMC_PMACRO_BG_BIAS_CTRL_0_BGLP_E_PWRD                   (1 << 2)
+
+#define EMC_PMACRO_PAD_CFG_CTRL                                 0xc40
+#define EMC_PMACRO_CMD_PAD_RX_CTRL                              0xc50
+#define EMC_PMACRO_DATA_PAD_RX_CTRL                             0xc54
+#define EMC_PMACRO_CMD_RX_TERM_MODE                             0xc58
+#define EMC_PMACRO_DATA_RX_TERM_MODE                            0xc5c
+#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT 8
+#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK (0x3 << \
+        EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_SHIFT)
+#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT 4
+#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK (0x3 << \
+        EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_SHIFT)
+#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT   0
+#define EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK   (0x3 << \
+        EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_SHIFT)
+
+/* Convenience macro... */
+#define RX_TERM_MODE                                                    \
+        ~(EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSN_RX_TERM_MODE_MASK |    \
+          EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQSP_RX_TERM_MODE_MASK |    \
+          EMC_PMACRO_DATA_RX_TERM_MODE_DATA_DQ_RX_TERM_MODE_MASK)
+
+#define EMC_PMACRO_CMD_PAD_TX_CTRL                              0xc60
+#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_E_DCC              (1 << 1)
+#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSP_TX_E_DCC            (1 << 9)
+#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQSN_TX_E_DCC            (1 << 16)
+#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_CMD_TX_E_DCC             (1 << 24)
+#define EMC_PMACRO_CMD_PAD_TX_CTRL_CMD_DQ_TX_DRVFORCEON         (1 << 26)
+
+#define EMC_PMACRO_DATA_PAD_TX_CTRL                             0xc64
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_E_IVREF             (1 << 0)
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQ_TX_E_DCC            (1 << 1)
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQS_E_IVREF            (1 << 8)
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSP_TX_E_DCC          (1 << 9)
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_DQSN_TX_E_DCC          (1 << 16)
+#define EMC_PMACRO_DATA_PAD_TX_CTRL_DATA_CMD_TX_E_DCC           (1 << 24)
+
+#define EMC_PMACRO_COMMON_PAD_TX_CTRL                           0xc68
+#define EMC_PMACRO_BRICK_MAPPING_0                              0xc80
+#define EMC_PMACRO_BRICK_MAPPING_1                              0xc84
+#define EMC_PMACRO_BRICK_MAPPING_2                              0xc88
+#define EMC_PMACRO_DDLLCAL_CAL                                  0xce0
+#define EMC_PMACRO_DDLL_OFFSET                                  0xce4
+#define EMC_PMACRO_DDLL_PERIODIC_OFFSET                         0xce8
+#define EMC_PMACRO_BRICK_CTRL_RFU1                              0x330
+#define EMC_PMACRO_BRICK_CTRL_RFU2                              0x334
+#define EMC_PMACRO_CMD_BRICK_CTRL_FDPD                          0x318
+#define EMC_PMACRO_DATA_BRICK_CTRL_FDPD                         0x31c
+#define EMC_PMACRO_TRAINING_CTRL_0                              0xcf8
+#define EMC_PMACRO_TRAINING_CTRL_0_CH0_TRAINING_E_WRPTR         (1 << 3)
+
+#define EMC_PMACRO_TRAINING_CTRL_1                              0xcfc
+#define EMC_PMACRO_TRAINING_CTRL_1_CH1_TRAINING_E_WRPTR         (1 << 3)
+
+#define EMC_PMC_SCRATCH1                                        0x440
+#define EMC_PMC_SCRATCH2                                        0x444
+#define EMC_PMC_SCRATCH3                                        0x448
+
+
+#define MC_EMEM_ARB_MISC0_EMC_SAME_FREQ         (1 << 27)
+#define MC_EMEM_ARB_MISC1                       0xdc
+#define MC_EMEM_ARB_RING1_THROTTLE              0xe0
+#define MC_EMEM_ARB_RING3_THROTTLE              0xe4
+#define MC_EMEM_ARB_OVERRIDE                    0xe8
+#define MC_EMEM_ARB_RSV                         0xec
+
+#define MC_CLKEN_OVERRIDE                       0xf4
+#define MC_TIMING_CONTROL_DBG                   0xf8
+#define MC_TIMING_CONTROL                       0xfc
+#define MC_EMEM_ARB_ISOCHRONOUS_0               0x208
+#define MC_EMEM_ARB_ISOCHRONOUS_1               0x20c
+#define MC_EMEM_ARB_ISOCHRONOUS_2               0x210
+#define MC_EMEM_ARB_HYSTERESIS_0_0              0x218
+#define MC_EMEM_ARB_HYSTERESIS_1_0              0x21c
+#define MC_EMEM_ARB_HYSTERESIS_2_0              0x220
+#define MC_EMEM_ARB_HYSTERESIS_3_0              0x224
+
+#define HYST_SATAR                              (0x1 << 31)
+#define HYST_PPCSAHBSLVR                        (0x1 << 30)
+#define HYST_PPCSAHBDMAR                        (0x1 << 29)
+#define HYST_NVENCSRD                           (0x1 << 28)
+#define HYST_HOST1XR                            (0x1 << 23)
+#define HYST_HOST1XDMAR                         (0x1 << 22)
+#define HYST_HDAR                               (0x1 << 21)
+#define HYST_DISPLAYHCB                         (0x1 << 17)
+#define HYST_DISPLAYHC                          (0x1 << 16)
+#define HYST_AVPCARM7R                          (0x1 << 15)
+#define HYST_AFIR                               (0x1 << 14)
+#define HYST_DISPLAY0CB                         (0x1 << 6)
+#define HYST_DISPLAY0C                          (0x1 << 5)
+#define HYST_DISPLAY0BB                         (0x1 << 4)
+#define HYST_DISPLAY0B                          (0x1 << 3)
+#define HYST_DISPLAY0AB                         (0x1 << 2)
+#define HYST_DISPLAY0A                          (0x1 << 1)
+#define HYST_PTCR                               (0x1 << 0)
+
+#define HYST_VDEDBGW                            (0x1 << 31)
+#define HYST_VDEBSEVW                           (0x1 << 30)
+#define HYST_SATAW                              (0x1 << 29)
+#define HYST_PPCSAHBSLVW                        (0x1 << 28)
+#define HYST_PPCSAHBDMAW                        (0x1 << 27)
+#define HYST_MPCOREW                            (0x1 << 25)
+#define HYST_MPCORELPW                          (0x1 << 24)
+#define HYST_HOST1XW                            (0x1 << 22)
+#define HYST_HDAW                               (0x1 << 21)
+#define HYST_AVPCARM7W                          (0x1 << 18)
+#define HYST_AFIW                               (0x1 << 17)
+#define HYST_NVENCSWR                           (0x1 << 11)
+#define HYST_MPCORER                            (0x1 << 7)
+#define HYST_MPCORELPR                          (0x1 << 6)
+#define HYST_VDETPER                            (0x1 << 5)
+#define HYST_VDEMCER                            (0x1 << 4)
+#define HYST_VDEMBER                            (0x1 << 3)
+#define HYST_VDEBSEVR                           (0x1 << 2)
+
+#define HYST_DISPLAYT                           (0x1 << 26)
+#define HYST_GPUSWR                             (0x1 << 25)
+#define HYST_GPUSRD                             (0x1 << 24)
+#define HYST_A9AVPSCW                           (0x1 << 23)
+#define HYST_A9AVPSCR                           (0x1 << 22)
+#define HYST_TSECSWR                            (0x1 << 21)
+#define HYST_TSECSRD                            (0x1 << 20)
+#define HYST_ISPWBB                             (0x1 << 17)
+#define HYST_ISPWAB                             (0x1 << 16)
+#define HYST_ISPRAB                             (0x1 << 14)
+#define HYST_XUSB_DEVW                          (0x1 << 13)
+#define HYST_XUSB_DEVR                          (0x1 << 12)
+#define HYST_XUSB_HOSTW                         (0x1 << 11)
+#define HYST_XUSB_HOSTR                         (0x1 << 10)
+#define HYST_ISPWB                              (0x1 << 7)
+#define HYST_ISPWA                              (0x1 << 6)
+#define HYST_ISPRA                              (0x1 << 4)
+#define HYST_VDETPMW                            (0x1 << 1)
+#define HYST_VDEMBEW                            (0x1 << 0)
+
+#define HYST_DISPLAYD                           (0x1 << 19)
+#define HYST_VIW                                (0x1 << 18)
+#define HYST_VICSWR                             (0x1 << 13)
+#define HYST_VICSRD                             (0x1 << 12)
+#define HYST_SDMMCWAB                           (0x1 << 7)
+#define HYST_SDMMCW                             (0x1 << 6)
+#define HYST_SDMMCWAA                           (0x1 << 5)
+#define HYST_SDMMCWA                            (0x1 << 4)
+#define HYST_SDMMCRAB                           (0x1 << 3)
+#define HYST_SDMMCR                             (0x1 << 2)
+#define HYST_SDMMCRAA                           (0x1 << 1)
+#define HYST_SDMMCRA                            (0x1 << 0)
+
+#endif
diff --git a/include/linux/platform/tegra/tegra_cl_dvfs.h b/include/linux/platform/tegra/tegra_cl_dvfs.h
new file mode 100644
index 000000000..5f408494e
--- /dev/null
+++ b/include/linux/platform/tegra/tegra_cl_dvfs.h
@@ -0,0 +1,159 @@
+/*
+ * include/linux/platform/tegra/tegra_cl_dvfs.h
+ *
+ * Copyright (c) 2012-2015 NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _TEGRA_CL_DVFS_H_
+#define _TEGRA_CL_DVFS_H_
+
+struct tegra_cl_dvfs;
+struct pinctrl_dev;
+
+#define MAX_CL_DVFS_VOLTAGES            33
+
+enum tegra_cl_dvfs_force_mode {
+        TEGRA_CL_DVFS_FORCE_NONE = 0,
+        TEGRA_CL_DVFS_FORCE_FIXED = 1,
+        TEGRA_CL_DVFS_FORCE_AUTO = 2,
+};
+
+enum tegra_cl_dvfs_pmu_if {
+        TEGRA_CL_DVFS_PMU_I2C,
+        TEGRA_CL_DVFS_PMU_PWM,
+};
+
+enum tegra_cl_dvfs_pwm_bus {
+        TEGRA_CL_DVFS_PWM_1WIRE_BUFFER,
+        TEGRA_CL_DVFS_PWM_1WIRE_DIRECT,
+        TEGRA_CL_DVFS_PWM_2WIRE,
+};
+
+/* CL DVFS plaform flags*/
+/* set if output to PMU can be disabled only between I2C transactions */
+#define TEGRA_CL_DVFS_FLAGS_I2C_WAIT_QUIET      (0x1UL << 0)
+/* dynamic output registers update is supported */
+#define TEGRA_CL_DVFS_DYN_OUTPUT_CFG            (0x1UL << 1)
+/* monitor data new synchronization can not be used */
+#define TEGRA_CL_DVFS_DATA_NEW_NO_USE           (0x1UL << 2)
+/* set if control settings are overridden when CPU is idle */
+#define TEGRA_CL_DVFS_HAS_IDLE_OVERRIDE         (0x1UL << 3)
+/* set if calibration should be deferred for voltage matching force value */
+#define TEGRA_CL_DVFS_DEFER_FORCE_CALIBRATE     (0x1UL << 4)
+/* set if request scale is applied in open loop (not set: enforce 1:1 scale) */
+#define TEGRA_CL_DVFS_SCALE_IN_OPEN_LOOP        (0x1UL << 5)
+/* set if min output is forced during calibration */
+#define TEGRA_CL_DVFS_CALIBRATE_FORCE_VMIN      (0x1UL << 6)
+
+
+
+struct tegra_cl_dvfs_cfg_param {
+        unsigned long   sample_rate;
+
+        enum tegra_cl_dvfs_force_mode force_mode;
+        u8              cf;
+        u8              ci;
+        s8              cg;
+        bool            cg_scale;
+
+        u8              droop_cut_value;
+        u8              droop_restore_ramp;
+        u8              scale_out_ramp;
+};
+
+struct voltage_reg_map {
+        u8              reg_value;
+        int             reg_uV;
+};
+
+struct tegra_cl_dvfs_platform_data {
+        const char *dfll_clk_name;
+        u32 flags;
+
+        enum tegra_cl_dvfs_pmu_if pmu_if;
+        union {
+                struct {
+                        unsigned long           fs_rate;
+                        unsigned long           hs_rate; /* if 0 - no hs mode */
+                        u8                      hs_master_code;
+                        u8                      reg;
+                        u16                     slave_addr;
+                        bool                    addr_10;
+                        u32                     sel_mul;
+                        u32                     sel_offs;
+                } pmu_i2c;
+                struct {
+                        unsigned long           pwm_rate;
+                        bool                    delta_mode;
+                        int                     min_uV;
+                        int                     step_uV;
+                        int                     init_uV;
+
+                        enum tegra_cl_dvfs_pwm_bus pwm_bus;
+                        int                     pwm_pingroup;
+                        int                     pwm_clk_pingroup;
+                        int                     out_gpio;
+                        bool                    out_enable_high;
+                        struct platform_device  *dfll_bypass_dev;
+                        struct pinctrl_dev      *pinctrl_dev;
+                } pmu_pwm;
+        } u;
+
+        struct voltage_reg_map  *vdd_map;
+        int                     vdd_map_size;
+        int                     pmu_undershoot_gb;
+        int                     resume_ramp_delay;
+        int                     tune_ramp_delay;
+
+        struct tegra_cl_dvfs_cfg_param          *cfg_param;
+};
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+int tegra_init_cl_dvfs(void);
+int tegra_cl_dvfs_debug_init(struct clk *dfll_clk);
+void tegra_cl_dvfs_resume(struct tegra_cl_dvfs *cld);
+
+/* functions below are called only within DFLL clock interface DFLL lock held */
+void tegra_cl_dvfs_disable(struct tegra_cl_dvfs *cld);
+int tegra_cl_dvfs_enable(struct tegra_cl_dvfs *cld);
+int tegra_cl_dvfs_lock(struct tegra_cl_dvfs *cld);
+int tegra_cl_dvfs_unlock(struct tegra_cl_dvfs *cld);
+int tegra_cl_dvfs_request_rate(struct tegra_cl_dvfs *cld, unsigned long rate);
+unsigned long tegra_cl_dvfs_request_get(struct tegra_cl_dvfs *cld);
+
+#else
+static inline int tegra_init_cl_dvfs(void)
+{ return -ENOSYS; }
+static inline int tegra_cl_dvfs_debug_init(struct clk *dfll_clk)
+{ return -ENOSYS; }
+static inline void tegra_cl_dvfs_resume(struct tegra_cl_dvfs *cld)
+{}
+
+static inline void tegra_cl_dvfs_disable(struct tegra_cl_dvfs *cld)
+{}
+static inline int tegra_cl_dvfs_enable(struct tegra_cl_dvfs *cld)
+{ return -ENOSYS; }
+static inline int tegra_cl_dvfs_lock(struct tegra_cl_dvfs *cld)
+{ return -ENOSYS; }
+static inline int tegra_cl_dvfs_unlock(struct tegra_cl_dvfs *cld)
+{ return -ENOSYS; }
+static inline int tegra_cl_dvfs_request_rate(
+        struct tegra_cl_dvfs *cld, unsigned long rate)
+{ return -ENOSYS; }
+static inline unsigned long tegra_cl_dvfs_request_get(struct tegra_cl_dvfs *cld)
+{ return 0; }
+#endif
+
+#endif
diff --git a/include/linux/platform/tegra/tegra_mc.h b/include/linux/platform/tegra/tegra_mc.h
new file mode 100644
index 000000000..9aae94d33
--- /dev/null
+++ b/include/linux/platform/tegra/tegra_mc.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2017-2018, NVIDIA Corporation.  All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __TEGRA_MC_H
+#define __TEGRA_MC_H
+
+/*
+ * API for reading carveout info.
+ */
+enum carveout_desc {
+        MC_SECURITY_CARVEOUT1 = 0,
+        MC_SECURITY_CARVEOUT2,
+        MC_SECURITY_CARVEOUT3,
+        MC_SECURITY_CARVEOUT4,
+        MC_NR_CARVEOUTS
+};
+
+struct mc_carveout_info {
+        enum carveout_desc desc;
+
+        u64 base;
+        u64 size;
+};
+
+#if defined(CONFIG_TEGRA_MC)
+
+/**
+ * Read from the MC.
+ *
+ * @idx The MC channel to read from.
+ * @reg The offset of the register to read.
+ *
+ * Read from the specified MC channel: 0 -> MC0, 1 -> MC1, etc. If @idx
+ * corresponds to a non-existent channel then 0 is returned.
+ */
+extern u32 tegra_mc_readl(u32 reg);
+
+/**
+ * Write to the MC.
+ *
+ * @idx The MC channel to write to.
+ * @val Value to write.
+ * @reg The offset of the register to write.
+ *
+ * Write to the specified MC channel: 0 -> MC0, 1 -> MC1, etc. For writes there
+ * is a special channel, %MC_BROADCAST_CHANNEL, which writes to all channels. If
+ * @idx corresponds to a non-existent channel then the write is dropped.
+ */
+extern void tegra_mc_writel(u32 val, u32 reg);
+
+extern int mc_get_carveout_info(struct mc_carveout_info *inf, int *nr,
+                         enum carveout_desc co);
+
+#else
+
+static inline u32 tegra_mc_readl(u32 reg)
+{
+        return 0xffffffff;
+}
+
+static inline void tegra_mc_writel(u32 val, u32 reg)
+{
+}
+
+static inline int mc_get_carveout_info(struct mc_carveout_info *inf, int *nr,
+                         enum carveout_desc co)
+{
+        return -ENODEV;
+}
+
+#endif
+
+#endif