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-rw-r--r--drivers/video/tegra/dc/dsi.c636
-rw-r--r--drivers/video/tegra/dc/dsi.h4
2 files changed, 444 insertions, 196 deletions
diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c
index 0c189609f..259307208 100644
--- a/drivers/video/tegra/dc/dsi.c
+++ b/drivers/video/tegra/dc/dsi.c
@@ -316,7 +316,7 @@ static int tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
316 ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt, 316 ret = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
317 dsi->syncpt_id, dsi->syncpt_val + 1); 317 dsi->syncpt_id, dsi->syncpt_val + 1);
318 if (ret < 0) { 318 if (ret < 0) {
319 printk(KERN_ERR "DSI sync point failure\n"); 319 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
320 goto fail; 320 goto fail;
321 } 321 }
322 322
@@ -504,7 +504,8 @@ static void tegra_dsi_init_sw(struct tegra_dc *dc,
504 if (dsi->info.enable_hs_clock_on_lp_cmd_mode) { 504 if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
505 if (dsi->info.video_clock_mode != 505 if (dsi->info.video_clock_mode !=
506 TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) 506 TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
507 printk(KERN_WARNING "Force clock continuous mode\n"); 507 dev_warn(&dc->ndev->dev,
508 "Force clock continuous mode\n");
508 509
509 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS; 510 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
510 } 511 }
@@ -874,7 +875,8 @@ void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
874 tegra_dc_writel(dc, val, DC_CMD_INT_MASK); 875 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
875 876
876 if (timeout == 0) 877 if (timeout == 0)
877 printk(KERN_WARNING "DC doesn't stop at end of frame.\n"); 878 dev_warn(&dc->ndev->dev,
879 "DC doesn't stop at end of frame.\n");
878} 880}
879 881
880static void tegra_dsi_start_dc_stream(struct tegra_dc *dc, 882static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
@@ -1259,15 +1261,15 @@ fail:
1259 return err; 1261 return err;
1260} 1262}
1261 1263
1262static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi) 1264static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
1263{ 1265{
1264 u32 timeout = 0; 1266 u32 timeout = 0;
1265 bool retVal; 1267 bool retVal = true;
1266 1268
1267 retVal = false;
1268 while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) { 1269 while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
1269 if (!tegra_dsi_readl(dsi, DSI_TRIGGER)) { 1270 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
1270 retVal = true; 1271 tegra_dsi_readl(dsi, DSI_TRIGGER))) {
1272 retVal = false;
1271 break; 1273 break;
1272 } 1274 }
1273 udelay(DSI_COMMAND_DELAY_STEPS_USEC); 1275 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
@@ -1277,6 +1279,244 @@ static bool tegra_dsi_is_controller_idle(struct tegra_dc_dsi_data *dsi)
1277 return retVal; 1279 return retVal;
1278} 1280}
1279 1281
1282static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
1283{
1284 u32 timeout = 0;
1285 bool retVal = true;
1286
1287 while (timeout < DSI_STATUS_POLLING_DURATION_USEC) {
1288 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
1289 tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
1290 retVal = false;
1291 break;
1292 }
1293 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1294 timeout += DSI_STATUS_POLLING_DELAY_USEC;
1295 }
1296
1297 return retVal;
1298}
1299
1300static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
1301{
1302 int err = 0;
1303
1304 if (tegra_dsi_write_busy(dsi)) {
1305 err = -EBUSY;
1306 dev_err(&dsi->dc->ndev->dev,
1307 "DSI trigger bit already set\n");
1308 goto fail;
1309 }
1310
1311 if (tegra_dsi_read_busy(dsi)) {
1312 err = -EBUSY;
1313 dev_err(&dsi->dc->ndev->dev,
1314 "DSI immediate bta bit already set\n");
1315 goto fail;
1316 }
1317fail:
1318 return err;
1319}
1320
1321static void tegra_dsi_reset_underflow_overflow
1322 (struct tegra_dc_dsi_data *dsi)
1323{
1324 u32 val;
1325
1326 val = tegra_dsi_readl(dsi, DSI_STATUS);
1327 val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1328 if (val) {
1329 dev_warn(&dsi->dc->ndev->dev, "Reset overflow/underflow\n");
1330 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1331 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1332 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1333 ndelay(200);
1334 }
1335}
1336
1337static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1338{
1339 u32 val;
1340
1341 tegra_dsi_writel(dsi,
1342 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1343 DSI_POWER_CONTROL);
1344 mdelay(1);
1345
1346 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE);
1347 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1348
1349 while (tegra_dsi_readl(dsi, DSI_POWER_CONTROL) != val)
1350 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
1351}
1352
1353static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
1354{
1355 u32 val;
1356
1357 val = tegra_dsi_readl(dsi, DSI_STATUS);
1358 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1359 if (val) {
1360 dev_warn(&dsi->dc->ndev->dev,
1361 "DSI read count not zero, resetting\n");
1362 tegra_dsi_soft_reset(dsi);
1363 }
1364}
1365
1366static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
1367 struct tegra_dc_dsi_data *dsi,
1368 struct tegra_dc *dc,
1369 u8 lp_op)
1370{
1371 struct dsi_status *init_status;
1372 int err;
1373
1374 init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
1375 if (!init_status)
1376 return ERR_PTR(-ENOMEM);
1377
1378 *init_status = dsi->status;
1379
1380 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1381 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1382 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1383 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi);
1384 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1385 if (dsi->info.hs_cmd_mode_supported) {
1386 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1387 if (err < 0) {
1388 dev_err(&dc->ndev->dev,
1389 "Switch to HS host mode failed\n");
1390 goto fail;
1391 }
1392 }
1393 }
1394 if (!dsi->info.hs_cmd_mode_supported) {
1395 err =
1396 tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1397 if (err < 0) {
1398 dev_err(&dc->ndev->dev,
1399 "DSI failed to go to LP mode\n");
1400 goto fail;
1401 }
1402 }
1403 } else if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE) {
1404 if (dsi->status.lp_op != lp_op) {
1405 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1406 if (err < 0) {
1407 dev_err(&dc->ndev->dev,
1408 "DSI failed to go to LP mode\n");
1409 goto fail;
1410 }
1411 }
1412 }
1413
1414 return init_status;
1415fail:
1416 kfree(init_status);
1417 return ERR_PTR(err);
1418}
1419
1420static struct dsi_status *tegra_dsi_prepare_host_transmission(
1421 struct tegra_dc *dc,
1422 struct tegra_dc_dsi_data *dsi,
1423 u8 lp_op)
1424{
1425 int err = 0;
1426 struct dsi_status *init_status;
1427
1428 if (dsi->status.init != DSI_MODULE_INIT ||
1429 dsi->ulpm) {
1430 err = -EPERM;
1431 goto fail;
1432 }
1433
1434 if (tegra_dsi_host_busy(dsi)) {
1435 err = -EBUSY;
1436 dev_err(&dc->ndev->dev, "DSI host busy\n");
1437 goto fail;
1438 }
1439
1440 tegra_dsi_reset_underflow_overflow(dsi);
1441
1442 if (lp_op == DSI_LP_OP_READ)
1443 tegra_dsi_reset_read_count(dsi);
1444
1445 if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
1446 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
1447 if (err < 0) {
1448 dev_err(&dc->ndev->dev, "Failed to config LP write\n");
1449 goto fail;
1450 }
1451 }
1452
1453 init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
1454 (dsi, dc, lp_op);
1455 if (IS_ERR_OR_NULL(init_status)) {
1456 err = PTR_ERR(init_status);
1457 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
1458 goto fail;
1459 }
1460
1461 return init_status;
1462fail:
1463 return ERR_PTR(err);
1464}
1465
1466static int tegra_dsi_restore_state(struct tegra_dc *dc,
1467 struct tegra_dc_dsi_data *dsi,
1468 struct dsi_status *init_status)
1469{
1470 bool switch_back_to_dc_mode = false;
1471 bool switch_back_to_hs_mode = false;
1472 bool restart_dc_stream;
1473 int err = 0;
1474
1475 switch_back_to_dc_mode = (dsi->status.driven ==
1476 DSI_DRIVEN_MODE_HOST &&
1477 init_status->driven ==
1478 DSI_DRIVEN_MODE_DC);
1479 switch_back_to_hs_mode = (dsi->status.lphs ==
1480 DSI_LPHS_IN_LP_MODE &&
1481 init_status->lphs ==
1482 DSI_LPHS_IN_HS_MODE);
1483 restart_dc_stream = (dsi->status.dc_stream ==
1484 DSI_DC_STREAM_DISABLE &&
1485 init_status->dc_stream ==
1486 DSI_DC_STREAM_ENABLE);
1487
1488 if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
1489 init_status->lphs == DSI_LPHS_IN_LP_MODE) {
1490 if (dsi->status.lp_op != init_status->lp_op) {
1491 err =
1492 tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
1493 if (err < 0) {
1494 dev_err(&dc->ndev->dev,
1495 "Failed to config LP mode\n");
1496 goto fail;
1497 }
1498 }
1499 goto success;
1500 }
1501
1502 if (switch_back_to_dc_mode)
1503 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1504 if (switch_back_to_dc_mode || switch_back_to_hs_mode) {
1505 err = tegra_dsi_set_to_hs_mode(dc, dsi);
1506 if (err < 0) {
1507 dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
1508 goto fail;
1509 }
1510 }
1511 if (restart_dc_stream)
1512 tegra_dsi_start_dc_stream(dc, dsi);
1513
1514success:
1515fail:
1516 kfree(init_status);
1517 return err;
1518}
1519
1280static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi) 1520static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1281{ 1521{
1282 int status = 0; 1522 int status = 0;
@@ -1292,12 +1532,16 @@ static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
1292#if DSI_USE_SYNC_POINTS 1532#if DSI_USE_SYNC_POINTS
1293 status = tegra_dsi_syncpt(dsi); 1533 status = tegra_dsi_syncpt(dsi);
1294 if (status < 0) { 1534 if (status < 0) {
1295 printk(KERN_ERR "DSI syncpt for host trigger failed\n"); 1535 dev_err(&dsi->dc->ndev->dev,
1536 "DSI syncpt for host trigger failed\n");
1296 goto fail; 1537 goto fail;
1297 } 1538 }
1298#else 1539#else
1299 if (!tegra_dsi_is_controller_idle(dsi)) 1540 if (tegra_dsi_write_busy(dsi)) {
1300 status = -EIO; 1541 status = -EBUSY;
1542 dev_err(&dsi->dc->ndev->dev,
1543 "Timeout waiting on write completion\n");
1544 }
1301#endif 1545#endif
1302 1546
1303fail: 1547fail:
@@ -1342,7 +1586,7 @@ static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
1342 1586
1343 err = tegra_dsi_host_trigger(dsi); 1587 err = tegra_dsi_host_trigger(dsi);
1344 if (err < 0) 1588 if (err < 0)
1345 printk(KERN_ERR "DSI host trigger failed\n"); 1589 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
1346 1590
1347 return err; 1591 return err;
1348} 1592}
@@ -1351,50 +1595,25 @@ int tegra_dsi_write_data(struct tegra_dc *dc,
1351 struct tegra_dc_dsi_data *dsi, 1595 struct tegra_dc_dsi_data *dsi,
1352 u8 *pdata, u8 data_id, u16 data_len) 1596 u8 *pdata, u8 data_id, u16 data_len)
1353{ 1597{
1354 bool switch_back_to_hs_mode; 1598 int err = 0;
1355 bool switch_back_to_dc_mode; 1599 struct dsi_status *init_status;
1356 int err;
1357
1358 err = 0;
1359 switch_back_to_hs_mode = false;
1360 switch_back_to_dc_mode = false;
1361 1600
1362 if ((dsi->status.init != DSI_MODULE_INIT) || 1601 tegra_dc_io_start(dc);
1363 (dsi->status.lphs == DSI_LPHS_NOT_INIT) ||
1364 (dsi->status.lp_op == DSI_LP_OP_NOT_INIT)) {
1365 err = -EPERM;
1366 goto fail;
1367 }
1368 1602
1369 if (!tegra_dsi_is_controller_idle(dsi)) { 1603 init_status = tegra_dsi_prepare_host_transmission(
1370 err = -EBUSY; 1604 dc, dsi, DSI_LP_OP_WRITE);
1605 if (IS_ERR_OR_NULL(init_status)) {
1606 err = PTR_ERR(init_status);
1607 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1371 goto fail; 1608 goto fail;
1372 } 1609 }
1373 1610
1374 err = 0;
1375
1376 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) {
1377 if (dsi->info.hs_cmd_mode_supported) {
1378 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) {
1379 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
1380 tegra_dsi_set_to_hs_mode(dc, dsi);
1381 switch_back_to_dc_mode = true;
1382 }
1383 } else {
1384 tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1385 switch_back_to_hs_mode = true;
1386 }
1387 }
1388
1389 err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len); 1611 err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
1390
1391
1392 if (switch_back_to_dc_mode)
1393 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
1394 if (switch_back_to_dc_mode || switch_back_to_hs_mode)
1395 tegra_dsi_set_to_hs_mode(dc, dsi);
1396
1397fail: 1612fail:
1613 err = tegra_dsi_restore_state(dc, dsi, init_status);
1614 if (err < 0)
1615 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1616 tegra_dc_io_end(dc);
1398 return err; 1617 return err;
1399} 1618}
1400EXPORT_SYMBOL(tegra_dsi_write_data); 1619EXPORT_SYMBOL(tegra_dsi_write_data);
@@ -1536,49 +1755,21 @@ static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
1536 err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt, 1755 err = nvhost_syncpt_wait(&dsi->dc->ndev->host->syncpt,
1537 dsi->syncpt_id, dsi->syncpt_val + 1); 1756 dsi->syncpt_id, dsi->syncpt_val + 1);
1538 if (err < 0) 1757 if (err < 0)
1539 printk(KERN_ERR "DSI sync point failure\n"); 1758 dev_err(&dsi->dc->ndev->dev,
1759 "DSI sync point failure\n");
1540 else 1760 else
1541 (dsi->syncpt_val)++; 1761 (dsi->syncpt_val)++;
1542#else 1762#else
1543 while (poll_time < DSI_STATUS_POLLING_DURATION_USEC) { 1763 if (tegra_dsi_read_busy(dsi)) {
1544 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1545 val &= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
1546 if (!val)
1547 break;
1548 udelay(DSI_STATUS_POLLING_DELAY_USEC);
1549 poll_time += DSI_STATUS_POLLING_DELAY_USEC;
1550 }
1551 if (poll_time > DSI_STATUS_POLLING_DURATION_USEC)
1552 err = -EBUSY; 1764 err = -EBUSY;
1765 dev_err(&dsi->dc->ndev->dev,
1766 "Timeout wating on read completion\n");
1767 }
1553#endif 1768#endif
1554 1769
1555 return err; 1770 return err;
1556} 1771}
1557 1772
1558static void tegra_dsi_read_fifo(struct tegra_dc *dc,
1559 struct tegra_dc_dsi_data *dsi,
1560 u32 rd_fifo_cnt, u8 *read_fifo)
1561{
1562 u32 val;
1563 u32 i;
1564
1565 /* Read data from FIFO */
1566 for (i = 0; i < rd_fifo_cnt; i++) {
1567 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1568 if (enable_read_debug)
1569 printk(KERN_INFO "Read data[%d]: 0x%x\n", i, val);
1570 memcpy(read_fifo, &val, 4);
1571 read_fifo += 4;
1572 }
1573
1574 /* Make sure all the data is read from the FIFO */
1575 val = tegra_dsi_readl(dsi, DSI_STATUS);
1576 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1577 if (val)
1578 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1579 " even after reading FIFO_RD_CNT words from read fifo\n");
1580}
1581
1582static int tegra_dsi_parse_read_response(struct tegra_dc *dc, 1773static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1583 u32 rd_fifo_cnt, u8 *read_fifo) 1774 u32 rd_fifo_cnt, u8 *read_fifo)
1584{ 1775{
@@ -1588,122 +1779,133 @@ static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
1588 payload_size = 0; 1779 payload_size = 0;
1589 err = 0; 1780 err = 0;
1590 1781
1591 printk(KERN_INFO "escape sequence[0x%x]\n", read_fifo[0]); 1782 switch (read_fifo[0]) {
1783 case DSI_ESCAPE_CMD:
1784 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
1785 break;
1786 case DSI_ACK_NO_ERR:
1787 dev_info(&dc->ndev->dev,
1788 "Panel ack, no err[0x%x]\n", read_fifo[0]);
1789 return err;
1790 default:
1791 dev_info(&dc->ndev->dev, "Invalid read response\n");
1792 break;
1793 }
1794
1592 switch (read_fifo[4] & 0xff) { 1795 switch (read_fifo[4] & 0xff) {
1593 case GEN_LONG_RD_RES: 1796 case GEN_LONG_RD_RES:
1594 /* Fall through */ 1797 /* Fall through */
1595 case DCS_LONG_RD_RES: 1798 case DCS_LONG_RD_RES:
1596 payload_size = (read_fifo[5] | 1799 payload_size = (read_fifo[5] |
1597 (read_fifo[6] << 8)) & 0xFFFF; 1800 (read_fifo[6] << 8)) & 0xFFFF;
1598 printk(KERN_INFO "Long read response Packet\n" 1801 dev_info(&dc->ndev->dev, "Long read response Packet\n"
1599 "payload_size[0x%x]\n", payload_size); 1802 "payload_size[0x%x]\n", payload_size);
1600 break; 1803 break;
1601 case GEN_1_BYTE_SHORT_RD_RES: 1804 case GEN_1_BYTE_SHORT_RD_RES:
1602 /* Fall through */ 1805 /* Fall through */
1603 case DCS_1_BYTE_SHORT_RD_RES: 1806 case DCS_1_BYTE_SHORT_RD_RES:
1604 payload_size = 1; 1807 payload_size = 1;
1605 printk(KERN_INFO "Short read response Packet\n" 1808 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1606 "payload_size[0x%x]\n", payload_size); 1809 "payload_size[0x%x]\n", payload_size);
1607 break; 1810 break;
1608 case GEN_2_BYTE_SHORT_RD_RES: 1811 case GEN_2_BYTE_SHORT_RD_RES:
1609 /* Fall through */ 1812 /* Fall through */
1610 case DCS_2_BYTE_SHORT_RD_RES: 1813 case DCS_2_BYTE_SHORT_RD_RES:
1611 payload_size = 2; 1814 payload_size = 2;
1612 printk(KERN_INFO "Short read response Packet\n" 1815 dev_info(&dc->ndev->dev, "Short read response Packet\n"
1613 "payload_size[0x%x]\n", payload_size); 1816 "payload_size[0x%x]\n", payload_size);
1614 break; 1817 break;
1615 case ACK_ERR_RES: 1818 case ACK_ERR_RES:
1616 payload_size = 2; 1819 payload_size = 2;
1617 printk(KERN_INFO "Acknowledge error report response\n" 1820 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
1618 "Packet payload_size[0x%x]\n", payload_size); 1821 "Packet payload_size[0x%x]\n", payload_size);
1619 break; 1822 break;
1620 default: 1823 default:
1621 /*reading from RD_FIFO_COUNT*/ 1824 dev_info(&dc->ndev->dev, "Invalid response packet\n");
1622 printk(KERN_INFO "Invalid read response payload_size\n");
1623 err = -EINVAL; 1825 err = -EINVAL;
1624 break; 1826 break;
1625 } 1827 }
1626 return err; 1828 return err;
1627} 1829}
1628 1830
1629int tegra_dsi_read_data(struct tegra_dc *dc, 1831static int tegra_dsi_read_fifo(struct tegra_dc *dc,
1630 struct tegra_dc_dsi_data *dsi, 1832 struct tegra_dc_dsi_data *dsi,
1631 u32 max_ret_payload_size, 1833 u8 *read_fifo)
1632 u32 panel_reg_addr, u8 *read_data)
1633{ 1834{
1634 u32 val; 1835 u32 val;
1635 int err; 1836 u32 i;
1636 u32 poll_time; 1837 u32 poll_time = 0;
1637 u32 rd_fifo_cnt; 1838 u32 rd_fifo_cnt;
1638 bool switch_back_to_hs_mode; 1839 int err = 0;
1639 bool restart_dc_stream; 1840 u8 *read_fifo_cp = read_fifo;
1640 bool switch_back_to_dc_mode;
1641 1841
1642 err = 0; 1842 while (poll_time < DSI_DELAY_FOR_READ_FIFO) {
1643 switch_back_to_hs_mode = false; 1843 mdelay(1);
1644 restart_dc_stream = false; 1844 val = tegra_dsi_readl(dsi, DSI_STATUS);
1645 switch_back_to_dc_mode = false; 1845 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1846 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1847 dev_err(&dc->ndev->dev,
1848 "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1849 break;
1850 poll_time++;
1851 }
1646 1852
1647 if ((dsi->status.init != DSI_MODULE_INIT) || 1853 if (rd_fifo_cnt == 0) {
1648 (dsi->status.lphs == DSI_LPHS_NOT_INIT) || 1854 dev_info(&dc->ndev->dev,
1649 (dsi->status.driven == DSI_DRIVEN_MODE_NOT_INIT)) { 1855 "DSI RD_FIFO_CNT is zero\n");
1650 err = -EPERM; 1856 err = -EINVAL;
1651 goto fail; 1857 goto fail;
1652 } 1858 }
1653 1859
1654 tegra_dc_io_start(dc); 1860 if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
1655 1861 DSI_STATUS_LB_OVERFLOW(0x1))) {
1656 val = tegra_dsi_readl(dsi, DSI_STATUS); 1862 dev_warn(&dc->ndev->dev,
1657 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f); 1863 "DSI overflow/underflow error\n");
1658 if (val) {
1659 err = -EBUSY;
1660 dev_err(&dc->ndev->dev, "DSI fifo count not zero\n");
1661 goto fail;
1662 } 1864 }
1663 1865
1664 if (!tegra_dsi_is_controller_idle(dsi)) { 1866 /* Read data from FIFO */
1665 err = -EBUSY; 1867 for (i = 0; i < rd_fifo_cnt; i++) {
1666 dev_err(&dc->ndev->dev, "DSI trigger bit is already set\n"); 1868 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
1667 goto fail; 1869 if (enable_read_debug)
1870 dev_info(&dc->ndev->dev,
1871 "Read data[%d]: 0x%x\n", i, val);
1872 memcpy(read_fifo, &val, 4);
1873 read_fifo += 4;
1668 } 1874 }
1669 1875
1876 /* Make sure all the data is read from the FIFO */
1670 val = tegra_dsi_readl(dsi, DSI_STATUS); 1877 val = tegra_dsi_readl(dsi, DSI_STATUS);
1671 val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1)); 1878 val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
1672 if (val) { 1879 if (val)
1673 dev_warn(&dc->ndev->dev, "Reset overflow/underflow\n"); 1880 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
1674 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL); 1881 " even after reading FIFO_RD_CNT words from read fifo\n");
1675 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1); 1882
1676 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL); 1883 if (enable_read_debug) {
1677 ndelay(200); 1884 err =
1885 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
1886 if (err < 0)
1887 dev_warn(&dc->ndev->dev, "Unexpected read data\n");
1678 } 1888 }
1889fail:
1890 return err;
1891}
1679 1892
1680 if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE) { 1893int tegra_dsi_read_data(struct tegra_dc *dc,
1681 if (dsi->status.driven == DSI_DRIVEN_MODE_DC) { 1894 struct tegra_dc_dsi_data *dsi,
1682 if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) { 1895 u32 max_ret_payload_size,
1683 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi); 1896 u32 panel_reg_addr, u8 *read_data)
1684 restart_dc_stream = true; 1897{
1685 } 1898 int err = 0;
1686 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST; 1899 struct dsi_status *init_status;
1687 switch_back_to_dc_mode = true; 1900
1688 if (dsi->info.hs_cmd_mode_supported) { 1901 tegra_dc_io_start(dc);
1689 err = tegra_dsi_set_to_hs_mode(dc, dsi); 1902
1690 if (err < 0) { 1903 init_status = tegra_dsi_prepare_host_transmission(
1691 dev_err(&dc->ndev->dev, 1904 dc, dsi, DSI_LP_OP_WRITE);
1692 "DSI failed to go to HS host driven mode\n"); 1905 if (IS_ERR_OR_NULL(init_status)) {
1693 goto fail; 1906 err = PTR_ERR(init_status);
1694 } 1907 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1695 } 1908 goto fail;
1696 }
1697 if (!dsi->info.hs_cmd_mode_supported) {
1698 err =
1699 tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
1700 if (err < 0) {
1701 dev_err(&dc->ndev->dev,
1702 "DSI failed to go to LP mode\n");
1703 goto fail;
1704 }
1705 switch_back_to_hs_mode = true;
1706 }
1707 } 1909 }
1708 1910
1709 /* Set max return payload size in words */ 1911 /* Set max return payload size in words */
@@ -1726,11 +1928,13 @@ int tegra_dsi_read_data(struct tegra_dc *dc,
1726 goto fail; 1928 goto fail;
1727 } 1929 }
1728 1930
1931 tegra_dsi_reset_read_count(dsi);
1932
1729 if (dsi->status.lp_op == DSI_LP_OP_WRITE) { 1933 if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1730 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ); 1934 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1731 if (err < 0) { 1935 if (err < 0) {
1732 dev_err(&dc->ndev->dev, 1936 dev_err(&dc->ndev->dev,
1733 "DSI failed to go to LP mode\n"); 1937 "DSI failed to go to LP read mode\n");
1734 goto fail; 1938 goto fail;
1735 } 1939 }
1736 } 1940 }
@@ -1742,51 +1946,81 @@ int tegra_dsi_read_data(struct tegra_dc *dc,
1742 goto fail; 1946 goto fail;
1743 } 1947 }
1744 1948
1745 poll_time = 0; 1949 err = tegra_dsi_read_fifo(dc, dsi, read_data);
1746 while (poll_time < DSI_DELAY_FOR_READ_FIFO) { 1950 if (err < 0) {
1747 mdelay(1); 1951 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
1748 val = tegra_dsi_readl(dsi, DSI_STATUS); 1952 goto fail;
1749 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
1750 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH)
1751 dev_err(&dc->ndev->dev,
1752 "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
1753 break;
1754 poll_time++;
1755 } 1953 }
1954fail:
1955 err = tegra_dsi_restore_state(dc, dsi, init_status);
1956 if (err < 0)
1957 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
1958 tegra_dc_io_end(dc);
1959 return err;
1960}
1961EXPORT_SYMBOL(tegra_dsi_read_data);
1756 1962
1757 if (rd_fifo_cnt == 0) { 1963int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
1758 dev_info(&dc->ndev->dev, 1964 struct tegra_dc_dsi_data *dsi)
1759 "DSI RD_FIFO_CNT is zero\n"); 1965{
1760 err = -EINVAL; 1966 int err = 0;
1967 u8 read_fifo[DSI_READ_FIFO_DEPTH];
1968 struct dsi_status *init_status;
1969 static struct tegra_dsi_cmd dsi_nop_cmd =
1970 DSI_CMD_SHORT(0x05, 0x0, 0x0);
1971
1972 tegra_dc_io_start(dc);
1973
1974 init_status = tegra_dsi_prepare_host_transmission(
1975 dc, dsi, DSI_LP_OP_WRITE);
1976 if (IS_ERR_OR_NULL(init_status)) {
1977 err = PTR_ERR(init_status);
1978 dev_err(&dc->ndev->dev, "DSI host config failed\n");
1761 goto fail; 1979 goto fail;
1762 } 1980 }
1763 1981
1764 if (val & DSI_STATUS_LB_UNDERFLOW(0x1) || 1982 err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
1765 val & DSI_STATUS_LB_OVERFLOW(0x1)) { 1983 if (err < 0) {
1766 dev_err(&dc->ndev->dev, 1984 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
1767 "DSI overflow/underflow error\n");
1768 err = -EINVAL;
1769 goto fail; 1985 goto fail;
1770 } 1986 }
1771 1987
1772 tegra_dsi_read_fifo(dc, dsi, rd_fifo_cnt, read_data); 1988 tegra_dsi_reset_read_count(dsi);
1773 1989
1774 if (enable_read_debug) 1990 if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
1775 err = tegra_dsi_parse_read_response 1991 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
1776 (dc, rd_fifo_cnt, read_data); 1992 if (err < 0) {
1777fail: 1993 dev_err(&dc->ndev->dev,
1778 if (switch_back_to_dc_mode) 1994 "DSI failed to go to LP read mode\n");
1779 dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC; 1995 goto fail;
1780 if (switch_back_to_dc_mode || switch_back_to_hs_mode) 1996 }
1781 tegra_dsi_set_to_hs_mode(dc, dsi); 1997 }
1782 if (restart_dc_stream)
1783 tegra_dsi_start_dc_stream(dc, dsi);
1784 1998
1785 tegra_dc_io_end(dc); 1999 err = tegra_dsi_bta(dsi);
2000 if (err < 0) {
2001 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
2002 goto fail;
2003 }
1786 2004
2005 err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
2006 if (err < 0) {
2007 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
2008 goto fail;
2009 }
2010
2011 if (read_fifo[0] != DSI_ACK_NO_ERR) {
2012 dev_warn(&dc->ndev->dev,
2013 "Ack no error trigger message not received\n");
2014 err = -EAGAIN;
2015 }
2016fail:
2017 err = tegra_dsi_restore_state(dc, dsi, init_status);
2018 if (err < 0)
2019 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2020 tegra_dc_io_end(dc);
1787 return err; 2021 return err;
1788} 2022}
1789EXPORT_SYMBOL(tegra_dsi_read_data); 2023EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
1790 2024
1791static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi) 2025static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1792{ 2026{
@@ -1803,7 +2037,8 @@ static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
1803#if DSI_USE_SYNC_POINTS 2037#if DSI_USE_SYNC_POINTS
1804 ret = tegra_dsi_syncpt(dsi); 2038 ret = tegra_dsi_syncpt(dsi);
1805 if (ret < 0) { 2039 if (ret < 0) {
1806 printk(KERN_ERR "DSI syncpt for ulpm enter failed\n"); 2040 dev_err(&dsi->dc->ndev->dev,
2041 "DSI syncpt for ulpm enter failed\n");
1807 goto fail; 2042 goto fail;
1808 } 2043 }
1809#else 2044#else
@@ -1830,7 +2065,8 @@ static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
1830#if DSI_USE_SYNC_POINTS 2065#if DSI_USE_SYNC_POINTS
1831 ret = tegra_dsi_syncpt(dsi); 2066 ret = tegra_dsi_syncpt(dsi);
1832 if (ret < 0) { 2067 if (ret < 0) {
1833 printk(KERN_ERR "DSI syncpt for ulpm exit failed\n"); 2068 dev_err(&dsi->dc->ndev->dev,
2069 "DSI syncpt for ulpm exit failed\n");
1834 goto fail; 2070 goto fail;
1835 } 2071 }
1836#else 2072#else
@@ -1866,7 +2102,8 @@ static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1866 if (dsi->enabled) { 2102 if (dsi->enabled) {
1867 if (dsi->ulpm) { 2103 if (dsi->ulpm) {
1868 if (tegra_dsi_exit_ulpm(dsi) < 0) { 2104 if (tegra_dsi_exit_ulpm(dsi) < 0) {
1869 printk(KERN_ERR "DSI failed to exit ulpm\n"); 2105 dev_err(&dc->ndev->dev,
2106 "DSI failed to exit ulpm\n");
1870 goto fail; 2107 goto fail;
1871 } 2108 }
1872 } 2109 }
@@ -1900,7 +2137,8 @@ static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1900 2137
1901 if (dsi->ulpm) { 2138 if (dsi->ulpm) {
1902 if (tegra_dsi_enter_ulpm(dsi) < 0) { 2139 if (tegra_dsi_enter_ulpm(dsi) < 0) {
1903 printk(KERN_ERR "DSI failed to enter ulpm\n"); 2140 dev_err(&dc->ndev->dev,
2141 "DSI failed to enter ulpm\n");
1904 goto fail; 2142 goto fail;
1905 } 2143 }
1906 val = DSI_PAD_CONTROL_PAD_PDIO(0) | 2144 val = DSI_PAD_CONTROL_PAD_PDIO(0) |
@@ -1909,7 +2147,8 @@ static void tegra_dc_dsi_enable(struct tegra_dc *dc)
1909 (TEGRA_DSI_DISABLE); 2147 (TEGRA_DSI_DISABLE);
1910 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL); 2148 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1911 if (tegra_dsi_exit_ulpm(dsi) < 0) { 2149 if (tegra_dsi_exit_ulpm(dsi) < 0) {
1912 printk(KERN_ERR "DSI failed to exit ulpm\n"); 2150 dev_err(&dc->ndev->dev,
2151 "DSI failed to exit ulpm\n");
1913 goto fail; 2152 goto fail;
1914 } 2153 }
1915 } 2154 }
@@ -2084,7 +2323,8 @@ static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
2084 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ; 2323 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
2085 2324
2086 if (!dsi->info.chip_id || !dsi->info.chip_rev) 2325 if (!dsi->info.chip_id || !dsi->info.chip_rev)
2087 printk(KERN_WARNING "DSI: Failed to get chip info\n"); 2326 dev_warn(&dsi->dc->ndev->dev,
2327 "DSI: Failed to get chip info\n");
2088 2328
2089 if (!dsi->info.lp_read_cmd_mode_freq_khz) 2329 if (!dsi->info.lp_read_cmd_mode_freq_khz)
2090 dsi->info.lp_read_cmd_mode_freq_khz = 2330 dsi->info.lp_read_cmd_mode_freq_khz =
@@ -2321,7 +2561,8 @@ static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2321 2561
2322 if (dsi->info.power_saving_suspend) { 2562 if (dsi->info.power_saving_suspend) {
2323 if (tegra_dsi_deep_sleep(dc, dsi) < 0) { 2563 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2324 printk(KERN_ERR "DSI failed to enter deep sleep\n"); 2564 dev_err(&dc->ndev->dev,
2565 "DSI failed to enter deep sleep\n");
2325 goto fail; 2566 goto fail;
2326 } 2567 }
2327 } else { 2568 } else {
@@ -2338,7 +2579,8 @@ static void tegra_dc_dsi_disable(struct tegra_dc *dc)
2338 2579
2339 if (!dsi->ulpm) { 2580 if (!dsi->ulpm) {
2340 if (tegra_dsi_enter_ulpm(dsi) < 0) { 2581 if (tegra_dsi_enter_ulpm(dsi) < 0) {
2341 printk(KERN_ERR "DSI failed to enter ulpm\n"); 2582 dev_err(&dc->ndev->dev,
2583 "DSI failed to enter ulpm\n");
2342 goto fail; 2584 goto fail;
2343 } 2585 }
2344 } 2586 }
@@ -2365,13 +2607,15 @@ static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
2365 if (!dsi->info.power_saving_suspend) { 2607 if (!dsi->info.power_saving_suspend) {
2366 if (dsi->ulpm) { 2608 if (dsi->ulpm) {
2367 if (tegra_dsi_exit_ulpm(dsi) < 0) { 2609 if (tegra_dsi_exit_ulpm(dsi) < 0) {
2368 printk(KERN_ERR "DSI failed to exit ulpm"); 2610 dev_err(&dc->ndev->dev,
2611 "DSI failed to exit ulpm");
2369 goto fail; 2612 goto fail;
2370 } 2613 }
2371 } 2614 }
2372 2615
2373 if (tegra_dsi_deep_sleep(dc, dsi) < 0) { 2616 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
2374 printk(KERN_ERR "DSI failed to enter deep sleep\n"); 2617 dev_err(&dc->ndev->dev,
2618 "DSI failed to enter deep sleep\n");
2375 goto fail; 2619 goto fail;
2376 } 2620 }
2377 } 2621 }
diff --git a/drivers/video/tegra/dc/dsi.h b/drivers/video/tegra/dc/dsi.h
index 95636c0e0..d86a60a50 100644
--- a/drivers/video/tegra/dc/dsi.h
+++ b/drivers/video/tegra/dc/dsi.h
@@ -41,6 +41,10 @@ enum{
41#define DSI_MAX_COMMAND_DELAY_USEC 250000 41#define DSI_MAX_COMMAND_DELAY_USEC 250000
42#define DSI_COMMAND_DELAY_STEPS_USEC 10 42#define DSI_COMMAND_DELAY_STEPS_USEC 10
43 43
44/* Trigger message */
45#define DSI_ESCAPE_CMD 0x87
46#define DSI_ACK_NO_ERR 0x84
47
44/* DSI return packet types */ 48/* DSI return packet types */
45#define GEN_LONG_RD_RES 0x1A 49#define GEN_LONG_RD_RES 0x1A
46#define DCS_LONG_RD_RES 0x1C 50#define DCS_LONG_RD_RES 0x1C
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 00:36:19 -0500