2 files changed, 30 insertions, 1 deletions

diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-eqos.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-eqos.dtsi
index d15036182..774dabb5c 100644
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-eqos.dtsi
+++ b/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-eqos.dtsi
@@ -37,7 +37,9 @@
 / {
         ether_qos@2490000 {
                 compatible = "nvidia,eqos";
-                reg = <0x0 0x02490000 0x0 0x10000>;
+                reg = <0x0 0x02490000 0x0 0x10000        /* EQOS Base Register */
+                       0x0 0x02439000 0x0 0x00000074>;   /* PADS registers */
+                reg-names = "eqos_base", "eqos_pads";
                 interrupts =    <0 194 0x4>,    /* common */
                                 <0 195 0x4>,    /* power */
                                 <0 190 0x4>,    /* rx0 */
diff --git a/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-prod.dtsi b/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-prod.dtsi
index 56cfe3f75..cc1ef2edc 100644
--- a/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-prod.dtsi
+++ b/arch/arm64/boot/dts/nvidia/t18x/tegra186-soc/tegra186-soc-prod.dtsi
@@ -35,6 +35,33 @@
                 };
         };
 
+        ether_qos@2490000 {
+                prod-settings {
+                        #prod-cells = <3>;
+                        mask-one-style;
+                        tx_tristate_enable {
+                                prod = <
+                                        0x00000018 0x00000050 0x00000010        // PADCTL_SDMMC2_HV_EQOS_TD0_0
+                                        0x00000010 0x00000050 0x00000010        // PADCTL_SDMMC2_HV_EQOS_TD1_0
+                                        0x00000008 0x00000050 0x00000010        // PADCTL_SDMMC2_HV_EQOS_TD2_0
+                                        0x00000000 0x00000050 0x00000010        // PADCTL_SDMMC2_HV_EQOS_TD3_0
+                                        0x00000054 0x00000050 0x00000010        // PADCTL_SDMMC2_HV_EQOS_TXC_0
+                                        0x00000064 0x00000050 0x00000010        // PADCTL_SDMMC2_HV_EQOS_TX_CTL_0
+                                >;
+                        };
+                        tx_tristate_disable {
+                                prod = <
+                                        0x00000018 0x00000050 0x00000000        // PADCTL_SDMMC2_HV_EQOS_TD0_0
+                                        0x00000010 0x00000050 0x00000000        // PADCTL_SDMMC2_HV_EQOS_TD1_0
+                                        0x00000008 0x00000050 0x00000000        // PADCTL_SDMMC2_HV_EQOS_TD2_0
+                                        0x00000000 0x00000050 0x00000000        // PADCTL_SDMMC2_HV_EQOS_TD3_0
+                                        0x00000054 0x00000050 0x00000000        // PADCTL_SDMMC2_HV_EQOS_TXC_0
+                                        0x00000064 0x00000050 0x00000000        // PADCTL_SDMMC2_HV_EQOS_TX_CTL_0
+                                >;
+                        };
+                };
+        };
+
         sdhci@3460000 {
                 prod-settings {
                         #prod-cells = <3>;