tegra: cache: fix dcache flush retry

Presently, dcache flush instruction is called
repeatedly in a loop and not giving chance
to context switch and service pending interrupts.

Hw recommends that if there are pending interrupts
in CPU side and flush operation is underway,
flush may exit without completing.

The change adds delay of 1 Micro second to let
interrupts should be serviced in CPU side.

It also adds debug version of flush code which
profiles latency, executing the flush instruction.
It bails out complete flush operation if flush
instruction doesn't pass after 1000 micro second.

Measured flush instruction takes 95us to 110 us
to complete the operation.

Bug 200424202

Change-Id: I625926eebc45c17d9141b0a341fe16d082da8293
Signed-off-by: Puneet Saxena <puneets@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760527
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

0 files changed, 0 insertions, 0 deletions