tegra-hv-net: Updated default mac address

- Updated deault mac address to a fixed
  private address. It is needed to fix
  telnet issue when only Linux VM is
  rebooted as other VM may still have
  old MAC address, cached earlier.
- In case of valid mac address found in
  dt, copying mac address from dt to ndev
- Also copied drivers/virt/tegra/syscalls.h
  to include/soc/tegra/virt/syscalls.h. Later
  drivers/virt/tegra/syscalls.h will be deleted.

Bug 200244271

Change-Id: Ief5c0bdc2941a02f7eba05a599fd2600f7e6a170
Reviewed-on: http://git-master/r/1252622
Signed-off-by: Aniruddha Banerjee <aniruddhab@nvidia.com>
Reviewed-on: http://git-master/r/1314845
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>

1 files changed, 336 insertions, 0 deletions

diff --git a/include/soc/tegra/virt/syscalls.h b/include/soc/tegra/virt/syscalls.h
new file mode 100644
index 000000000..32ad31297
--- /dev/null
+++ b/include/soc/tegra/virt/syscalls.h
@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2014-2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Hypervisor interfaces
+ *
+ * This header is BSD licensed so anyone can use the definitions to implement
+ * compatible drivers/servers.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of NVIDIA CORPORATION nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL NVIDIA CORPORATION OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __VMM_SYSCALLS_H__
+#define __VMM_SYSCALLS_H__
+
+#define HVC_NR_READ_STAT                1
+#define HVC_NR_READ_IVC                 2
+#define HVC_NR_READ_GID                 3
+#define HVC_NR_RAISE_IRQ                4
+#define HVC_NR_READ_NGUESTS             5
+#define HVC_NR_READ_IPA_PA              6
+#define HVC_NR_READ_GUEST_RESET_MASK    7
+#define HVC_NR_ACK_GUEST_CLEANUP        8
+#define HVC_NR_READ_HYP_INFO            9
+#define HVC_NR_GUEST_RESET              10
+#define HVC_NR_SYSINFO_IPA              13
+
+#define GUEST_PRIMARY           0
+#define GUEST_IVC_SERVER        0
+
+#define NGUESTS_MAX 16
+
+#ifndef __ASSEMBLY__
+
+#if defined(__KERNEL__)
+#include <linux/types.h>
+#endif
+
+struct tegra_hv_queue_data {
+        uint32_t        id;     /* IVC id */
+        uint32_t        peers[2];
+        uint32_t        size;
+        uint32_t        nframes;
+        uint32_t        frame_size;
+        uint32_t        offset;
+        uint16_t        irq, raise_irq;
+};
+
+struct ivc_mempool {
+        uint64_t pa;
+        uint64_t size;
+        uint32_t id;
+        uint32_t peer_vmid;
+};
+
+struct ivc_shared_area {
+        uint64_t pa;
+        uint64_t size;
+        uint32_t guest;
+        uint16_t free_irq_start;
+        uint16_t free_irq_count;
+};
+
+struct ivc_info_page {
+        uint32_t nr_queues;
+        uint32_t nr_areas;
+        uint32_t nr_mempools;
+
+        /* The actual length of this array is nr_areas. */
+        struct ivc_shared_area areas[];
+
+        /*
+         * Following the shared array is an array of queue data structures with
+         * an entry per queue that is assigned to the guest. This  array is
+         * terminated by an entry with no frames.
+         *
+         * struct tegra_hv_queue_data queue_data[nr_queues];
+         */
+
+        /*
+         * Following the queue data array is an array of mempool structures
+         * with an entry per mempool assigned to the guest.
+         *
+         * struct ivc_mempool[nr_mempools];
+         */
+};
+
+static inline struct ivc_shared_area *ivc_shared_area_addr(
+                const struct ivc_info_page *info, uint32_t area_num)
+{
+        return ((struct ivc_shared_area *) (((uintptr_t) info) + sizeof(*info)))
+                + area_num;
+}
+
+static inline const struct tegra_hv_queue_data *ivc_info_queue_array(
+                const struct ivc_info_page *info)
+{
+        return (struct tegra_hv_queue_data *)&info->areas[info->nr_areas];
+}
+
+static inline const struct ivc_mempool *ivc_info_mempool_array(
+                const struct ivc_info_page *info)
+{
+        return (struct ivc_mempool *)
+                        &ivc_info_queue_array(info)[info->nr_queues];
+}
+
+struct hyp_ipa_pa_info {
+        uint64_t base;       /* base of contiguous pa region */
+        uint64_t offset;     /* offset for requested ipa address */
+        uint64_t size;       /* size of pa region */
+};
+
+#define HVC_MAX_VCPU 128
+
+struct trapped_access {
+        uint64_t ipa;
+        uint32_t size;
+        int32_t write_not_read;
+        uint64_t data;
+        uint32_t guest_id;
+};
+
+struct hyp_server_page {
+        /* guest reset protocol */
+        uint32_t guest_reset_virq;
+        /* boot delay offsets per VM needed by monitor partition */
+        uint32_t boot_delay[NGUESTS_MAX];
+
+        uint32_t trap_virq;
+
+        /*
+         * Bitmap of VCPU indices in vcpu_trapped_accesses containing active
+         * trap information.
+         */
+        uint32_t trapped_vcpus[HVC_MAX_VCPU / 32];
+        struct trapped_access vcpu_trapped_accesses[HVC_MAX_VCPU];
+
+        /* hypervisor trace log */
+        uint64_t log_ipa;
+        uint64_t log_size;
+};
+
+/* For backwards compatibility, alias the old name for hyp_server_name. */
+#define hyp_info_page hyp_server_page
+
+#ifdef CONFIG_ARM64
+
+#define _X4_X17 "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", \
+"x13", "x14", "x15", "x16", "x17"
+
+static inline int hyp_read_gid(unsigned int *gid)
+{
+        register uint64_t r0 asm("x0");
+        register uint64_t r1 asm("x1");
+
+        asm("hvc %2"
+                : "=r"(r0), "=r"(r1)
+                : "i"(HVC_NR_READ_GID)
+                : "x2", "x3", _X4_X17);
+
+        *gid = r1;
+        return (int)r0;
+}
+
+static inline int hyp_read_nguests(unsigned int *nguests)
+{
+        register uint64_t r0 asm("x0");
+        register uint64_t r1 asm("x1");
+
+        asm("hvc %2"
+                : "=r"(r0), "=r"(r1)
+                : "i"(HVC_NR_READ_NGUESTS)
+                : "x2", "x3", _X4_X17);
+
+        *nguests = r1;
+        return (int)r0;
+}
+
+static inline int hyp_read_ivc_info(uint64_t *ivc_info_page_pa)
+{
+        register uint64_t r0 asm("x0");