diff options
| author | Rohit Khanna <rokhanna@nvidia.com> | 2017-02-08 14:45:45 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-16 13:43:22 -0500 |
| commit | 78d32dc63994e20376fe35dfbc3f98b2a34346eb (patch) | |
| tree | 07d76022f06decce6de5dca23c4e05c5c8080f6c /include | |
| parent | 0f38ddabcb908b7c92d303730323342033c12882 (diff) | |
arm64: platform: tegra: detect cpu using MIDR
This patch modifies the CPU detection macros
so that CPUs are identified by reading the
MIDR register value from per_cpu cpuinfo struct
rather than determining based on which cluster
they belong to.
Bug 1827294
Change-Id: I82eb452d6fc80db9ddaa5cfa9afdee50e3079a10
Signed-off-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-on: http://git-master/r/1301621
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/platform/tegra/tegra18_cpu_map.h | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/include/linux/platform/tegra/tegra18_cpu_map.h b/include/linux/platform/tegra/tegra18_cpu_map.h index 826498c20..77773e8e8 100644 --- a/include/linux/platform/tegra/tegra18_cpu_map.h +++ b/include/linux/platform/tegra/tegra18_cpu_map.h | |||
| @@ -2,6 +2,12 @@ | |||
| 2 | #include <asm/cputype.h> | 2 | #include <asm/cputype.h> |
| 3 | #include <asm/cpu.h> | 3 | #include <asm/cpu.h> |
| 4 | #include <asm/smp_plat.h> | 4 | #include <asm/smp_plat.h> |
| 5 | #include <asm/cputype.h> | ||
| 6 | |||
| 7 | /* MIDR Variant and Revision masked*/ | ||
| 8 | #define MIDR_CPU_MASK 0xFF0FFFF0 | ||
| 9 | #define MIDR_CPU_DENVER2 0x4E0F0030 | ||
| 10 | #define MIDR_CPU_A57 0x410FD070 | ||
| 5 | 11 | ||
| 6 | static inline u8 tegra18_logical_to_cluster(u8 cpu) { | 12 | static inline u8 tegra18_logical_to_cluster(u8 cpu) { |
| 7 | return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1); | 13 | return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 1); |
| @@ -11,14 +17,18 @@ static inline u8 tegra18_logical_to_cpu(u8 cpu) { | |||
| 11 | return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); | 17 | return MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0); |
| 12 | } | 18 | } |
| 13 | 19 | ||
| 20 | /* check if CPU is Denver2 */ | ||
| 14 | static inline int tegra18_is_cpu_denver(u8 cpu) | 21 | static inline int tegra18_is_cpu_denver(u8 cpu) |
| 15 | { | 22 | { |
| 16 | return tegra18_logical_to_cluster(cpu) == 0; | 23 | struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, cpu); |
| 24 | return ((cpuinfo->reg_midr & MIDR_CPU_MASK) == MIDR_CPU_DENVER2); | ||
| 17 | } | 25 | } |
| 18 | 26 | ||
| 27 | /* check if CPU is A57 */ | ||
| 19 | static inline int tegra18_is_cpu_arm(u8 cpu) | 28 | static inline int tegra18_is_cpu_arm(u8 cpu) |
| 20 | { | 29 | { |
| 21 | return tegra18_logical_to_cluster(cpu) == 1; | 30 | struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, cpu); |
| 31 | return ((cpuinfo->reg_midr & MIDR_CPU_MASK) == MIDR_CPU_A57); | ||
| 22 | } | 32 | } |
| 23 | 33 | ||
| 24 | static inline int tegra18_logical_to_physical_cpu(u8 cpu) | 34 | static inline int tegra18_logical_to_physical_cpu(u8 cpu) |
