ASoC: tegra-alt: Fix Tegra186 ARAD regmap

The Tegra186 ARAD driver lists the TEGRA186_ARAD_LANE_ENABLE register
as volatile implying that the register has status bits that may change
automatically. The ARAD Lane Enable register for both Tegra186 and
Tegra194 have 6 bits which are enable bits and no status bits.
Therefore, this register is not volatile and should not be listed as
volatile. Furthermore, during overnight stress testing, I sometimes see
one of the ARAD lanes become enabled randomly (by diff'ing the ALSA
state, as shown below, before and after running a test that is not using
ARAD). So far after making the ARAD Lane Enable register non-volatile
this has no longer been seen.

--- /home/ubuntu/audio-start.state      2018-06-07 19:45:34.054566952 +0000
+++ /home/ubuntu/audio-end.state        2018-06-07 19:45:34.134568418 +0000
@@ -6101,7 +6101,7 @@
        control.533 {
		iface MIXER
		name 'Lane1 enable'
-               value false
+               value true
                comment {
                        access 'read write'
                        type BOOLEAN

Bug 2225626

Change-Id: Id261067874b523e64ab165fc283cf9f61910ba5b
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1765364
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

0 files changed, 0 insertions, 0 deletions