platform: tegra: create generic debugfs for RAS error inject

Creating generic debugfs node for injecting
RAS errors(one of each type).

How to use:
  - reading the node gives help info about using.
      cat /d/RAS_MCA_ERR-trip
  - write node to cause error.
    e.g:
	echo EEDDCCBBAA > /d/RAS_MCA_ERR-trip
	where:
	   EE[32-39] - L3_Bank_ID
	   DD[24-31] - Logical_Cluster_ID
	   CC[16-23] - Logical_CPU_ID
	   BB[08-15] - Error type(Corr is 0, UnCorr is 1)
	   AA[00-07] - Unit
        Unit numbers will be printed in help info on reading same node

Bug 200420692

Change-Id: Ib83548b1781a55e9b980b0a506b93d5ef14b5119
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1770600
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 26 insertions, 1 deletions

diff --git a/include/linux/platform/tegra/carmel_ras.h b/include/linux/platform/tegra/carmel_ras.h
index d533439e3..d1f8c1371 100644
--- a/include/linux/platform/tegra/carmel_ras.h
+++ b/include/linux/platform/tegra/carmel_ras.h
@@ -40,7 +40,7 @@
 #define ERR_CTL_MTS_JSR_ERRUC_ERR       RAS_BIT(32)
 
 /* ERR_CTLR bits for LSD_1/LSD_STQ */
-#define ERR_CTL_LSD1_CCDEMLECC_ERR      RAS_BIT(41)
+#define ERR_CTL_LSD1_CCDSMLECC_ERR      RAS_BIT(41)
 #define ERR_CTL_LSD1_CCDSECC_D_ERR      RAS_BIT(40)
 #define ERR_CTL_LSD1_CCDSECC_S_ERR      RAS_BIT(39)
 #define ERR_CTL_LSD1_CCDLECC_D_ERR      RAS_BIT(38)
@@ -167,3 +167,28 @@
 #define ERRi_MISC0_CONST                0x2222222222222222UL
 #define ERRi_MISC1_CONST                0x3333333333333333UL
 #define ERRi_ADDR_CONST                 0x4444444444444444UL
+
+
+enum {
+        IFU,            /* 0 */
+        JSR_RET,        /* 1 */
+        JSR_MTS,        /* 2 */
+        LSD_STQ,        /* 3 */
+        LSD_DCC,        /* 4 */
+        LSD_L1HPF,      /* 5 */
+        L2,             /* 6 */
+        Cluster_Clocks, /* 7 */
+        MMU,            /* 8 */
+        L3,             /* 9 */
+        CCPMU,          /* A */
+        SCF_IOB,        /* B */
+        SCF_SNOC,       /* C */
+        SCF_CTU,        /* D */
+        CMU_Clocks,     /* E */
+};
+
+struct tegra_ras_impl_err_bit {
+        u64     uncorr_bit;
+        u64     corr_bit;
+};
+