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authorChris Dragan <kdragan@nvidia.com>2020-03-04 10:41:50 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2020-03-26 09:54:30 -0400
commit5dc99b83afdc03e2d27ee5d6ebd937dd6a2f0785 (patch)
treec792c7c79a0a588b99539c6d9fe08686ab820a14 /include/uapi/misc
parentbf16e6cf1cc0290d3b581bd67a79ff3845f4afb6 (diff)
misc: mods: move mods.h to uapi
moved mods.h to uapi directory as per Linux user-space ABI to give userland access of mods.h * Update SPDX license header. Bug 2657961 Change-Id: I65f4a8ff48c534144afc5aca7ce556dcc82d9342 (cherry picked from commit a525dd043ba3fc98d7f8fd9d5d1509c39df2b005) Signed-off-by: Ankit Patel <anpatel@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2315156 Reviewed-by: automaticguardword <automaticguardword@nvidia.com> Reviewed-by: Chris Dragan <kdragan@nvidia.com> Reviewed-by: Bibek Basu <bbasu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/uapi/misc')
-rw-r--r--include/uapi/misc/mods.h1494
1 files changed, 1494 insertions, 0 deletions
diff --git a/include/uapi/misc/mods.h b/include/uapi/misc/mods.h
new file mode 100644
index 000000000..0230364ba
--- /dev/null
+++ b/include/uapi/misc/mods.h
@@ -0,0 +1,1494 @@
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * mods.h - This file is part of NVIDIA MODS kernel driver.
4 *
5 * Copyright (c) 2008-2020, NVIDIA CORPORATION. All rights reserved.
6 *
7 * NVIDIA MODS kernel driver is free software: you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * NVIDIA MODS kernel driver is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with NVIDIA MODS kernel driver.
18 * If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#ifndef _UAPI_MODS_H_
22#define _UAPI_MODS_H_
23
24#include <linux/types.h>
25
26/* Driver version */
27#define MODS_DRIVER_VERSION_MAJOR 3
28#define MODS_DRIVER_VERSION_MINOR 96
29#define MODS_DRIVER_VERSION ((MODS_DRIVER_VERSION_MAJOR << 8) | \
30 ((MODS_DRIVER_VERSION_MINOR/10) << 4) | \
31 (MODS_DRIVER_VERSION_MINOR%10))
32
33#pragma pack(push, 1)
34
35/* ************************************************************************* */
36/* ** ESCAPE INTERFACE STRUCTURE */
37/* ************************************************************************* */
38
39struct mods_pci_dev_2 {
40 __u16 domain;
41 __u16 bus;
42 __u16 device;
43 __u16 function;
44};
45
46struct mods_pci_dev {
47 __u16 bus;
48 __u8 device;
49 __u8 function;
50};
51
52/* MODS_ESC_ALLOC_PAGES_2 */
53struct MODS_ALLOC_PAGES_2 {
54 /* IN */
55 __u64 num_bytes;
56 __u32 flags; /* MODS_ALLOC_* */
57 __s32 numa_node;
58 struct mods_pci_dev_2 pci_device;
59
60 /* OUT */
61 __u64 memory_handle;
62};
63
64/* numa_node */
65#define MODS_ANY_NUMA_NODE (-1)
66
67/* flags */
68#define MODS_ALLOC_CACHED 0 /* Default WB cache attr */
69#define MODS_ALLOC_UNCACHED 1 /* UC cache attr */
70#define MODS_ALLOC_WRITECOMBINE 2 /* WC cache attr */
71#define MODS_ALLOC_CACHE_MASK 7U /* The first three bits are cache attr */
72
73#define MODS_ALLOC_DMA32 8 /* Force 32-bit PA, else any PA */
74#define MODS_ALLOC_CONTIGUOUS 16 /* Force contiguous, else any PA */
75#define MODS_ALLOC_USE_NUMA 32 /* Use numa_node instead of PCI dev for
76 * NUMA node hint
77 */
78#define MODS_ALLOC_FORCE_NUMA 64 /* Force memory to be from a given NUMA
79 * node (same as PCI dev or numa_node).
80 * Otherwise use PCI dev/numa_node as
81 * a hint and if that is not possible,
82 * allocate from any NUMA node
83 */
84#define MODS_ALLOC_MAP_DEV 128 /* DMA map to PCI device */
85
86/* MODS_ESC_ALLOC_PAGES */
87struct MODS_ALLOC_PAGES {
88 /* IN */
89 __u32 num_bytes;
90 __u32 contiguous;
91 __u32 address_bits;
92 __u32 attrib;
93
94 /* OUT */
95 __u64 memory_handle;
96};
97
98/* MODS_ESC_DEVICE_ALLOC_PAGES_2 */
99struct MODS_DEVICE_ALLOC_PAGES_2 {
100 /* IN */
101 __u32 num_bytes;
102 __u32 contiguous;
103 __u32 address_bits;
104 __u32 attrib;
105 struct mods_pci_dev_2 pci_device;
106
107 /* OUT */
108 __u64 memory_handle;
109};
110
111/* MODS_ESC_DEVICE_ALLOC_PAGES */
112struct MODS_DEVICE_ALLOC_PAGES {
113 /* IN */
114 __u32 num_bytes;
115 __u32 contiguous;
116 __u32 address_bits;
117 __u32 attrib;
118 struct mods_pci_dev pci_device;
119
120 /* OUT */
121 __u64 memory_handle;
122};
123
124/* MODS_ESC_FREE_PAGES */
125struct MODS_FREE_PAGES {
126 /* IN */
127 __u64 memory_handle;
128};
129
130#define MODS_MAX_MERGE_HANDLES 64
131
132/* MODS_ESC_MERGE_PAGES */
133struct MODS_MERGE_PAGES {
134 /* IN */
135 __u64 in_memory_handles[MODS_MAX_MERGE_HANDLES];
136 __u32 num_in_handles;
137 __u32 dummy_align;
138
139 /* OUT */
140 __u64 memory_handle;
141};
142
143/* MODS_ESC_GET_PHYSICAL_ADDRESS */
144struct MODS_GET_PHYSICAL_ADDRESS {
145 /* IN */
146 __u64 memory_handle;
147 __u32 offset;
148
149 /* OUT */
150 __u64 physical_address;
151};
152
153/* MODS_ESC_GET_PHYSICAL_ADDRESS */
154struct MODS_GET_PHYSICAL_ADDRESS_2 {
155 /* IN */
156 __u64 memory_handle;
157 __u32 offset;
158 struct mods_pci_dev_2 pci_device;
159
160 /* OUT */
161 __u64 physical_address;
162};
163
164/* MODS_ESC_GET_PHYSICAL_ADDRESS_3 */
165struct MODS_GET_PHYSICAL_ADDRESS_3 {
166 /* IN */
167 __u64 memory_handle;
168 __u64 offset;
169 struct mods_pci_dev_2 pci_device;
170
171 /* OUT */
172 __u64 physical_address;
173};
174
175/* MODS_ESC_VIRTUAL_TO_PHYSICAL */
176struct MODS_VIRTUAL_TO_PHYSICAL {
177 /* IN */
178 __u64 virtual_address;
179
180 /* OUT */
181 __u64 physical_address;
182};
183
184/* MODS_ESC_PHYSICAL_TO_VIRTUAL */
185struct MODS_PHYSICAL_TO_VIRTUAL {
186 /* IN */
187 __u64 physical_address;
188
189 /* OUT */
190 __u64 virtual_address;
191
192};
193
194/* MODS_ESC_FLUSH_CACHE_RANGE */
195#define MODS_FLUSH_CPU_CACHE 1
196#define MODS_INVALIDATE_CPU_CACHE 2
197
198struct MODS_FLUSH_CPU_CACHE_RANGE {
199 /* IN */
200 __u64 virt_addr_start;
201 __u64 virt_addr_end;
202 __u32 flags;
203};
204
205/* MODS_ESC_DMA_MAP_MEMORY */
206struct MODS_DMA_MAP_MEMORY {
207 /* IN */
208 __u64 memory_handle;
209 struct mods_pci_dev_2 pci_device;
210};
211
212/* MODS_ESC_PCI_SET_DMA_MASK */
213struct MODS_PCI_DMA_MASK {
214 /* IN */
215 struct mods_pci_dev_2 pci_device;
216 __u32 num_bits;
217};
218
219#define MODS_SWIOTLB_DISABLED 0
220#define MODS_SWIOTLB_ACTIVE 1
221#define MODS_SWIOTLB_INDETERMINATE 2
222
223/* MODS_ESC_GET_IOMMU_STATE */
224struct MODS_GET_IOMMU_STATE {
225 /* IN */
226 struct mods_pci_dev_2 pci_device;
227 /* OUT */
228 __u32 state;
229};
230
231/* MODS_ESC_FIND_PCI_DEVICE_2 */
232struct MODS_FIND_PCI_DEVICE_2 {
233 /* IN */
234 __u32 device_id;
235 __u32 vendor_id;
236 __u32 index;
237
238 /* OUT */
239 struct mods_pci_dev_2 pci_device;
240};
241
242/* MODS_ESC_FIND_PCI_DEVICE */
243struct MODS_FIND_PCI_DEVICE {
244 /* IN */
245 __u32 device_id;
246 __u32 vendor_id;
247 __u32 index;
248
249 /* OUT */
250 __u32 bus_number;
251 __u32 device_number;
252 __u32 function_number;
253};
254
255/* MODS_ESC_FIND_PCI_CLASS_CODE_2 */
256struct MODS_FIND_PCI_CLASS_CODE_2 {
257 /* IN */
258 __u32 class_code;
259 __u32 index;
260
261 /* OUT */
262 struct mods_pci_dev_2 pci_device;
263};
264
265/* MODS_ESC_FIND_PCI_CLASS_CODE */
266struct MODS_FIND_PCI_CLASS_CODE {
267 /* IN */
268 __u32 class_code;
269 __u32 index;
270
271 /* OUT */
272 __u32 bus_number;
273 __u32 device_number;
274 __u32 function_number;
275};
276
277/* MODS_ESC_PCI_GET_BAR_INFO_2 */
278struct MODS_PCI_GET_BAR_INFO_2 {
279 /* IN */
280 struct mods_pci_dev_2 pci_device;
281 __u32 bar_index;
282
283 /* OUT */
284 __u64 base_address;
285 __u64 bar_size;
286};
287
288/* MODS_ESC_PCI_GET_BAR_INFO */
289struct MODS_PCI_GET_BAR_INFO {
290 /* IN */
291 struct mods_pci_dev pci_device;
292 __u32 bar_index;
293
294 /* OUT */
295 __u64 base_address;
296 __u64 bar_size;
297};
298
299/* MODS_ESC_PCI_GET_IRQ_2 */
300struct MODS_PCI_GET_IRQ_2 {
301 /* IN */
302 struct mods_pci_dev_2 pci_device;
303
304 /* OUT */
305 __u32 irq;
306};
307
308/* MODS_ESC_PCI_GET_IRQ */
309struct MODS_PCI_GET_IRQ {
310 /* IN */
311 struct mods_pci_dev pci_device;
312
313 /* OUT */
314 __u32 irq;
315};
316
317/* MODS_ESC_PCI_READ_2 */
318struct MODS_PCI_READ_2 {
319 /* IN */
320 struct mods_pci_dev_2 pci_device;
321 __u32 address;
322 __u32 data_size;
323
324 /* OUT */
325 __u32 data;
326};
327
328/* MODS_ESC_PCI_READ */
329struct MODS_PCI_READ {
330 /* IN */
331 __u32 bus_number;
332 __u32 device_number;
333 __u32 function_number;
334 __u32 address;
335 __u32 data_size;
336
337 /* OUT */
338 __u32 data;
339};
340
341/* MODS_ESC_PCI_WRITE_2 */
342struct MODS_PCI_WRITE_2 {
343 /* IN */
344 struct mods_pci_dev_2 pci_device;
345 __u32 address;
346 __u32 data;
347 __u32 data_size;
348};
349
350/* MODS_ESC_PCI_WRITE */
351struct MODS_PCI_WRITE {
352 /* IN */
353 __u32 bus_number;
354 __u32 device_number;
355 __u32 function_number;
356 __u32 address;
357 __u32 data;
358 __u32 data_size;
359};
360
361/* MODS_ESC_PCI_HOT_RESET */
362struct MODS_PCI_HOT_RESET {
363 /* IN */
364 struct mods_pci_dev_2 pci_device;
365};
366
367/* MODS_ESC_PCI_BUS_REMOVE_DEV */
368struct MODS_PCI_BUS_REMOVE_DEV {
369 /* IN */
370 struct mods_pci_dev_2 pci_device;
371};
372
373/* MODS_ESC_SET_PPC_TCE_BYPASS */
374#define MODS_PPC_TCE_BYPASS_DEFAULT 0
375#define MODS_PPC_TCE_BYPASS_ON 1
376#define MODS_PPC_TCE_BYPASS_OFF 2
377struct MODS_SET_PPC_TCE_BYPASS {
378 /* IN */
379 __u8 mode;
380 __u8 _dummy_align[7];
381 struct mods_pci_dev_2 pci_device;
382 __u64 device_dma_mask;
383
384 /* OUT */
385 __u64 dma_base_address;
386};
387
388/* MODS_ESC_PCI_BUS_ADD_DEVICES*/
389struct MODS_PCI_BUS_ADD_DEVICES {
390 /* IN */
391 __u32 bus;
392};
393
394/* MODS_ESC_PCI_BUS_RESCAN */
395struct MODS_PCI_BUS_RESCAN {
396 __u16 domain;
397 __u16 bus;
398};
399
400/* MODS_ESC_PCI_MAP_RESOURCE */
401struct MODS_PCI_MAP_RESOURCE {
402 /* IN */
403 struct mods_pci_dev_2 local_pci_device;
404 struct mods_pci_dev_2 remote_pci_device;
405 __u32 resource_index;
406 __u64 page_count;
407
408 /* IN/OUT */
409 __u64 va;
410};
411
412/* MODS_ESC_PCI_UNMAP_RESOURCE */
413struct MODS_PCI_UNMAP_RESOURCE {
414 /* IN */
415 struct mods_pci_dev_2 pci_device;
416 __u64 va;
417};
418
419/* MODS_ESC_PIO_READ */
420struct MODS_PIO_READ {
421 /* IN */
422 __u16 port;
423 __u32 data_size;
424
425 /* OUT */
426 __u32 data;
427};
428
429/* MODS_ESC_PIO_WRITE */
430struct MODS_PIO_WRITE {
431 /* IN */
432 __u16 port;
433 __u32 data;
434 __u32 data_size;
435};
436
437#define INQ_CNT 8
438
439struct mods_irq_data {
440 __u32 irq;
441 __u32 delay;
442};
443
444struct mods_irq_status {
445 struct mods_irq_data data[INQ_CNT];
446 __u32 irqbits:INQ_CNT;
447 __u32 otherirq:1;
448};
449
450/* MODS_ESC_IRQ */
451struct MODS_IRQ {
452 /* IN */
453 __u32 cmd;
454 __u32 size; /* memory size */
455 __u32 irq; /* the irq number to be registered in driver */
456
457 /* IN OUT */
458 __u32 channel; /* application id allocated by driver. */
459
460 /* OUT */
461 struct mods_irq_status stat; /* for querying irq */
462 __u64 phys; /* the memory physical address */
463};
464#define MODS_IRQ_MAX_MASKS 16
465
466/* MODS_ESC_REGISTER_IRQ_3 */
467struct mods_mask_info2 {
468 __u8 mask_type; /*mask type 32/64 bit access*/
469 __u8 reserved[7]; /*force 64bit alignment */
470 __u32 irq_pending_offset; /* register to read IRQ pending status*/
471 __u32 irq_enabled_offset; /* register to read IRQ enabled status */
472 __u32 irq_enable_offset; /* register to write to enable IRQs */
473 __u32 irq_disable_offset; /* register to write to disable IRQs */
474 __u64 and_mask; /*and mask for clearing bits in this register */
475 __u64 or_mask; /*or mask for setting bit in this register */
476};
477
478struct MODS_REGISTER_IRQ_4 {
479 /* IN */
480 struct mods_pci_dev_2 dev; /* device identifying interrupt for */
481 /* which the mask will be applied */
482 __u64 aperture_addr; /* physical address of aperture */
483 __u32 aperture_size; /* size of the mapped region */
484 __u32 mask_info_cnt; /* number of entries in mask_info[]*/
485 struct mods_mask_info2 mask_info[MODS_IRQ_MAX_MASKS];
486 __u32 irq_count; /* number of irq's to allocate */
487 __u32 irq_flags; /* irq type and affinity */
488};
489
490struct MODS_REGISTER_IRQ_3 {
491 /* IN */
492 struct mods_pci_dev_2 dev; /* device identifying interrupt for */
493 /* which the mask will be applied */
494 __u64 aperture_addr; /* physical address of aperture */
495 __u32 aperture_size; /* size of the mapped region */
496 __u32 mask_info_cnt; /* number of entries in mask_info[]*/
497 struct mods_mask_info2 mask_info[MODS_IRQ_MAX_MASKS];
498 __u8 irq_type; /* MODS_IRQ_TYPE_* */
499 __u8 reserved[7]; /* keep alignment to 64bits */
500};
501
502/* MODS_ESC_REGISTER_IRQ_2 */
503/* MODS_ESC_UNREGISTER_IRQ_2 */
504/* MODS_ESC_IRQ_HANDLED_2 */
505struct MODS_REGISTER_IRQ_2 {
506 /* IN */
507 struct mods_pci_dev_2 dev; /* device which generates the interrupt */
508 __u8 type; /* MODS_IRQ_TYPE_* */
509};
510
511/* MODS_ESC_REGISTER_IRQ */
512/* MODS_ESC_UNREGISTER_IRQ */
513/* MODS_ESC_IRQ_HANDLED */
514struct MODS_REGISTER_IRQ {
515 /* IN */
516 struct mods_pci_dev dev; /* device which generates */
517 /* the interrupt */
518 __u8 type; /* MODS_IRQ_TYPE_* */
519};
520
521struct mods_irq_3 {
522 struct mods_pci_dev_2 dev; /* device which generated the interrupt */
523 __u32 irq_index; /* index of irq 0 for INTx & MSI */
524 __u32 delay; /* delay in ns between the irq */
525 /* occurring and MODS querying for it */
526};
527
528struct mods_irq_2 {
529 __u32 delay; /* delay in ns between the irq */
530 /* occurring and MODS querying for it */
531 struct mods_pci_dev_2 dev; /* device which generated the interrupt */
532};
533
534struct mods_irq {
535 __u32 delay; /* delay in ns between the irq */
536 /* occurring and MODS querying */
537 /* for it */
538 struct mods_pci_dev dev; /* device which generated */
539 /* the interrupt */
540};
541
542#define MODS_MAX_IRQS 32
543
544/* MODS_ESC_QUERY_IRQ_3 */
545struct MODS_QUERY_IRQ_3 {
546 /* OUT */
547 struct mods_irq_3 irq_list[MODS_MAX_IRQS];
548 __u8 more; /* indicates that more interrupts */
549 /* are waiting */
550};
551
552/* MODS_ESC_QUERY_IRQ_2 */
553struct MODS_QUERY_IRQ_2 {
554 /* OUT */
555 struct mods_irq_2 irq_list[MODS_MAX_IRQS];
556 __u8 more; /* indicates that more interrupts */
557 /* are waiting */
558};
559
560/* MODS_ESC_QUERY_IRQ */
561struct MODS_QUERY_IRQ {
562 /* OUT */
563 struct mods_irq irq_list[MODS_MAX_IRQS];
564 __u8 more; /* indicates that more interrupts are waiting */
565};
566
567#define MODS_IRQ_TYPE_INT 0
568#define MODS_IRQ_TYPE_MSI 1
569#define MODS_IRQ_TYPE_CPU 2
570#define MODS_IRQ_TYPE_MSIX 3
571#define MODS_IRQ_TYPE_MASK 0xff
572
573/* MODS_ESC_SET_IRQ_MULTIMASK */
574struct mods_mask_info {
575 __u8 mask_type; /*mask type 32/64 bit access*/
576 __u8 reserved[3];
577 __u32 reg_offset; /* offset of register within the bar aperture*/
578 __u64 and_mask; /*and mask for clearing bits in this register */
579 __u64 or_mask; /*or value for setting bit in this register */
580};
581
582struct MODS_SET_IRQ_MULTIMASK {
583 /* IN */
584 __u64 aperture_addr; /* physical address of aperture */
585 __u32 aperture_size; /* size of the mapped region */
586 struct mods_pci_dev_2 dev; /* device identifying interrupt for */
587 /* which the mask will be applied */
588 __u32 mask_info_cnt; /* number of entries in mask_info[]*/
589 struct mods_mask_info mask_info[MODS_IRQ_MAX_MASKS];
590 __u8 irq_type; /* irq type */
591};
592
593/* MODS_ESC_SET_IRQ_MASK_2 */
594struct MODS_SET_IRQ_MASK_2 {
595 /* IN */
596 __u64 aperture_addr;/* physical address of aperture */
597 __u32 aperture_size;/* size of the mapped region */
598 __u32 reg_offset; /* offset of the irq mask */
599 /* register within the aperture */
600 __u64 and_mask; /* and mask for clearing bits */
601 /* in the irq mask register */
602 __u64 or_mask; /* or mask for setting bits in */
603 /* the irq mask register */
604 struct mods_pci_dev_2 dev; /* device identifying interrupt */
605 /* for which the mask will be */
606 /* applied */
607 __u8 irq_type; /* irq type */
608 __u8 mask_type; /* mask type */
609};
610
611/* MODS_ESC_SET_IRQ_MASK */
612struct MODS_SET_IRQ_MASK {
613 /* IN */
614 __u64 aperture_addr; /* physical address of aperture */
615 __u32 aperture_size; /* size of the mapped region */
616 __u32 reg_offset; /* offset of the irq mask register */
617 /* within the aperture */
618 __u32 and_mask; /* and mask for clearing bits in */
619 /* the irq mask register */
620 __u32 or_mask; /* or mask for setting bits in */
621 /* the irq mask register */
622 struct mods_pci_dev dev; /* device identifying interrupt */
623 /* for which the mask will be */
624 /* applied */
625 __u8 irq_type; /* irq type */
626 __u8 mask_type; /* mask type */
627};
628
629#define MAX_DT_SIZE 64
630#define MAX_FULL_SIZE 128
631
632/*MODS_ESC_MAP_INTERRUPT*/
633struct MODS_DT_INFO {
634 /* OUT */
635 /* Logical irq number*/
636 __u32 irq;
637 /* IN */
638 /* DT name for looking up device tree node */
639 char dt_name[MAX_DT_SIZE];
640 /* Full name of node as in device tree */
641 char full_name[MAX_FULL_SIZE];
642 /* Irq index corresponding to physical irq */
643 __u32 index;
644};
645
646#define MAX_GPIO_NAME_SIZE 256
647struct MODS_GPIO_INFO {
648 /* OUTPUT */
649 /* Irq number to be mapped to gpio and returned to user */
650 __u32 irq;
651 /* IN */
652 /* Name of Gpio to be mapped */
653 char name[MAX_GPIO_NAME_SIZE];
654 /* IN */
655 /* DT Name of device that gpio belongs to */
656 char dt_name[MAX_DT_SIZE];
657 /* IN */
658 /* Name of device that gpio belongs to */
659 char full_name[MAX_DT_SIZE];
660};
661
662#define MODS_MASK_TYPE_IRQ_DISABLE 0
663#define MODS_MASK_TYPE_IRQ_DISABLE64 1
664
665#define ACPI_MODS_TYPE_INTEGER 1
666#define ACPI_MODS_TYPE_BUFFER 2
667#define ACPI_MODS_IGNORE_ACPI_ID 0xffffffff
668#define ACPI_MAX_BUFFER_LENGTH 4096
669#define ACPI_MAX_METHOD_LENGTH 12
670#define ACPI_MAX_ARGUMENT_NUMBER 12
671
672union ACPI_ARGUMENT {
673 __u32 type;
674
675 struct {
676 __u32 type;
677 __u32 value;
678 } integer;
679
680 struct {
681 __u32 type;
682 __u32 length;
683 __u32 offset;
684 } buffer;
685};
686
687/* MODS_ESC_EVAL_ACPI_METHOD */
688struct MODS_EVAL_ACPI_METHOD {
689 /* IN */
690 char method_name[ACPI_MAX_METHOD_LENGTH];
691 __u32 argument_count;
692 union ACPI_ARGUMENT argument[ACPI_MAX_ARGUMENT_NUMBER];
693 __u8 in_buffer[ACPI_MAX_BUFFER_LENGTH];
694
695 /* IN OUT */
696 __u32 out_data_size;
697
698 /* OUT */
699 __u8 out_buffer[ACPI_MAX_BUFFER_LENGTH];
700 __u32 out_status;
701};
702
703/* MODS_ESC_EVAL_DEV_ACPI_METHOD_3 */
704struct MODS_EVAL_DEV_ACPI_METHOD_3 {
705 /* IN OUT */
706 struct MODS_EVAL_ACPI_METHOD method;
707
708 /* IN */
709 struct mods_pci_dev_2 device;
710 __u32 acpi_id;
711};
712
713/* MODS_ESC_EVAL_DEV_ACPI_METHOD_2 */
714struct MODS_EVAL_DEV_ACPI_METHOD_2 {
715 /* IN OUT */
716 struct MODS_EVAL_ACPI_METHOD method;
717
718 /* IN */
719 struct mods_pci_dev_2 device;
720};
721
722/* MODS_ESC_EVAL_DEV_ACPI_METHOD */
723struct MODS_EVAL_DEV_ACPI_METHOD {
724 /* IN OUT */
725 struct MODS_EVAL_ACPI_METHOD method;
726
727 /* IN */
728 struct mods_pci_dev device;
729};
730
731/* MODS_ESC_ACPI_GET_DDC_2 */
732struct MODS_ACPI_GET_DDC_2 {
733 /* OUT */
734 __u32 out_data_size;
735 __u8 out_buffer[ACPI_MAX_BUFFER_LENGTH];
736
737 /* IN */
738 struct mods_pci_dev_2 device;
739};
740
741/* MODS_ESC_ACPI_GET_DDC */
742struct MODS_ACPI_GET_DDC {
743 /* OUT */
744 __u32 out_data_size;
745 __u8 out_buffer[ACPI_MAX_BUFFER_LENGTH];
746
747 /* IN */
748 struct mods_pci_dev device;
749};
750
751/* MODS_ESC_GET_VERSION */
752struct MODS_GET_VERSION {
753 /* OUT */
754 __u64 version;
755};
756
757/* MODS_ESC_SET_PARA */
758struct MODS_SET_PARA {
759 /* IN */
760 __u64 Highmem4g;
761 __u64 debug;
762};
763
764/* MODS_ESC_SET_MEMORY_TYPE */
765struct MODS_MEMORY_TYPE {
766 /* IN */
767 __u64 physical_address;
768 __u64 size;
769 __u32 type;
770};
771
772#define MAX_CLOCK_HANDLE_NAME 64
773
774/* MODS_ESC_GET_CLOCK_HANDLE */
775struct MODS_GET_CLOCK_HANDLE {
776 /* OUT */
777 __u32 clock_handle;
778
779 /* IN */
780 char device_name[MAX_CLOCK_HANDLE_NAME];
781 char controller_name[MAX_CLOCK_HANDLE_NAME];
782};
783
784/* MODS_ESC_SET_CLOCK_RATE, MODS_ESC_GET_CLOCK_RATE, */
785/* MODS_ESC_GET_CLOCK_MAX_RATE, MODS_ESC_SET_CLOCK_MAX_RATE */
786struct MODS_CLOCK_RATE {
787 /* IN/OUT */
788 __u64 clock_rate_hz;
789
790 /* IN */
791 __u32 clock_handle;
792};
793
794/* MODS_ESC_SET_CLOCK_PARENT, MODS_ESC_GET_CLOCK_PARENT */
795struct MODS_CLOCK_PARENT {
796 /* IN */
797 __u32 clock_handle;
798
799 /* IN/OUT */
800 __u32 clock_parent_handle;
801};
802
803/* MODS_ESC_ENABLE_CLOCK, MODS_ESC_DISABLE_CLOCK, */
804/* MODS_ESC_CLOCK_RESET_ASSERT, MODS_ESC_CLOCK_RESET_DEASSERT */
805struct MODS_CLOCK_HANDLE {
806 /* IN */
807 __u32 clock_handle;
808};
809
810/* MODS_ESC_IS_CLOCK_ENABLED */
811struct MODS_CLOCK_ENABLED {
812 /* IN */
813 __u32 clock_handle;
814
815 /* OUT */
816 __u32 enable_count;
817};
818
819#define MAX_CPU_MASKS_3 128 /* CPU indices can be at most 4096 apart */
820
821/* MODS_ESC_DEVICE_NUMA_INFO_3 */
822struct MODS_DEVICE_NUMA_INFO_3 {
823 /* IN */
824 struct mods_pci_dev_2 pci_device;
825
826 /* OUT */
827 __s32 node;
828 __u32 node_count;
829 __u32 cpu_count;
830 __u32 first_cpu_mask_offset;
831 __u32 node_cpu_mask[MAX_CPU_MASKS_3];
832};
833
834#if defined(__powerpc64__)
835#define MAX_CPU_MASKS 64 /* 32 masks of 32bits = 2048 CPUs max */
836#else
837#define MAX_CPU_MASKS 32 /* 32 masks of 32bits = 1024 CPUs max */
838#endif
839
840/* MODS_ESC_DEVICE_NUMA_INFO_2 */
841struct MODS_DEVICE_NUMA_INFO_2 {
842 /* IN */
843 struct mods_pci_dev_2 pci_device;
844
845 /* OUT */
846 __s32 node;
847 __u32 node_count;
848 __u32 node_cpu_mask[MAX_CPU_MASKS];
849 __u32 cpu_count;
850};
851
852/* MODS_ESC_DEVICE_NUMA_INFO */
853struct MODS_DEVICE_NUMA_INFO {
854 /* IN */
855 struct mods_pci_dev pci_device;
856
857 /* OUT */
858 __s32 node;
859 __u32 node_count;
860 __u32 node_cpu_mask[MAX_CPU_MASKS];
861 __u32 cpu_count;
862};
863
864/* The ids match MODS ids */
865#define MODS_MEMORY_CACHED 5
866#define MODS_MEMORY_UNCACHED 1
867#define MODS_MEMORY_WRITECOMBINE 2
868
869struct MODS_TEGRA_DC_WINDOW {
870 __s32 index;
871 __u32 flags;
872 __u32 x;
873 __u32 y;
874 __u32 w;
875 __u32 h;
876 __u32 out_x;
877 __u32 out_y;
878 __u32 out_w;
879 __u32 out_h;
880 __u32 pixformat; /* NVDC pix format */
881
882 __u32 bandwidth;
883};
884#define MODS_TEGRA_DC_WINDOW_FLAG_ENABLED (1 << 0)
885#define MODS_TEGRA_DC_WINDOW_FLAG_TILED (1 << 1)
886#define MODS_TEGRA_DC_WINDOW_FLAG_SCAN_COL (1 << 2)
887#define MODS_TEGRA_DC_MAX_WINDOWS (6)
888
889/* MODS_ESC_TEGRA_DC_CONFIG_POSSIBLE */
890struct MODS_TEGRA_DC_CONFIG_POSSIBLE {
891 /* IN/OUT */
892 struct MODS_TEGRA_DC_WINDOW windows[MODS_TEGRA_DC_MAX_WINDOWS];
893
894 /* IN */
895 __u8 head;
896 __u8 win_num;
897
898 /* OUT */
899 __u8 possible;
900};
901
902
903#define MODS_TEGRA_DC_SETUP_SD_LUT_SIZE 9
904#define MODS_TEGRA_DC_SETUP_BLTF_SIZE 16
905/* MODS_ESC_TEGRA_DC_SETUP_SD */
906struct MODS_TEGRA_DC_SETUP_SD {
907 /* IN */
908 __u8 head;
909 __u8 enable;
910
911 __u8 use_vid_luma;
912 __u8 csc_r;
913 __u8 csc_g;
914 __u8 csc_b;
915 __u8 aggressiveness;
916 __u8 bin_width_log2;
917
918 __u32 lut[MODS_TEGRA_DC_SETUP_SD_LUT_SIZE];
919 __u32 bltf[MODS_TEGRA_DC_SETUP_BLTF_SIZE];
920
921 __u32 klimit;
922 __u32 soft_clipping_threshold;
923 __u32 smooth_k_inc;
924 __u8 k_init_bias;
925
926
927 __u32 win_x;
928 __u32 win_y;
929 __u32 win_w;
930 __u32 win_h;
931};
932
933/* MODS_ESC_DMABUF_GET_PHYSICAL_ADDRESS */
934struct MODS_DMABUF_GET_PHYSICAL_ADDRESS {
935 /* IN */
936 __s32 buf_fd;
937 __u32 padding;
938 __u64 offset;
939
940 /* OUT */
941 __u64 physical_address;
942 __u64 segment_size;
943};
944
945#define MODS_ADSP_APP_NAME_SIZE 64
946#define MODS_ADSP_APP_MAX_PARAM 128
947struct MODS_ADSP_RUN_APP_INFO {
948 char app_name[MODS_ADSP_APP_NAME_SIZE];
949 char app_file_name[MODS_ADSP_APP_NAME_SIZE];
950 __u32 argc;
951 __u32 argv[MODS_ADSP_APP_MAX_PARAM];
952 __u32 timeout;
953};
954
955/* MODS_ESC_GET_SCREEN_INFO */
956struct MODS_SCREEN_INFO {
957 /* OUT */
958 __u8 orig_video_mode;
959 __u8 orig_video_is_vga;
960 __u16 lfb_width;
961 __u16 lfb_height;
962 __u16 lfb_depth;
963 __u32 lfb_base;
964 __u32 lfb_size;
965 __u16 lfb_linelength;
966};
967
968/* MODS_ESC_GET_SCREEN_INFO_2 */
969struct MODS_SCREEN_INFO_2 {
970 /* OUT */
971 struct MODS_SCREEN_INFO info;
972 __u32 ext_lfb_base;
973};
974
975enum MODS_DMA_TRANSACTION_TYPE {
976 MODS_DMA_MEMCPY,
977 MODS_DMA_XOR,
978 MODS_DMA_PQ,
979 MODS_DMA_XOR_VAL,
980 MODS_DMA_PQ_VAL,
981 MODS_DMA_MEMSET,
982 MODS_DMA_MEMSET_SG,
983 MODS_DMA_INTERRUPT,
984 MODS_DMA_SG,
985 MODS_DMA_PRIVATE,
986 MODS_DMA_ASYNC_TX,
987 MODS_DMA_SLAVE,
988 MODS_DMA_CYCLIC,
989 MODS_DMA_INTERLEAVE,
990/* last transaction type for creation of the capabilities mask */
991 MODS_DMA_TX_TYPE_END
992};
993
994struct MODS_DMA_HANDLE {
995 /* IN */
996 __u32 dma_type; /* Indicate the DMA Type*/
997 /* OUT */
998 __u32 dma_id; /* Inditify for the DMA */
999};
1000
1001enum MODS_DMA_TRANSFER_DIRECTION {
1002 MODS_DMA_MEM_TO_MEM,
1003 MODS_DMA_MEM_TO_DEV,
1004 MODS_DMA_DEV_TO_MEM,
1005 MODS_DMA_DEV_TO_DEV,
1006 MODS_DMA_TRANS_NONE
1007};
1008
1009enum MODS_DMA_BUSWIDTH {
1010 MODS_DMA_BUSWIDTH_UNDEFINED = 0,
1011 MODS_DMA_BUSWIDTH_1_BYTE = 1,
1012 MODS_DMA_BUSWIDTH_2_BYTES = 2,
1013 MODS_DMA_BUSWIDTH_4_BYTES = 4,
1014 MODS_DMA_BUSWIDTH_8_BYTES = 8
1015};
1016
1017struct MODS_DMA_CHANNEL_CONFIG {
1018 __u64 src_addr;
1019 __u64 dst_addr;
1020 struct MODS_DMA_HANDLE handle;
1021 __u32 direction;
1022 __u32 src_addr_width;
1023 __u32 dst_addr_width;
1024 __u32 src_maxburst;
1025 __u32 dst_maxburst;
1026 __u32 slave_id;
1027 __u32 device_fc;
1028};
1029
1030/* Node: Only support SINGLE MODS so far*/
1031enum MODS_DMA_TX_MODE {
1032 MODS_DMA_SINGLE = 0,
1033 MODS_DMA_TX_CYCLIC,
1034 MODS_DMA_INTERLEAVED /* Common to Slave as well as M2M clients. */
1035};
1036
1037typedef __s32 mods_dma_cookie_t;
1038
1039struct MODS_DMA_TX_DESC {
1040 /* IN */
1041 __u64 phys;
1042 __u64 phys_2; /* only valid for MEMCPY */
1043 struct MODS_DMA_HANDLE handle;
1044 __u32 mode;
1045 __u32 data_dir;
1046 __u32 length;
1047 __u32 flags;
1048 /* OUT */
1049 mods_dma_cookie_t cookie;
1050};
1051
1052enum MODS_DMA_WAIT_TYPE {
1053 MODS_DMA_SYNC_WAIT, /* wait until finished */
1054 MODS_DMA_ASYNC_WAIT /* just check tx status */
1055};
1056
1057struct MODS_DMA_WAIT_DESC {
1058 struct MODS_DMA_HANDLE handle;
1059 mods_dma_cookie_t cookie;
1060 __u32 type;
1061 /* OUT */
1062 __u32 tx_complete;
1063};
1064
1065#define MAX_NET_DEVICE_NAME_LENGTH 16
1066struct MODS_NET_DEVICE_NAME {
1067 /* in */
1068 char device_name[MAX_NET_DEVICE_NAME_LENGTH];
1069};
1070struct MODS_DMA_COHERENT_MEM_HANDLE {
1071 __u32 num_bytes;
1072 __u32 attrib;
1073 __u64 memory_handle_phys;
1074 __u64 memory_handle_virt;
1075};
1076
1077/* MODS_ESC_DMA_COPY_TO_USER */
1078struct MODS_DMA_COPY_TO_USER {
1079 __u32 num_bytes;
1080 __u32 attrib;
1081 __u64 memory_handle_src;
1082 __u64 memory_handle_dst;
1083};
1084
1085struct MODS_TEGRA_PROD_SET_TUPLE {
1086 /* IN */
1087 __u64 prod_dev_handle;
1088 __u64 ctrl_dev_handle;
1089 char prod_name[MAX_DT_SIZE];
1090 __u32 index;
1091 __u32 offset;
1092 __u32 mask;
1093};
1094
1095struct MODS_TEGRA_PROD_IS_SUPPORTED {
1096 /* IN */
1097 __u64 prod_dev_handle;
1098 char prod_name[MAX_DT_SIZE];
1099 /* OUT */
1100 __u32 is_supported;
1101};
1102
1103struct MODS_TEGRA_PROD_ITERATOR {
1104 /* IN */
1105 __u64 device_handle;
1106 char name[MAX_DT_SIZE];
1107 char next_name[MAX_DT_SIZE];
1108 __u32 index;
1109 __u32 is_leaf;
1110 /* OUT */
1111 __u64 next_device_handle;
1112};
1113
1114/* MODS_ESC_GET_ATS_ADDRESS_RANGE */
1115struct MODS_GET_ATS_ADDRESS_RANGE {
1116 /* IN */
1117 struct mods_pci_dev_2 pci_device;
1118 __s32 npu_index;
1119 __u8 reserved[4]; /* Alignment */
1120
1121 /* OUT */
1122 struct mods_pci_dev_2 npu_device;
1123 __u64 phys_addr;
1124 __u64 guest_addr;
1125 __u64 aperture_size;
1126 __s32 numa_memory_node;
1127};
1128
1129/* MODS_ESC_SET_NVLINK_SYSMEM_TRAINED */
1130struct MODS_SET_NVLINK_SYSMEM_TRAINED {
1131 /* IN */
1132 struct mods_pci_dev_2 pci_device;
1133 __u8 trained;
1134};
1135
1136/* MODS_ESC_GET_NVLINK_LINE_RATE */
1137struct MODS_GET_NVLINK_LINE_RATE {
1138 /* IN */
1139 struct mods_pci_dev_2 pci_device;
1140 __s32 npu_index;
1141
1142 /* OUT */
1143 __u32 speed;
1144};
1145
1146/* MODS_ESC_ACQUIRE_ACCESS_TOKEN
1147 * MODS_ESC_RELEASE_ACCESS_TOKEN
1148 * MODS_ESC_VERIFY_ACCESS_TOKEN
1149 */
1150#define MODS_ACCESS_TOKEN_NONE ~0U
1151struct MODS_ACCESS_TOKEN {
1152 /* IN/OUT */
1153 __u32 token;
1154};
1155
1156#define MODS_MAX_SYSFS_PATH_BUF_SIZE 512
1157#define MODS_MAX_SYSFS_PATH_LEN (512 - 6)
1158#define MODS_MAX_SYSFS_FILE_SIZE 4096
1159
1160/* MODS_ESC_WRITE_SYSFS_NODE */
1161struct MODS_SYSFS_NODE {
1162 /* IN */
1163 char path[MODS_MAX_SYSFS_PATH_BUF_SIZE];
1164 char contents[MODS_MAX_SYSFS_FILE_SIZE];
1165 __u32 size;
1166};
1167
1168#define MODS_IRQ_TYPE_FROM_FLAGS(flags) ((flags)&0xf)
1169#define MODS_IRQ_FLAG_FROM_FLAGS(flags) (((flags)&0xfff0)>>4)
1170
1171/* MODS_ESC_SET_NUM_VF */
1172struct MODS_SET_NUM_VF {
1173 /* IN */
1174 struct mods_pci_dev_2 dev;
1175 __u32 numvfs; /* number of virtual functions */
1176};
1177
1178/* MODS_ESC_READ_MSR
1179 * MODS_ESC_WRITE_MSR
1180 */
1181struct MODS_MSR {
1182 /* IN */
1183 __u32 reg;
1184 __u32 cpu_num;
1185
1186 /* IN/OUT */
1187 __u32 low;
1188 __u32 high;
1189};
1190
1191#pragma pack(pop)
1192
1193/* ************************************************************************* */
1194/* ************************************************************************* */
1195/* ** */
1196/* ** ESCAPE CALLS */
1197/* ** */
1198/* ************************************************************************* */
1199/* ************************************************************************* */
1200#define MODS_IOC_MAGIC 'x'
1201#define MODS_ESC_ALLOC_PAGES \
1202 _IOWR(MODS_IOC_MAGIC, 0, struct MODS_ALLOC_PAGES)
1203#define MODS_ESC_FREE_PAGES \
1204 _IOWR(MODS_IOC_MAGIC, 1, struct MODS_FREE_PAGES)
1205#define MODS_ESC_GET_PHYSICAL_ADDRESS \
1206 _IOWR(MODS_IOC_MAGIC, 2, struct MODS_GET_PHYSICAL_ADDRESS)
1207#define MODS_ESC_VIRTUAL_TO_PHYSICAL \
1208 _IOWR(MODS_IOC_MAGIC, 3, struct MODS_VIRTUAL_TO_PHYSICAL)
1209#define MODS_ESC_PHYSICAL_TO_VIRTUAL \
1210 _IOWR(MODS_IOC_MAGIC, 4, struct MODS_PHYSICAL_TO_VIRTUAL)
1211#define MODS_ESC_FIND_PCI_DEVICE \
1212 _IOWR(MODS_IOC_MAGIC, 5, struct MODS_FIND_PCI_DEVICE)
1213#define MODS_ESC_FIND_PCI_CLASS_CODE \
1214 _IOWR(MODS_IOC_MAGIC, 6, struct MODS_FIND_PCI_CLASS_CODE)
1215#define MODS_ESC_PCI_READ \
1216 _IOWR(MODS_IOC_MAGIC, 7, struct MODS_PCI_READ)
1217#define MODS_ESC_PCI_WRITE \
1218 _IOWR(MODS_IOC_MAGIC, 8, struct MODS_PCI_WRITE)
1219#define MODS_ESC_PIO_READ \
1220 _IOWR(MODS_IOC_MAGIC, 9, struct MODS_PIO_READ)
1221#define MODS_ESC_PIO_WRITE \
1222 _IOWR(MODS_IOC_MAGIC, 10, struct MODS_PIO_WRITE)
1223/* Deprecated */
1224#define MODS_ESC_IRQ_REGISTER \
1225 _IOWR(MODS_IOC_MAGIC, 11, struct MODS_IRQ)
1226/* Deprecated */
1227#define MODS_ESC_IRQ_FREE \
1228 _IOWR(MODS_IOC_MAGIC, 12, struct MODS_IRQ)
1229/* Deprecated */
1230#define MODS_ESC_IRQ_INQUIRY \
1231 _IOWR(MODS_IOC_MAGIC, 13, struct MODS_IRQ)
1232#define MODS_ESC_EVAL_ACPI_METHOD \
1233 _IOWR_BAD(MODS_IOC_MAGIC, 16, struct MODS_EVAL_ACPI_METHOD)
1234#define MODS_ESC_GET_API_VERSION \
1235 _IOWR(MODS_IOC_MAGIC, 17, struct MODS_GET_VERSION)
1236/* Deprecated */
1237#define MODS_ESC_GET_KERNEL_VERSION \
1238 _IOWR(MODS_IOC_MAGIC, 18, struct MODS_GET_VERSION)
1239/* Deprecated */
1240#define MODS_ESC_SET_DRIVER_PARA \
1241 _IOWR(MODS_IOC_MAGIC, 19, struct MODS_SET_PARA)
1242/* Deprecated */
1243#define MODS_ESC_MSI_REGISTER \
1244 _IOWR(MODS_IOC_MAGIC, 20, struct MODS_IRQ)
1245/* Deprecated */
1246#define MODS_ESC_REARM_MSI \
1247 _IOWR(MODS_IOC_MAGIC, 21, struct MODS_IRQ)
1248#define MODS_ESC_SET_MEMORY_TYPE \
1249 _IOW(MODS_IOC_MAGIC, 22, struct MODS_MEMORY_TYPE)
1250/* Deprecated */
1251#define MODS_ESC_PCI_BUS_ADD_DEVICES \
1252 _IOW(MODS_IOC_MAGIC, 23, struct MODS_PCI_BUS_ADD_DEVICES)
1253#define MODS_ESC_REGISTER_IRQ \
1254 _IOW(MODS_IOC_MAGIC, 24, struct MODS_REGISTER_IRQ)
1255#define MODS_ESC_UNREGISTER_IRQ \
1256 _IOW(MODS_IOC_MAGIC, 25, struct MODS_REGISTER_IRQ)
1257#define MODS_ESC_QUERY_IRQ \
1258 _IOR(MODS_IOC_MAGIC, 26, struct MODS_QUERY_IRQ)
1259#define MODS_ESC_EVAL_DEV_ACPI_METHOD \
1260 _IOWR_BAD(MODS_IOC_MAGIC, 27, struct MODS_EVAL_DEV_ACPI_METHOD)
1261#define MODS_ESC_ACPI_GET_DDC \
1262 _IOWR(MODS_IOC_MAGIC, 28, struct MODS_ACPI_GET_DDC)
1263#define MODS_ESC_GET_CLOCK_HANDLE \
1264 _IOWR(MODS_IOC_MAGIC, 29, struct MODS_GET_CLOCK_HANDLE)
1265#define MODS_ESC_SET_CLOCK_RATE \
1266 _IOW(MODS_IOC_MAGIC, 30, struct MODS_CLOCK_RATE)
1267#define MODS_ESC_GET_CLOCK_RATE \
1268 _IOWR(MODS_IOC_MAGIC, 31, struct MODS_CLOCK_RATE)
1269#define MODS_ESC_SET_CLOCK_PARENT \
1270 _IOW(MODS_IOC_MAGIC, 32, struct MODS_CLOCK_PARENT)
1271#define MODS_ESC_GET_CLOCK_PARENT \
1272 _IOWR(MODS_IOC_MAGIC, 33, struct MODS_CLOCK_PARENT)
1273#define MODS_ESC_ENABLE_CLOCK \
1274 _IOW(MODS_IOC_MAGIC, 34, struct MODS_CLOCK_HANDLE)
1275#define MODS_ESC_DISABLE_CLOCK \
1276 _IOW(MODS_IOC_MAGIC, 35, struct MODS_CLOCK_HANDLE)
1277#define MODS_ESC_IS_CLOCK_ENABLED \
1278 _IOWR(MODS_IOC_MAGIC, 36, struct MODS_CLOCK_ENABLED)
1279#define MODS_ESC_CLOCK_RESET_ASSERT \
1280 _IOW(MODS_IOC_MAGIC, 37, struct MODS_CLOCK_HANDLE)
1281#define MODS_ESC_CLOCK_RESET_DEASSERT \
1282 _IOW(MODS_IOC_MAGIC, 38, struct MODS_CLOCK_HANDLE)
1283/* Deprecated */
1284#define MODS_ESC_SET_IRQ_MASK \
1285 _IOW(MODS_IOC_MAGIC, 39, struct MODS_SET_IRQ_MASK)
1286#define MODS_ESC_MEMORY_BARRIER \
1287 _IO(MODS_IOC_MAGIC, 40)
1288#define MODS_ESC_IRQ_HANDLED \
1289 _IOW(MODS_IOC_MAGIC, 41, struct MODS_REGISTER_IRQ)
1290#define MODS_ESC_FLUSH_CPU_CACHE_RANGE \
1291 _IOW(MODS_IOC_MAGIC, 42, struct MODS_FLUSH_CPU_CACHE_RANGE)
1292#define MODS_ESC_GET_CLOCK_MAX_RATE \
1293 _IOWR(MODS_IOC_MAGIC, 43, struct MODS_CLOCK_RATE)
1294#define MODS_ESC_SET_CLOCK_MAX_RATE \
1295 _IOW(MODS_IOC_MAGIC, 44, struct MODS_CLOCK_RATE)
1296#define MODS_ESC_DEVICE_ALLOC_PAGES \
1297 _IOWR(MODS_IOC_MAGIC, 45, struct MODS_DEVICE_ALLOC_PAGES)
1298#define MODS_ESC_DEVICE_NUMA_INFO \
1299 _IOWR(MODS_IOC_MAGIC, 46, struct MODS_DEVICE_NUMA_INFO)
1300#define MODS_ESC_TEGRA_DC_CONFIG_POSSIBLE \
1301 _IOWR(MODS_IOC_MAGIC, 47, \
1302 struct MODS_TEGRA_DC_CONFIG_POSSIBLE)
1303#define MODS_ESC_TEGRA_DC_SETUP_SD \
1304 _IOW(MODS_IOC_MAGIC, 48, struct MODS_TEGRA_DC_SETUP_SD)
1305#define MODS_ESC_DMABUF_GET_PHYSICAL_ADDRESS \
1306 _IOWR(MODS_IOC_MAGIC, 49, \
1307 struct MODS_DMABUF_GET_PHYSICAL_ADDRESS)
1308#define MODS_ESC_ADSP_LOAD \
1309 _IO(MODS_IOC_MAGIC, 50)
1310#define MODS_ESC_ADSP_START \
1311 _IO(MODS_IOC_MAGIC, 51)
1312#define MODS_ESC_ADSP_STOP \
1313 _IO(MODS_IOC_MAGIC, 52)
1314#define MODS_ESC_ADSP_RUN_APP \
1315 _IOW(MODS_IOC_MAGIC, 53, struct MODS_ADSP_RUN_APP_INFO)
1316#define MODS_ESC_PCI_GET_BAR_INFO \
1317 _IOWR(MODS_IOC_MAGIC, 54, struct MODS_PCI_GET_BAR_INFO)
1318#define MODS_ESC_PCI_GET_IRQ \
1319 _IOWR(MODS_IOC_MAGIC, 55, struct MODS_PCI_GET_IRQ)
1320/* Deprecated */
1321#define MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS \
1322 _IOWR(MODS_IOC_MAGIC, 56, \
1323 struct MODS_GET_PHYSICAL_ADDRESS)
1324#define MODS_ESC_DEVICE_ALLOC_PAGES_2 \
1325 _IOWR(MODS_IOC_MAGIC, 57, struct MODS_DEVICE_ALLOC_PAGES_2)
1326#define MODS_ESC_FIND_PCI_DEVICE_2 \
1327 _IOWR(MODS_IOC_MAGIC, 58, struct MODS_FIND_PCI_DEVICE_2)
1328#define MODS_ESC_FIND_PCI_CLASS_CODE_2 \
1329 _IOWR(MODS_IOC_MAGIC, 59, \
1330 struct MODS_FIND_PCI_CLASS_CODE_2)
1331#define MODS_ESC_PCI_GET_BAR_INFO_2 \
1332 _IOWR(MODS_IOC_MAGIC, 60, struct MODS_PCI_GET_BAR_INFO_2)
1333#define MODS_ESC_PCI_GET_IRQ_2 \
1334 _IOWR(MODS_IOC_MAGIC, 61, struct MODS_PCI_GET_IRQ_2)
1335#define MODS_ESC_PCI_READ_2 \
1336 _IOWR(MODS_IOC_MAGIC, 62, struct MODS_PCI_READ_2)
1337#define MODS_ESC_PCI_WRITE_2 \
1338 _IOW(MODS_IOC_MAGIC, 63, struct MODS_PCI_WRITE_2)
1339#define MODS_ESC_REGISTER_IRQ_2 \
1340 _IOW(MODS_IOC_MAGIC, 64, struct MODS_REGISTER_IRQ_2)
1341#define MODS_ESC_UNREGISTER_IRQ_2 \
1342 _IOW(MODS_IOC_MAGIC, 65, struct MODS_REGISTER_IRQ_2)
1343#define MODS_ESC_IRQ_HANDLED_2 \
1344 _IOW(MODS_IOC_MAGIC, 66, struct MODS_REGISTER_IRQ_2)
1345#define MODS_ESC_QUERY_IRQ_2 \
1346 _IOR(MODS_IOC_MAGIC, 67, struct MODS_QUERY_IRQ_2)
1347/* Deprecated */
1348#define MODS_ESC_SET_IRQ_MASK_2 \
1349 _IOW(MODS_IOC_MAGIC, 68, struct MODS_SET_IRQ_MASK_2)
1350#define MODS_ESC_EVAL_DEV_ACPI_METHOD_2 \
1351 _IOWR_BAD(MODS_IOC_MAGIC, 69,\
1352 struct MODS_EVAL_DEV_ACPI_METHOD_2)
1353#define MODS_ESC_DEVICE_NUMA_INFO_2 \
1354 _IOWR(MODS_IOC_MAGIC, 70, struct MODS_DEVICE_NUMA_INFO_2)
1355#define MODS_ESC_ACPI_GET_DDC_2 \
1356 _IOWR(MODS_IOC_MAGIC, 71, struct MODS_ACPI_GET_DDC_2)
1357#define MODS_ESC_GET_SCREEN_INFO \
1358 _IOR(MODS_IOC_MAGIC, 72, struct MODS_SCREEN_INFO)
1359#define MODS_ESC_PCI_HOT_RESET \
1360 _IOW(MODS_IOC_MAGIC, 73, struct MODS_PCI_HOT_RESET)
1361#define MODS_ESC_SET_PPC_TCE_BYPASS \
1362 _IOWR(MODS_IOC_MAGIC, 74, struct MODS_SET_PPC_TCE_BYPASS)
1363#define MODS_ESC_DMA_MAP_MEMORY \
1364 _IOW(MODS_IOC_MAGIC, 75, struct MODS_DMA_MAP_MEMORY)
1365#define MODS_ESC_DMA_UNMAP_MEMORY \
1366 _IOW(MODS_IOC_MAGIC, 76, struct MODS_DMA_MAP_MEMORY)
1367/* Deprecated */
1368#define MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS_2 \
1369 _IOWR(MODS_IOC_MAGIC, 77, \
1370 struct MODS_GET_PHYSICAL_ADDRESS_2)
1371/* Deprecated */
1372#define MODS_ESC_PCI_MAP_RESOURCE \
1373 _IOWR(MODS_IOC_MAGIC, 78, struct MODS_PCI_MAP_RESOURCE)
1374/* Deprecated */
1375#define MODS_ESC_PCI_UNMAP_RESOURCE \
1376 _IOW(MODS_IOC_MAGIC, 79, struct MODS_PCI_UNMAP_RESOURCE)
1377#define MODS_ESC_DMA_REQUEST_HANDLE \
1378 _IOR(MODS_IOC_MAGIC, 80, struct MODS_DMA_HANDLE)
1379#define MODS_ESC_DMA_RELEASE_HANDLE \
1380 _IOW(MODS_IOC_MAGIC, 81, struct MODS_DMA_HANDLE)
1381#define MODS_ESC_DMA_SET_CONFIG \
1382 _IOW(MODS_IOC_MAGIC, 82, struct MODS_DMA_CHANNEL_CONFIG)
1383#define MODS_ESC_DMA_TX_SUBMIT \
1384 _IOW(MODS_IOC_MAGIC, 83, struct MODS_DMA_TX_DESC)
1385#define MODS_ESC_DMA_TX_WAIT \
1386 _IOWR(MODS_IOC_MAGIC, 84, struct MODS_DMA_WAIT_DESC)
1387#define MODS_ESC_DMA_ISSUE_PENDING \
1388 _IOW(MODS_IOC_MAGIC, 85, struct MODS_DMA_HANDLE)
1389/* Deprecated */
1390#define MODS_ESC_SET_IRQ_MULTIMASK \
1391 _IOW(MODS_IOC_MAGIC, 86, struct MODS_SET_IRQ_MULTIMASK)
1392#define MODS_ESC_NET_FORCE_LINK \
1393 _IOW(MODS_IOC_MAGIC, 87, struct MODS_NET_DEVICE_NAME)
1394#define MODS_ESC_REGISTER_IRQ_3 \
1395 _IOW(MODS_IOC_MAGIC, 88, struct MODS_REGISTER_IRQ_3)
1396#define MODS_ESC_DMA_ALLOC_COHERENT \
1397 _IOWR(MODS_IOC_MAGIC, 89, \
1398 struct MODS_DMA_COHERENT_MEM_HANDLE)
1399#define MODS_ESC_DMA_FREE_COHERENT \
1400 _IOWR(MODS_IOC_MAGIC, 90, \
1401 struct MODS_DMA_COHERENT_MEM_HANDLE)
1402#define MODS_ESC_DMA_COPY_TO_USER \
1403 _IOWR(MODS_IOC_MAGIC, 91, \
1404 struct MODS_DMA_COPY_TO_USER)
1405#define MODS_ESC_MAP_INTERRUPT \
1406 _IOWR(MODS_IOC_MAGIC, 92, \
1407 struct MODS_DT_INFO)
1408#define MODS_ESC_LOCK_CONSOLE \
1409 _IO(MODS_IOC_MAGIC, 93)
1410#define MODS_ESC_UNLOCK_CONSOLE \
1411 _IO(MODS_IOC_MAGIC, 94)
1412#define MODS_ESC_TEGRA_PROD_IS_SUPPORTED \
1413 _IOWR(MODS_IOC_MAGIC, 95, \
1414 struct MODS_TEGRA_PROD_IS_SUPPORTED)
1415#define MODS_ESC_TEGRA_PROD_SET_PROD_ALL \
1416 _IOW(MODS_IOC_MAGIC, 96, \
1417 struct MODS_TEGRA_PROD_SET_TUPLE)
1418#define MODS_ESC_TEGRA_PROD_SET_PROD_BOOT \
1419 _IOW(MODS_IOC_MAGIC, 97, \
1420 struct MODS_TEGRA_PROD_SET_TUPLE)
1421#define MODS_ESC_TEGRA_PROD_SET_PROD_BY_NAME \
1422 _IOW(MODS_IOC_MAGIC, 98, \
1423 struct MODS_TEGRA_PROD_SET_TUPLE)
1424#define MODS_ESC_TEGRA_PROD_SET_PROD_EXACT \
1425 _IOW(MODS_IOC_MAGIC, 99, \
1426 struct MODS_TEGRA_PROD_SET_TUPLE)
1427#define MODS_ESC_TEGRA_PROD_ITERATE_DT \
1428 _IOWR(MODS_IOC_MAGIC, 100, \
1429 struct MODS_TEGRA_PROD_ITERATOR)
1430#define MODS_ESC_GET_ATS_ADDRESS_RANGE \
1431 _IOWR(MODS_IOC_MAGIC, 101, \
1432 struct MODS_GET_ATS_ADDRESS_RANGE)
1433#define MODS_ESC_SET_NVLINK_SYSMEM_TRAINED \
1434 _IOW(MODS_IOC_MAGIC, 102, \
1435 struct MODS_SET_NVLINK_SYSMEM_TRAINED)
1436#define MODS_ESC_GET_NVLINK_LINE_RATE \
1437 _IOWR(MODS_IOC_MAGIC, 103, \
1438 struct MODS_GET_NVLINK_LINE_RATE)
1439#define MODS_ESC_SUSPEND_CONSOLE \
1440 _IO(MODS_IOC_MAGIC, 104)
1441#define MODS_ESC_RESUME_CONSOLE \
1442 _IO(MODS_IOC_MAGIC, 105)
1443#define MODS_ESC_GET_SCREEN_INFO_2 \
1444 _IOR(MODS_IOC_MAGIC, 106, struct MODS_SCREEN_INFO_2)
1445#define MODS_ESC_ACQUIRE_ACCESS_TOKEN \
1446 _IOR(MODS_IOC_MAGIC, 107, struct MODS_ACCESS_TOKEN)
1447#define MODS_ESC_RELEASE_ACCESS_TOKEN \
1448 _IOW(MODS_IOC_MAGIC, 108, struct MODS_ACCESS_TOKEN)
1449#define MODS_ESC_VERIFY_ACCESS_TOKEN \
1450 _IOW(MODS_IOC_MAGIC, 109, struct MODS_ACCESS_TOKEN)
1451#define MODS_ESC_GET_IOMMU_STATE \
1452 _IOWR(MODS_IOC_MAGIC, 110, struct MODS_GET_IOMMU_STATE)
1453#define MODS_ESC_WRITE_SYSFS_NODE \
1454 _IOW(MODS_IOC_MAGIC, 111, struct MODS_SYSFS_NODE)
1455#define MODS_ESC_GET_PHYSICAL_ADDRESS_2 \
1456 _IOWR(MODS_IOC_MAGIC, 112, \
1457 struct MODS_GET_PHYSICAL_ADDRESS_3)
1458#define MODS_ESC_GET_MAPPED_PHYSICAL_ADDRESS_3 \
1459 _IOWR(MODS_IOC_MAGIC, 113, \
1460 struct MODS_GET_PHYSICAL_ADDRESS_3)
1461#define MODS_ESC_REGISTER_IRQ_4 \
1462 _IOW(MODS_IOC_MAGIC, 114, struct MODS_REGISTER_IRQ_4)
1463#define MODS_ESC_QUERY_IRQ_3 \
1464 _IOR(MODS_IOC_MAGIC, 115, struct MODS_QUERY_IRQ_3)
1465#define MODS_ESC_SET_NUM_VF \
1466 _IOW(MODS_IOC_MAGIC, 116, struct MODS_SET_NUM_VF)
1467#define MODS_ESC_SET_TOTAL_VF \
1468 _IOW(MODS_IOC_MAGIC, 117, struct MODS_SET_NUM_VF)
1469#define MODS_ESC_PCI_SET_DMA_MASK \
1470 _IOW(MODS_IOC_MAGIC, 118, struct MODS_PCI_DMA_MASK)
1471#define MODS_ESC_GET_IOMMU_STATE_2 \
1472 _IOWR(MODS_IOC_MAGIC, 119, struct MODS_GET_IOMMU_STATE)
1473#define MODS_ESC_READ_MSR \
1474 _IOWR(MODS_IOC_MAGIC, 120, struct MODS_MSR)
1475#define MODS_ESC_WRITE_MSR \
1476 _IOW(MODS_IOC_MAGIC, 121, struct MODS_MSR)
1477#define MODS_ESC_EVAL_DEV_ACPI_METHOD_3 \
1478 _IOWR_BAD(MODS_IOC_MAGIC, 122,\
1479 struct MODS_EVAL_DEV_ACPI_METHOD_3)
1480#define MODS_ESC_PCI_BUS_REMOVE_DEV\
1481 _IOW(MODS_IOC_MAGIC, 123, struct MODS_PCI_BUS_REMOVE_DEV)
1482#define MODS_ESC_ALLOC_PAGES_2 \
1483 _IOWR(MODS_IOC_MAGIC, 124, struct MODS_ALLOC_PAGES_2)
1484#define MODS_ESC_MERGE_PAGES \
1485 _IOWR(MODS_IOC_MAGIC, 125, struct MODS_MERGE_PAGES)
1486#define MODS_ESC_DEVICE_NUMA_INFO_3 \
1487 _IOWR(MODS_IOC_MAGIC, 126, struct MODS_DEVICE_NUMA_INFO_3)
1488#define MODS_ESC_PCI_BUS_RESCAN \
1489 _IOW(MODS_IOC_MAGIC, 127, struct MODS_PCI_BUS_RESCAN)
1490#define MODS_ESC_MAP_GPIO \
1491 _IOWR(MODS_IOC_MAGIC, 128, \
1492 struct MODS_GPIO_INFO)
1493
1494#endif /* _UAPI_MODS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-22 20:38:34 -0500