video: tegra: t210: fix dram width and bw reset

DRAM width was updated to 128bit as per Shield's (T214) configuration.
But, T210 SoCs have 64bit DRAM width. Since Shield is on a different
branch than rel-32, updating the T21x DRAM width parameter to match
that of T210 SoCs on rel-32.

Also, a recent update to display bandwidth programming logic caused
issues with clearing/resetting bandwidth when userspace clients go
down. Updated logic to avoid ignoring requests to reset bandwidth.

bug 200555268

Change-Id: Ib67587ff01e26bc472167d0781cd57404f22d7a9
Signed-off-by: Naveen Kumar S <nkumars@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2207027
Reviewed-by: Shu Zhong <shuz@nvidia.com>
Reviewed-by: Prafull Suryawanshi <prafulls@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Ninad Malwade <nmalwade@nvidia.com>
Tested-by: Ninad Malwade <nmalwade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

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