diff options
| author | Igor Nabirushkin <inabirushkin@nvidia.com> | 2014-01-26 08:59:25 -0500 |
|---|---|---|
| committer | Igor Nabirushkin <inabirushkin@nvidia.com> | 2017-07-13 10:18:39 -0400 |
| commit | faefcfd87cdaa071edfb6c4194867d80548b5377 (patch) | |
| tree | e681f1481a02e2827bfee1bd93fbb92054a88cbe /include/linux | |
| parent | a68baee1ececd39e8fe18dec9f0df07dd52dba5e (diff) | |
misc: tegra-profiler: add group samples
Group CPU cycles and cache misses samples.
To reduce the amount of data passed from the target to the host,
we can group samples that have a lot of common information.
Bug 1447582
Change-Id: I9b16bf4f18455ff6219fd58373eceba4cb71e352
Signed-off-by: Igor Nabirushkin <inabirushkin@nvidia.com>
Reviewed-on: http://git-master/r/360133
(cherry picked from commit c71f7e558a9c36752d8f845a17e64aaa9ccf90a2)
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/tegra_profiler.h | 87 |
1 files changed, 51 insertions, 36 deletions
diff --git a/include/linux/tegra_profiler.h b/include/linux/tegra_profiler.h index b122b97dd..e3f90a268 100644 --- a/include/linux/tegra_profiler.h +++ b/include/linux/tegra_profiler.h | |||
| @@ -1,7 +1,7 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * include/linux/tegra_profiler.h | 2 | * include/linux/tegra_profiler.h |
| 3 | * | 3 | * |
| 4 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. |
| 5 | * | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
| @@ -19,7 +19,7 @@ | |||
| 19 | 19 | ||
| 20 | #include <linux/ioctl.h> | 20 | #include <linux/ioctl.h> |
| 21 | 21 | ||
| 22 | #define QUADD_SAMPLES_VERSION 17 | 22 | #define QUADD_SAMPLES_VERSION 18 |
| 23 | #define QUADD_IO_VERSION 9 | 23 | #define QUADD_IO_VERSION 9 |
| 24 | 24 | ||
| 25 | #define QUADD_IO_VERSION_DYNAMIC_RB 5 | 25 | #define QUADD_IO_VERSION_DYNAMIC_RB 5 |
| @@ -29,6 +29,7 @@ | |||
| 29 | #define QUADD_IO_VERSION_GET_MMAP 9 | 29 | #define QUADD_IO_VERSION_GET_MMAP 9 |
| 30 | 30 | ||
| 31 | #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17 | 31 | #define QUADD_SAMPLE_VERSION_THUMB_MODE_FLAG 17 |
| 32 | #define QUADD_SAMPLE_VERSION_GROUP_SAMPLES 18 | ||
| 32 | 33 | ||
| 33 | #define QUADD_MAX_COUNTERS 32 | 34 | #define QUADD_MAX_COUNTERS 32 |
| 34 | #define QUADD_MAX_PROCESS 64 | 35 | #define QUADD_MAX_PROCESS 64 |
| @@ -93,8 +94,6 @@ enum quadd_events_id { | |||
| 93 | QUADD_EVENT_TYPE_MAX, | 94 | QUADD_EVENT_TYPE_MAX, |
| 94 | }; | 95 | }; |
| 95 | 96 | ||
| 96 | #pragma pack(push, 4) | ||
| 97 | |||
| 98 | struct event_data { | 97 | struct event_data { |
| 99 | int event_source; | 98 | int event_source; |
| 100 | int event_id; | 99 | int event_id; |
| @@ -125,49 +124,56 @@ enum quadd_cpu_mode { | |||
| 125 | QUADD_CPU_MODE_NONE, | 124 | QUADD_CPU_MODE_NONE, |
| 126 | }; | 125 | }; |
| 127 | 126 | ||
| 128 | struct quadd_sample_data { | 127 | typedef u32 quadd_bt_addr_t; |
| 129 | u32 event_id; | 128 | |
| 129 | #pragma pack(push, 1) | ||
| 130 | 130 | ||
| 131 | u32 ip; | 131 | struct quadd_sample_data { |
| 132 | u64 ip; | ||
| 132 | u32 pid; | 133 | u32 pid; |
| 133 | u64 time; | 134 | u64 time; |
| 134 | u32 cpu; | ||
| 135 | u64 period; | ||
| 136 | 135 | ||
| 137 | u32 callchain_nr; | 136 | u16 cpu:6, |
| 137 | user_mode:1, | ||
| 138 | lp_mode:1, | ||
| 139 | thumb_mode:1, | ||
| 140 | reserved:7; | ||
| 141 | |||
| 142 | u8 callchain_nr; | ||
| 143 | u32 events_flags; | ||
| 138 | }; | 144 | }; |
| 139 | 145 | ||
| 140 | struct quadd_mmap_data { | 146 | struct quadd_mmap_data { |
| 141 | u32 pid; | 147 | u32 pid; |
| 142 | u32 addr; | 148 | u64 addr; |
| 143 | u64 len; | 149 | u64 len; |
| 144 | u64 pgoff; | 150 | u32 pgoff; |
| 145 | 151 | ||
| 146 | u32 filename_length; | 152 | u16 filename_length; |
| 147 | }; | 153 | }; |
| 148 | 154 | ||
| 149 | struct quadd_ma_data { | 155 | struct quadd_ma_data { |
| 150 | u32 pid; | 156 | u32 pid; |
| 151 | u64 time; | 157 | u64 time; |
| 152 | 158 | ||
| 153 | u64 vm_size; | 159 | u32 vm_size; |
| 154 | u64 rss_size; | 160 | u32 rss_size; |
| 155 | }; | 161 | }; |
| 156 | 162 | ||
| 157 | struct quadd_power_rate_data { | 163 | struct quadd_power_rate_data { |
| 158 | u64 time; | 164 | u64 time; |
| 159 | 165 | ||
| 160 | u32 nr_cpus; | 166 | u8 nr_cpus; |
| 161 | 167 | ||
| 162 | u32 gpu; | 168 | u32 gpu; |
| 163 | u32 emc; | 169 | u32 emc; |
| 164 | }; | 170 | }; |
| 165 | 171 | ||
| 166 | struct quadd_additional_sample { | 172 | struct quadd_additional_sample { |
| 167 | u32 type; | 173 | u8 type; |
| 168 | 174 | ||
| 169 | u32 values[8]; | 175 | u32 values[6]; |
| 170 | u32 extra_length; | 176 | u16 extra_length; |
| 171 | }; | 177 | }; |
| 172 | 178 | ||
| 173 | enum { | 179 | enum { |
| @@ -186,42 +192,48 @@ enum { | |||
| 186 | }; | 192 | }; |
| 187 | 193 | ||
| 188 | struct quadd_debug_data { | 194 | struct quadd_debug_data { |
| 189 | u32 type; | 195 | u8 type; |
| 190 | 196 | ||
| 191 | u32 cpu; | ||
| 192 | u32 pid; | 197 | u32 pid; |
| 193 | u64 time; | 198 | u64 time; |
| 194 | 199 | ||
| 195 | u64 timer_period; | 200 | u16 cpu:6, |
| 201 | user_mode:1, | ||
| 202 | lp_mode:1, | ||
| 203 | thumb_mode:1, | ||
| 204 | reserved:7; | ||
| 196 | 205 | ||
| 197 | u32 extra_value1; | 206 | u32 extra_value[2]; |
| 198 | u32 extra_value2; | 207 | u16 extra_length; |
| 199 | u32 extra_value3; | ||
| 200 | }; | 208 | }; |
| 201 | 209 | ||
| 210 | #define QUADD_HEADER_MAGIC 0x1122 | ||
| 202 | 211 | ||
| 203 | struct quadd_header_data { | 212 | struct quadd_header_data { |
| 204 | u32 version; | 213 | u16 magic; |
| 214 | u16 version; | ||
| 205 | 215 | ||
| 206 | u32 backtrace:1, | 216 | u32 backtrace:1, |
| 207 | use_freq:1, | 217 | use_freq:1, |
| 208 | system_wide:1, | 218 | system_wide:1, |
| 209 | power_rate:1, | 219 | power_rate:1, |
| 210 | debug_samples:1; | 220 | debug_samples:1, |
| 221 | get_mmap:1, | ||
| 222 | reserved:26; /* reserved fields for future extensions */ | ||
| 211 | 223 | ||
| 212 | u64 period; | 224 | u32 freq; |
| 213 | u32 ma_period; | 225 | u16 ma_freq; |
| 214 | u32 power_rate_period; | 226 | u16 power_rate_freq; |
| 215 | 227 | ||
| 216 | u32 reserved[4]; /* reserved fields for future extensions */ | 228 | u8 nr_events; |
| 229 | u16 extra_length; | ||
| 217 | }; | 230 | }; |
| 218 | 231 | ||
| 219 | #define QUADD_RECORD_MAGIC 0x33557799 | 232 | #define QUADD_RECORD_MAGIC 0x335577aa |
| 220 | 233 | ||
| 221 | struct quadd_record_data { | 234 | struct quadd_record_data { |
| 222 | u32 magic; /* for debug */ | 235 | u32 magic; /* temporary, it will be removed later */ |
| 223 | u32 record_type; | 236 | u8 record_type; |
| 224 | u32 cpu_mode; | ||
| 225 | 237 | ||
| 226 | union { | 238 | union { |
| 227 | struct quadd_sample_data sample; | 239 | struct quadd_sample_data sample; |
| @@ -232,7 +244,9 @@ struct quadd_record_data { | |||
| 232 | struct quadd_power_rate_data power_rate; | 244 | struct quadd_power_rate_data power_rate; |
| 233 | struct quadd_additional_sample additional_sample; | 245 | struct quadd_additional_sample additional_sample; |
| 234 | }; | 246 | }; |
| 235 | }; | 247 | } __aligned(4); |
| 248 | |||
| 249 | #pragma pack(4) | ||
| 236 | 250 | ||
| 237 | #define QUADD_MAX_PACKAGE_NAME 320 | 251 | #define QUADD_MAX_PACKAGE_NAME 320 |
| 238 | 252 | ||
| @@ -286,6 +300,7 @@ enum { | |||
| 286 | 300 | ||
| 287 | #define QUADD_COMM_CAP_EXTRA_BT_KERNEL_CTX (1 << 0) | 301 | #define QUADD_COMM_CAP_EXTRA_BT_KERNEL_CTX (1 << 0) |
| 288 | #define QUADD_COMM_CAP_EXTRA_GET_MMAP (1 << 1) | 302 | #define QUADD_COMM_CAP_EXTRA_GET_MMAP (1 << 1) |
| 303 | #define QUADD_COMM_CAP_EXTRA_GROUP_SAMPLES (1 << 2) | ||
| 289 | 304 | ||
| 290 | struct quadd_comm_cap { | 305 | struct quadd_comm_cap { |
| 291 | u32 pmu:1, | 306 | u32 pmu:1, |
