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| author | Santosh Reddy Galma <galmar@nvidia.com> | 2017-08-29 10:23:35 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-09-11 14:22:46 -0400 |
| commit | c20fb12aebbefd13dd334a2b60b8e43b85e9eb48 (patch) | |
| tree | a988bd3c474adcdcc155116a5008e107e056dad9 /include/linux | |
| parent | 41338a0f55d79d3e4958e809ee75707bb3857d70 (diff) | |
video: tegra: dc: fix display powerdomains
Change does the following
- enable clocks nvdisplayhub,nvdisplay_disp,nvdisplay_p0,
nvdisplay_p1,nvdisplay_p2,nvdisplay_dsc before enabling
head0 powerdomain before accessing any display register
as WAR to fix issues in kernel due to BL enabling all
display power domains unconditionally.
- unpowergate/powergate DPAUX powerdomain instead
of corresponding head power domain in display drivers
as per display powerdomains in guidelines.
- read powergate id for DPAUX based on compatible field
from dt.
- enable/disable dpaux powerdomain before I2C transfer
using DDC.
- code refactoring and cleanup.
Bug 200292406
Change-Id: I473c5aa74aceed6131dec9da848c588e9e3c490c
Signed-off-by: Santosh Reddy Galma <galmar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1547730
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux')
0 files changed, 0 insertions, 0 deletions