ASoC: tegra-alt: Control AHUB rate from DT

AHUB clock currently uses pll_a_out0 derivative clock from plla source
but the max frequency for pll_a_out0 was limited to ~49MHz to derive
all possible clock rates for i2s sampling rates. This limits the AHUB
clock rate to be used at peak possible rate for ahub which can help in
some high bandwidth usecase. Considering this AHUB rate can be derived
from PLLP clock to support max possible rate for AHUB.

Making use of assigned-clock-rates and assigned-clock-parents to set the
desired settings as per dvfs table for a given platforms.

Bug 200537672

Change-Id: Ica556fc68456b52516c82b6601b54cae0b5d1b73
Signed-off-by: Mohan Kumar <mkumard@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvidia/+/2204283
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sameer Pujar <spujar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sharad Gupta <sharadg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

0 files changed, 0 insertions, 0 deletions