diff options
| author | Sumit Gupta <sumitg@nvidia.com> | 2018-07-09 09:07:00 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-13 20:27:44 -0400 |
| commit | 8be06c2bf3ca96fb216f064f18da7ac6470633a7 (patch) | |
| tree | fd259d0006f968f956bc274e317199a63b44d241 /include/linux | |
| parent | 262b58181ec4259f6458ad9ad986c7de962327cb (diff) | |
platform: tegra: update RAS error codes
Updating ERR<x>CTLR bits and IERR codes to report correct error.
RAS/MCA error codes and bits have been changed in recent MTS code
due to which error info will not be reported correctly. So, updating
related codevalues and bits in RAS driver as per latest sheet
from MTS member "New_MCA_20180619_0114.xlsx".
Bug 200420692
Change-Id: If5268a8f0b8005cf97b147b154b9249529c108ec
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774516
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rohit Khanna <rokhanna@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/platform/tegra/carmel_ras.h | 129 |
1 files changed, 66 insertions, 63 deletions
diff --git a/include/linux/platform/tegra/carmel_ras.h b/include/linux/platform/tegra/carmel_ras.h index 886772a59..d533439e3 100644 --- a/include/linux/platform/tegra/carmel_ras.h +++ b/include/linux/platform/tegra/carmel_ras.h | |||
| @@ -15,8 +15,6 @@ | |||
| 15 | 15 | ||
| 16 | /* Error Records Per Core */ | 16 | /* Error Records Per Core */ |
| 17 | /* ERR_CTLR bits for IFU */ | 17 | /* ERR_CTLR bits for IFU */ |
| 18 | #define ERR_CTL_IFU_ITLB_SNP_ERR RAS_BIT(43) | ||
| 19 | #define ERR_CTL_IFU_MITGRP_ERR RAS_BIT(42) | ||
| 20 | #define ERR_CTL_IFU_IMQDP_ERR RAS_BIT(41) | 18 | #define ERR_CTL_IFU_IMQDP_ERR RAS_BIT(41) |
| 21 | #define ERR_CTL_IFU_L2UC_ERR RAS_BIT(40) | 19 | #define ERR_CTL_IFU_L2UC_ERR RAS_BIT(40) |
| 22 | #define ERR_CTL_IFU_ICTPSNP_ERR RAS_BIT(38) | 20 | #define ERR_CTL_IFU_ICTPSNP_ERR RAS_BIT(38) |
| @@ -34,97 +32,102 @@ | |||
| 34 | #define ERR_CTL_RET_JSR_TO_ERR RAS_BIT(32) | 32 | #define ERR_CTL_RET_JSR_TO_ERR RAS_BIT(32) |
| 35 | 33 | ||
| 36 | /* ERR_CTLR bits for MTS_JSR */ | 34 | /* ERR_CTLR bits for MTS_JSR */ |
| 37 | #define ERR_CTL_MTS_JSR_ERRUC_ERR RAS_BIT(32) | ||
| 38 | #define ERR_CTL_MTS_JSR_ERRC_ERR RAS_BIT(33) | ||
| 39 | #define ERR_CTL_MTS_JSR_NAFLL_ERR RAS_BIT(34) | ||
| 40 | #define ERR_CTL_MTS_JSR_CARVE_ERR RAS_BIT(35) | ||
| 41 | #define ERR_CTL_MTS_JSR_CRAB_ERR RAS_BIT(36) | ||
| 42 | #define ERR_CTL_MTS_JSR_MMIO_ERR RAS_BIT(37) | 35 | #define ERR_CTL_MTS_JSR_MMIO_ERR RAS_BIT(37) |
| 36 | #define ERR_CTL_MTS_JSR_CRAB_ERR RAS_BIT(36) | ||
| 37 | #define ERR_CTL_MTS_JSR_CARVE_ERR RAS_BIT(35) | ||
| 38 | #define ERR_CTL_MTS_JSR_NAFLL_ERR RAS_BIT(34) | ||
| 39 | #define ERR_CTL_MTS_JSR_ERRC_ERR RAS_BIT(33) | ||
| 40 | #define ERR_CTL_MTS_JSR_ERRUC_ERR RAS_BIT(32) | ||
| 43 | 41 | ||
| 44 | /* ERR_CTLR bits for LSD_1 */ | 42 | /* ERR_CTLR bits for LSD_1/LSD_STQ */ |
| 45 | #define ERR_CTL_LSD1_CCTP_ERR RAS_BIT(32) | 43 | #define ERR_CTL_LSD1_CCDEMLECC_ERR RAS_BIT(41) |
| 46 | #define ERR_CTL_LSD1_MCMH_ERR RAS_BIT(33) | 44 | #define ERR_CTL_LSD1_CCDSECC_D_ERR RAS_BIT(40) |
| 47 | #define ERR_CTL_LSD1_CCMH_ERR RAS_BIT(34) | 45 | #define ERR_CTL_LSD1_CCDSECC_S_ERR RAS_BIT(39) |
| 48 | #define ERR_CTL_LSD1_MCDLP_ERR RAS_BIT(35) | 46 | #define ERR_CTL_LSD1_CCDLECC_D_ERR RAS_BIT(38) |
| 49 | #define ERR_CTL_LSD1_CCDLECC_S_ERR RAS_BIT(36) | 47 | #define ERR_CTL_LSD1_CCDLECC_S_ERR RAS_BIT(37) |
| 50 | #define ERR_CTL_LSD1_CCDLECC_D_ERR RAS_BIT(37) | 48 | #define ERR_CTL_LSD1_CCMH_ERR RAS_BIT(35) |
| 51 | #define ERR_CTL_LSD1_CCDSECC_S_ERR RAS_BIT(38) | 49 | #define ERR_CTL_LSD1_CCTSP_ERR RAS_BIT(33) |
| 52 | #define ERR_CTL_LSD1_CCDSECC_D_ERR RAS_BIT(39) | 50 | #define ERR_CTL_LSD1_CCTLP_ERR RAS_BIT(32) |
| 53 | #define ERR_CTL_LSD1_CCDEMLECC_ERR RAS_BIT(40) | 51 | |
| 54 | 52 | /* ERR_CTLR bits for LSD_2/LSD_DCC */ | |
| 55 | /* ERR_CTLR bits for LSD_2 */ | 53 | #define ERR_CTL_LSD2_BTMCMH_ERR RAS_BIT(41) |
| 56 | #define ERR_CTL_LSD2_BTCCVPP_ERR RAS_BIT(32) | 54 | #define ERR_CTL_LSD2_CCDEECC_D_ERR RAS_BIT(39) |
| 57 | #define ERR_CTL_LSD2_BTCCPPP_ERR RAS_BIT(33) | 55 | #define ERR_CTL_LSD2_CCDEECC_S_ERR RAS_BIT(38) |
| 58 | #define ERR_CTL_LSD2_BTCCMH_ERR RAS_BIT(34) | 56 | #define ERR_CTL_LSD2_VRCBP_ERR RAS_BIT(37) |
| 59 | #define ERR_CTL_LSD2_VRCDECC_S_ERR RAS_BIT(35) | ||
| 60 | #define ERR_CTL_LSD2_VRCDECC_D_ERR RAS_BIT(36) | 57 | #define ERR_CTL_LSD2_VRCDECC_D_ERR RAS_BIT(36) |
| 61 | #define ERR_CTL_LSD2_VRCDP_ERR RAS_BIT(37) | 58 | #define ERR_CTL_LSD2_VRCDECC_S_ERR RAS_BIT(35) |
| 62 | #define ERR_CTL_LSD2_MCDEP_ERR RAS_BIT(38) | 59 | #define ERR_CTL_LSD2_BTCCPPP_ERR RAS_BIT(33) |
| 63 | #define ERR_CTL_LSD2_CCDEECC_S_ERR RAS_BIT(39) | 60 | #define ERR_CTL_LSD2_BTCCVPP_ERR RAS_BIT(32) |
| 64 | #define ERR_CTL_LSD2_CCDEECC_D_ERR RAS_BIT(40) | ||
| 65 | #define ERR_CTL_LSD2_L2REQ_UNCORR_ERR RAS_BIT(41) | ||
| 66 | 61 | ||
| 67 | /* ERR_CTLR bits for LSD_3 */ | 62 | /* ERR_CTLR bits for LSD_3/LSD_L1HPF */ |
| 68 | #define ERR_CTL_LSD3_L2TLBP_ERR RAS_BIT(32) | 63 | #define ERR_CTL_LSD3_L2TLBP_ERR RAS_BIT(32) |
| 69 | #define ERR_CTL_LSD3_LATENT_ERR RAS_BIT(63) | ||
| 70 | 64 | ||
| 71 | /* Error records per CCPLEX */ | 65 | /* Error records per CCPLEX */ |
| 72 | /* ERR_CTLR bits for CMU:CCPMU or DPMU*/ | 66 | /* ERR_CTLR bits for CMU:CCPMU or DPMU*/ |
| 73 | #define ERR_CTL_DPMU_DMCE_CRAB_ACC_ERR RAS_BIT(32) | 67 | #define ERR_CTL_DPMU_DMCE_UCODE_ERR RAS_BIT(36) |
| 68 | #define ERR_CTL_DPMU_DMCE_IL1_PAR_ERR RAS_BIT(35) | ||
| 69 | #define ERR_CTL_DPMU_DMCE_TIMEOUT_ERR RAS_BIT(34) | ||
| 74 | #define ERR_CTL_DPMU_CRAB_ACC_ERR RAS_BIT(33) | 70 | #define ERR_CTL_DPMU_CRAB_ACC_ERR RAS_BIT(33) |
| 75 | #define ERR_CTL_DPMU_DMCE_UCODE_ERR RAS_BIT(35) | 71 | #define ERR_CTL_DPMU_DMCE_CRAB_ACC_ERR RAS_BIT(32) |
| 76 | 72 | ||
| 77 | /* ERR_CTLR bits for SCF:IOB*/ | 73 | /* ERR_CTLR bits for SCF:IOB*/ |
| 78 | #define ERR_CTL_SCFIOB_REQ_PAR_ERR RAS_BIT(41) | 74 | #define ERR_CTL_SCFIOB_REQ_PAR_ERR RAS_BIT(41) |
| 79 | #define ERR_CTL_SCFIOB_PUT_PAR_ERR RAS_BIT(40) | 75 | #define ERR_CTL_SCFIOB_PUT_PAR_ERR RAS_BIT(40) |
| 80 | #define ERR_CTL_SCFIOB_PUT_CECC_ERR RAS_BIT(32) | ||
| 81 | #define ERR_CTL_SCFIOB_PUT_UECC_ERR RAS_BIT(39) | 76 | #define ERR_CTL_SCFIOB_PUT_UECC_ERR RAS_BIT(39) |
| 82 | #define ERR_CTL_SCFIOB_EVP_ERR RAS_BIT(33) | 77 | #define ERR_CTL_SCFIOB_CBB_ERR RAS_BIT(38) |
| 83 | #define ERR_CTL_SCFIOB_TBX_ERR RAS_BIT(34) | ||
| 84 | #define ERR_CTL_SCFIOB_CRI_ERR RAS_BIT(35) | ||
| 85 | #define ERR_CTL_SCFIOB_MMCRAB_ERR RAS_BIT(37) | 78 | #define ERR_CTL_SCFIOB_MMCRAB_ERR RAS_BIT(37) |
| 86 | #define ERR_CTL_SCFIOB_IHI_ERR RAS_BIT(36) | 79 | #define ERR_CTL_SCFIOB_IHI_ERR RAS_BIT(36) |
| 87 | #define ERR_CTL_SCFIOB_CBB_ERR RAS_BIT(38) | 80 | #define ERR_CTL_SCFIOB_CRI_ERR RAS_BIT(35) |
| 81 | #define ERR_CTL_SCFIOB_TBX_ERR RAS_BIT(34) | ||
| 82 | #define ERR_CTL_SCFIOB_EVP_ERR RAS_BIT(33) | ||
| 83 | #define ERR_CTL_SCFIOB_PUT_CECC_ERR RAS_BIT(32) | ||
| 88 | #define ERRX_SCFIOB 1025 | 84 | #define ERRX_SCFIOB 1025 |
| 89 | 85 | ||
| 90 | /* ERR_CTLR bits for SCF:SNOC*/ | 86 | /* ERR_CTLR bits for SCF:SNOC*/ |
| 91 | #define ERR_CTL_SCFSNOC_CPE_TO_ERR RAS_BIT(34) | 87 | #define ERR_CTL_SCFSNOC_MISC_RSP_ERR RAS_BIT(42) |
| 92 | #define ERR_CTL_SCFSNOC_CPE_RSP_ERR RAS_BIT(35) | 88 | #define ERR_CTL_SCFSNOC_MISC_PAR_ERR RAS_BIT(41) |
| 93 | #define ERR_CTL_SCFSNOC_CPE_REQ_ERR RAS_BIT(36) | 89 | #define ERR_CTL_SCFSNOC_MISC_UECC_ERR RAS_BIT(40) |
| 94 | #define ERR_CTL_SCFSNOC_DVMU_TO_ERR RAS_BIT(37) | 90 | #define ERR_CTL_SCFSNOC_DVMU_PAR_ERR RAS_BIT(39) |
| 95 | #define ERR_CTL_SCFSNOC_DVMU_PAR_ERR RAS_BIT(38) | 91 | #define ERR_CTL_SCFSNOC_DVMU_TO_ERR RAS_BIT(38) |
| 96 | #define ERR_CTL_SCFSNOC_MISC_CECC_ERR RAS_BIT(32) | 92 | #define ERR_CTL_SCFSNOC_CPE_REQ_ERR RAS_BIT(37) |
| 97 | #define ERR_CTL_SCFSNOC_MISC_UECC_ERR RAS_BIT(39) | 93 | #define ERR_CTL_SCFSNOC_CPE_RSP_ERR RAS_BIT(36) |
| 98 | #define ERR_CTL_SCFSNOC_MISC_PAR_ERR RAS_BIT(40) | 94 | #define ERR_CTL_SCFSNOC_CPE_TO_ERR RAS_BIT(35) |
| 99 | #define ERR_CTL_SCFSNOC_MISC_RSP_ERR RAS_BIT(41) | 95 | #define ERR_CTL_SCFSNOC_CARVEOUT_ERR RAS_BIT(34) |
| 100 | #define ERR_CTL_SCFSNOC_CARVEOUT_ERR RAS_BIT(33) | 96 | #define ERR_CTL_SCFSNOC_MISC_CECC_ERR RAS_BIT(33) |
| 101 | 97 | #define ERR_CTL_SCFSNOC_CARVEOUT_CECC_ERR RAS_BIT(32) | |
| 102 | /* ERR_CTLR bits for CMU:CTU*/ | 98 | |
| 103 | #define ERR_CTL_CMUCTU_TRCDMA_PAR_ERR RAS_BIT(32) | 99 | /* ERR_CTLR bits for SCF:CTU*/ |
| 104 | #define ERR_CTL_CMUCTU_MCF_PAR_ERR RAS_BIT(33) | 100 | #define ERR_CTL_CMUCTU_TRCDMA_REQ_ERR RAS_BIT(39) |
| 101 | #define ERR_CTL_CMUCTU_CTU_SNP_ERR RAS_BIT(38) | ||
| 102 | #define ERR_CTL_CMUCTU_TAG_PAR_ERR RAS_BIT(37) | ||
| 103 | #define ERR_CTL_CMUCTU_CTU_DATA_PAR_ERR RAS_BIT(36) | ||
| 104 | #define ERR_CTL_CMUCTU_RSP_PAR_ERR RAS_BIT(35) | ||
| 105 | #define ERR_CTL_CMUCTU_TRL_PAR_ERR RAS_BIT(34) | 105 | #define ERR_CTL_CMUCTU_TRL_PAR_ERR RAS_BIT(34) |
| 106 | #define ERR_CTL_CMUCTU_CTU_DATA_PAR_ERR RAS_BIT(35) | 106 | #define ERR_CTL_CMUCTU_MCF_PAR_ERR RAS_BIT(33) |
| 107 | #define ERR_CTL_CMUCTU_TAG_PAR_ERR RAS_BIT(36) | 107 | #define ERR_CTL_CMUCTU_TRCDMA_PAR_ERR RAS_BIT(32) |
| 108 | #define ERR_CTL_CMUCTU_CTU_SNP_ERR RAS_BIT(37) | ||
| 109 | #define ERR_CTL_CMUCTU_TRCDMA_REQ_ERR RAS_BIT(38) | ||
| 110 | 108 | ||
| 111 | /* ERR_CTLR bits for SCF:L3_* */ | 109 | /* ERR_CTLR bits for SCF:L3_* */ |
| 112 | #define ERR_CTL_SCFL3_ADR_ERR RAS_BIT(38) | ||
| 113 | #define ERR_CTL_SCFL3_PERR_ERR RAS_BIT(40) | ||
| 114 | #define ERR_CTL_SCFL3_UECC_ERR RAS_BIT(39) | ||
| 115 | #define ERR_CTL_SCFL3_CECC_ERR RAS_BIT(44) | 110 | #define ERR_CTL_SCFL3_CECC_ERR RAS_BIT(44) |
| 111 | #define ERR_CTL_SCFL3_SNOC_INTFC_ERR RAS_BIT(43) | ||
| 112 | #define ERR_CTL_SCFL3_MCF_INTFC_ERR RAS_BIT(42) | ||
| 113 | #define ERR_CTL_SCFL3_TAG_ERR RAS_BIT(41) | ||
| 114 | #define ERR_CTL_SCFL3_L2DIR_ERR RAS_BIT(41) | ||
| 115 | #define ERR_CTL_SCFL3_UECC_ERR RAS_BIT(39) | ||
| 116 | #define ERR_CTL_SCFL3_MH_CAM_ERR RAS_BIT(37) | 116 | #define ERR_CTL_SCFL3_MH_CAM_ERR RAS_BIT(37) |
| 117 | #define ERR_CTL_SCFL3_MH_TAG_ERR RAS_BIT(36) | 117 | #define ERR_CTL_SCFL3_MH_TAG_ERR RAS_BIT(36) |
| 118 | #define ERR_CTL_SCFL3_UNSUPP_REQ_ERR RAS_BIT(35) | 118 | #define ERR_CTL_SCFL3_UNSUPP_REQ_ERR RAS_BIT(35) |
| 119 | #define ERR_CTL_SCFL3_PROT_ERR RAS_BIT(34) | 119 | #define ERR_CTL_SCFL3_PROT_ERR RAS_BIT(34) |
| 120 | #define ERR_CTL_SCFL3_TO_ERR RAS_BIT(33) | ||
| 121 | #define ERRX_SCFL3 768 | 120 | #define ERRX_SCFL3 768 |
| 122 | 121 | ||
| 123 | /* ERR_CTLR bits for SCFCMU_CLOCKS */ | 122 | /* ERR_CTLR bits for SCFCMU_CLOCKS */ |
| 124 | #define ERR_CTL_SCFCMU_LUT0_PAR_ERR RAS_BIT(32) | 123 | #define ERR_CTL_SCFCMU_FREQ3_MON_ERR RAS_BIT(39) |
| 125 | #define ERR_CTL_SCFCMU_LUT1_PAR_ERR RAS_BIT(33) | 124 | #define ERR_CTL_SCFCMU_FREQ2_MON_ERR RAS_BIT(38) |
| 126 | #define ERR_CTL_SCFCMU_ADC0_MON_ERR RAS_BIT(34) | 125 | #define ERR_CTL_SCFCMU_FREQ1_MON_ERR RAS_BIT(37) |
| 126 | #define ERR_CTL_SCFCMU_FREQ0_MON_ERR RAS_BIT(36) | ||
| 127 | #define ERR_CTL_SCFCMU_ADC1_MON_ERR RAS_BIT(35) | 127 | #define ERR_CTL_SCFCMU_ADC1_MON_ERR RAS_BIT(35) |
| 128 | #define ERR_CTL_SCFCMU_ADC0_MON_ERR RAS_BIT(34) | ||
| 129 | #define ERR_CTL_SCFCMU_LUT1_PAR_ERR RAS_BIT(33) | ||
| 130 | #define ERR_CTL_SCFCMU_LUT0_PAR_ERR RAS_BIT(32) | ||
| 128 | 131 | ||
| 129 | /* Error records per Core Cluster */ | 132 | /* Error records per Core Cluster */ |
| 130 | /* ERR_CTLR bits for L2 */ | 133 | /* ERR_CTLR bits for L2 */ |
| @@ -154,8 +157,8 @@ | |||
| 154 | #define ERR_CTL_L2_URTTO_ERR RAS_BIT(56) | 157 | #define ERR_CTL_L2_URTTO_ERR RAS_BIT(56) |
| 155 | 158 | ||
| 156 | /* ERR_CTLR bits for MMU */ | 159 | /* ERR_CTLR bits for MMU */ |
| 160 | #define ERR_CTL_MMU_WCPERR_ERR RAS_BIT(33) | ||
| 157 | #define ERR_CTL_MMU_ACPERR_ERR RAS_BIT(32) | 161 | #define ERR_CTL_MMU_ACPERR_ERR RAS_BIT(32) |
| 158 | #define ERR_CTL_MMU_WCPERR_ERR RAS_BIT(34) | ||
| 159 | 162 | ||
| 160 | /* ERR_CTLR bits for CLUSTER_CLOCKS */ | 163 | /* ERR_CTLR bits for CLUSTER_CLOCKS */ |
| 161 | #define ERR_CTL_CC_FREQ_MON_ERR RAS_BIT(32) | 164 | #define ERR_CTL_CC_FREQ_MON_ERR RAS_BIT(32) |