nvlink: fix TX clock model

Initially BPMP modeled NVLINK TX clock source mux as clock gate
TEGRA194_CLK_NVLINK_TXCLK_CTRL. This allowed NVLINK driver to just
enable TEGRA194_CLK_NVLINK_TXCLK_CTRL when it needed to switch to PLL
source, and disable TEGRA194_CLK_NVLINK_TXCLK_CTRL in order to switch
back to clk_m/oscillator source. This model is incorrect (gate instated
of mux). It doesn’t allow proper voltage scaling for NVLINK clock, and
it is not consistent with NVLINK clock monitoring.

The NVLINK clock model is now fixed in BPMP. The following changes have
been made to the NVLINK kernel driver in order to comply with the new
clock model:
   1. call clk_set_rate() on TEGRA194_CLK_NVLINK_PLL_TXCLK after
      INITPLL/XAVIER_CALIBRATEPLL DLCMDs
   2. Instead of enabling/disabling TEGRA194_CLK_NVLINK_TXCLK_CTRL, the
      NVLINK driver calls clk_set_parent() on TEGRA194_CLK_NVLINK_TX
      clock

Bug 2048310

Change-Id: I55c23a0b8f07335b8e331442a208288260a8953d
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649119
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/include/linux/platform/tegra/tegra-nvlink.h b/include/linux/platform/tegra/tegra-nvlink.h
index 3502ce4fe..4c4589e54 100644
--- a/include/linux/platform/tegra/tegra-nvlink.h
+++ b/include/linux/platform/tegra/tegra-nvlink.h
@@ -25,6 +25,10 @@
 #define NVLINK_MAX_LINKS                        2
 #define DEFAULT_LOOP_SLEEP_US                   100
 #define DEFAULT_LOOP_TIMEOUT_US                 1000000
+#define LINK_BITRATE_150MHZ_20GBPS              19200000000ULL
+#define LINK_BITRATE_156MHZ_20GBPS              20001280000ULL
+#define LINK_BITRATE_150MHZ_25GBPS              24750000000ULL
+#define LINK_BITRATE_156MHZ_25GBPS              25782900000ULL
 
 struct nvlink_link;
 struct nvlink_device;
@@ -236,6 +240,8 @@ struct nvlink_device {
         bool is_master;
         /* NVlink Speed */
         enum nvlink_speed speed;
+        /* The bitrate at which the link is operating */
+        u64 link_bitrate;
         /*nvlink link data. We assume there is single link per device*/
         struct nvlink_link link;
         /* Pointer to struct containing callback functions to do device specific