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authorErik Lilliebjerg <elilliebjerg@nvidia.com>2013-06-06 10:25:35 -0400
committerRobert Collins <rcollins@nvidia.com>2017-07-13 17:12:48 -0400
commit556c732d220ce8ebcdca7ae047c6ffbeb871e451 (patch)
treee673b7ec7eaf4e2aa57592993be38f389f913c90 /include/linux
parent87496fe1c0093bcaa680f05d7874081f70426eac (diff)
input: misc: fix sysfs permissions
- Fix sysfs permissions. - Fix raw accelerometer access. - Fix autodetection behind MPU. - Add self-test. Bug 1224709 Bug 1243584 Bug 1291044 Bug 1295651 Bug 1290313 Bug 1298831 Change-Id: I55847fd158abdb9f12dc830218619c6ed7913396 Signed-off-by: Erik Lilliebjerg <elilliebjerg@nvidia.com> Reviewed-on: http://git-master/r/243010 Reviewed-by: Seema Khowala <seemaj@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com>
Diffstat (limited to 'include/linux')
-rw-r--r--include/linux/mpu.h61
1 files changed, 28 insertions, 33 deletions
diff --git a/include/linux/mpu.h b/include/linux/mpu.h
index 3f303da82..0b15d7c02 100644
--- a/include/linux/mpu.h
+++ b/include/linux/mpu.h
@@ -40,25 +40,25 @@
40* Adds SYSFS attributes to read/write MPU registers from ADB 40* Adds SYSFS attributes to read/write MPU registers from ADB
41* shell: 41* shell:
42* dbg_reg = REGISTER 42* dbg_reg = REGISTER
43* - A write to dbg_reg sets the device register to use 43* A write to dbg_reg sets the device register to use.
44* - A read reads the current value of dbg_reg 44* A read reads the current value of dbg_reg.
45* dbg_dat = DATA 45* dbg_dat = DATA
46* - A write to dbg_dat initiates an I2C write transaction 46* A write to dbg_dat initiates an I2C write transaction
47* to the device register defined by dbg_reg with the 47* to the device register defined by dbg_reg with the
48* data defined by dbg_dat 48* data defined by dbg_dat
49* - A read to dbg_dat initiates an I2C read transaction 49* A read to dbg_dat initiates an I2C read transaction
50* to the device register defined by dbg_reg. 50* to the device register defined by dbg_reg.
51* dbg_i2c_addr = I2C device address 51* dbg_i2c_addr = I2C device address
52* - if set to 0 (default) the MPU I2C address is used. 52* If set to 0 (default) the MPU I2C address is used.
53* - other devices can be accessed by setting this to the 53* Other devices can be accessed by setting this to
54* that device I2C address. When used after enabling 54* that device's I2C address. When used after enabling
55* bypass mode, devices behind the MPU can be accessed. 55* bypass mode, devices behind the MPU can be accessed.
56* aux_dbg = write 1 to spew auxiliary port register dumps after 56* aux_dbg = write 1 to spew auxiliary port register dumps after
57* after each external driver call. 57* each external driver call.
58* Write 0 to disable the spew. 58* Write 0 to disable the spew.
59* Writing anything takes a snapshot of the registers. 59* Writing anything takes a snapshot of the registers.
60* Therefore, a write of 0 can take snapshots whenever 60* Therefore, a write of 0 can take snapshots whenever
61* without the external driver call spew. 61* without the external driver call spew.
62**********************************************************************/ 62**********************************************************************/
63#define DEBUG_SYSFS_INTERFACE 1 63#define DEBUG_SYSFS_INTERFACE 1
64 64
@@ -67,14 +67,14 @@
67 * XXX : mount position. TOP for top and BOT for bottom. 67 * XXX : mount position. TOP for top and BOT for bottom.
68 * YYY : couter-clockwise rotation angle in degree. 68 * YYY : couter-clockwise rotation angle in degree.
69 */ 69 */
70#define MTMAT_TOP_CCW_0 { 1, 0, 0, 0, 1, 0, 0, 0, 1 } 70#define MTMAT_TOP_CCW_0 { 1, 0, 0, 0, 1, 0, 0, 0, 1 }
71#define MTMAT_TOP_CCW_90 { 0, -1, 0, 1, 0, 0, 0, 0, 1 } 71#define MTMAT_TOP_CCW_90 { 0, -1, 0, 1, 0, 0, 0, 0, 1 }
72#define MTMAT_TOP_CCW_180 { -1, 0, 0, 0, -1, 0, 0, 0, 1 } 72#define MTMAT_TOP_CCW_180 { -1, 0, 0, 0, -1, 0, 0, 0, 1 }
73#define MTMAT_TOP_CCW_270 { 0, 1, 0, -1, 0, 0, 0, 0, 1 } 73#define MTMAT_TOP_CCW_270 { 0, 1, 0, -1, 0, 0, 0, 0, 1 }
74#define MTMAT_BOT_CCW_0 { -1, 0, 0, 0, 1, 0, 0, 0, -1 } 74#define MTMAT_BOT_CCW_0 { -1, 0, 0, 0, 1, 0, 0, 0, -1 }
75#define MTMAT_BOT_CCW_90 { 0, -1, 0, -1, 0, 0, 0, 0, -1 } 75#define MTMAT_BOT_CCW_90 { 0, -1, 0, -1, 0, 0, 0, 0, -1 }
76#define MTMAT_BOT_CCW_180 { 1, 0, 0, 0, -1, 0, 0, 0, -1 } 76#define MTMAT_BOT_CCW_180 { 1, 0, 0, 0, -1, 0, 0, 0, -1 }
77#define MTMAT_BOT_CCW_270 { 0, 1, 0, 1, 0, 0, 0, 0, -1 } 77#define MTMAT_BOT_CCW_270 { 0, 1, 0, 1, 0, 0, 0, 0, -1 }
78 78
79/*********************************************************************/ 79/*********************************************************************/
80/* Structure and function prototypes */ 80/* Structure and function prototypes */
@@ -372,7 +372,7 @@ struct ext_slave_descr {
372 372
373#define NVI_CONFIG_BOOT_AUTO (0) /* auto detect connection to MPU */ 373#define NVI_CONFIG_BOOT_AUTO (0) /* auto detect connection to MPU */
374#define NVI_CONFIG_BOOT_MPU (1) /* connected to MPU */ 374#define NVI_CONFIG_BOOT_MPU (1) /* connected to MPU */
375#define NVI_CONFIG_BOOT_EXTERNAL (2) /* connected to host */ 375#define NVI_CONFIG_BOOT_HOST (2) /* connected to host */
376#define NVI_CONFIG_BOOT_MASK (0x03) 376#define NVI_CONFIG_BOOT_MASK (0x03)
377 377
378/** 378/**
@@ -488,7 +488,7 @@ struct nvi_mpu_port {
488 * connected to the host (that the MPU is connected to). 488 * connected to the host (that the MPU is connected to).
489 * This is a global connection switch affecting all ports 489 * This is a global connection switch affecting all ports
490 * so a mechanism is in place of whether the request is 490 * so a mechanism is in place of whether the request is
491 * honored or not. See the funtion notes for 491 * honored or not. See the function notes for
492 * nvi_mpu_bypass_request. 492 * nvi_mpu_bypass_request.
493 */ 493 */
494 494
@@ -670,13 +670,8 @@ int nvi_mpu_bypass_request(bool enable);
670 670
671/** 671/**
672 * See the nvi_mpu_bypass_request notes. 672 * See the nvi_mpu_bypass_request notes.
673 * @return int error: calls that return with an error must be 673 * @return int 0: Always returns 0. The call return should be
674 * tried again. 674 * void but for backward compatibility it returns 0.
675 * Possible errors are:
676 * - -EAGAIN: MPU is not initialized yet.
677 * - -EPERM: MPU is shutdown. MPU API won't be
678 * available until a system restart.
679 * - -EBUSY: MPU is busy with another request.
680 */ 675 */
681int nvi_mpu_bypass_release(void); 676int nvi_mpu_bypass_release(void);
682 677